hw/unin_pci.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc_mac.h"
  26 #include "pci.h"
  27 #include "pci_host.h"
  28
  29 /* debug UniNorth */
  30 //#define DEBUG_UNIN
  31
  32 #ifdef DEBUG_UNIN
  33 #define UNIN_DPRINTF(fmt, ...)                                  \
  34     do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define UNIN_DPRINTF(fmt, ...)
  37 #endif
  38
  39 static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
  40
  41 #define TYPE_UNI_NORTH_PCI_HOST_BRIDGE "uni-north-pci-pcihost"
  42 #define TYPE_UNI_NORTH_AGP_HOST_BRIDGE "uni-north-agp-pcihost"
  43 #define TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE "uni-north-internal-pci-pcihost"
  44 #define TYPE_U3_AGP_HOST_BRIDGE "u3-agp-pcihost"
  45
  46 #define UNI_NORTH_PCI_HOST_BRIDGE(obj) \
  47     OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_PCI_HOST_BRIDGE)
  48 #define UNI_NORTH_AGP_HOST_BRIDGE(obj) \
  49     OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_AGP_HOST_BRIDGE)
  50 #define UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj) \
  51     OBJECT_CHECK(UNINState, (obj), TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE)
  52 #define U3_AGP_HOST_BRIDGE(obj) \
  53     OBJECT_CHECK(UNINState, (obj), TYPE_U3_AGP_HOST_BRIDGE)
  54
  55 typedef struct UNINState {
  56     PCIHostState host_state;
  57
  58     MemoryRegion pci_mmio;
  59     MemoryRegion pci_hole;
  60 } UNINState;
  61
  62 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
  63 {
  64     int retval;
  65     int devfn = pci_dev->devfn & 0x00FFFFFF;
  66
  67     retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
  68
  69     return retval;
  70 }
  71
  72 static void pci_unin_set_irq(void *opaque, int irq_num, int level)
  73 {
  74     qemu_irq *pic = opaque;
  75
  76     UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
  77                  unin_irq_line[irq_num], level);
  78     qemu_set_irq(pic[unin_irq_line[irq_num]], level);
  79 }
  80
  81 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
  82 {
  83     uint32_t retval;
  84
  85     if (reg & (1u << 31)) {
  86         /* XXX OpenBIOS compatibility hack */
  87         retval = reg | (addr & 3);
  88     } else if (reg & 1) {
  89         /* CFA1 style */
  90         retval = (reg & ~7u) | (addr & 7);
  91     } else {
  92         uint32_t slot, func;
  93
  94         /* Grab CFA0 style values */
  95         slot = ffs(reg & 0xfffff800) - 1;
  96         func = (reg >> 8) & 7;
  97
  98         /* ... and then convert them to x86 format */
  99         /* config pointer */
 100         retval = (reg & (0xff - 7)) | (addr & 7);
 101         /* slot */
 102         retval |= slot << 11;
 103         /* fn */
 104         retval |= func << 8;
 105     }
 106
 107
 108     UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
 109                  reg, addr, retval);
 110
 111     return retval;
 112 }
 113
 114 static void unin_data_write(void *opaque, target_phys_addr_t addr,
 115                             uint64_t val, unsigned len)
 116 {
 117     UNINState *s = opaque;
 118     UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
 119                  addr, len, val);
 120     pci_data_write(s->host_state.bus,
 121                    unin_get_config_reg(s->host_state.config_reg, addr),
 122                    val, len);
 123 }
 124
 125 static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
 126                                unsigned len)
 127 {
 128     UNINState *s = opaque;
 129     uint32_t val;
 130
 131     val = pci_data_read(s->host_state.bus,
 132                         unin_get_config_reg(s->host_state.config_reg, addr),
 133                         len);
 134     UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
 135                  addr, len, val);
 136     return val;
 137 }
 138
 139 static const MemoryRegionOps unin_data_ops = {
 140     .read = unin_data_read,
 141     .write = unin_data_write,
 142     .endianness = DEVICE_LITTLE_ENDIAN,
 143 };
 144
 145 static int pci_unin_main_init_device(SysBusDevice *dev)
 146 {
 147     PCIHostState *h;
 148
 149     /* Use values found on a real PowerMac */
 150     /* Uninorth main bus */
 151     h = PCI_HOST_BRIDGE(dev);
 152
 153     memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
 154                           dev, "pci-conf-idx", 0x1000);
 155     memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
 156                           "pci-conf-data", 0x1000);
 157     sysbus_init_mmio(dev, &h->conf_mem);
 158     sysbus_init_mmio(dev, &h->data_mem);
 159
 160     return 0;
 161 }
 162
 163
 164 static int pci_u3_agp_init_device(SysBusDevice *dev)
 165 {
 166     PCIHostState *h;
 167
 168     /* Uninorth U3 AGP bus */
 169     h = PCI_HOST_BRIDGE(dev);
 170
 171     memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
 172                           dev, "pci-conf-idx", 0x1000);
 173     memory_region_init_io(&h->data_mem, &unin_data_ops, dev,
 174                           "pci-conf-data", 0x1000);
 175     sysbus_init_mmio(dev, &h->conf_mem);
 176     sysbus_init_mmio(dev, &h->data_mem);
 177
 178     return 0;
 179 }
 180
 181 static int pci_unin_agp_init_device(SysBusDevice *dev)
 182 {
 183     PCIHostState *h;
 184
 185     /* Uninorth AGP bus */
 186     h = PCI_HOST_BRIDGE(dev);
 187
 188     memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
 189                           dev, "pci-conf-idx", 0x1000);
 190     memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
 191                           dev, "pci-conf-data", 0x1000);
 192     sysbus_init_mmio(dev, &h->conf_mem);
 193     sysbus_init_mmio(dev, &h->data_mem);
 194     return 0;
 195 }
 196
 197 static int pci_unin_internal_init_device(SysBusDevice *dev)
 198 {
 199     PCIHostState *h;
 200
 201     /* Uninorth internal bus */
 202     h = PCI_HOST_BRIDGE(dev);
 203
 204     memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops,
 205                           dev, "pci-conf-idx", 0x1000);
 206     memory_region_init_io(&h->data_mem, &pci_host_data_le_ops,
 207                           dev, "pci-conf-data", 0x1000);
 208     sysbus_init_mmio(dev, &h->conf_mem);
 209     sysbus_init_mmio(dev, &h->data_mem);
 210     return 0;
 211 }
 212
 213 PCIBus *pci_pmac_init(qemu_irq *pic,
 214                       MemoryRegion *address_space_mem,
 215                       MemoryRegion *address_space_io)
 216 {
 217     DeviceState *dev;
 218     SysBusDevice *s;
 219     PCIHostState *h;
 220     UNINState *d;
 221
 222     /* Use values found on a real PowerMac */
 223     /* Uninorth main bus */
 224     dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
 225     qdev_init_nofail(dev);
 226     s = SYS_BUS_DEVICE(dev);
 227     h = PCI_HOST_BRIDGE(s);
 228     d = UNI_NORTH_PCI_HOST_BRIDGE(dev);
 229     memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
 230     memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
 231                              0x80000000ULL, 0x70000000ULL);
 232     memory_region_add_subregion(address_space_mem, 0x80000000ULL,
 233                                 &d->pci_hole);
 234
 235     h->bus = pci_register_bus(dev, "pci",
 236                               pci_unin_set_irq, pci_unin_map_irq,
 237                               pic,
 238                               &d->pci_mmio,
 239                               address_space_io,
 240                               PCI_DEVFN(11, 0), 4);
 241
 242 #if 0
 243     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north");
 244 #endif
 245
 246     sysbus_mmio_map(s, 0, 0xf2800000);
 247     sysbus_mmio_map(s, 1, 0xf2c00000);
 248
 249     /* DEC 21154 bridge */
 250 #if 0
 251     /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
 252     pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
 253 #endif
 254
 255     /* Uninorth AGP bus */
 256     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
 257     dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
 258     qdev_init_nofail(dev);
 259     s = SYS_BUS_DEVICE(dev);
 260     sysbus_mmio_map(s, 0, 0xf0800000);
 261     sysbus_mmio_map(s, 1, 0xf0c00000);
 262
 263     /* Uninorth internal bus */
 264 #if 0
 265     /* XXX: not needed for now */
 266     pci_create_simple(h->bus, PCI_DEVFN(14, 0),
 267                       "uni-north-internal-pci");
 268     dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
 269     qdev_init_nofail(dev);
 270     s = SYS_BUS_DEVICE(dev);
 271     sysbus_mmio_map(s, 0, 0xf4800000);
 272     sysbus_mmio_map(s, 1, 0xf4c00000);
 273 #endif
 274
 275     return h->bus;
 276 }
 277
 278 PCIBus *pci_pmac_u3_init(qemu_irq *pic,
 279                          MemoryRegion *address_space_mem,
 280                          MemoryRegion *address_space_io)
 281 {
 282     DeviceState *dev;
 283     SysBusDevice *s;
 284     PCIHostState *h;
 285     UNINState *d;
 286
 287     /* Uninorth AGP bus */
 288
 289     dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE);
 290     qdev_init_nofail(dev);
 291     s = SYS_BUS_DEVICE(dev);
 292     h = PCI_HOST_BRIDGE(dev);
 293     d = U3_AGP_HOST_BRIDGE(dev);
 294
 295     memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
 296     memory_region_init_alias(&d->pci_hole, "pci-hole", &d->pci_mmio,
 297                              0x80000000ULL, 0x70000000ULL);
 298     memory_region_add_subregion(address_space_mem, 0x80000000ULL,
 299                                 &d->pci_hole);
 300
 301     h->bus = pci_register_bus(dev, "pci",
 302                               pci_unin_set_irq, pci_unin_map_irq,
 303                               pic,
 304                               &d->pci_mmio,
 305                               address_space_io,
 306                               PCI_DEVFN(11, 0), 4);
 307
 308     sysbus_mmio_map(s, 0, 0xf0800000);
 309     sysbus_mmio_map(s, 1, 0xf0c00000);
 310
 311     pci_create_simple(h->bus, 11 << 3, "u3-agp");
 312
 313     return h->bus;
 314 }
 315
 316 static int unin_main_pci_host_init(PCIDevice *d)
 317 {
 318     d->config[0x0C] = 0x08; // cache_line_size
 319     d->config[0x0D] = 0x10; // latency_timer
 320     d->config[0x34] = 0x00; // capabilities_pointer
 321     return 0;
 322 }
 323
 324 static int unin_agp_pci_host_init(PCIDevice *d)
 325 {
 326     d->config[0x0C] = 0x08; // cache_line_size
 327     d->config[0x0D] = 0x10; // latency_timer
 328     //    d->config[0x34] = 0x80; // capabilities_pointer
 329     return 0;
 330 }
 331
 332 static int u3_agp_pci_host_init(PCIDevice *d)
 333 {
 334     /* cache line size */
 335     d->config[0x0C] = 0x08;
 336     /* latency timer */
 337     d->config[0x0D] = 0x10;
 338     return 0;
 339 }
 340
 341 static int unin_internal_pci_host_init(PCIDevice *d)
 342 {
 343     d->config[0x0C] = 0x08; // cache_line_size
 344     d->config[0x0D] = 0x10; // latency_timer
 345     d->config[0x34] = 0x00; // capabilities_pointer
 346     return 0;
 347 }
 348
 349 static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
 350 {
 351     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 352
 353     k->init      = unin_main_pci_host_init;
 354     k->vendor_id = PCI_VENDOR_ID_APPLE;
 355     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
 356     k->revision  = 0x00;
 357     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 358 }
 359
 360 static const TypeInfo unin_main_pci_host_info = {
 361     .name = "uni-north-pci",
 362     .parent = TYPE_PCI_DEVICE,
 363     .instance_size = sizeof(PCIDevice),
 364     .class_init = unin_main_pci_host_class_init,
 365 };
 366
 367 static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
 368 {
 369     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 370
 371     k->init      = u3_agp_pci_host_init;
 372     k->vendor_id = PCI_VENDOR_ID_APPLE;
 373     k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
 374     k->revision  = 0x00;
 375     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 376 }
 377
 378 static const TypeInfo u3_agp_pci_host_info = {
 379     .name = "u3-agp",
 380     .parent = TYPE_PCI_DEVICE,
 381     .instance_size = sizeof(PCIDevice),
 382     .class_init = u3_agp_pci_host_class_init,
 383 };
 384
 385 static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
 386 {
 387     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 388
 389     k->init      = unin_agp_pci_host_init;
 390     k->vendor_id = PCI_VENDOR_ID_APPLE;
 391     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
 392     k->revision  = 0x00;
 393     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 394 }
 395
 396 static const TypeInfo unin_agp_pci_host_info = {
 397     .name = "uni-north-agp",
 398     .parent = TYPE_PCI_DEVICE,
 399     .instance_size = sizeof(PCIDevice),
 400     .class_init = unin_agp_pci_host_class_init,
 401 };
 402
 403 static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
 404 {
 405     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 406
 407     k->init      = unin_internal_pci_host_init;
 408     k->vendor_id = PCI_VENDOR_ID_APPLE;
 409     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
 410     k->revision  = 0x00;
 411     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 412 }
 413
 414 static const TypeInfo unin_internal_pci_host_info = {
 415     .name = "uni-north-internal-pci",
 416     .parent = TYPE_PCI_DEVICE,
 417     .instance_size = sizeof(PCIDevice),
 418     .class_init = unin_internal_pci_host_class_init,
 419 };
 420
 421 static void pci_unin_main_class_init(ObjectClass *klass, void *data)
 422 {
 423     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 424
 425     sbc->init = pci_unin_main_init_device;
 426 }
 427
 428 static const TypeInfo pci_unin_main_info = {
 429     .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
 430     .parent        = TYPE_PCI_HOST_BRIDGE,
 431     .instance_size = sizeof(UNINState),
 432     .class_init    = pci_unin_main_class_init,
 433 };
 434
 435 static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
 436 {
 437     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 438
 439     sbc->init = pci_u3_agp_init_device;
 440 }
 441
 442 static const TypeInfo pci_u3_agp_info = {
 443     .name          = TYPE_U3_AGP_HOST_BRIDGE,
 444     .parent        = TYPE_PCI_HOST_BRIDGE,
 445     .instance_size = sizeof(UNINState),
 446     .class_init    = pci_u3_agp_class_init,
 447 };
 448
 449 static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
 450 {
 451     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 452
 453     sbc->init = pci_unin_agp_init_device;
 454 }
 455
 456 static const TypeInfo pci_unin_agp_info = {
 457     .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
 458     .parent        = TYPE_PCI_HOST_BRIDGE,
 459     .instance_size = sizeof(UNINState),
 460     .class_init    = pci_unin_agp_class_init,
 461 };
 462
 463 static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
 464 {
 465     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 466
 467     sbc->init = pci_unin_internal_init_device;
 468 }
 469
 470 static const TypeInfo pci_unin_internal_info = {
 471     .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
 472     .parent        = TYPE_PCI_HOST_BRIDGE,
 473     .instance_size = sizeof(UNINState),
 474     .class_init    = pci_unin_internal_class_init,
 475 };
 476
 477 static void unin_register_types(void)
 478 {
 479     type_register_static(&unin_main_pci_host_info);
 480     type_register_static(&u3_agp_pci_host_info);
 481     type_register_static(&unin_agp_pci_host_info);
 482     type_register_static(&unin_internal_pci_host_info);
 483
 484     type_register_static(&pci_unin_main_info);
 485     type_register_static(&pci_u3_agp_info);
 486     type_register_static(&pci_unin_agp_info);
 487     type_register_static(&pci_unin_internal_info);
 488 }
 489
 490 type_init(unin_register_types)