2 * QEMU USB EHCI Emulation
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or(at your option) any later version.
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "hw/usb/hcd-ehci.h"
20 static const VMStateDescription vmstate_ehci_sysbus
= {
21 .name
= "ehci-sysbus",
23 .minimum_version_id
= 1,
24 .fields
= (VMStateField
[]) {
25 VMSTATE_STRUCT(ehci
, EHCISysBusState
, 2, vmstate_ehci
, EHCIState
),
30 static Property ehci_sysbus_properties
[] = {
31 DEFINE_PROP_UINT32("maxframes", EHCISysBusState
, ehci
.maxframes
, 128),
32 DEFINE_PROP_END_OF_LIST(),
35 static void usb_ehci_sysbus_realize(DeviceState
*dev
, Error
**errp
)
37 SysBusDevice
*d
= SYS_BUS_DEVICE(dev
);
38 EHCISysBusState
*i
= SYS_BUS_EHCI(dev
);
39 EHCIState
*s
= &i
->ehci
;
41 usb_ehci_realize(s
, dev
, errp
);
42 sysbus_init_irq(d
, &s
->irq
);
45 static void ehci_sysbus_init(Object
*obj
)
47 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
48 EHCISysBusState
*i
= SYS_BUS_EHCI(obj
);
49 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_GET_CLASS(obj
);
50 EHCIState
*s
= &i
->ehci
;
52 s
->capsbase
= sec
->capsbase
;
53 s
->opregbase
= sec
->opregbase
;
54 s
->portscbase
= sec
->portscbase
;
55 s
->portnr
= sec
->portnr
;
56 s
->as
= &address_space_memory
;
58 usb_ehci_init(s
, DEVICE(obj
));
59 sysbus_init_mmio(d
, &s
->mem
);
62 static void ehci_sysbus_class_init(ObjectClass
*klass
, void *data
)
64 DeviceClass
*dc
= DEVICE_CLASS(klass
);
65 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(klass
);
67 sec
->portscbase
= 0x44;
68 sec
->portnr
= NB_PORTS
;
70 dc
->realize
= usb_ehci_sysbus_realize
;
71 dc
->vmsd
= &vmstate_ehci_sysbus
;
72 dc
->props
= ehci_sysbus_properties
;
75 static const TypeInfo ehci_type_info
= {
76 .name
= TYPE_SYS_BUS_EHCI
,
77 .parent
= TYPE_SYS_BUS_DEVICE
,
78 .instance_size
= sizeof(EHCISysBusState
),
79 .instance_init
= ehci_sysbus_init
,
81 .class_init
= ehci_sysbus_class_init
,
82 .class_size
= sizeof(SysBusEHCIClass
),
85 static void ehci_xlnx_class_init(ObjectClass
*oc
, void *data
)
87 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
89 sec
->capsbase
= 0x100;
90 sec
->opregbase
= 0x140;
93 static const TypeInfo ehci_xlnx_type_info
= {
94 .name
= "xlnx,ps7-usb",
95 .parent
= TYPE_SYS_BUS_EHCI
,
96 .class_init
= ehci_xlnx_class_init
,
99 static void ehci_exynos4210_class_init(ObjectClass
*oc
, void *data
)
101 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
104 sec
->opregbase
= 0x10;
107 static const TypeInfo ehci_exynos4210_type_info
= {
108 .name
= TYPE_EXYNOS4210_EHCI
,
109 .parent
= TYPE_SYS_BUS_EHCI
,
110 .class_init
= ehci_exynos4210_class_init
,
113 static void ehci_tegra2_class_init(ObjectClass
*oc
, void *data
)
115 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
117 sec
->capsbase
= 0x100;
118 sec
->opregbase
= 0x140;
121 static const TypeInfo ehci_tegra2_type_info
= {
122 .name
= TYPE_TEGRA2_EHCI
,
123 .parent
= TYPE_SYS_BUS_EHCI
,
124 .class_init
= ehci_tegra2_class_init
,
128 * Faraday FUSBH200 USB 2.0 EHCI
133 * @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
134 * @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register
136 enum FUSBH200EHCIRegs
{
137 FUSBH200_REG_EOF_ASTR
= 0x34,
138 FUSBH200_REG_BMCSR
= 0x40,
141 static uint64_t fusbh200_ehci_read(void *opaque
, hwaddr addr
, unsigned size
)
143 EHCIState
*s
= opaque
;
144 hwaddr off
= s
->opregbase
+ s
->portscbase
+ 4 * s
->portnr
+ addr
;
147 case FUSBH200_REG_EOF_ASTR
:
149 case FUSBH200_REG_BMCSR
:
150 /* High-Speed, VBUS valid, interrupt level-high active */
151 return (2 << 9) | (1 << 8) | (1 << 3);
157 static void fusbh200_ehci_write(void *opaque
, hwaddr addr
, uint64_t val
,
162 static const MemoryRegionOps fusbh200_ehci_mmio_ops
= {
163 .read
= fusbh200_ehci_read
,
164 .write
= fusbh200_ehci_write
,
165 .valid
.min_access_size
= 4,
166 .valid
.max_access_size
= 4,
167 .endianness
= DEVICE_LITTLE_ENDIAN
,
170 static void fusbh200_ehci_init(Object
*obj
)
172 EHCISysBusState
*i
= SYS_BUS_EHCI(obj
);
173 FUSBH200EHCIState
*f
= FUSBH200_EHCI(obj
);
174 EHCIState
*s
= &i
->ehci
;
176 memory_region_init_io(&f
->mem_vendor
, &fusbh200_ehci_mmio_ops
, s
,
178 memory_region_add_subregion(&s
->mem
,
179 s
->opregbase
+ s
->portscbase
+ 4 * s
->portnr
,
183 static void fusbh200_ehci_class_init(ObjectClass
*oc
, void *data
)
185 SysBusEHCIClass
*sec
= SYS_BUS_EHCI_CLASS(oc
);
188 sec
->opregbase
= 0x10;
189 sec
->portscbase
= 0x20;
193 static const TypeInfo ehci_fusbh200_type_info
= {
194 .name
= TYPE_FUSBH200_EHCI
,
195 .parent
= TYPE_SYS_BUS_EHCI
,
196 .instance_size
= sizeof(FUSBH200EHCIState
),
197 .instance_init
= fusbh200_ehci_init
,
198 .class_init
= fusbh200_ehci_class_init
,
201 static void ehci_sysbus_register_types(void)
203 type_register_static(&ehci_type_info
);
204 type_register_static(&ehci_xlnx_type_info
);
205 type_register_static(&ehci_exynos4210_type_info
);
206 type_register_static(&ehci_tegra2_type_info
);
207 type_register_static(&ehci_fusbh200_type_info
);
210 type_init(ehci_sysbus_register_types
)