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ehci: keep the frame timer running in case the guest asked for frame list rollover...
[qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
6 *
7 * Red Hat Authors:
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
10 *
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
14 *
15 *
16 * This library is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU Lesser General Public
18 * License as published by the Free Software Foundation; either
19 * version 2 of the License, or(at your option) any later version.
20 *
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * Lesser General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
28 */
29
30 #include "hw/usb/hcd-ehci.h"
31
32 /* Capability Registers Base Address - section 2.2 */
33 #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
34 #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
35 #define HCSPARAMS 0x0004 /* 4-bytes, structural params */
36 #define HCCPARAMS 0x0008 /* 4-bytes, capability params */
37 #define EECP HCCPARAMS + 1
38 #define HCSPPORTROUTE1 0x000c
39 #define HCSPPORTROUTE2 0x0010
40
41 #define USBCMD 0x0000
42 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
43 #define USBCMD_HCRESET (1 << 1) // HC Reset
44 #define USBCMD_FLS (3 << 2) // Frame List Size
45 #define USBCMD_FLS_SH 2 // Frame List Size Shift
46 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
47 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
48 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
49 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
50 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
51 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
52 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
53 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
54
55 #define USBSTS 0x0004
56 #define USBSTS_RO_MASK 0x0000003f
57 #define USBSTS_INT (1 << 0) // USB Interrupt
58 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
59 #define USBSTS_PCD (1 << 2) // Port Change Detect
60 #define USBSTS_FLR (1 << 3) // Frame List Rollover
61 #define USBSTS_HSE (1 << 4) // Host System Error
62 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
63 #define USBSTS_HALT (1 << 12) // HC Halted
64 #define USBSTS_REC (1 << 13) // Reclamation
65 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
66 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
67
68 /*
69 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
70 * so no need to redefine here.
71 */
72 #define USBINTR 0x0008
73 #define USBINTR_MASK 0x0000003f
74
75 #define FRINDEX 0x000c
76 #define CTRLDSSEGMENT 0x0010
77 #define PERIODICLISTBASE 0x0014
78 #define ASYNCLISTADDR 0x0018
79 #define ASYNCLISTADDR_MASK 0xffffffe0
80
81 #define CONFIGFLAG 0x0040
82
83 /*
84 * Bits that are reserved or are read-only are masked out of values
85 * written to us by software
86 */
87 #define PORTSC_RO_MASK 0x007001c0
88 #define PORTSC_RWC_MASK 0x0000002a
89 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
90 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
91 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
92 #define PORTSC_PTC (15 << 16) // Port Test Control
93 #define PORTSC_PTC_SH 16 // Port Test Control shift
94 #define PORTSC_PIC (3 << 14) // Port Indicator Control
95 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
96 #define PORTSC_POWNER (1 << 13) // Port Owner
97 #define PORTSC_PPOWER (1 << 12) // Port Power
98 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
99 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
100 #define PORTSC_PRESET (1 << 8) // Port Reset
101 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
102 #define PORTSC_FPRES (1 << 6) // Force Port Resume
103 #define PORTSC_OCC (1 << 5) // Over Current Change
104 #define PORTSC_OCA (1 << 4) // Over Current Active
105 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
106 #define PORTSC_PED (1 << 2) // Port Enable/Disable
107 #define PORTSC_CSC (1 << 1) // Connect Status Change
108 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
109
110 #define FRAME_TIMER_FREQ 1000
111 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
112
113 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
114 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
115 #define MAX_QH 100 // Max allowable queue heads in a chain
116 #define MIN_FR_PER_TICK 3 // Min frames to process when catching up
117
118 /* Internal periodic / asynchronous schedule state machine states
119 */
120 typedef enum {
121 EST_INACTIVE = 1000,
122 EST_ACTIVE,
123 EST_EXECUTING,
124 EST_SLEEPING,
125 /* The following states are internal to the state machine function
126 */
127 EST_WAITLISTHEAD,
128 EST_FETCHENTRY,
129 EST_FETCHQH,
130 EST_FETCHITD,
131 EST_FETCHSITD,
132 EST_ADVANCEQUEUE,
133 EST_FETCHQTD,
134 EST_EXECUTE,
135 EST_WRITEBACK,
136 EST_HORIZONTALQH
137 } EHCI_STATES;
138
139 /* macros for accessing fields within next link pointer entry */
140 #define NLPTR_GET(x) ((x) & 0xffffffe0)
141 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
142 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
143
144 /* link pointer types */
145 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
146 #define NLPTR_TYPE_QH 1 // queue head
147 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
148 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
149
150 #define SET_LAST_RUN_CLOCK(s) \
151 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
152
153 /* nifty macros from Arnon's EHCI version */
154 #define get_field(data, field) \
155 (((data) & field##_MASK) >> field##_SH)
156
157 #define set_field(data, newval, field) do { \
158 uint32_t val = *data; \
159 val &= ~ field##_MASK; \
160 val |= ((newval) << field##_SH) & field##_MASK; \
161 *data = val; \
162 } while(0)
163
164 static const char *ehci_state_names[] = {
165 [EST_INACTIVE] = "INACTIVE",
166 [EST_ACTIVE] = "ACTIVE",
167 [EST_EXECUTING] = "EXECUTING",
168 [EST_SLEEPING] = "SLEEPING",
169 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
170 [EST_FETCHENTRY] = "FETCH ENTRY",
171 [EST_FETCHQH] = "FETCH QH",
172 [EST_FETCHITD] = "FETCH ITD",
173 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
174 [EST_FETCHQTD] = "FETCH QTD",
175 [EST_EXECUTE] = "EXECUTE",
176 [EST_WRITEBACK] = "WRITEBACK",
177 [EST_HORIZONTALQH] = "HORIZONTALQH",
178 };
179
180 static const char *ehci_mmio_names[] = {
181 [USBCMD] = "USBCMD",
182 [USBSTS] = "USBSTS",
183 [USBINTR] = "USBINTR",
184 [FRINDEX] = "FRINDEX",
185 [PERIODICLISTBASE] = "P-LIST BASE",
186 [ASYNCLISTADDR] = "A-LIST ADDR",
187 [CONFIGFLAG] = "CONFIGFLAG",
188 };
189
190 static int ehci_state_executing(EHCIQueue *q);
191 static int ehci_state_writeback(EHCIQueue *q);
192 static int ehci_state_advqueue(EHCIQueue *q);
193 static int ehci_fill_queue(EHCIPacket *p);
194
195 static const char *nr2str(const char **n, size_t len, uint32_t nr)
196 {
197 if (nr < len && n[nr] != NULL) {
198 return n[nr];
199 } else {
200 return "unknown";
201 }
202 }
203
204 static const char *state2str(uint32_t state)
205 {
206 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
207 }
208
209 static const char *addr2str(hwaddr addr)
210 {
211 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
212 }
213
214 static void ehci_trace_usbsts(uint32_t mask, int state)
215 {
216 /* interrupts */
217 if (mask & USBSTS_INT) {
218 trace_usb_ehci_usbsts("INT", state);
219 }
220 if (mask & USBSTS_ERRINT) {
221 trace_usb_ehci_usbsts("ERRINT", state);
222 }
223 if (mask & USBSTS_PCD) {
224 trace_usb_ehci_usbsts("PCD", state);
225 }
226 if (mask & USBSTS_FLR) {
227 trace_usb_ehci_usbsts("FLR", state);
228 }
229 if (mask & USBSTS_HSE) {
230 trace_usb_ehci_usbsts("HSE", state);
231 }
232 if (mask & USBSTS_IAA) {
233 trace_usb_ehci_usbsts("IAA", state);
234 }
235
236 /* status */
237 if (mask & USBSTS_HALT) {
238 trace_usb_ehci_usbsts("HALT", state);
239 }
240 if (mask & USBSTS_REC) {
241 trace_usb_ehci_usbsts("REC", state);
242 }
243 if (mask & USBSTS_PSS) {
244 trace_usb_ehci_usbsts("PSS", state);
245 }
246 if (mask & USBSTS_ASS) {
247 trace_usb_ehci_usbsts("ASS", state);
248 }
249 }
250
251 static inline void ehci_set_usbsts(EHCIState *s, int mask)
252 {
253 if ((s->usbsts & mask) == mask) {
254 return;
255 }
256 ehci_trace_usbsts(mask, 1);
257 s->usbsts |= mask;
258 }
259
260 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
261 {
262 if ((s->usbsts & mask) == 0) {
263 return;
264 }
265 ehci_trace_usbsts(mask, 0);
266 s->usbsts &= ~mask;
267 }
268
269 /* update irq line */
270 static inline void ehci_update_irq(EHCIState *s)
271 {
272 int level = 0;
273
274 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
275 level = 1;
276 }
277
278 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr);
279 qemu_set_irq(s->irq, level);
280 }
281
282 /* flag interrupt condition */
283 static inline void ehci_raise_irq(EHCIState *s, int intr)
284 {
285 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
286 s->usbsts |= intr;
287 ehci_update_irq(s);
288 } else {
289 s->usbsts_pending |= intr;
290 }
291 }
292
293 /*
294 * Commit pending interrupts (added via ehci_raise_irq),
295 * at the rate allowed by "Interrupt Threshold Control".
296 */
297 static inline void ehci_commit_irq(EHCIState *s)
298 {
299 uint32_t itc;
300
301 if (!s->usbsts_pending) {
302 return;
303 }
304 if (s->usbsts_frindex > s->frindex) {
305 return;
306 }
307
308 itc = (s->usbcmd >> 16) & 0xff;
309 s->usbsts |= s->usbsts_pending;
310 s->usbsts_pending = 0;
311 s->usbsts_frindex = s->frindex + itc;
312 ehci_update_irq(s);
313 }
314
315 static void ehci_update_halt(EHCIState *s)
316 {
317 if (s->usbcmd & USBCMD_RUNSTOP) {
318 ehci_clear_usbsts(s, USBSTS_HALT);
319 } else {
320 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
321 ehci_set_usbsts(s, USBSTS_HALT);
322 }
323 }
324 }
325
326 static void ehci_set_state(EHCIState *s, int async, int state)
327 {
328 if (async) {
329 trace_usb_ehci_state("async", state2str(state));
330 s->astate = state;
331 if (s->astate == EST_INACTIVE) {
332 ehci_clear_usbsts(s, USBSTS_ASS);
333 ehci_update_halt(s);
334 } else {
335 ehci_set_usbsts(s, USBSTS_ASS);
336 }
337 } else {
338 trace_usb_ehci_state("periodic", state2str(state));
339 s->pstate = state;
340 if (s->pstate == EST_INACTIVE) {
341 ehci_clear_usbsts(s, USBSTS_PSS);
342 ehci_update_halt(s);
343 } else {
344 ehci_set_usbsts(s, USBSTS_PSS);
345 }
346 }
347 }
348
349 static int ehci_get_state(EHCIState *s, int async)
350 {
351 return async ? s->astate : s->pstate;
352 }
353
354 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
355 {
356 if (async) {
357 s->a_fetch_addr = addr;
358 } else {
359 s->p_fetch_addr = addr;
360 }
361 }
362
363 static int ehci_get_fetch_addr(EHCIState *s, int async)
364 {
365 return async ? s->a_fetch_addr : s->p_fetch_addr;
366 }
367
368 static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
369 {
370 /* need three here due to argument count limits */
371 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
372 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
373 trace_usb_ehci_qh_fields(addr,
374 get_field(qh->epchar, QH_EPCHAR_RL),
375 get_field(qh->epchar, QH_EPCHAR_MPLEN),
376 get_field(qh->epchar, QH_EPCHAR_EPS),
377 get_field(qh->epchar, QH_EPCHAR_EP),
378 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
379 trace_usb_ehci_qh_bits(addr,
380 (bool)(qh->epchar & QH_EPCHAR_C),
381 (bool)(qh->epchar & QH_EPCHAR_H),
382 (bool)(qh->epchar & QH_EPCHAR_DTC),
383 (bool)(qh->epchar & QH_EPCHAR_I));
384 }
385
386 static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
387 {
388 /* need three here due to argument count limits */
389 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
390 trace_usb_ehci_qtd_fields(addr,
391 get_field(qtd->token, QTD_TOKEN_TBYTES),
392 get_field(qtd->token, QTD_TOKEN_CPAGE),
393 get_field(qtd->token, QTD_TOKEN_CERR),
394 get_field(qtd->token, QTD_TOKEN_PID));
395 trace_usb_ehci_qtd_bits(addr,
396 (bool)(qtd->token & QTD_TOKEN_IOC),
397 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
398 (bool)(qtd->token & QTD_TOKEN_HALT),
399 (bool)(qtd->token & QTD_TOKEN_BABBLE),
400 (bool)(qtd->token & QTD_TOKEN_XACTERR));
401 }
402
403 static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
404 {
405 trace_usb_ehci_itd(addr, itd->next,
406 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
407 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
408 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
409 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
410 }
411
412 static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
413 EHCIsitd *sitd)
414 {
415 trace_usb_ehci_sitd(addr, sitd->next,
416 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
417 }
418
419 static void ehci_trace_guest_bug(EHCIState *s, const char *message)
420 {
421 trace_usb_ehci_guest_bug(message);
422 fprintf(stderr, "ehci warning: %s\n", message);
423 }
424
425 static inline bool ehci_enabled(EHCIState *s)
426 {
427 return s->usbcmd & USBCMD_RUNSTOP;
428 }
429
430 static inline bool ehci_async_enabled(EHCIState *s)
431 {
432 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
433 }
434
435 static inline bool ehci_periodic_enabled(EHCIState *s)
436 {
437 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
438 }
439
440 /* packet management */
441
442 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
443 {
444 EHCIPacket *p;
445
446 p = g_new0(EHCIPacket, 1);
447 p->queue = q;
448 usb_packet_init(&p->packet);
449 QTAILQ_INSERT_TAIL(&q->packets, p, next);
450 trace_usb_ehci_packet_action(p->queue, p, "alloc");
451 return p;
452 }
453
454 static void ehci_free_packet(EHCIPacket *p)
455 {
456 if (p->async == EHCI_ASYNC_FINISHED) {
457 EHCIQueue *q = p->queue;
458 int state = ehci_get_state(q->ehci, q->async);
459 /* This is a normal, but rare condition (cancel racing completion) */
460 fprintf(stderr, "EHCI: Warning packet completed but not processed\n");
461 ehci_state_executing(q);
462 ehci_state_writeback(q);
463 if (!(q->qh.token & QTD_TOKEN_HALT)) {
464 ehci_state_advqueue(q);
465 }
466 ehci_set_state(q->ehci, q->async, state);
467 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
468 return;
469 }
470 trace_usb_ehci_packet_action(p->queue, p, "free");
471 if (p->async == EHCI_ASYNC_INITIALIZED) {
472 usb_packet_unmap(&p->packet, &p->sgl);
473 qemu_sglist_destroy(&p->sgl);
474 }
475 if (p->async == EHCI_ASYNC_INFLIGHT) {
476 usb_cancel_packet(&p->packet);
477 usb_packet_unmap(&p->packet, &p->sgl);
478 qemu_sglist_destroy(&p->sgl);
479 }
480 QTAILQ_REMOVE(&p->queue->packets, p, next);
481 usb_packet_cleanup(&p->packet);
482 g_free(p);
483 }
484
485 /* queue management */
486
487 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
488 {
489 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
490 EHCIQueue *q;
491
492 q = g_malloc0(sizeof(*q));
493 q->ehci = ehci;
494 q->qhaddr = addr;
495 q->async = async;
496 QTAILQ_INIT(&q->packets);
497 QTAILQ_INSERT_HEAD(head, q, next);
498 trace_usb_ehci_queue_action(q, "alloc");
499 return q;
500 }
501
502 static int ehci_cancel_queue(EHCIQueue *q)
503 {
504 EHCIPacket *p;
505 int packets = 0;
506
507 p = QTAILQ_FIRST(&q->packets);
508 if (p == NULL) {
509 return 0;
510 }
511
512 trace_usb_ehci_queue_action(q, "cancel");
513 do {
514 ehci_free_packet(p);
515 packets++;
516 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL);
517 return packets;
518 }
519
520 static int ehci_reset_queue(EHCIQueue *q)
521 {
522 int packets;
523
524 trace_usb_ehci_queue_action(q, "reset");
525 packets = ehci_cancel_queue(q);
526 q->dev = NULL;
527 q->qtdaddr = 0;
528 return packets;
529 }
530
531 static void ehci_free_queue(EHCIQueue *q, const char *warn)
532 {
533 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
534 int cancelled;
535
536 trace_usb_ehci_queue_action(q, "free");
537 cancelled = ehci_cancel_queue(q);
538 if (warn && cancelled > 0) {
539 ehci_trace_guest_bug(q->ehci, warn);
540 }
541 QTAILQ_REMOVE(head, q, next);
542 g_free(q);
543 }
544
545 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
546 int async)
547 {
548 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
549 EHCIQueue *q;
550
551 QTAILQ_FOREACH(q, head, next) {
552 if (addr == q->qhaddr) {
553 return q;
554 }
555 }
556 return NULL;
557 }
558
559 static void ehci_queues_rip_unused(EHCIState *ehci, int async)
560 {
561 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
562 const char *warn = async ? "guest unlinked busy QH" : NULL;
563 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
564 EHCIQueue *q, *tmp;
565
566 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
567 if (q->seen) {
568 q->seen = 0;
569 q->ts = ehci->last_run_ns;
570 continue;
571 }
572 if (ehci->last_run_ns < q->ts + maxage) {
573 continue;
574 }
575 ehci_free_queue(q, warn);
576 }
577 }
578
579 static void ehci_queues_rip_unseen(EHCIState *ehci, int async)
580 {
581 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
582 EHCIQueue *q, *tmp;
583
584 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
585 if (!q->seen) {
586 ehci_free_queue(q, NULL);
587 }
588 }
589 }
590
591 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
592 {
593 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
594 EHCIQueue *q, *tmp;
595
596 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
597 if (q->dev != dev) {
598 continue;
599 }
600 ehci_free_queue(q, NULL);
601 }
602 }
603
604 static void ehci_queues_rip_all(EHCIState *ehci, int async)
605 {
606 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
607 const char *warn = async ? "guest stopped busy async schedule" : NULL;
608 EHCIQueue *q, *tmp;
609
610 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
611 ehci_free_queue(q, warn);
612 }
613 }
614
615 /* Attach or detach a device on root hub */
616
617 static void ehci_attach(USBPort *port)
618 {
619 EHCIState *s = port->opaque;
620 uint32_t *portsc = &s->portsc[port->index];
621 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
622
623 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
624
625 if (*portsc & PORTSC_POWNER) {
626 USBPort *companion = s->companion_ports[port->index];
627 companion->dev = port->dev;
628 companion->ops->attach(companion);
629 return;
630 }
631
632 *portsc |= PORTSC_CONNECT;
633 *portsc |= PORTSC_CSC;
634
635 ehci_raise_irq(s, USBSTS_PCD);
636 ehci_commit_irq(s);
637 }
638
639 static void ehci_detach(USBPort *port)
640 {
641 EHCIState *s = port->opaque;
642 uint32_t *portsc = &s->portsc[port->index];
643 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
644
645 trace_usb_ehci_port_detach(port->index, owner);
646
647 if (*portsc & PORTSC_POWNER) {
648 USBPort *companion = s->companion_ports[port->index];
649 companion->ops->detach(companion);
650 companion->dev = NULL;
651 /*
652 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
653 * the port ownership is returned immediately to the EHCI controller."
654 */
655 *portsc &= ~PORTSC_POWNER;
656 return;
657 }
658
659 ehci_queues_rip_device(s, port->dev, 0);
660 ehci_queues_rip_device(s, port->dev, 1);
661
662 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
663 *portsc |= PORTSC_CSC;
664
665 ehci_raise_irq(s, USBSTS_PCD);
666 ehci_commit_irq(s);
667 }
668
669 static void ehci_child_detach(USBPort *port, USBDevice *child)
670 {
671 EHCIState *s = port->opaque;
672 uint32_t portsc = s->portsc[port->index];
673
674 if (portsc & PORTSC_POWNER) {
675 USBPort *companion = s->companion_ports[port->index];
676 companion->ops->child_detach(companion, child);
677 return;
678 }
679
680 ehci_queues_rip_device(s, child, 0);
681 ehci_queues_rip_device(s, child, 1);
682 }
683
684 static void ehci_wakeup(USBPort *port)
685 {
686 EHCIState *s = port->opaque;
687 uint32_t portsc = s->portsc[port->index];
688
689 if (portsc & PORTSC_POWNER) {
690 USBPort *companion = s->companion_ports[port->index];
691 if (companion->ops->wakeup) {
692 companion->ops->wakeup(companion);
693 }
694 return;
695 }
696
697 qemu_bh_schedule(s->async_bh);
698 }
699
700 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
701 uint32_t portcount, uint32_t firstport)
702 {
703 EHCIState *s = container_of(bus, EHCIState, bus);
704 uint32_t i;
705
706 if (firstport + portcount > NB_PORTS) {
707 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
708 "firstport on masterbus");
709 error_printf_unless_qmp(
710 "firstport value of %u makes companion take ports %u - %u, which "
711 "is outside of the valid range of 0 - %u\n", firstport, firstport,
712 firstport + portcount - 1, NB_PORTS - 1);
713 return -1;
714 }
715
716 for (i = 0; i < portcount; i++) {
717 if (s->companion_ports[firstport + i]) {
718 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
719 "an USB masterbus");
720 error_printf_unless_qmp(
721 "port %u on masterbus %s already has a companion assigned\n",
722 firstport + i, bus->qbus.name);
723 return -1;
724 }
725 }
726
727 for (i = 0; i < portcount; i++) {
728 s->companion_ports[firstport + i] = ports[i];
729 s->ports[firstport + i].speedmask |=
730 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
731 /* Ensure devs attached before the initial reset go to the companion */
732 s->portsc[firstport + i] = PORTSC_POWNER;
733 }
734
735 s->companion_count++;
736 s->caps[0x05] = (s->companion_count << 4) | portcount;
737
738 return 0;
739 }
740
741 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
742 {
743 USBDevice *dev;
744 USBPort *port;
745 int i;
746
747 for (i = 0; i < NB_PORTS; i++) {
748 port = &ehci->ports[i];
749 if (!(ehci->portsc[i] & PORTSC_PED)) {
750 DPRINTF("Port %d not enabled\n", i);
751 continue;
752 }
753 dev = usb_find_device(port, addr);
754 if (dev != NULL) {
755 return dev;
756 }
757 }
758 return NULL;
759 }
760
761 /* 4.1 host controller initialization */
762 static void ehci_reset(void *opaque)
763 {
764 EHCIState *s = opaque;
765 int i;
766 USBDevice *devs[NB_PORTS];
767
768 trace_usb_ehci_reset();
769
770 /*
771 * Do the detach before touching portsc, so that it correctly gets send to
772 * us or to our companion based on PORTSC_POWNER before the reset.
773 */
774 for(i = 0; i < NB_PORTS; i++) {
775 devs[i] = s->ports[i].dev;
776 if (devs[i] && devs[i]->attached) {
777 usb_detach(&s->ports[i]);
778 }
779 }
780
781 memset(&s->opreg, 0x00, sizeof(s->opreg));
782 memset(&s->portsc, 0x00, sizeof(s->portsc));
783
784 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
785 s->usbsts = USBSTS_HALT;
786 s->usbsts_pending = 0;
787 s->usbsts_frindex = 0;
788
789 s->astate = EST_INACTIVE;
790 s->pstate = EST_INACTIVE;
791
792 for(i = 0; i < NB_PORTS; i++) {
793 if (s->companion_ports[i]) {
794 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
795 } else {
796 s->portsc[i] = PORTSC_PPOWER;
797 }
798 if (devs[i] && devs[i]->attached) {
799 usb_attach(&s->ports[i]);
800 usb_device_reset(devs[i]);
801 }
802 }
803 ehci_queues_rip_all(s, 0);
804 ehci_queues_rip_all(s, 1);
805 qemu_del_timer(s->frame_timer);
806 qemu_bh_cancel(s->async_bh);
807 }
808
809 static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
810 unsigned size)
811 {
812 EHCIState *s = ptr;
813 return s->caps[addr];
814 }
815
816 static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
817 unsigned size)
818 {
819 EHCIState *s = ptr;
820 uint32_t val;
821
822 val = s->opreg[addr >> 2];
823 trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val);
824 return val;
825 }
826
827 static uint64_t ehci_port_read(void *ptr, hwaddr addr,
828 unsigned size)
829 {
830 EHCIState *s = ptr;
831 uint32_t val;
832
833 val = s->portsc[addr >> 2];
834 trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val);
835 return val;
836 }
837
838 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
839 {
840 USBDevice *dev = s->ports[port].dev;
841 uint32_t *portsc = &s->portsc[port];
842 uint32_t orig;
843
844 if (s->companion_ports[port] == NULL)
845 return;
846
847 owner = owner & PORTSC_POWNER;
848 orig = *portsc & PORTSC_POWNER;
849
850 if (!(owner ^ orig)) {
851 return;
852 }
853
854 if (dev && dev->attached) {
855 usb_detach(&s->ports[port]);
856 }
857
858 *portsc &= ~PORTSC_POWNER;
859 *portsc |= owner;
860
861 if (dev && dev->attached) {
862 usb_attach(&s->ports[port]);
863 }
864 }
865
866 static void ehci_port_write(void *ptr, hwaddr addr,
867 uint64_t val, unsigned size)
868 {
869 EHCIState *s = ptr;
870 int port = addr >> 2;
871 uint32_t *portsc = &s->portsc[port];
872 uint32_t old = *portsc;
873 USBDevice *dev = s->ports[port].dev;
874
875 trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val);
876
877 /* Clear rwc bits */
878 *portsc &= ~(val & PORTSC_RWC_MASK);
879 /* The guest may clear, but not set the PED bit */
880 *portsc &= val | ~PORTSC_PED;
881 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
882 handle_port_owner_write(s, port, val);
883 /* And finally apply RO_MASK */
884 val &= PORTSC_RO_MASK;
885
886 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
887 trace_usb_ehci_port_reset(port, 1);
888 }
889
890 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
891 trace_usb_ehci_port_reset(port, 0);
892 if (dev && dev->attached) {
893 usb_port_reset(&s->ports[port]);
894 *portsc &= ~PORTSC_CSC;
895 }
896
897 /*
898 * Table 2.16 Set the enable bit(and enable bit change) to indicate
899 * to SW that this port has a high speed device attached
900 */
901 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
902 val |= PORTSC_PED;
903 }
904 }
905
906 *portsc &= ~PORTSC_RO_MASK;
907 *portsc |= val;
908 trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
909 }
910
911 static void ehci_opreg_write(void *ptr, hwaddr addr,
912 uint64_t val, unsigned size)
913 {
914 EHCIState *s = ptr;
915 uint32_t *mmio = s->opreg + (addr >> 2);
916 uint32_t old = *mmio;
917 int i;
918
919 trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val);
920
921 switch (addr) {
922 case USBCMD:
923 if (val & USBCMD_HCRESET) {
924 ehci_reset(s);
925 val = s->usbcmd;
926 break;
927 }
928
929 /* not supporting dynamic frame list size at the moment */
930 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
931 fprintf(stderr, "attempt to set frame list size -- value %d\n",
932 (int)val & USBCMD_FLS);
933 val &= ~USBCMD_FLS;
934 }
935
936 if (val & USBCMD_IAAD) {
937 /*
938 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
939 * trigger and re-use a qh without us seeing the unlink.
940 */
941 s->async_stepdown = 0;
942 qemu_bh_schedule(s->async_bh);
943 trace_usb_ehci_doorbell_ring();
944 }
945
946 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
947 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
948 if (s->pstate == EST_INACTIVE) {
949 SET_LAST_RUN_CLOCK(s);
950 }
951 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
952 ehci_update_halt(s);
953 s->async_stepdown = 0;
954 qemu_bh_schedule(s->async_bh);
955 }
956 break;
957
958 case USBSTS:
959 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
960 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
961 val = s->usbsts;
962 ehci_update_irq(s);
963 break;
964
965 case USBINTR:
966 val &= USBINTR_MASK;
967 if (ehci_enabled(s) && (USBSTS_FLR & val)) {
968 qemu_bh_schedule(s->async_bh);
969 }
970 break;
971
972 case FRINDEX:
973 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
974 break;
975
976 case CONFIGFLAG:
977 val &= 0x1;
978 if (val) {
979 for(i = 0; i < NB_PORTS; i++)
980 handle_port_owner_write(s, i, 0);
981 }
982 break;
983
984 case PERIODICLISTBASE:
985 if (ehci_periodic_enabled(s)) {
986 fprintf(stderr,
987 "ehci: PERIODIC list base register set while periodic schedule\n"
988 " is enabled and HC is enabled\n");
989 }
990 break;
991
992 case ASYNCLISTADDR:
993 if (ehci_async_enabled(s)) {
994 fprintf(stderr,
995 "ehci: ASYNC list address register set while async schedule\n"
996 " is enabled and HC is enabled\n");
997 }
998 break;
999 }
1000
1001 *mmio = val;
1002 trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr),
1003 *mmio, old);
1004 }
1005
1006
1007 // TODO : Put in common header file, duplication from usb-ohci.c
1008
1009 /* Get an array of dwords from main memory */
1010 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1011 uint32_t *buf, int num)
1012 {
1013 int i;
1014
1015 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1016 dma_memory_read(ehci->dma, addr, buf, sizeof(*buf));
1017 *buf = le32_to_cpu(*buf);
1018 }
1019
1020 return 1;
1021 }
1022
1023 /* Put an array of dwords in to main memory */
1024 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1025 uint32_t *buf, int num)
1026 {
1027 int i;
1028
1029 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1030 uint32_t tmp = cpu_to_le32(*buf);
1031 dma_memory_write(ehci->dma, addr, &tmp, sizeof(tmp));
1032 }
1033
1034 return 1;
1035 }
1036
1037 /*
1038 * Write the qh back to guest physical memory. This step isn't
1039 * in the EHCI spec but we need to do it since we don't share
1040 * physical memory with our guest VM.
1041 *
1042 * The first three dwords are read-only for the EHCI, so skip them
1043 * when writing back the qh.
1044 */
1045 static void ehci_flush_qh(EHCIQueue *q)
1046 {
1047 uint32_t *qh = (uint32_t *) &q->qh;
1048 uint32_t dwords = sizeof(EHCIqh) >> 2;
1049 uint32_t addr = NLPTR_GET(q->qhaddr);
1050
1051 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1052 }
1053
1054 // 4.10.2
1055
1056 static int ehci_qh_do_overlay(EHCIQueue *q)
1057 {
1058 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1059 int i;
1060 int dtoggle;
1061 int ping;
1062 int eps;
1063 int reload;
1064
1065 assert(p != NULL);
1066 assert(p->qtdaddr == q->qtdaddr);
1067
1068 // remember values in fields to preserve in qh after overlay
1069
1070 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1071 ping = q->qh.token & QTD_TOKEN_PING;
1072
1073 q->qh.current_qtd = p->qtdaddr;
1074 q->qh.next_qtd = p->qtd.next;
1075 q->qh.altnext_qtd = p->qtd.altnext;
1076 q->qh.token = p->qtd.token;
1077
1078
1079 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1080 if (eps == EHCI_QH_EPS_HIGH) {
1081 q->qh.token &= ~QTD_TOKEN_PING;
1082 q->qh.token |= ping;
1083 }
1084
1085 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1086 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1087
1088 for (i = 0; i < 5; i++) {
1089 q->qh.bufptr[i] = p->qtd.bufptr[i];
1090 }
1091
1092 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1093 // preserve QH DT bit
1094 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1095 q->qh.token |= dtoggle;
1096 }
1097
1098 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1099 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1100
1101 ehci_flush_qh(q);
1102
1103 return 0;
1104 }
1105
1106 static int ehci_init_transfer(EHCIPacket *p)
1107 {
1108 uint32_t cpage, offset, bytes, plen;
1109 dma_addr_t page;
1110
1111 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1112 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1113 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1114 qemu_sglist_init(&p->sgl, 5, p->queue->ehci->dma);
1115
1116 while (bytes > 0) {
1117 if (cpage > 4) {
1118 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1119 return -1;
1120 }
1121
1122 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1123 page += offset;
1124 plen = bytes;
1125 if (plen > 4096 - offset) {
1126 plen = 4096 - offset;
1127 offset = 0;
1128 cpage++;
1129 }
1130
1131 qemu_sglist_add(&p->sgl, page, plen);
1132 bytes -= plen;
1133 }
1134 return 0;
1135 }
1136
1137 static void ehci_finish_transfer(EHCIQueue *q, int len)
1138 {
1139 uint32_t cpage, offset;
1140
1141 if (len > 0) {
1142 /* update cpage & offset */
1143 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1144 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1145
1146 offset += len;
1147 cpage += offset >> QTD_BUFPTR_SH;
1148 offset &= ~QTD_BUFPTR_MASK;
1149
1150 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1151 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1152 q->qh.bufptr[0] |= offset;
1153 }
1154 }
1155
1156 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1157 {
1158 EHCIPacket *p;
1159 EHCIState *s = port->opaque;
1160 uint32_t portsc = s->portsc[port->index];
1161
1162 if (portsc & PORTSC_POWNER) {
1163 USBPort *companion = s->companion_ports[port->index];
1164 companion->ops->complete(companion, packet);
1165 return;
1166 }
1167
1168 p = container_of(packet, EHCIPacket, packet);
1169 assert(p->async == EHCI_ASYNC_INFLIGHT);
1170
1171 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
1172 trace_usb_ehci_packet_action(p->queue, p, "remove");
1173 ehci_free_packet(p);
1174 return;
1175 }
1176
1177 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1178 p->async = EHCI_ASYNC_FINISHED;
1179
1180 if (p->queue->async) {
1181 qemu_bh_schedule(p->queue->ehci->async_bh);
1182 }
1183 }
1184
1185 static void ehci_execute_complete(EHCIQueue *q)
1186 {
1187 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1188 uint32_t tbytes;
1189
1190 assert(p != NULL);
1191 assert(p->qtdaddr == q->qtdaddr);
1192 assert(p->async == EHCI_ASYNC_INITIALIZED ||
1193 p->async == EHCI_ASYNC_FINISHED);
1194
1195 DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, "
1196 "status %d, actual_length %d\n",
1197 q->qhaddr, q->qh.next, q->qtdaddr,
1198 p->packet.status, p->packet.actual_length);
1199
1200 switch (p->packet.status) {
1201 case USB_RET_SUCCESS:
1202 break;
1203 case USB_RET_IOERROR:
1204 case USB_RET_NODEV:
1205 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1206 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1207 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1208 break;
1209 case USB_RET_STALL:
1210 q->qh.token |= QTD_TOKEN_HALT;
1211 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1212 break;
1213 case USB_RET_NAK:
1214 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1215 return; /* We're not done yet with this transaction */
1216 case USB_RET_BABBLE:
1217 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1218 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1219 break;
1220 default:
1221 /* should not be triggerable */
1222 fprintf(stderr, "USB invalid response %d\n", p->packet.status);
1223 assert(0);
1224 break;
1225 }
1226
1227 /* TODO check 4.12 for splits */
1228 tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1229 if (tbytes && p->pid == USB_TOKEN_IN) {
1230 tbytes -= p->packet.actual_length;
1231 if (tbytes) {
1232 /* 4.15.1.2 must raise int on a short input packet */
1233 ehci_raise_irq(q->ehci, USBSTS_INT);
1234 }
1235 } else {
1236 tbytes = 0;
1237 }
1238 DPRINTF("updating tbytes to %d\n", tbytes);
1239 set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES);
1240
1241 ehci_finish_transfer(q, p->packet.actual_length);
1242 usb_packet_unmap(&p->packet, &p->sgl);
1243 qemu_sglist_destroy(&p->sgl);
1244 p->async = EHCI_ASYNC_NONE;
1245
1246 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1247 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1248
1249 if (q->qh.token & QTD_TOKEN_IOC) {
1250 ehci_raise_irq(q->ehci, USBSTS_INT);
1251 if (q->async) {
1252 q->ehci->int_req_by_async = true;
1253 }
1254 }
1255 }
1256
1257 /* 4.10.3 returns "again" */
1258 static int ehci_execute(EHCIPacket *p, const char *action)
1259 {
1260 USBEndpoint *ep;
1261 int endp;
1262 bool spd;
1263
1264 assert(p->async == EHCI_ASYNC_NONE ||
1265 p->async == EHCI_ASYNC_INITIALIZED);
1266
1267 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1268 fprintf(stderr, "Attempting to execute inactive qtd\n");
1269 return -1;
1270 }
1271
1272 if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) {
1273 ehci_trace_guest_bug(p->queue->ehci,
1274 "guest requested more bytes than allowed");
1275 return -1;
1276 }
1277
1278 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1279 switch (p->pid) {
1280 case 0:
1281 p->pid = USB_TOKEN_OUT;
1282 break;
1283 case 1:
1284 p->pid = USB_TOKEN_IN;
1285 break;
1286 case 2:
1287 p->pid = USB_TOKEN_SETUP;
1288 break;
1289 default:
1290 fprintf(stderr, "bad token\n");
1291 break;
1292 }
1293
1294 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1295 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1296
1297 if (p->async == EHCI_ASYNC_NONE) {
1298 if (ehci_init_transfer(p) != 0) {
1299 return -1;
1300 }
1301
1302 spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0);
1303 usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr, spd,
1304 (p->qtd.token & QTD_TOKEN_IOC) != 0);
1305 usb_packet_map(&p->packet, &p->sgl);
1306 p->async = EHCI_ASYNC_INITIALIZED;
1307 }
1308
1309 trace_usb_ehci_packet_action(p->queue, p, action);
1310 usb_handle_packet(p->queue->dev, &p->packet);
1311 DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x "
1312 "status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next,
1313 p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status,
1314 p->packet.actual_length);
1315
1316 if (p->packet.actual_length > BUFF_SIZE) {
1317 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1318 return -1;
1319 }
1320
1321 return 1;
1322 }
1323
1324 /* 4.7.2
1325 */
1326
1327 static int ehci_process_itd(EHCIState *ehci,
1328 EHCIitd *itd,
1329 uint32_t addr)
1330 {
1331 USBDevice *dev;
1332 USBEndpoint *ep;
1333 uint32_t i, len, pid, dir, devaddr, endp;
1334 uint32_t pg, off, ptr1, ptr2, max, mult;
1335
1336 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1337 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1338 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1339 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1340 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1341
1342 for(i = 0; i < 8; i++) {
1343 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1344 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1345 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1346 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1347 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1348 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1349
1350 if (len > max * mult) {
1351 len = max * mult;
1352 }
1353
1354 if (len > BUFF_SIZE) {
1355 return -1;
1356 }
1357
1358 qemu_sglist_init(&ehci->isgl, 2, ehci->dma);
1359 if (off + len > 4096) {
1360 /* transfer crosses page border */
1361 uint32_t len2 = off + len - 4096;
1362 uint32_t len1 = len - len2;
1363 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1364 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1365 } else {
1366 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1367 }
1368
1369 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1370
1371 dev = ehci_find_device(ehci, devaddr);
1372 ep = usb_ep_get(dev, pid, endp);
1373 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
1374 usb_packet_setup(&ehci->ipacket, pid, ep, addr, false,
1375 (itd->transact[i] & ITD_XACT_IOC) != 0);
1376 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1377 usb_handle_packet(dev, &ehci->ipacket);
1378 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1379 } else {
1380 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1381 ehci->ipacket.status = USB_RET_NAK;
1382 ehci->ipacket.actual_length = 0;
1383 }
1384 qemu_sglist_destroy(&ehci->isgl);
1385
1386 switch (ehci->ipacket.status) {
1387 case USB_RET_SUCCESS:
1388 break;
1389 default:
1390 fprintf(stderr, "Unexpected iso usb result: %d\n",
1391 ehci->ipacket.status);
1392 /* Fall through */
1393 case USB_RET_IOERROR:
1394 case USB_RET_NODEV:
1395 /* 3.3.2: XACTERR is only allowed on IN transactions */
1396 if (dir) {
1397 itd->transact[i] |= ITD_XACT_XACTERR;
1398 ehci_raise_irq(ehci, USBSTS_ERRINT);
1399 }
1400 break;
1401 case USB_RET_BABBLE:
1402 itd->transact[i] |= ITD_XACT_BABBLE;
1403 ehci_raise_irq(ehci, USBSTS_ERRINT);
1404 break;
1405 case USB_RET_NAK:
1406 /* no data for us, so do a zero-length transfer */
1407 ehci->ipacket.actual_length = 0;
1408 break;
1409 }
1410 if (!dir) {
1411 set_field(&itd->transact[i], len - ehci->ipacket.actual_length,
1412 ITD_XACT_LENGTH); /* OUT */
1413 } else {
1414 set_field(&itd->transact[i], ehci->ipacket.actual_length,
1415 ITD_XACT_LENGTH); /* IN */
1416 }
1417 if (itd->transact[i] & ITD_XACT_IOC) {
1418 ehci_raise_irq(ehci, USBSTS_INT);
1419 }
1420 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1421 }
1422 }
1423 return 0;
1424 }
1425
1426
1427 /* This state is the entry point for asynchronous schedule
1428 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1429 */
1430 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1431 {
1432 EHCIqh qh;
1433 int i = 0;
1434 int again = 0;
1435 uint32_t entry = ehci->asynclistaddr;
1436
1437 /* set reclamation flag at start event (4.8.6) */
1438 if (async) {
1439 ehci_set_usbsts(ehci, USBSTS_REC);
1440 }
1441
1442 ehci_queues_rip_unused(ehci, async);
1443
1444 /* Find the head of the list (4.9.1.1) */
1445 for(i = 0; i < MAX_QH; i++) {
1446 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1447 sizeof(EHCIqh) >> 2);
1448 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1449
1450 if (qh.epchar & QH_EPCHAR_H) {
1451 if (async) {
1452 entry |= (NLPTR_TYPE_QH << 1);
1453 }
1454
1455 ehci_set_fetch_addr(ehci, async, entry);
1456 ehci_set_state(ehci, async, EST_FETCHENTRY);
1457 again = 1;
1458 goto out;
1459 }
1460
1461 entry = qh.next;
1462 if (entry == ehci->asynclistaddr) {
1463 break;
1464 }
1465 }
1466
1467 /* no head found for list. */
1468
1469 ehci_set_state(ehci, async, EST_ACTIVE);
1470
1471 out:
1472 return again;
1473 }
1474
1475
1476 /* This state is the entry point for periodic schedule processing as
1477 * well as being a continuation state for async processing.
1478 */
1479 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1480 {
1481 int again = 0;
1482 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1483
1484 if (NLPTR_TBIT(entry)) {
1485 ehci_set_state(ehci, async, EST_ACTIVE);
1486 goto out;
1487 }
1488
1489 /* section 4.8, only QH in async schedule */
1490 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1491 fprintf(stderr, "non queue head request in async schedule\n");
1492 return -1;
1493 }
1494
1495 switch (NLPTR_TYPE_GET(entry)) {
1496 case NLPTR_TYPE_QH:
1497 ehci_set_state(ehci, async, EST_FETCHQH);
1498 again = 1;
1499 break;
1500
1501 case NLPTR_TYPE_ITD:
1502 ehci_set_state(ehci, async, EST_FETCHITD);
1503 again = 1;
1504 break;
1505
1506 case NLPTR_TYPE_STITD:
1507 ehci_set_state(ehci, async, EST_FETCHSITD);
1508 again = 1;
1509 break;
1510
1511 default:
1512 /* TODO: handle FSTN type */
1513 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1514 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1515 return -1;
1516 }
1517
1518 out:
1519 return again;
1520 }
1521
1522 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1523 {
1524 EHCIPacket *p;
1525 uint32_t entry, devaddr, endp;
1526 EHCIQueue *q;
1527 EHCIqh qh;
1528
1529 entry = ehci_get_fetch_addr(ehci, async);
1530 q = ehci_find_queue_by_qh(ehci, entry, async);
1531 if (NULL == q) {
1532 q = ehci_alloc_queue(ehci, entry, async);
1533 }
1534 p = QTAILQ_FIRST(&q->packets);
1535
1536 q->seen++;
1537 if (q->seen > 1) {
1538 /* we are going in circles -- stop processing */
1539 ehci_set_state(ehci, async, EST_ACTIVE);
1540 q = NULL;
1541 goto out;
1542 }
1543
1544 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1545 (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1546 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh);
1547
1548 /*
1549 * The overlay area of the qh should never be changed by the guest,
1550 * except when idle, in which case the reset is a nop.
1551 */
1552 devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR);
1553 endp = get_field(qh.epchar, QH_EPCHAR_EP);
1554 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
1555 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) ||
1556 (qh.current_qtd != q->qh.current_qtd) ||
1557 (q->async && qh.next_qtd != q->qh.next_qtd) ||
1558 (memcmp(&qh.altnext_qtd, &q->qh.altnext_qtd,
1559 7 * sizeof(uint32_t)) != 0) ||
1560 (q->dev != NULL && q->dev->addr != devaddr)) {
1561 if (ehci_reset_queue(q) > 0) {
1562 ehci_trace_guest_bug(ehci, "guest updated active QH");
1563 }
1564 p = NULL;
1565 }
1566 q->qh = qh;
1567
1568 q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1569 if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */
1570 q->transact_ctr = 4;
1571 }
1572
1573 if (q->dev == NULL) {
1574 q->dev = ehci_find_device(q->ehci, devaddr);
1575 }
1576
1577 if (p && p->async == EHCI_ASYNC_FINISHED) {
1578 /* I/O finished -- continue processing queue */
1579 trace_usb_ehci_packet_action(p->queue, p, "complete");
1580 ehci_set_state(ehci, async, EST_EXECUTING);
1581 goto out;
1582 }
1583
1584 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1585
1586 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1587 if (ehci->usbsts & USBSTS_REC) {
1588 ehci_clear_usbsts(ehci, USBSTS_REC);
1589 } else {
1590 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1591 " - done processing\n", q->qhaddr);
1592 ehci_set_state(ehci, async, EST_ACTIVE);
1593 q = NULL;
1594 goto out;
1595 }
1596 }
1597
1598 #if EHCI_DEBUG
1599 if (q->qhaddr != q->qh.next) {
1600 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1601 q->qhaddr,
1602 q->qh.epchar & QH_EPCHAR_H,
1603 q->qh.token & QTD_TOKEN_HALT,
1604 q->qh.token & QTD_TOKEN_ACTIVE,
1605 q->qh.next);
1606 }
1607 #endif
1608
1609 if (q->qh.token & QTD_TOKEN_HALT) {
1610 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1611
1612 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1613 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1614 q->qtdaddr = q->qh.current_qtd;
1615 ehci_set_state(ehci, async, EST_FETCHQTD);
1616
1617 } else {
1618 /* EHCI spec version 1.0 Section 4.10.2 */
1619 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1620 }
1621
1622 out:
1623 return q;
1624 }
1625
1626 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1627 {
1628 uint32_t entry;
1629 EHCIitd itd;
1630
1631 assert(!async);
1632 entry = ehci_get_fetch_addr(ehci, async);
1633
1634 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1635 sizeof(EHCIitd) >> 2);
1636 ehci_trace_itd(ehci, entry, &itd);
1637
1638 if (ehci_process_itd(ehci, &itd, entry) != 0) {
1639 return -1;
1640 }
1641
1642 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1643 sizeof(EHCIitd) >> 2);
1644 ehci_set_fetch_addr(ehci, async, itd.next);
1645 ehci_set_state(ehci, async, EST_FETCHENTRY);
1646
1647 return 1;
1648 }
1649
1650 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1651 {
1652 uint32_t entry;
1653 EHCIsitd sitd;
1654
1655 assert(!async);
1656 entry = ehci_get_fetch_addr(ehci, async);
1657
1658 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1659 sizeof(EHCIsitd) >> 2);
1660 ehci_trace_sitd(ehci, entry, &sitd);
1661
1662 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1663 /* siTD is not active, nothing to do */;
1664 } else {
1665 /* TODO: split transfers are not implemented */
1666 fprintf(stderr, "WARNING: Skipping active siTD\n");
1667 }
1668
1669 ehci_set_fetch_addr(ehci, async, sitd.next);
1670 ehci_set_state(ehci, async, EST_FETCHENTRY);
1671 return 1;
1672 }
1673
1674 /* Section 4.10.2 - paragraph 3 */
1675 static int ehci_state_advqueue(EHCIQueue *q)
1676 {
1677 #if 0
1678 /* TO-DO: 4.10.2 - paragraph 2
1679 * if I-bit is set to 1 and QH is not active
1680 * go to horizontal QH
1681 */
1682 if (I-bit set) {
1683 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1684 goto out;
1685 }
1686 #endif
1687
1688 /*
1689 * want data and alt-next qTD is valid
1690 */
1691 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1692 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1693 q->qtdaddr = q->qh.altnext_qtd;
1694 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1695
1696 /*
1697 * next qTD is valid
1698 */
1699 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1700 q->qtdaddr = q->qh.next_qtd;
1701 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1702
1703 /*
1704 * no valid qTD, try next QH
1705 */
1706 } else {
1707 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1708 }
1709
1710 return 1;
1711 }
1712
1713 /* Section 4.10.2 - paragraph 4 */
1714 static int ehci_state_fetchqtd(EHCIQueue *q)
1715 {
1716 EHCIqtd qtd;
1717 EHCIPacket *p;
1718 int again = 1;
1719
1720 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1721 sizeof(EHCIqtd) >> 2);
1722 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1723
1724 p = QTAILQ_FIRST(&q->packets);
1725 if (p != NULL) {
1726 if (p->qtdaddr != q->qtdaddr ||
1727 (q->async && !NLPTR_TBIT(p->qtd.next) &&
1728 (p->qtd.next != qtd.next)) ||
1729 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) ||
1730 p->qtd.bufptr[0] != qtd.bufptr[0]) {
1731 ehci_cancel_queue(q);
1732 ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD");
1733 p = NULL;
1734 } else {
1735 p->qtd = qtd;
1736 ehci_qh_do_overlay(q);
1737 }
1738 }
1739
1740 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1741 if (p != NULL) {
1742 /* transfer canceled by guest (clear active) */
1743 ehci_cancel_queue(q);
1744 p = NULL;
1745 }
1746 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1747 } else if (p != NULL) {
1748 switch (p->async) {
1749 case EHCI_ASYNC_NONE:
1750 case EHCI_ASYNC_INITIALIZED:
1751 /* Not yet executed (MULT), or previously nacked (int) packet */
1752 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1753 break;
1754 case EHCI_ASYNC_INFLIGHT:
1755 /* Check if the guest has added new tds to the queue */
1756 again = ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head));
1757 /* Unfinished async handled packet, go horizontal */
1758 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1759 break;
1760 case EHCI_ASYNC_FINISHED:
1761 /*
1762 * We get here when advqueue moves to a packet which is already
1763 * finished, which can happen with packets queued up by fill_queue
1764 */
1765 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1766 break;
1767 }
1768 } else {
1769 p = ehci_alloc_packet(q);
1770 p->qtdaddr = q->qtdaddr;
1771 p->qtd = qtd;
1772 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1773 }
1774
1775 return again;
1776 }
1777
1778 static int ehci_state_horizqh(EHCIQueue *q)
1779 {
1780 int again = 0;
1781
1782 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1783 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1784 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1785 again = 1;
1786 } else {
1787 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1788 }
1789
1790 return again;
1791 }
1792
1793 /* Returns "again" */
1794 static int ehci_fill_queue(EHCIPacket *p)
1795 {
1796 USBEndpoint *ep = p->packet.ep;
1797 EHCIQueue *q = p->queue;
1798 EHCIqtd qtd = p->qtd;
1799 uint32_t qtdaddr;
1800
1801 for (;;) {
1802 if (NLPTR_TBIT(qtd.next) != 0) {
1803 break;
1804 }
1805 qtdaddr = qtd.next;
1806 /*
1807 * Detect circular td lists, Windows creates these, counting on the
1808 * active bit going low after execution to make the queue stop.
1809 */
1810 QTAILQ_FOREACH(p, &q->packets, next) {
1811 if (p->qtdaddr == qtdaddr) {
1812 goto leave;
1813 }
1814 }
1815 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1816 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
1817 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1818 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1819 break;
1820 }
1821 p = ehci_alloc_packet(q);
1822 p->qtdaddr = qtdaddr;
1823 p->qtd = qtd;
1824 if (ehci_execute(p, "queue") == -1) {
1825 return -1;
1826 }
1827 assert(p->packet.status == USB_RET_ASYNC);
1828 p->async = EHCI_ASYNC_INFLIGHT;
1829 }
1830 leave:
1831 usb_device_flush_ep_queue(ep->dev, ep);
1832 return 1;
1833 }
1834
1835 static int ehci_state_execute(EHCIQueue *q)
1836 {
1837 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1838 int again = 0;
1839
1840 assert(p != NULL);
1841 assert(p->qtdaddr == q->qtdaddr);
1842
1843 if (ehci_qh_do_overlay(q) != 0) {
1844 return -1;
1845 }
1846
1847 // TODO verify enough time remains in the uframe as in 4.4.1.1
1848 // TODO write back ptr to async list when done or out of time
1849
1850 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
1851 if (!q->async && q->transact_ctr == 0) {
1852 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1853 again = 1;
1854 goto out;
1855 }
1856
1857 if (q->async) {
1858 ehci_set_usbsts(q->ehci, USBSTS_REC);
1859 }
1860
1861 again = ehci_execute(p, "process");
1862 if (again == -1) {
1863 goto out;
1864 }
1865 if (p->packet.status == USB_RET_ASYNC) {
1866 ehci_flush_qh(q);
1867 trace_usb_ehci_packet_action(p->queue, p, "async");
1868 p->async = EHCI_ASYNC_INFLIGHT;
1869 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1870 if (q->async) {
1871 again = ehci_fill_queue(p);
1872 } else {
1873 again = 1;
1874 }
1875 goto out;
1876 }
1877
1878 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1879 again = 1;
1880
1881 out:
1882 return again;
1883 }
1884
1885 static int ehci_state_executing(EHCIQueue *q)
1886 {
1887 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1888
1889 assert(p != NULL);
1890 assert(p->qtdaddr == q->qtdaddr);
1891
1892 ehci_execute_complete(q);
1893
1894 /* 4.10.3 */
1895 if (!q->async && q->transact_ctr > 0) {
1896 q->transact_ctr--;
1897 }
1898
1899 /* 4.10.5 */
1900 if (p->packet.status == USB_RET_NAK) {
1901 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1902 } else {
1903 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
1904 }
1905
1906 ehci_flush_qh(q);
1907 return 1;
1908 }
1909
1910
1911 static int ehci_state_writeback(EHCIQueue *q)
1912 {
1913 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1914 uint32_t *qtd, addr;
1915 int again = 0;
1916
1917 /* Write back the QTD from the QH area */
1918 assert(p != NULL);
1919 assert(p->qtdaddr == q->qtdaddr);
1920
1921 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
1922 qtd = (uint32_t *) &q->qh.next_qtd;
1923 addr = NLPTR_GET(p->qtdaddr);
1924 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2);
1925 ehci_free_packet(p);
1926
1927 /*
1928 * EHCI specs say go horizontal here.
1929 *
1930 * We can also advance the queue here for performance reasons. We
1931 * need to take care to only take that shortcut in case we've
1932 * processed the qtd just written back without errors, i.e. halt
1933 * bit is clear.
1934 */
1935 if (q->qh.token & QTD_TOKEN_HALT) {
1936 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1937 again = 1;
1938 } else {
1939 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
1940 again = 1;
1941 }
1942 return again;
1943 }
1944
1945 /*
1946 * This is the state machine that is common to both async and periodic
1947 */
1948
1949 static void ehci_advance_state(EHCIState *ehci, int async)
1950 {
1951 EHCIQueue *q = NULL;
1952 int again;
1953
1954 do {
1955 switch(ehci_get_state(ehci, async)) {
1956 case EST_WAITLISTHEAD:
1957 again = ehci_state_waitlisthead(ehci, async);
1958 break;
1959
1960 case EST_FETCHENTRY:
1961 again = ehci_state_fetchentry(ehci, async);
1962 break;
1963
1964 case EST_FETCHQH:
1965 q = ehci_state_fetchqh(ehci, async);
1966 if (q != NULL) {
1967 assert(q->async == async);
1968 again = 1;
1969 } else {
1970 again = 0;
1971 }
1972 break;
1973
1974 case EST_FETCHITD:
1975 again = ehci_state_fetchitd(ehci, async);
1976 break;
1977
1978 case EST_FETCHSITD:
1979 again = ehci_state_fetchsitd(ehci, async);
1980 break;
1981
1982 case EST_ADVANCEQUEUE:
1983 again = ehci_state_advqueue(q);
1984 break;
1985
1986 case EST_FETCHQTD:
1987 again = ehci_state_fetchqtd(q);
1988 break;
1989
1990 case EST_HORIZONTALQH:
1991 again = ehci_state_horizqh(q);
1992 break;
1993
1994 case EST_EXECUTE:
1995 again = ehci_state_execute(q);
1996 if (async) {
1997 ehci->async_stepdown = 0;
1998 }
1999 break;
2000
2001 case EST_EXECUTING:
2002 assert(q != NULL);
2003 if (async) {
2004 ehci->async_stepdown = 0;
2005 }
2006 again = ehci_state_executing(q);
2007 break;
2008
2009 case EST_WRITEBACK:
2010 assert(q != NULL);
2011 again = ehci_state_writeback(q);
2012 break;
2013
2014 default:
2015 fprintf(stderr, "Bad state!\n");
2016 again = -1;
2017 assert(0);
2018 break;
2019 }
2020
2021 if (again < 0) {
2022 fprintf(stderr, "processing error - resetting ehci HC\n");
2023 ehci_reset(ehci);
2024 again = 0;
2025 }
2026 }
2027 while (again);
2028 }
2029
2030 static void ehci_advance_async_state(EHCIState *ehci)
2031 {
2032 const int async = 1;
2033
2034 switch(ehci_get_state(ehci, async)) {
2035 case EST_INACTIVE:
2036 if (!ehci_async_enabled(ehci)) {
2037 break;
2038 }
2039 ehci_set_state(ehci, async, EST_ACTIVE);
2040 // No break, fall through to ACTIVE
2041
2042 case EST_ACTIVE:
2043 if (!ehci_async_enabled(ehci)) {
2044 ehci_queues_rip_all(ehci, async);
2045 ehci_set_state(ehci, async, EST_INACTIVE);
2046 break;
2047 }
2048
2049 /* make sure guest has acknowledged the doorbell interrupt */
2050 /* TO-DO: is this really needed? */
2051 if (ehci->usbsts & USBSTS_IAA) {
2052 DPRINTF("IAA status bit still set.\n");
2053 break;
2054 }
2055
2056 /* check that address register has been set */
2057 if (ehci->asynclistaddr == 0) {
2058 break;
2059 }
2060
2061 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2062 ehci_advance_state(ehci, async);
2063
2064 /* If the doorbell is set, the guest wants to make a change to the
2065 * schedule. The host controller needs to release cached data.
2066 * (section 4.8.2)
2067 */
2068 if (ehci->usbcmd & USBCMD_IAAD) {
2069 /* Remove all unseen qhs from the async qhs queue */
2070 ehci_queues_rip_unseen(ehci, async);
2071 trace_usb_ehci_doorbell_ack();
2072 ehci->usbcmd &= ~USBCMD_IAAD;
2073 ehci_raise_irq(ehci, USBSTS_IAA);
2074 }
2075 break;
2076
2077 default:
2078 /* this should only be due to a developer mistake */
2079 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2080 "Resetting to active\n", ehci->astate);
2081 assert(0);
2082 }
2083 }
2084
2085 static void ehci_advance_periodic_state(EHCIState *ehci)
2086 {
2087 uint32_t entry;
2088 uint32_t list;
2089 const int async = 0;
2090
2091 // 4.6
2092
2093 switch(ehci_get_state(ehci, async)) {
2094 case EST_INACTIVE:
2095 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2096 ehci_set_state(ehci, async, EST_ACTIVE);
2097 // No break, fall through to ACTIVE
2098 } else
2099 break;
2100
2101 case EST_ACTIVE:
2102 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2103 ehci_queues_rip_all(ehci, async);
2104 ehci_set_state(ehci, async, EST_INACTIVE);
2105 break;
2106 }
2107
2108 list = ehci->periodiclistbase & 0xfffff000;
2109 /* check that register has been set */
2110 if (list == 0) {
2111 break;
2112 }
2113 list |= ((ehci->frindex & 0x1ff8) >> 1);
2114
2115 dma_memory_read(ehci->dma, list, &entry, sizeof entry);
2116 entry = le32_to_cpu(entry);
2117
2118 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2119 ehci->frindex / 8, list, entry);
2120 ehci_set_fetch_addr(ehci, async,entry);
2121 ehci_set_state(ehci, async, EST_FETCHENTRY);
2122 ehci_advance_state(ehci, async);
2123 ehci_queues_rip_unused(ehci, async);
2124 break;
2125
2126 default:
2127 /* this should only be due to a developer mistake */
2128 fprintf(stderr, "ehci: Bad periodic state %d. "
2129 "Resetting to active\n", ehci->pstate);
2130 assert(0);
2131 }
2132 }
2133
2134 static void ehci_update_frindex(EHCIState *ehci, int frames)
2135 {
2136 int i;
2137
2138 if (!ehci_enabled(ehci)) {
2139 return;
2140 }
2141
2142 for (i = 0; i < frames; i++) {
2143 ehci->frindex += 8;
2144
2145 if (ehci->frindex == 0x00002000) {
2146 ehci_raise_irq(ehci, USBSTS_FLR);
2147 }
2148
2149 if (ehci->frindex == 0x00004000) {
2150 ehci_raise_irq(ehci, USBSTS_FLR);
2151 ehci->frindex = 0;
2152 if (ehci->usbsts_frindex >= 0x00004000) {
2153 ehci->usbsts_frindex -= 0x00004000;
2154 } else {
2155 ehci->usbsts_frindex = 0;
2156 }
2157 }
2158 }
2159 }
2160
2161 static void ehci_frame_timer(void *opaque)
2162 {
2163 EHCIState *ehci = opaque;
2164 int need_timer = 0;
2165 int64_t expire_time, t_now;
2166 uint64_t ns_elapsed;
2167 int frames, skipped_frames;
2168 int i;
2169
2170 t_now = qemu_get_clock_ns(vm_clock);
2171 ns_elapsed = t_now - ehci->last_run_ns;
2172 frames = ns_elapsed / FRAME_TIMER_NS;
2173
2174 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2175 need_timer++;
2176 ehci->async_stepdown = 0;
2177
2178 if (frames > ehci->maxframes) {
2179 skipped_frames = frames - ehci->maxframes;
2180 ehci_update_frindex(ehci, skipped_frames);
2181 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2182 frames -= skipped_frames;
2183 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2184 }
2185
2186 for (i = 0; i < frames; i++) {
2187 /*
2188 * If we're running behind schedule, we should not catch up
2189 * too fast, as that will make some guests unhappy:
2190 * 1) We must process a minimum of MIN_FR_PER_TICK frames,
2191 * otherwise we will never catch up
2192 * 2) Process frames until the guest has requested an irq (IOC)
2193 */
2194 if (i >= MIN_FR_PER_TICK) {
2195 ehci_commit_irq(ehci);
2196 if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) {
2197 break;
2198 }
2199 }
2200 ehci_update_frindex(ehci, 1);
2201 ehci_advance_periodic_state(ehci);
2202 ehci->last_run_ns += FRAME_TIMER_NS;
2203 }
2204 } else {
2205 if (ehci->async_stepdown < ehci->maxframes / 2) {
2206 ehci->async_stepdown++;
2207 }
2208 ehci_update_frindex(ehci, frames);
2209 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2210 }
2211
2212 /* Async is not inside loop since it executes everything it can once
2213 * called
2214 */
2215 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2216 need_timer++;
2217 ehci_advance_async_state(ehci);
2218 }
2219
2220 ehci_commit_irq(ehci);
2221 if (ehci->usbsts_pending) {
2222 need_timer++;
2223 ehci->async_stepdown = 0;
2224 }
2225
2226 if (ehci_enabled(ehci) && (ehci->usbintr & USBSTS_FLR)) {
2227 need_timer++;
2228 }
2229
2230 if (need_timer) {
2231 /* If we've raised int, we speed up the timer, so that we quickly
2232 * notice any new packets queued up in response */
2233 if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
2234 expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 2);
2235 ehci->int_req_by_async = false;
2236 } else {
2237 expire_time = t_now + (get_ticks_per_sec()
2238 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2239 }
2240 qemu_mod_timer(ehci->frame_timer, expire_time);
2241 }
2242 }
2243
2244 static const MemoryRegionOps ehci_mmio_caps_ops = {
2245 .read = ehci_caps_read,
2246 .valid.min_access_size = 1,
2247 .valid.max_access_size = 4,
2248 .impl.min_access_size = 1,
2249 .impl.max_access_size = 1,
2250 .endianness = DEVICE_LITTLE_ENDIAN,
2251 };
2252
2253 static const MemoryRegionOps ehci_mmio_opreg_ops = {
2254 .read = ehci_opreg_read,
2255 .write = ehci_opreg_write,
2256 .valid.min_access_size = 4,
2257 .valid.max_access_size = 4,
2258 .endianness = DEVICE_LITTLE_ENDIAN,
2259 };
2260
2261 static const MemoryRegionOps ehci_mmio_port_ops = {
2262 .read = ehci_port_read,
2263 .write = ehci_port_write,
2264 .valid.min_access_size = 4,
2265 .valid.max_access_size = 4,
2266 .endianness = DEVICE_LITTLE_ENDIAN,
2267 };
2268
2269 static USBPortOps ehci_port_ops = {
2270 .attach = ehci_attach,
2271 .detach = ehci_detach,
2272 .child_detach = ehci_child_detach,
2273 .wakeup = ehci_wakeup,
2274 .complete = ehci_async_complete_packet,
2275 };
2276
2277 static USBBusOps ehci_bus_ops = {
2278 .register_companion = ehci_register_companion,
2279 };
2280
2281 static int usb_ehci_post_load(void *opaque, int version_id)
2282 {
2283 EHCIState *s = opaque;
2284 int i;
2285
2286 for (i = 0; i < NB_PORTS; i++) {
2287 USBPort *companion = s->companion_ports[i];
2288 if (companion == NULL) {
2289 continue;
2290 }
2291 if (s->portsc[i] & PORTSC_POWNER) {
2292 companion->dev = s->ports[i].dev;
2293 } else {
2294 companion->dev = NULL;
2295 }
2296 }
2297
2298 return 0;
2299 }
2300
2301 static void usb_ehci_vm_state_change(void *opaque, int running, RunState state)
2302 {
2303 EHCIState *ehci = opaque;
2304
2305 /*
2306 * We don't migrate the EHCIQueue-s, instead we rebuild them for the
2307 * schedule in guest memory. We must do the rebuilt ASAP, so that
2308 * USB-devices which have async handled packages have a packet in the
2309 * ep queue to match the completion with.
2310 */
2311 if (state == RUN_STATE_RUNNING) {
2312 ehci_advance_async_state(ehci);
2313 }
2314
2315 /*
2316 * The schedule rebuilt from guest memory could cause the migration dest
2317 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH
2318 * will never have existed on the destination. Therefor we must flush the
2319 * async schedule on savevm to catch any not yet noticed unlinks.
2320 */
2321 if (state == RUN_STATE_SAVE_VM) {
2322 ehci_advance_async_state(ehci);
2323 ehci_queues_rip_unseen(ehci, 1);
2324 }
2325 }
2326
2327 const VMStateDescription vmstate_ehci = {
2328 .name = "ehci-core",
2329 .version_id = 2,
2330 .minimum_version_id = 1,
2331 .post_load = usb_ehci_post_load,
2332 .fields = (VMStateField[]) {
2333 /* mmio registers */
2334 VMSTATE_UINT32(usbcmd, EHCIState),
2335 VMSTATE_UINT32(usbsts, EHCIState),
2336 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
2337 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
2338 VMSTATE_UINT32(usbintr, EHCIState),
2339 VMSTATE_UINT32(frindex, EHCIState),
2340 VMSTATE_UINT32(ctrldssegment, EHCIState),
2341 VMSTATE_UINT32(periodiclistbase, EHCIState),
2342 VMSTATE_UINT32(asynclistaddr, EHCIState),
2343 VMSTATE_UINT32(configflag, EHCIState),
2344 VMSTATE_UINT32(portsc[0], EHCIState),
2345 VMSTATE_UINT32(portsc[1], EHCIState),
2346 VMSTATE_UINT32(portsc[2], EHCIState),
2347 VMSTATE_UINT32(portsc[3], EHCIState),
2348 VMSTATE_UINT32(portsc[4], EHCIState),
2349 VMSTATE_UINT32(portsc[5], EHCIState),
2350 /* frame timer */
2351 VMSTATE_TIMER(frame_timer, EHCIState),
2352 VMSTATE_UINT64(last_run_ns, EHCIState),
2353 VMSTATE_UINT32(async_stepdown, EHCIState),
2354 /* schedule state */
2355 VMSTATE_UINT32(astate, EHCIState),
2356 VMSTATE_UINT32(pstate, EHCIState),
2357 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2358 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2359 VMSTATE_END_OF_LIST()
2360 }
2361 };
2362
2363 void usb_ehci_initfn(EHCIState *s, DeviceState *dev)
2364 {
2365 int i;
2366
2367 /* 2.2 host controller interface version */
2368 s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
2369 s->caps[0x01] = 0x00;
2370 s->caps[0x02] = 0x00;
2371 s->caps[0x03] = 0x01; /* HC version */
2372 s->caps[0x04] = NB_PORTS; /* Number of downstream ports */
2373 s->caps[0x05] = 0x00; /* No companion ports at present */
2374 s->caps[0x06] = 0x00;
2375 s->caps[0x07] = 0x00;
2376 s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2377 s->caps[0x0a] = 0x00;
2378 s->caps[0x0b] = 0x00;
2379
2380 usb_bus_new(&s->bus, &ehci_bus_ops, dev);
2381 for(i = 0; i < NB_PORTS; i++) {
2382 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2383 USB_SPEED_MASK_HIGH);
2384 s->ports[i].dev = 0;
2385 }
2386
2387 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2388 s->async_bh = qemu_bh_new(ehci_frame_timer, s);
2389 QTAILQ_INIT(&s->aqueues);
2390 QTAILQ_INIT(&s->pqueues);
2391 usb_packet_init(&s->ipacket);
2392
2393 qemu_register_reset(ehci_reset, s);
2394 qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s);
2395
2396 memory_region_init(&s->mem, "ehci", MMIO_SIZE);
2397 memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s,
2398 "capabilities", CAPA_SIZE);
2399 memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s,
2400 "operational", PORTSC_BEGIN);
2401 memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s,
2402 "ports", PORTSC_END - PORTSC_BEGIN);
2403
2404 memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps);
2405 memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg);
2406 memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN,
2407 &s->mem_ports);
2408 }
2409
2410 /*
2411 * vim: expandtab ts=4
2412 */
Qemu copy for testing