]> git.proxmox.com Git - qemu.git/blob - hw/usb/hcd-ehci.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'sstabellini/saverestore-8' into staging
[qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw/hw.h"
26 #include "qemu-timer.h"
27 #include "hw/usb.h"
28 #include "hw/pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
137 #define MAX_QH 100 // Max allowable queue heads in a chain
138
139 /* Internal periodic / asynchronous schedule state machine states
140 */
141 typedef enum {
142 EST_INACTIVE = 1000,
143 EST_ACTIVE,
144 EST_EXECUTING,
145 EST_SLEEPING,
146 /* The following states are internal to the state machine function
147 */
148 EST_WAITLISTHEAD,
149 EST_FETCHENTRY,
150 EST_FETCHQH,
151 EST_FETCHITD,
152 EST_FETCHSITD,
153 EST_ADVANCEQUEUE,
154 EST_FETCHQTD,
155 EST_EXECUTE,
156 EST_WRITEBACK,
157 EST_HORIZONTALQH
158 } EHCI_STATES;
159
160 /* macros for accessing fields within next link pointer entry */
161 #define NLPTR_GET(x) ((x) & 0xffffffe0)
162 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
163 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
164
165 /* link pointer types */
166 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
167 #define NLPTR_TYPE_QH 1 // queue head
168 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
169 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
170
171
172 /* EHCI spec version 1.0 Section 3.3
173 */
174 typedef struct EHCIitd {
175 uint32_t next;
176
177 uint32_t transact[8];
178 #define ITD_XACT_ACTIVE (1 << 31)
179 #define ITD_XACT_DBERROR (1 << 30)
180 #define ITD_XACT_BABBLE (1 << 29)
181 #define ITD_XACT_XACTERR (1 << 28)
182 #define ITD_XACT_LENGTH_MASK 0x0fff0000
183 #define ITD_XACT_LENGTH_SH 16
184 #define ITD_XACT_IOC (1 << 15)
185 #define ITD_XACT_PGSEL_MASK 0x00007000
186 #define ITD_XACT_PGSEL_SH 12
187 #define ITD_XACT_OFFSET_MASK 0x00000fff
188
189 uint32_t bufptr[7];
190 #define ITD_BUFPTR_MASK 0xfffff000
191 #define ITD_BUFPTR_SH 12
192 #define ITD_BUFPTR_EP_MASK 0x00000f00
193 #define ITD_BUFPTR_EP_SH 8
194 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
195 #define ITD_BUFPTR_DEVADDR_SH 0
196 #define ITD_BUFPTR_DIRECTION (1 << 11)
197 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
198 #define ITD_BUFPTR_MAXPKT_SH 0
199 #define ITD_BUFPTR_MULT_MASK 0x00000003
200 #define ITD_BUFPTR_MULT_SH 0
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 #define QTD_BUFPTR_SH 12
275 } EHCIqtd;
276
277 /* EHCI spec version 1.0 Section 3.6
278 */
279 typedef struct EHCIqh {
280 uint32_t next; // Standard next link pointer
281
282 /* endpoint characteristics */
283 uint32_t epchar;
284 #define QH_EPCHAR_RL_MASK 0xf0000000
285 #define QH_EPCHAR_RL_SH 28
286 #define QH_EPCHAR_C (1 << 27)
287 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
288 #define QH_EPCHAR_MPLEN_SH 16
289 #define QH_EPCHAR_H (1 << 15)
290 #define QH_EPCHAR_DTC (1 << 14)
291 #define QH_EPCHAR_EPS_MASK 0x00003000
292 #define QH_EPCHAR_EPS_SH 12
293 #define EHCI_QH_EPS_FULL 0
294 #define EHCI_QH_EPS_LOW 1
295 #define EHCI_QH_EPS_HIGH 2
296 #define EHCI_QH_EPS_RESERVED 3
297
298 #define QH_EPCHAR_EP_MASK 0x00000f00
299 #define QH_EPCHAR_EP_SH 8
300 #define QH_EPCHAR_I (1 << 7)
301 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
302 #define QH_EPCHAR_DEVADDR_SH 0
303
304 /* endpoint capabilities */
305 uint32_t epcap;
306 #define QH_EPCAP_MULT_MASK 0xc0000000
307 #define QH_EPCAP_MULT_SH 30
308 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
309 #define QH_EPCAP_PORTNUM_SH 23
310 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
311 #define QH_EPCAP_HUBADDR_SH 16
312 #define QH_EPCAP_CMASK_MASK 0x0000ff00
313 #define QH_EPCAP_CMASK_SH 8
314 #define QH_EPCAP_SMASK_MASK 0x000000ff
315 #define QH_EPCAP_SMASK_SH 0
316
317 uint32_t current_qtd; // Standard next link pointer
318 uint32_t next_qtd; // Standard next link pointer
319 uint32_t altnext_qtd;
320 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
321 #define QH_ALTNEXT_NAKCNT_SH 1
322
323 uint32_t token; // Same as QTD token
324 uint32_t bufptr[5]; // Standard buffer pointer
325 #define BUFPTR_CPROGMASK_MASK 0x000000ff
326 #define BUFPTR_FRAMETAG_MASK 0x0000001f
327 #define BUFPTR_SBYTES_MASK 0x00000fe0
328 #define BUFPTR_SBYTES_SH 5
329 } EHCIqh;
330
331 /* EHCI spec version 1.0 Section 3.7
332 */
333 typedef struct EHCIfstn {
334 uint32_t next; // Standard next link pointer
335 uint32_t backptr; // Standard next link pointer
336 } EHCIfstn;
337
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIQueue {
348 EHCIState *ehci;
349 QTAILQ_ENTRY(EHCIQueue) next;
350 uint32_t seen;
351 uint64_t ts;
352
353 /* cached data from guest - needs to be flushed
354 * when guest removes an entry (doorbell, handshake sequence)
355 */
356 EHCIqh qh; // copy of current QH (being worked on)
357 uint32_t qhaddr; // address QH read from
358 EHCIqtd qtd; // copy of current QTD (being worked on)
359 uint32_t qtdaddr; // address QTD read from
360
361 USBPacket packet;
362 QEMUSGList sgl;
363 int pid;
364 uint32_t tbytes;
365 enum async_state async;
366 int usb_status;
367 };
368
369 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
370
371 struct EHCIState {
372 PCIDevice dev;
373 USBBus bus;
374 qemu_irq irq;
375 MemoryRegion mem;
376 int companion_count;
377
378 /* properties */
379 uint32_t freq;
380 uint32_t maxframes;
381
382 /*
383 * EHCI spec version 1.0 Section 2.3
384 * Host Controller Operational Registers
385 */
386 union {
387 uint8_t mmio[MMIO_SIZE];
388 struct {
389 uint8_t cap[OPREGBASE];
390 uint32_t usbcmd;
391 uint32_t usbsts;
392 uint32_t usbintr;
393 uint32_t frindex;
394 uint32_t ctrldssegment;
395 uint32_t periodiclistbase;
396 uint32_t asynclistaddr;
397 uint32_t notused[9];
398 uint32_t configflag;
399 uint32_t portsc[NB_PORTS];
400 };
401 };
402
403 /*
404 * Internal states, shadow registers, etc
405 */
406 uint32_t sofv;
407 QEMUTimer *frame_timer;
408 int attach_poll_counter;
409 int astate; // Current state in asynchronous schedule
410 int pstate; // Current state in periodic schedule
411 USBPort ports[NB_PORTS];
412 USBPort *companion_ports[NB_PORTS];
413 uint32_t usbsts_pending;
414 EHCIQueueHead aqueues;
415 EHCIQueueHead pqueues;
416
417 uint32_t a_fetch_addr; // which address to look at next
418 uint32_t p_fetch_addr; // which address to look at next
419
420 USBPacket ipacket;
421 QEMUSGList isgl;
422
423 uint64_t last_run_ns;
424 };
425
426 #define SET_LAST_RUN_CLOCK(s) \
427 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
428
429 /* nifty macros from Arnon's EHCI version */
430 #define get_field(data, field) \
431 (((data) & field##_MASK) >> field##_SH)
432
433 #define set_field(data, newval, field) do { \
434 uint32_t val = *data; \
435 val &= ~ field##_MASK; \
436 val |= ((newval) << field##_SH) & field##_MASK; \
437 *data = val; \
438 } while(0)
439
440 static const char *ehci_state_names[] = {
441 [EST_INACTIVE] = "INACTIVE",
442 [EST_ACTIVE] = "ACTIVE",
443 [EST_EXECUTING] = "EXECUTING",
444 [EST_SLEEPING] = "SLEEPING",
445 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
446 [EST_FETCHENTRY] = "FETCH ENTRY",
447 [EST_FETCHQH] = "FETCH QH",
448 [EST_FETCHITD] = "FETCH ITD",
449 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
450 [EST_FETCHQTD] = "FETCH QTD",
451 [EST_EXECUTE] = "EXECUTE",
452 [EST_WRITEBACK] = "WRITEBACK",
453 [EST_HORIZONTALQH] = "HORIZONTALQH",
454 };
455
456 static const char *ehci_mmio_names[] = {
457 [CAPLENGTH] = "CAPLENGTH",
458 [HCIVERSION] = "HCIVERSION",
459 [HCSPARAMS] = "HCSPARAMS",
460 [HCCPARAMS] = "HCCPARAMS",
461 [USBCMD] = "USBCMD",
462 [USBSTS] = "USBSTS",
463 [USBINTR] = "USBINTR",
464 [FRINDEX] = "FRINDEX",
465 [PERIODICLISTBASE] = "P-LIST BASE",
466 [ASYNCLISTADDR] = "A-LIST ADDR",
467 [PORTSC_BEGIN] = "PORTSC #0",
468 [PORTSC_BEGIN + 4] = "PORTSC #1",
469 [PORTSC_BEGIN + 8] = "PORTSC #2",
470 [PORTSC_BEGIN + 12] = "PORTSC #3",
471 [PORTSC_BEGIN + 16] = "PORTSC #4",
472 [PORTSC_BEGIN + 20] = "PORTSC #5",
473 [CONFIGFLAG] = "CONFIGFLAG",
474 };
475
476 static const char *nr2str(const char **n, size_t len, uint32_t nr)
477 {
478 if (nr < len && n[nr] != NULL) {
479 return n[nr];
480 } else {
481 return "unknown";
482 }
483 }
484
485 static const char *state2str(uint32_t state)
486 {
487 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
488 }
489
490 static const char *addr2str(target_phys_addr_t addr)
491 {
492 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
493 }
494
495 static void ehci_trace_usbsts(uint32_t mask, int state)
496 {
497 /* interrupts */
498 if (mask & USBSTS_INT) {
499 trace_usb_ehci_usbsts("INT", state);
500 }
501 if (mask & USBSTS_ERRINT) {
502 trace_usb_ehci_usbsts("ERRINT", state);
503 }
504 if (mask & USBSTS_PCD) {
505 trace_usb_ehci_usbsts("PCD", state);
506 }
507 if (mask & USBSTS_FLR) {
508 trace_usb_ehci_usbsts("FLR", state);
509 }
510 if (mask & USBSTS_HSE) {
511 trace_usb_ehci_usbsts("HSE", state);
512 }
513 if (mask & USBSTS_IAA) {
514 trace_usb_ehci_usbsts("IAA", state);
515 }
516
517 /* status */
518 if (mask & USBSTS_HALT) {
519 trace_usb_ehci_usbsts("HALT", state);
520 }
521 if (mask & USBSTS_REC) {
522 trace_usb_ehci_usbsts("REC", state);
523 }
524 if (mask & USBSTS_PSS) {
525 trace_usb_ehci_usbsts("PSS", state);
526 }
527 if (mask & USBSTS_ASS) {
528 trace_usb_ehci_usbsts("ASS", state);
529 }
530 }
531
532 static inline void ehci_set_usbsts(EHCIState *s, int mask)
533 {
534 if ((s->usbsts & mask) == mask) {
535 return;
536 }
537 ehci_trace_usbsts(mask, 1);
538 s->usbsts |= mask;
539 }
540
541 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
542 {
543 if ((s->usbsts & mask) == 0) {
544 return;
545 }
546 ehci_trace_usbsts(mask, 0);
547 s->usbsts &= ~mask;
548 }
549
550 static inline void ehci_set_interrupt(EHCIState *s, int intr)
551 {
552 int level = 0;
553
554 // TODO honour interrupt threshold requests
555
556 ehci_set_usbsts(s, intr);
557
558 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
559 level = 1;
560 }
561
562 qemu_set_irq(s->irq, level);
563 }
564
565 static inline void ehci_record_interrupt(EHCIState *s, int intr)
566 {
567 s->usbsts_pending |= intr;
568 }
569
570 static inline void ehci_commit_interrupt(EHCIState *s)
571 {
572 if (!s->usbsts_pending) {
573 return;
574 }
575 ehci_set_interrupt(s, s->usbsts_pending);
576 s->usbsts_pending = 0;
577 }
578
579 static void ehci_set_state(EHCIState *s, int async, int state)
580 {
581 if (async) {
582 trace_usb_ehci_state("async", state2str(state));
583 s->astate = state;
584 } else {
585 trace_usb_ehci_state("periodic", state2str(state));
586 s->pstate = state;
587 }
588 }
589
590 static int ehci_get_state(EHCIState *s, int async)
591 {
592 return async ? s->astate : s->pstate;
593 }
594
595 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
596 {
597 if (async) {
598 s->a_fetch_addr = addr;
599 } else {
600 s->p_fetch_addr = addr;
601 }
602 }
603
604 static int ehci_get_fetch_addr(EHCIState *s, int async)
605 {
606 return async ? s->a_fetch_addr : s->p_fetch_addr;
607 }
608
609 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
610 {
611 /* need three here due to argument count limits */
612 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
613 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
614 trace_usb_ehci_qh_fields(addr,
615 get_field(qh->epchar, QH_EPCHAR_RL),
616 get_field(qh->epchar, QH_EPCHAR_MPLEN),
617 get_field(qh->epchar, QH_EPCHAR_EPS),
618 get_field(qh->epchar, QH_EPCHAR_EP),
619 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
620 trace_usb_ehci_qh_bits(addr,
621 (bool)(qh->epchar & QH_EPCHAR_C),
622 (bool)(qh->epchar & QH_EPCHAR_H),
623 (bool)(qh->epchar & QH_EPCHAR_DTC),
624 (bool)(qh->epchar & QH_EPCHAR_I));
625 }
626
627 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
628 {
629 /* need three here due to argument count limits */
630 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
631 trace_usb_ehci_qtd_fields(addr,
632 get_field(qtd->token, QTD_TOKEN_TBYTES),
633 get_field(qtd->token, QTD_TOKEN_CPAGE),
634 get_field(qtd->token, QTD_TOKEN_CERR),
635 get_field(qtd->token, QTD_TOKEN_PID));
636 trace_usb_ehci_qtd_bits(addr,
637 (bool)(qtd->token & QTD_TOKEN_IOC),
638 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
639 (bool)(qtd->token & QTD_TOKEN_HALT),
640 (bool)(qtd->token & QTD_TOKEN_BABBLE),
641 (bool)(qtd->token & QTD_TOKEN_XACTERR));
642 }
643
644 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
645 {
646 trace_usb_ehci_itd(addr, itd->next,
647 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
648 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
649 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
650 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
651 }
652
653 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
654 EHCIsitd *sitd)
655 {
656 trace_usb_ehci_sitd(addr, sitd->next,
657 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
658 }
659
660 /* queue management */
661
662 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
663 {
664 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
665 EHCIQueue *q;
666
667 q = g_malloc0(sizeof(*q));
668 q->ehci = ehci;
669 QTAILQ_INSERT_HEAD(head, q, next);
670 trace_usb_ehci_queue_action(q, "alloc");
671 return q;
672 }
673
674 static void ehci_free_queue(EHCIQueue *q, int async)
675 {
676 EHCIQueueHead *head = async ? &q->ehci->aqueues : &q->ehci->pqueues;
677 trace_usb_ehci_queue_action(q, "free");
678 if (q->async == EHCI_ASYNC_INFLIGHT) {
679 usb_cancel_packet(&q->packet);
680 }
681 QTAILQ_REMOVE(head, q, next);
682 g_free(q);
683 }
684
685 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
686 int async)
687 {
688 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
689 EHCIQueue *q;
690
691 QTAILQ_FOREACH(q, head, next) {
692 if (addr == q->qhaddr) {
693 return q;
694 }
695 }
696 return NULL;
697 }
698
699 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush)
700 {
701 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
702 EHCIQueue *q, *tmp;
703
704 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
705 if (q->seen) {
706 q->seen = 0;
707 q->ts = ehci->last_run_ns;
708 continue;
709 }
710 if (!flush && ehci->last_run_ns < q->ts + 250000000) {
711 /* allow 0.25 sec idle */
712 continue;
713 }
714 ehci_free_queue(q, async);
715 }
716 }
717
718 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
719 {
720 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
721 EHCIQueue *q, *tmp;
722
723 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
724 if (!usb_packet_is_inflight(&q->packet) ||
725 q->packet.ep->dev != dev) {
726 continue;
727 }
728 ehci_free_queue(q, async);
729 }
730 }
731
732 static void ehci_queues_rip_all(EHCIState *ehci, int async)
733 {
734 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
735 EHCIQueue *q, *tmp;
736
737 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
738 ehci_free_queue(q, async);
739 }
740 }
741
742 /* Attach or detach a device on root hub */
743
744 static void ehci_attach(USBPort *port)
745 {
746 EHCIState *s = port->opaque;
747 uint32_t *portsc = &s->portsc[port->index];
748
749 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
750
751 if (*portsc & PORTSC_POWNER) {
752 USBPort *companion = s->companion_ports[port->index];
753 companion->dev = port->dev;
754 companion->ops->attach(companion);
755 return;
756 }
757
758 *portsc |= PORTSC_CONNECT;
759 *portsc |= PORTSC_CSC;
760
761 ehci_set_interrupt(s, USBSTS_PCD);
762 }
763
764 static void ehci_detach(USBPort *port)
765 {
766 EHCIState *s = port->opaque;
767 uint32_t *portsc = &s->portsc[port->index];
768
769 trace_usb_ehci_port_detach(port->index);
770
771 if (*portsc & PORTSC_POWNER) {
772 USBPort *companion = s->companion_ports[port->index];
773 companion->ops->detach(companion);
774 companion->dev = NULL;
775 /*
776 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
777 * the port ownership is returned immediately to the EHCI controller."
778 */
779 *portsc &= ~PORTSC_POWNER;
780 return;
781 }
782
783 ehci_queues_rip_device(s, port->dev, 0);
784 ehci_queues_rip_device(s, port->dev, 1);
785
786 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
787 *portsc |= PORTSC_CSC;
788
789 ehci_set_interrupt(s, USBSTS_PCD);
790 }
791
792 static void ehci_child_detach(USBPort *port, USBDevice *child)
793 {
794 EHCIState *s = port->opaque;
795 uint32_t portsc = s->portsc[port->index];
796
797 if (portsc & PORTSC_POWNER) {
798 USBPort *companion = s->companion_ports[port->index];
799 companion->ops->child_detach(companion, child);
800 companion->dev = NULL;
801 return;
802 }
803
804 ehci_queues_rip_device(s, child, 0);
805 ehci_queues_rip_device(s, child, 1);
806 }
807
808 static void ehci_wakeup(USBPort *port)
809 {
810 EHCIState *s = port->opaque;
811 uint32_t portsc = s->portsc[port->index];
812
813 if (portsc & PORTSC_POWNER) {
814 USBPort *companion = s->companion_ports[port->index];
815 if (companion->ops->wakeup) {
816 companion->ops->wakeup(companion);
817 }
818 }
819 }
820
821 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
822 uint32_t portcount, uint32_t firstport)
823 {
824 EHCIState *s = container_of(bus, EHCIState, bus);
825 uint32_t i;
826
827 if (firstport + portcount > NB_PORTS) {
828 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
829 "firstport on masterbus");
830 error_printf_unless_qmp(
831 "firstport value of %u makes companion take ports %u - %u, which "
832 "is outside of the valid range of 0 - %u\n", firstport, firstport,
833 firstport + portcount - 1, NB_PORTS - 1);
834 return -1;
835 }
836
837 for (i = 0; i < portcount; i++) {
838 if (s->companion_ports[firstport + i]) {
839 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
840 "an USB masterbus");
841 error_printf_unless_qmp(
842 "port %u on masterbus %s already has a companion assigned\n",
843 firstport + i, bus->qbus.name);
844 return -1;
845 }
846 }
847
848 for (i = 0; i < portcount; i++) {
849 s->companion_ports[firstport + i] = ports[i];
850 s->ports[firstport + i].speedmask |=
851 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
852 /* Ensure devs attached before the initial reset go to the companion */
853 s->portsc[firstport + i] = PORTSC_POWNER;
854 }
855
856 s->companion_count++;
857 s->mmio[0x05] = (s->companion_count << 4) | portcount;
858
859 return 0;
860 }
861
862 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
863 {
864 USBDevice *dev;
865 USBPort *port;
866 int i;
867
868 for (i = 0; i < NB_PORTS; i++) {
869 port = &ehci->ports[i];
870 if (!(ehci->portsc[i] & PORTSC_PED)) {
871 DPRINTF("Port %d not enabled\n", i);
872 continue;
873 }
874 dev = usb_find_device(port, addr);
875 if (dev != NULL) {
876 return dev;
877 }
878 }
879 return NULL;
880 }
881
882 /* 4.1 host controller initialization */
883 static void ehci_reset(void *opaque)
884 {
885 EHCIState *s = opaque;
886 int i;
887 USBDevice *devs[NB_PORTS];
888
889 trace_usb_ehci_reset();
890
891 /*
892 * Do the detach before touching portsc, so that it correctly gets send to
893 * us or to our companion based on PORTSC_POWNER before the reset.
894 */
895 for(i = 0; i < NB_PORTS; i++) {
896 devs[i] = s->ports[i].dev;
897 if (devs[i] && devs[i]->attached) {
898 usb_detach(&s->ports[i]);
899 }
900 }
901
902 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
903
904 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
905 s->usbsts = USBSTS_HALT;
906
907 s->astate = EST_INACTIVE;
908 s->pstate = EST_INACTIVE;
909 s->attach_poll_counter = 0;
910
911 for(i = 0; i < NB_PORTS; i++) {
912 if (s->companion_ports[i]) {
913 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
914 } else {
915 s->portsc[i] = PORTSC_PPOWER;
916 }
917 if (devs[i] && devs[i]->attached) {
918 usb_attach(&s->ports[i]);
919 usb_device_reset(devs[i]);
920 }
921 }
922 ehci_queues_rip_all(s, 0);
923 ehci_queues_rip_all(s, 1);
924 qemu_del_timer(s->frame_timer);
925 }
926
927 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
928 {
929 EHCIState *s = ptr;
930 uint32_t val;
931
932 val = s->mmio[addr];
933
934 return val;
935 }
936
937 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
938 {
939 EHCIState *s = ptr;
940 uint32_t val;
941
942 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
943
944 return val;
945 }
946
947 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
948 {
949 EHCIState *s = ptr;
950 uint32_t val;
951
952 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
953 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
954
955 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
956 return val;
957 }
958
959 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
960 {
961 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
962 exit(1);
963 }
964
965 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
966 {
967 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
968 exit(1);
969 }
970
971 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
972 {
973 USBDevice *dev = s->ports[port].dev;
974 uint32_t *portsc = &s->portsc[port];
975 uint32_t orig;
976
977 if (s->companion_ports[port] == NULL)
978 return;
979
980 owner = owner & PORTSC_POWNER;
981 orig = *portsc & PORTSC_POWNER;
982
983 if (!(owner ^ orig)) {
984 return;
985 }
986
987 if (dev && dev->attached) {
988 usb_detach(&s->ports[port]);
989 }
990
991 *portsc &= ~PORTSC_POWNER;
992 *portsc |= owner;
993
994 if (dev && dev->attached) {
995 usb_attach(&s->ports[port]);
996 }
997 }
998
999 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1000 {
1001 uint32_t *portsc = &s->portsc[port];
1002 USBDevice *dev = s->ports[port].dev;
1003
1004 /* Clear rwc bits */
1005 *portsc &= ~(val & PORTSC_RWC_MASK);
1006 /* The guest may clear, but not set the PED bit */
1007 *portsc &= val | ~PORTSC_PED;
1008 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1009 handle_port_owner_write(s, port, val);
1010 /* And finally apply RO_MASK */
1011 val &= PORTSC_RO_MASK;
1012
1013 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1014 trace_usb_ehci_port_reset(port, 1);
1015 }
1016
1017 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1018 trace_usb_ehci_port_reset(port, 0);
1019 if (dev && dev->attached) {
1020 usb_port_reset(&s->ports[port]);
1021 *portsc &= ~PORTSC_CSC;
1022 }
1023
1024 /*
1025 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1026 * to SW that this port has a high speed device attached
1027 */
1028 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1029 val |= PORTSC_PED;
1030 }
1031 }
1032
1033 *portsc &= ~PORTSC_RO_MASK;
1034 *portsc |= val;
1035 }
1036
1037 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1038 {
1039 EHCIState *s = ptr;
1040 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1041 uint32_t old = *mmio;
1042 int i;
1043
1044 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1045
1046 /* Only aligned reads are allowed on OHCI */
1047 if (addr & 3) {
1048 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1049 TARGET_FMT_plx "\n", addr);
1050 return;
1051 }
1052
1053 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1054 handle_port_status_write(s, (addr-PORTSC)/4, val);
1055 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1056 return;
1057 }
1058
1059 if (addr < OPREGBASE) {
1060 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1061 TARGET_FMT_plx "\n", addr);
1062 return;
1063 }
1064
1065
1066 /* Do any register specific pre-write processing here. */
1067 switch(addr) {
1068 case USBCMD:
1069 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
1070 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1071 SET_LAST_RUN_CLOCK(s);
1072 ehci_clear_usbsts(s, USBSTS_HALT);
1073 }
1074
1075 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
1076 qemu_del_timer(s->frame_timer);
1077 ehci_queues_rip_all(s, 0);
1078 ehci_queues_rip_all(s, 1);
1079 ehci_set_usbsts(s, USBSTS_HALT);
1080 }
1081
1082 if (val & USBCMD_HCRESET) {
1083 ehci_reset(s);
1084 val = s->usbcmd;
1085 }
1086
1087 /* not supporting dynamic frame list size at the moment */
1088 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1089 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1090 val & USBCMD_FLS);
1091 val &= ~USBCMD_FLS;
1092 }
1093 break;
1094
1095 case USBSTS:
1096 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
1097 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
1098 val = s->usbsts;
1099 ehci_set_interrupt(s, 0);
1100 break;
1101
1102 case USBINTR:
1103 val &= USBINTR_MASK;
1104 break;
1105
1106 case FRINDEX:
1107 s->sofv = val >> 3;
1108 break;
1109
1110 case CONFIGFLAG:
1111 val &= 0x1;
1112 if (val) {
1113 for(i = 0; i < NB_PORTS; i++)
1114 handle_port_owner_write(s, i, 0);
1115 }
1116 break;
1117
1118 case PERIODICLISTBASE:
1119 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1120 fprintf(stderr,
1121 "ehci: PERIODIC list base register set while periodic schedule\n"
1122 " is enabled and HC is enabled\n");
1123 }
1124 break;
1125
1126 case ASYNCLISTADDR:
1127 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1128 fprintf(stderr,
1129 "ehci: ASYNC list address register set while async schedule\n"
1130 " is enabled and HC is enabled\n");
1131 }
1132 break;
1133 }
1134
1135 *mmio = val;
1136 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1137 }
1138
1139
1140 // TODO : Put in common header file, duplication from usb-ohci.c
1141
1142 /* Get an array of dwords from main memory */
1143 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1144 uint32_t *buf, int num)
1145 {
1146 int i;
1147
1148 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1149 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1150 *buf = le32_to_cpu(*buf);
1151 }
1152
1153 return 1;
1154 }
1155
1156 /* Put an array of dwords in to main memory */
1157 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1158 uint32_t *buf, int num)
1159 {
1160 int i;
1161
1162 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1163 uint32_t tmp = cpu_to_le32(*buf);
1164 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1165 }
1166
1167 return 1;
1168 }
1169
1170 // 4.10.2
1171
1172 static int ehci_qh_do_overlay(EHCIQueue *q)
1173 {
1174 int i;
1175 int dtoggle;
1176 int ping;
1177 int eps;
1178 int reload;
1179
1180 // remember values in fields to preserve in qh after overlay
1181
1182 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1183 ping = q->qh.token & QTD_TOKEN_PING;
1184
1185 q->qh.current_qtd = q->qtdaddr;
1186 q->qh.next_qtd = q->qtd.next;
1187 q->qh.altnext_qtd = q->qtd.altnext;
1188 q->qh.token = q->qtd.token;
1189
1190
1191 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1192 if (eps == EHCI_QH_EPS_HIGH) {
1193 q->qh.token &= ~QTD_TOKEN_PING;
1194 q->qh.token |= ping;
1195 }
1196
1197 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1198 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1199
1200 for (i = 0; i < 5; i++) {
1201 q->qh.bufptr[i] = q->qtd.bufptr[i];
1202 }
1203
1204 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1205 // preserve QH DT bit
1206 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1207 q->qh.token |= dtoggle;
1208 }
1209
1210 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1211 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1212
1213 put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh,
1214 sizeof(EHCIqh) >> 2);
1215
1216 return 0;
1217 }
1218
1219 static int ehci_init_transfer(EHCIQueue *q)
1220 {
1221 uint32_t cpage, offset, bytes, plen;
1222 dma_addr_t page;
1223
1224 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1225 bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1226 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1227 pci_dma_sglist_init(&q->sgl, &q->ehci->dev, 5);
1228
1229 while (bytes > 0) {
1230 if (cpage > 4) {
1231 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1232 return USB_RET_PROCERR;
1233 }
1234
1235 page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1236 page += offset;
1237 plen = bytes;
1238 if (plen > 4096 - offset) {
1239 plen = 4096 - offset;
1240 offset = 0;
1241 cpage++;
1242 }
1243
1244 qemu_sglist_add(&q->sgl, page, plen);
1245 bytes -= plen;
1246 }
1247 return 0;
1248 }
1249
1250 static void ehci_finish_transfer(EHCIQueue *q, int status)
1251 {
1252 uint32_t cpage, offset;
1253
1254 qemu_sglist_destroy(&q->sgl);
1255
1256 if (status > 0) {
1257 /* update cpage & offset */
1258 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1259 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1260
1261 offset += status;
1262 cpage += offset >> QTD_BUFPTR_SH;
1263 offset &= ~QTD_BUFPTR_MASK;
1264
1265 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1266 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1267 q->qh.bufptr[0] |= offset;
1268 }
1269 }
1270
1271 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1272 {
1273 EHCIQueue *q;
1274 EHCIState *s = port->opaque;
1275 uint32_t portsc = s->portsc[port->index];
1276
1277 if (portsc & PORTSC_POWNER) {
1278 USBPort *companion = s->companion_ports[port->index];
1279 companion->ops->complete(companion, packet);
1280 return;
1281 }
1282
1283 q = container_of(packet, EHCIQueue, packet);
1284 trace_usb_ehci_queue_action(q, "wakeup");
1285 assert(q->async == EHCI_ASYNC_INFLIGHT);
1286 q->async = EHCI_ASYNC_FINISHED;
1287 q->usb_status = packet->result;
1288 }
1289
1290 static void ehci_execute_complete(EHCIQueue *q)
1291 {
1292 assert(q->async != EHCI_ASYNC_INFLIGHT);
1293 q->async = EHCI_ASYNC_NONE;
1294
1295 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1296 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1297
1298 if (q->usb_status < 0) {
1299 switch(q->usb_status) {
1300 case USB_RET_IOERROR:
1301 case USB_RET_NODEV:
1302 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1303 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1304 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1305 break;
1306 case USB_RET_STALL:
1307 q->qh.token |= QTD_TOKEN_HALT;
1308 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1309 break;
1310 case USB_RET_NAK:
1311 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1312 return; /* We're not done yet with this transaction */
1313 case USB_RET_BABBLE:
1314 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1315 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1316 break;
1317 default:
1318 /* should not be triggerable */
1319 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1320 assert(0);
1321 break;
1322 }
1323 } else if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1324 q->usb_status = USB_RET_BABBLE;
1325 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1326 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1327 } else {
1328 // TODO check 4.12 for splits
1329
1330 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1331 q->tbytes -= q->usb_status;
1332 } else {
1333 q->tbytes = 0;
1334 }
1335
1336 DPRINTF("updating tbytes to %d\n", q->tbytes);
1337 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1338 }
1339 ehci_finish_transfer(q, q->usb_status);
1340 usb_packet_unmap(&q->packet);
1341
1342 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1343 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1344
1345 if (q->qh.token & QTD_TOKEN_IOC) {
1346 ehci_record_interrupt(q->ehci, USBSTS_INT);
1347 }
1348 }
1349
1350 // 4.10.3
1351
1352 static int ehci_execute(EHCIQueue *q)
1353 {
1354 USBDevice *dev;
1355 USBEndpoint *ep;
1356 int ret;
1357 int endp;
1358 int devadr;
1359
1360 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1361 fprintf(stderr, "Attempting to execute inactive QH\n");
1362 return USB_RET_PROCERR;
1363 }
1364
1365 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1366 if (q->tbytes > BUFF_SIZE) {
1367 fprintf(stderr, "Request for more bytes than allowed\n");
1368 return USB_RET_PROCERR;
1369 }
1370
1371 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1372 switch(q->pid) {
1373 case 0: q->pid = USB_TOKEN_OUT; break;
1374 case 1: q->pid = USB_TOKEN_IN; break;
1375 case 2: q->pid = USB_TOKEN_SETUP; break;
1376 default: fprintf(stderr, "bad token\n"); break;
1377 }
1378
1379 if (ehci_init_transfer(q) != 0) {
1380 return USB_RET_PROCERR;
1381 }
1382
1383 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1384 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1385
1386 /* TODO: associating device with ehci port */
1387 dev = ehci_find_device(q->ehci, devadr);
1388 ep = usb_ep_get(dev, q->pid, endp);
1389
1390 usb_packet_setup(&q->packet, q->pid, ep);
1391 usb_packet_map(&q->packet, &q->sgl);
1392
1393 ret = usb_handle_packet(dev, &q->packet);
1394 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1395 "(total %d) endp %x ret %d\n",
1396 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1397 q->packet.iov.size, q->tbytes, endp, ret);
1398
1399 if (ret > BUFF_SIZE) {
1400 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1401 return USB_RET_PROCERR;
1402 }
1403
1404 return ret;
1405 }
1406
1407 /* 4.7.2
1408 */
1409
1410 static int ehci_process_itd(EHCIState *ehci,
1411 EHCIitd *itd)
1412 {
1413 USBDevice *dev;
1414 USBEndpoint *ep;
1415 int ret;
1416 uint32_t i, len, pid, dir, devaddr, endp;
1417 uint32_t pg, off, ptr1, ptr2, max, mult;
1418
1419 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1420 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1421 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1422 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1423 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1424
1425 for(i = 0; i < 8; i++) {
1426 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1427 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1428 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1429 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1430 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1431 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1432
1433 if (len > max * mult) {
1434 len = max * mult;
1435 }
1436
1437 if (len > BUFF_SIZE) {
1438 return USB_RET_PROCERR;
1439 }
1440
1441 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1442 if (off + len > 4096) {
1443 /* transfer crosses page border */
1444 uint32_t len2 = off + len - 4096;
1445 uint32_t len1 = len - len2;
1446 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1447 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1448 } else {
1449 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1450 }
1451
1452 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1453
1454 dev = ehci_find_device(ehci, devaddr);
1455 ep = usb_ep_get(dev, pid, endp);
1456 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1457 usb_packet_setup(&ehci->ipacket, pid, ep);
1458 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1459 ret = usb_handle_packet(dev, &ehci->ipacket);
1460 assert(ret != USB_RET_ASYNC);
1461 usb_packet_unmap(&ehci->ipacket);
1462 } else {
1463 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1464 ret = USB_RET_NAK;
1465 }
1466 qemu_sglist_destroy(&ehci->isgl);
1467
1468 if (ret < 0) {
1469 switch (ret) {
1470 default:
1471 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1472 /* Fall through */
1473 case USB_RET_IOERROR:
1474 case USB_RET_NODEV:
1475 /* 3.3.2: XACTERR is only allowed on IN transactions */
1476 if (dir) {
1477 itd->transact[i] |= ITD_XACT_XACTERR;
1478 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1479 }
1480 break;
1481 case USB_RET_BABBLE:
1482 itd->transact[i] |= ITD_XACT_BABBLE;
1483 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1484 break;
1485 case USB_RET_NAK:
1486 /* no data for us, so do a zero-length transfer */
1487 ret = 0;
1488 break;
1489 }
1490 }
1491 if (ret >= 0) {
1492 if (!dir) {
1493 /* OUT */
1494 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1495 } else {
1496 /* IN */
1497 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1498 }
1499 }
1500 if (itd->transact[i] & ITD_XACT_IOC) {
1501 ehci_record_interrupt(ehci, USBSTS_INT);
1502 }
1503 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1504 }
1505 }
1506 return 0;
1507 }
1508
1509 /* This state is the entry point for asynchronous schedule
1510 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1511 */
1512 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1513 {
1514 EHCIqh qh;
1515 int i = 0;
1516 int again = 0;
1517 uint32_t entry = ehci->asynclistaddr;
1518
1519 /* set reclamation flag at start event (4.8.6) */
1520 if (async) {
1521 ehci_set_usbsts(ehci, USBSTS_REC);
1522 }
1523
1524 ehci_queues_rip_unused(ehci, async, 0);
1525
1526 /* Find the head of the list (4.9.1.1) */
1527 for(i = 0; i < MAX_QH; i++) {
1528 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1529 sizeof(EHCIqh) >> 2);
1530 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1531
1532 if (qh.epchar & QH_EPCHAR_H) {
1533 if (async) {
1534 entry |= (NLPTR_TYPE_QH << 1);
1535 }
1536
1537 ehci_set_fetch_addr(ehci, async, entry);
1538 ehci_set_state(ehci, async, EST_FETCHENTRY);
1539 again = 1;
1540 goto out;
1541 }
1542
1543 entry = qh.next;
1544 if (entry == ehci->asynclistaddr) {
1545 break;
1546 }
1547 }
1548
1549 /* no head found for list. */
1550
1551 ehci_set_state(ehci, async, EST_ACTIVE);
1552
1553 out:
1554 return again;
1555 }
1556
1557
1558 /* This state is the entry point for periodic schedule processing as
1559 * well as being a continuation state for async processing.
1560 */
1561 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1562 {
1563 int again = 0;
1564 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1565
1566 if (NLPTR_TBIT(entry)) {
1567 ehci_set_state(ehci, async, EST_ACTIVE);
1568 goto out;
1569 }
1570
1571 /* section 4.8, only QH in async schedule */
1572 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1573 fprintf(stderr, "non queue head request in async schedule\n");
1574 return -1;
1575 }
1576
1577 switch (NLPTR_TYPE_GET(entry)) {
1578 case NLPTR_TYPE_QH:
1579 ehci_set_state(ehci, async, EST_FETCHQH);
1580 again = 1;
1581 break;
1582
1583 case NLPTR_TYPE_ITD:
1584 ehci_set_state(ehci, async, EST_FETCHITD);
1585 again = 1;
1586 break;
1587
1588 case NLPTR_TYPE_STITD:
1589 ehci_set_state(ehci, async, EST_FETCHSITD);
1590 again = 1;
1591 break;
1592
1593 default:
1594 /* TODO: handle FSTN type */
1595 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1596 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1597 return -1;
1598 }
1599
1600 out:
1601 return again;
1602 }
1603
1604 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1605 {
1606 uint32_t entry;
1607 EHCIQueue *q;
1608
1609 entry = ehci_get_fetch_addr(ehci, async);
1610 q = ehci_find_queue_by_qh(ehci, entry, async);
1611 if (NULL == q) {
1612 q = ehci_alloc_queue(ehci, async);
1613 }
1614 q->qhaddr = entry;
1615 q->seen++;
1616
1617 if (q->seen > 1) {
1618 /* we are going in circles -- stop processing */
1619 ehci_set_state(ehci, async, EST_ACTIVE);
1620 q = NULL;
1621 goto out;
1622 }
1623
1624 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1625 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1626 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1627
1628 if (q->async == EHCI_ASYNC_INFLIGHT) {
1629 /* I/O still in progress -- skip queue */
1630 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1631 goto out;
1632 }
1633 if (q->async == EHCI_ASYNC_FINISHED) {
1634 /* I/O finished -- continue processing queue */
1635 trace_usb_ehci_queue_action(q, "resume");
1636 ehci_set_state(ehci, async, EST_EXECUTING);
1637 goto out;
1638 }
1639
1640 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1641
1642 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1643 if (ehci->usbsts & USBSTS_REC) {
1644 ehci_clear_usbsts(ehci, USBSTS_REC);
1645 } else {
1646 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1647 " - done processing\n", q->qhaddr);
1648 ehci_set_state(ehci, async, EST_ACTIVE);
1649 q = NULL;
1650 goto out;
1651 }
1652 }
1653
1654 #if EHCI_DEBUG
1655 if (q->qhaddr != q->qh.next) {
1656 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1657 q->qhaddr,
1658 q->qh.epchar & QH_EPCHAR_H,
1659 q->qh.token & QTD_TOKEN_HALT,
1660 q->qh.token & QTD_TOKEN_ACTIVE,
1661 q->qh.next);
1662 }
1663 #endif
1664
1665 if (q->qh.token & QTD_TOKEN_HALT) {
1666 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1667
1668 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1669 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1670 q->qtdaddr = q->qh.current_qtd;
1671 ehci_set_state(ehci, async, EST_FETCHQTD);
1672
1673 } else {
1674 /* EHCI spec version 1.0 Section 4.10.2 */
1675 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1676 }
1677
1678 out:
1679 return q;
1680 }
1681
1682 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1683 {
1684 uint32_t entry;
1685 EHCIitd itd;
1686
1687 assert(!async);
1688 entry = ehci_get_fetch_addr(ehci, async);
1689
1690 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1691 sizeof(EHCIitd) >> 2);
1692 ehci_trace_itd(ehci, entry, &itd);
1693
1694 if (ehci_process_itd(ehci, &itd) != 0) {
1695 return -1;
1696 }
1697
1698 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1699 sizeof(EHCIitd) >> 2);
1700 ehci_set_fetch_addr(ehci, async, itd.next);
1701 ehci_set_state(ehci, async, EST_FETCHENTRY);
1702
1703 return 1;
1704 }
1705
1706 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1707 {
1708 uint32_t entry;
1709 EHCIsitd sitd;
1710
1711 assert(!async);
1712 entry = ehci_get_fetch_addr(ehci, async);
1713
1714 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1715 sizeof(EHCIsitd) >> 2);
1716 ehci_trace_sitd(ehci, entry, &sitd);
1717
1718 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1719 /* siTD is not active, nothing to do */;
1720 } else {
1721 /* TODO: split transfers are not implemented */
1722 fprintf(stderr, "WARNING: Skipping active siTD\n");
1723 }
1724
1725 ehci_set_fetch_addr(ehci, async, sitd.next);
1726 ehci_set_state(ehci, async, EST_FETCHENTRY);
1727 return 1;
1728 }
1729
1730 /* Section 4.10.2 - paragraph 3 */
1731 static int ehci_state_advqueue(EHCIQueue *q, int async)
1732 {
1733 #if 0
1734 /* TO-DO: 4.10.2 - paragraph 2
1735 * if I-bit is set to 1 and QH is not active
1736 * go to horizontal QH
1737 */
1738 if (I-bit set) {
1739 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1740 goto out;
1741 }
1742 #endif
1743
1744 /*
1745 * want data and alt-next qTD is valid
1746 */
1747 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1748 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1749 q->qtdaddr = q->qh.altnext_qtd;
1750 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1751
1752 /*
1753 * next qTD is valid
1754 */
1755 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1756 q->qtdaddr = q->qh.next_qtd;
1757 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1758
1759 /*
1760 * no valid qTD, try next QH
1761 */
1762 } else {
1763 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1764 }
1765
1766 return 1;
1767 }
1768
1769 /* Section 4.10.2 - paragraph 4 */
1770 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1771 {
1772 int again = 0;
1773
1774 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qtd,
1775 sizeof(EHCIqtd) >> 2);
1776 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1777
1778 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1779 ehci_set_state(q->ehci, async, EST_EXECUTE);
1780 again = 1;
1781 } else {
1782 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1783 again = 1;
1784 }
1785
1786 return again;
1787 }
1788
1789 static int ehci_state_horizqh(EHCIQueue *q, int async)
1790 {
1791 int again = 0;
1792
1793 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1794 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1795 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1796 again = 1;
1797 } else {
1798 ehci_set_state(q->ehci, async, EST_ACTIVE);
1799 }
1800
1801 return again;
1802 }
1803
1804 /*
1805 * Write the qh back to guest physical memory. This step isn't
1806 * in the EHCI spec but we need to do it since we don't share
1807 * physical memory with our guest VM.
1808 *
1809 * The first three dwords are read-only for the EHCI, so skip them
1810 * when writing back the qh.
1811 */
1812 static void ehci_flush_qh(EHCIQueue *q)
1813 {
1814 uint32_t *qh = (uint32_t *) &q->qh;
1815 uint32_t dwords = sizeof(EHCIqh) >> 2;
1816 uint32_t addr = NLPTR_GET(q->qhaddr);
1817
1818 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1819 }
1820
1821 static int ehci_state_execute(EHCIQueue *q, int async)
1822 {
1823 int again = 0;
1824
1825 if (ehci_qh_do_overlay(q) != 0) {
1826 return -1;
1827 }
1828
1829 // TODO verify enough time remains in the uframe as in 4.4.1.1
1830 // TODO write back ptr to async list when done or out of time
1831 // TODO Windows does not seem to ever set the MULT field
1832
1833 if (!async) {
1834 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1835 if (!transactCtr) {
1836 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1837 again = 1;
1838 goto out;
1839 }
1840 }
1841
1842 if (async) {
1843 ehci_set_usbsts(q->ehci, USBSTS_REC);
1844 }
1845
1846 q->usb_status = ehci_execute(q);
1847 if (q->usb_status == USB_RET_PROCERR) {
1848 again = -1;
1849 goto out;
1850 }
1851 if (q->usb_status == USB_RET_ASYNC) {
1852 ehci_flush_qh(q);
1853 trace_usb_ehci_queue_action(q, "suspend");
1854 q->async = EHCI_ASYNC_INFLIGHT;
1855 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1856 again = 1;
1857 goto out;
1858 }
1859
1860 ehci_set_state(q->ehci, async, EST_EXECUTING);
1861 again = 1;
1862
1863 out:
1864 return again;
1865 }
1866
1867 static int ehci_state_executing(EHCIQueue *q, int async)
1868 {
1869 int again = 0;
1870
1871 ehci_execute_complete(q);
1872 if (q->usb_status == USB_RET_ASYNC) {
1873 goto out;
1874 }
1875 if (q->usb_status == USB_RET_PROCERR) {
1876 again = -1;
1877 goto out;
1878 }
1879
1880 // 4.10.3
1881 if (!async) {
1882 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1883 transactCtr--;
1884 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1885 // 4.10.3, bottom of page 82, should exit this state when transaction
1886 // counter decrements to 0
1887 }
1888
1889 /* 4.10.5 */
1890 if (q->usb_status == USB_RET_NAK) {
1891 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1892 } else {
1893 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1894 }
1895
1896 again = 1;
1897
1898 out:
1899 ehci_flush_qh(q);
1900 return again;
1901 }
1902
1903
1904 static int ehci_state_writeback(EHCIQueue *q, int async)
1905 {
1906 int again = 0;
1907
1908 /* Write back the QTD from the QH area */
1909 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1910 put_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qh.next_qtd,
1911 sizeof(EHCIqtd) >> 2);
1912
1913 /*
1914 * EHCI specs say go horizontal here.
1915 *
1916 * We can also advance the queue here for performance reasons. We
1917 * need to take care to only take that shortcut in case we've
1918 * processed the qtd just written back without errors, i.e. halt
1919 * bit is clear.
1920 */
1921 if (q->qh.token & QTD_TOKEN_HALT) {
1922 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1923 again = 1;
1924 } else {
1925 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1926 again = 1;
1927 }
1928 return again;
1929 }
1930
1931 /*
1932 * This is the state machine that is common to both async and periodic
1933 */
1934
1935 static void ehci_advance_state(EHCIState *ehci,
1936 int async)
1937 {
1938 EHCIQueue *q = NULL;
1939 int again;
1940 int iter = 0;
1941
1942 do {
1943 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1944 iter++;
1945 /* if we are roaming a lot of QH without executing a qTD
1946 * something is wrong with the linked list. TO-DO: why is
1947 * this hack needed?
1948 */
1949 assert(iter < MAX_ITERATIONS);
1950 #if 0
1951 if (iter > MAX_ITERATIONS) {
1952 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1953 ehci_set_state(ehci, async, EST_ACTIVE);
1954 break;
1955 }
1956 #endif
1957 }
1958 switch(ehci_get_state(ehci, async)) {
1959 case EST_WAITLISTHEAD:
1960 again = ehci_state_waitlisthead(ehci, async);
1961 break;
1962
1963 case EST_FETCHENTRY:
1964 again = ehci_state_fetchentry(ehci, async);
1965 break;
1966
1967 case EST_FETCHQH:
1968 q = ehci_state_fetchqh(ehci, async);
1969 again = q ? 1 : 0;
1970 break;
1971
1972 case EST_FETCHITD:
1973 again = ehci_state_fetchitd(ehci, async);
1974 break;
1975
1976 case EST_FETCHSITD:
1977 again = ehci_state_fetchsitd(ehci, async);
1978 break;
1979
1980 case EST_ADVANCEQUEUE:
1981 again = ehci_state_advqueue(q, async);
1982 break;
1983
1984 case EST_FETCHQTD:
1985 again = ehci_state_fetchqtd(q, async);
1986 break;
1987
1988 case EST_HORIZONTALQH:
1989 again = ehci_state_horizqh(q, async);
1990 break;
1991
1992 case EST_EXECUTE:
1993 iter = 0;
1994 again = ehci_state_execute(q, async);
1995 break;
1996
1997 case EST_EXECUTING:
1998 assert(q != NULL);
1999 again = ehci_state_executing(q, async);
2000 break;
2001
2002 case EST_WRITEBACK:
2003 assert(q != NULL);
2004 again = ehci_state_writeback(q, async);
2005 break;
2006
2007 default:
2008 fprintf(stderr, "Bad state!\n");
2009 again = -1;
2010 assert(0);
2011 break;
2012 }
2013
2014 if (again < 0) {
2015 fprintf(stderr, "processing error - resetting ehci HC\n");
2016 ehci_reset(ehci);
2017 again = 0;
2018 assert(0);
2019 }
2020 }
2021 while (again);
2022
2023 ehci_commit_interrupt(ehci);
2024 }
2025
2026 static void ehci_advance_async_state(EHCIState *ehci)
2027 {
2028 const int async = 1;
2029
2030 switch(ehci_get_state(ehci, async)) {
2031 case EST_INACTIVE:
2032 if (!(ehci->usbcmd & USBCMD_ASE)) {
2033 break;
2034 }
2035 ehci_set_usbsts(ehci, USBSTS_ASS);
2036 ehci_set_state(ehci, async, EST_ACTIVE);
2037 // No break, fall through to ACTIVE
2038
2039 case EST_ACTIVE:
2040 if ( !(ehci->usbcmd & USBCMD_ASE)) {
2041 ehci_queues_rip_all(ehci, async);
2042 ehci_clear_usbsts(ehci, USBSTS_ASS);
2043 ehci_set_state(ehci, async, EST_INACTIVE);
2044 break;
2045 }
2046
2047 /* make sure guest has acknowledged the doorbell interrupt */
2048 /* TO-DO: is this really needed? */
2049 if (ehci->usbsts & USBSTS_IAA) {
2050 DPRINTF("IAA status bit still set.\n");
2051 break;
2052 }
2053
2054 /* check that address register has been set */
2055 if (ehci->asynclistaddr == 0) {
2056 break;
2057 }
2058
2059 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2060 ehci_advance_state(ehci, async);
2061
2062 /* If the doorbell is set, the guest wants to make a change to the
2063 * schedule. The host controller needs to release cached data.
2064 * (section 4.8.2)
2065 */
2066 if (ehci->usbcmd & USBCMD_IAAD) {
2067 /* Remove all unseen qhs from the async qhs queue */
2068 ehci_queues_rip_unused(ehci, async, 1);
2069 DPRINTF("ASYNC: doorbell request acknowledged\n");
2070 ehci->usbcmd &= ~USBCMD_IAAD;
2071 ehci_set_interrupt(ehci, USBSTS_IAA);
2072 }
2073 break;
2074
2075 default:
2076 /* this should only be due to a developer mistake */
2077 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2078 "Resetting to active\n", ehci->astate);
2079 assert(0);
2080 }
2081 }
2082
2083 static void ehci_advance_periodic_state(EHCIState *ehci)
2084 {
2085 uint32_t entry;
2086 uint32_t list;
2087 const int async = 0;
2088
2089 // 4.6
2090
2091 switch(ehci_get_state(ehci, async)) {
2092 case EST_INACTIVE:
2093 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2094 ehci_set_usbsts(ehci, USBSTS_PSS);
2095 ehci_set_state(ehci, async, EST_ACTIVE);
2096 // No break, fall through to ACTIVE
2097 } else
2098 break;
2099
2100 case EST_ACTIVE:
2101 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2102 ehci_queues_rip_all(ehci, async);
2103 ehci_clear_usbsts(ehci, USBSTS_PSS);
2104 ehci_set_state(ehci, async, EST_INACTIVE);
2105 break;
2106 }
2107
2108 list = ehci->periodiclistbase & 0xfffff000;
2109 /* check that register has been set */
2110 if (list == 0) {
2111 break;
2112 }
2113 list |= ((ehci->frindex & 0x1ff8) >> 1);
2114
2115 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2116 entry = le32_to_cpu(entry);
2117
2118 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2119 ehci->frindex / 8, list, entry);
2120 ehci_set_fetch_addr(ehci, async,entry);
2121 ehci_set_state(ehci, async, EST_FETCHENTRY);
2122 ehci_advance_state(ehci, async);
2123 ehci_queues_rip_unused(ehci, async, 0);
2124 break;
2125
2126 default:
2127 /* this should only be due to a developer mistake */
2128 fprintf(stderr, "ehci: Bad periodic state %d. "
2129 "Resetting to active\n", ehci->pstate);
2130 assert(0);
2131 }
2132 }
2133
2134 static void ehci_frame_timer(void *opaque)
2135 {
2136 EHCIState *ehci = opaque;
2137 int64_t expire_time, t_now;
2138 uint64_t ns_elapsed;
2139 int frames;
2140 int i;
2141 int skipped_frames = 0;
2142
2143 t_now = qemu_get_clock_ns(vm_clock);
2144 expire_time = t_now + (get_ticks_per_sec() / ehci->freq);
2145
2146 ns_elapsed = t_now - ehci->last_run_ns;
2147 frames = ns_elapsed / FRAME_TIMER_NS;
2148
2149 for (i = 0; i < frames; i++) {
2150 if ( !(ehci->usbsts & USBSTS_HALT)) {
2151 ehci->frindex += 8;
2152
2153 if (ehci->frindex > 0x00001fff) {
2154 ehci->frindex = 0;
2155 ehci_set_interrupt(ehci, USBSTS_FLR);
2156 }
2157
2158 ehci->sofv = (ehci->frindex - 1) >> 3;
2159 ehci->sofv &= 0x000003ff;
2160 }
2161
2162 if (frames - i > ehci->maxframes) {
2163 skipped_frames++;
2164 } else {
2165 ehci_advance_periodic_state(ehci);
2166 }
2167
2168 ehci->last_run_ns += FRAME_TIMER_NS;
2169 }
2170
2171 #if 0
2172 if (skipped_frames) {
2173 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2174 }
2175 #endif
2176
2177 /* Async is not inside loop since it executes everything it can once
2178 * called
2179 */
2180 ehci_advance_async_state(ehci);
2181
2182 qemu_mod_timer(ehci->frame_timer, expire_time);
2183 }
2184
2185
2186 static const MemoryRegionOps ehci_mem_ops = {
2187 .old_mmio = {
2188 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2189 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2190 },
2191 .endianness = DEVICE_LITTLE_ENDIAN,
2192 };
2193
2194 static int usb_ehci_initfn(PCIDevice *dev);
2195
2196 static USBPortOps ehci_port_ops = {
2197 .attach = ehci_attach,
2198 .detach = ehci_detach,
2199 .child_detach = ehci_child_detach,
2200 .wakeup = ehci_wakeup,
2201 .complete = ehci_async_complete_packet,
2202 };
2203
2204 static USBBusOps ehci_bus_ops = {
2205 .register_companion = ehci_register_companion,
2206 };
2207
2208 static const VMStateDescription vmstate_ehci = {
2209 .name = "ehci",
2210 .unmigratable = 1,
2211 };
2212
2213 static Property ehci_properties[] = {
2214 DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ),
2215 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2216 DEFINE_PROP_END_OF_LIST(),
2217 };
2218
2219 static void ehci_class_init(ObjectClass *klass, void *data)
2220 {
2221 DeviceClass *dc = DEVICE_CLASS(klass);
2222 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2223
2224 k->init = usb_ehci_initfn;
2225 k->vendor_id = PCI_VENDOR_ID_INTEL;
2226 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2227 k->revision = 0x10;
2228 k->class_id = PCI_CLASS_SERIAL_USB;
2229 dc->vmsd = &vmstate_ehci;
2230 dc->props = ehci_properties;
2231 }
2232
2233 static TypeInfo ehci_info = {
2234 .name = "usb-ehci",
2235 .parent = TYPE_PCI_DEVICE,
2236 .instance_size = sizeof(EHCIState),
2237 .class_init = ehci_class_init,
2238 };
2239
2240 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2241 {
2242 DeviceClass *dc = DEVICE_CLASS(klass);
2243 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2244
2245 k->init = usb_ehci_initfn;
2246 k->vendor_id = PCI_VENDOR_ID_INTEL;
2247 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2248 k->revision = 0x03;
2249 k->class_id = PCI_CLASS_SERIAL_USB;
2250 dc->vmsd = &vmstate_ehci;
2251 dc->props = ehci_properties;
2252 }
2253
2254 static TypeInfo ich9_ehci_info = {
2255 .name = "ich9-usb-ehci1",
2256 .parent = TYPE_PCI_DEVICE,
2257 .instance_size = sizeof(EHCIState),
2258 .class_init = ich9_ehci_class_init,
2259 };
2260
2261 static int usb_ehci_initfn(PCIDevice *dev)
2262 {
2263 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2264 uint8_t *pci_conf = s->dev.config;
2265 int i;
2266
2267 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2268
2269 /* capabilities pointer */
2270 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2271 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2272
2273 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2274 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2275 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2276
2277 // pci_conf[0x50] = 0x01; // power management caps
2278
2279 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2280 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2281 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2282
2283 pci_conf[0x64] = 0x00;
2284 pci_conf[0x65] = 0x00;
2285 pci_conf[0x66] = 0x00;
2286 pci_conf[0x67] = 0x00;
2287 pci_conf[0x68] = 0x01;
2288 pci_conf[0x69] = 0x00;
2289 pci_conf[0x6a] = 0x00;
2290 pci_conf[0x6b] = 0x00; // USBLEGSUP
2291 pci_conf[0x6c] = 0x00;
2292 pci_conf[0x6d] = 0x00;
2293 pci_conf[0x6e] = 0x00;
2294 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2295
2296 // 2.2 host controller interface version
2297 s->mmio[0x00] = (uint8_t) OPREGBASE;
2298 s->mmio[0x01] = 0x00;
2299 s->mmio[0x02] = 0x00;
2300 s->mmio[0x03] = 0x01; // HC version
2301 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2302 s->mmio[0x05] = 0x00; // No companion ports at present
2303 s->mmio[0x06] = 0x00;
2304 s->mmio[0x07] = 0x00;
2305 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2306 s->mmio[0x09] = 0x68; // EECP
2307 s->mmio[0x0a] = 0x00;
2308 s->mmio[0x0b] = 0x00;
2309
2310 s->irq = s->dev.irq[3];
2311
2312 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2313 for(i = 0; i < NB_PORTS; i++) {
2314 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2315 USB_SPEED_MASK_HIGH);
2316 s->ports[i].dev = 0;
2317 }
2318
2319 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2320 QTAILQ_INIT(&s->aqueues);
2321 QTAILQ_INIT(&s->pqueues);
2322
2323 qemu_register_reset(ehci_reset, s);
2324
2325 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2326 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2327
2328 return 0;
2329 }
2330
2331 static void ehci_register_types(void)
2332 {
2333 type_register_static(&ehci_info);
2334 type_register_static(&ich9_ehci_info);
2335 }
2336
2337 type_init(ehci_register_types)
2338
2339 /*
2340 * vim: expandtab ts=4
2341 */
Qemu copy for testing