]> git.proxmox.com Git - qemu.git/blob - hw/usb/hcd-ehci.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'quintela/migration-anthony-v2' into staging
[qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw/hw.h"
26 #include "qemu-timer.h"
27 #include "hw/usb.h"
28 #include "hw/pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
137
138 /* Internal periodic / asynchronous schedule state machine states
139 */
140 typedef enum {
141 EST_INACTIVE = 1000,
142 EST_ACTIVE,
143 EST_EXECUTING,
144 EST_SLEEPING,
145 /* The following states are internal to the state machine function
146 */
147 EST_WAITLISTHEAD,
148 EST_FETCHENTRY,
149 EST_FETCHQH,
150 EST_FETCHITD,
151 EST_FETCHSITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIPacket EHCIPacket;
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIPacket {
348 EHCIQueue *queue;
349 QTAILQ_ENTRY(EHCIPacket) next;
350
351 EHCIqtd qtd; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr; /* address QTD read from */
353
354 USBPacket packet;
355 QEMUSGList sgl;
356 int pid;
357 uint32_t tbytes;
358 enum async_state async;
359 int usb_status;
360 };
361
362 struct EHCIQueue {
363 EHCIState *ehci;
364 QTAILQ_ENTRY(EHCIQueue) next;
365 uint32_t seen;
366 uint64_t ts;
367 int async;
368 int revalidate;
369
370 /* cached data from guest - needs to be flushed
371 * when guest removes an entry (doorbell, handshake sequence)
372 */
373 EHCIqh qh; /* copy of current QH (being worked on) */
374 uint32_t qhaddr; /* address QH read from */
375 uint32_t qtdaddr; /* address QTD read from */
376 USBDevice *dev;
377 QTAILQ_HEAD(, EHCIPacket) packets;
378 };
379
380 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
381
382 struct EHCIState {
383 PCIDevice dev;
384 USBBus bus;
385 qemu_irq irq;
386 MemoryRegion mem;
387 int companion_count;
388
389 /* properties */
390 uint32_t maxframes;
391
392 /*
393 * EHCI spec version 1.0 Section 2.3
394 * Host Controller Operational Registers
395 */
396 union {
397 uint8_t mmio[MMIO_SIZE];
398 struct {
399 uint8_t cap[OPREGBASE];
400 uint32_t usbcmd;
401 uint32_t usbsts;
402 uint32_t usbintr;
403 uint32_t frindex;
404 uint32_t ctrldssegment;
405 uint32_t periodiclistbase;
406 uint32_t asynclistaddr;
407 uint32_t notused[9];
408 uint32_t configflag;
409 uint32_t portsc[NB_PORTS];
410 };
411 };
412
413 /*
414 * Internal states, shadow registers, etc
415 */
416 QEMUTimer *frame_timer;
417 QEMUBH *async_bh;
418 uint32_t astate; /* Current state in asynchronous schedule */
419 uint32_t pstate; /* Current state in periodic schedule */
420 USBPort ports[NB_PORTS];
421 USBPort *companion_ports[NB_PORTS];
422 uint32_t usbsts_pending;
423 EHCIQueueHead aqueues;
424 EHCIQueueHead pqueues;
425
426 /* which address to look at next */
427 uint32_t a_fetch_addr;
428 uint32_t p_fetch_addr;
429
430 USBPacket ipacket;
431 QEMUSGList isgl;
432
433 uint64_t last_run_ns;
434 uint32_t async_stepdown;
435 };
436
437 #define SET_LAST_RUN_CLOCK(s) \
438 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
439
440 /* nifty macros from Arnon's EHCI version */
441 #define get_field(data, field) \
442 (((data) & field##_MASK) >> field##_SH)
443
444 #define set_field(data, newval, field) do { \
445 uint32_t val = *data; \
446 val &= ~ field##_MASK; \
447 val |= ((newval) << field##_SH) & field##_MASK; \
448 *data = val; \
449 } while(0)
450
451 static const char *ehci_state_names[] = {
452 [EST_INACTIVE] = "INACTIVE",
453 [EST_ACTIVE] = "ACTIVE",
454 [EST_EXECUTING] = "EXECUTING",
455 [EST_SLEEPING] = "SLEEPING",
456 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
457 [EST_FETCHENTRY] = "FETCH ENTRY",
458 [EST_FETCHQH] = "FETCH QH",
459 [EST_FETCHITD] = "FETCH ITD",
460 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
461 [EST_FETCHQTD] = "FETCH QTD",
462 [EST_EXECUTE] = "EXECUTE",
463 [EST_WRITEBACK] = "WRITEBACK",
464 [EST_HORIZONTALQH] = "HORIZONTALQH",
465 };
466
467 static const char *ehci_mmio_names[] = {
468 [CAPLENGTH] = "CAPLENGTH",
469 [HCIVERSION] = "HCIVERSION",
470 [HCSPARAMS] = "HCSPARAMS",
471 [HCCPARAMS] = "HCCPARAMS",
472 [USBCMD] = "USBCMD",
473 [USBSTS] = "USBSTS",
474 [USBINTR] = "USBINTR",
475 [FRINDEX] = "FRINDEX",
476 [PERIODICLISTBASE] = "P-LIST BASE",
477 [ASYNCLISTADDR] = "A-LIST ADDR",
478 [PORTSC_BEGIN] = "PORTSC #0",
479 [PORTSC_BEGIN + 4] = "PORTSC #1",
480 [PORTSC_BEGIN + 8] = "PORTSC #2",
481 [PORTSC_BEGIN + 12] = "PORTSC #3",
482 [PORTSC_BEGIN + 16] = "PORTSC #4",
483 [PORTSC_BEGIN + 20] = "PORTSC #5",
484 [CONFIGFLAG] = "CONFIGFLAG",
485 };
486
487 static const char *nr2str(const char **n, size_t len, uint32_t nr)
488 {
489 if (nr < len && n[nr] != NULL) {
490 return n[nr];
491 } else {
492 return "unknown";
493 }
494 }
495
496 static const char *state2str(uint32_t state)
497 {
498 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
499 }
500
501 static const char *addr2str(target_phys_addr_t addr)
502 {
503 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
504 }
505
506 static void ehci_trace_usbsts(uint32_t mask, int state)
507 {
508 /* interrupts */
509 if (mask & USBSTS_INT) {
510 trace_usb_ehci_usbsts("INT", state);
511 }
512 if (mask & USBSTS_ERRINT) {
513 trace_usb_ehci_usbsts("ERRINT", state);
514 }
515 if (mask & USBSTS_PCD) {
516 trace_usb_ehci_usbsts("PCD", state);
517 }
518 if (mask & USBSTS_FLR) {
519 trace_usb_ehci_usbsts("FLR", state);
520 }
521 if (mask & USBSTS_HSE) {
522 trace_usb_ehci_usbsts("HSE", state);
523 }
524 if (mask & USBSTS_IAA) {
525 trace_usb_ehci_usbsts("IAA", state);
526 }
527
528 /* status */
529 if (mask & USBSTS_HALT) {
530 trace_usb_ehci_usbsts("HALT", state);
531 }
532 if (mask & USBSTS_REC) {
533 trace_usb_ehci_usbsts("REC", state);
534 }
535 if (mask & USBSTS_PSS) {
536 trace_usb_ehci_usbsts("PSS", state);
537 }
538 if (mask & USBSTS_ASS) {
539 trace_usb_ehci_usbsts("ASS", state);
540 }
541 }
542
543 static inline void ehci_set_usbsts(EHCIState *s, int mask)
544 {
545 if ((s->usbsts & mask) == mask) {
546 return;
547 }
548 ehci_trace_usbsts(mask, 1);
549 s->usbsts |= mask;
550 }
551
552 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
553 {
554 if ((s->usbsts & mask) == 0) {
555 return;
556 }
557 ehci_trace_usbsts(mask, 0);
558 s->usbsts &= ~mask;
559 }
560
561 static inline void ehci_set_interrupt(EHCIState *s, int intr)
562 {
563 int level = 0;
564
565 // TODO honour interrupt threshold requests
566
567 ehci_set_usbsts(s, intr);
568
569 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
570 level = 1;
571 }
572
573 trace_usb_ehci_interrupt(level, s->usbsts, s->usbintr);
574 qemu_set_irq(s->irq, level);
575 }
576
577 static inline void ehci_record_interrupt(EHCIState *s, int intr)
578 {
579 s->usbsts_pending |= intr;
580 }
581
582 static inline void ehci_commit_interrupt(EHCIState *s)
583 {
584 if (!s->usbsts_pending) {
585 return;
586 }
587 ehci_set_interrupt(s, s->usbsts_pending);
588 s->usbsts_pending = 0;
589 }
590
591 static void ehci_update_halt(EHCIState *s)
592 {
593 if (s->usbcmd & USBCMD_RUNSTOP) {
594 ehci_clear_usbsts(s, USBSTS_HALT);
595 } else {
596 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
597 ehci_set_usbsts(s, USBSTS_HALT);
598 }
599 }
600 }
601
602 static void ehci_set_state(EHCIState *s, int async, int state)
603 {
604 if (async) {
605 trace_usb_ehci_state("async", state2str(state));
606 s->astate = state;
607 if (s->astate == EST_INACTIVE) {
608 ehci_clear_usbsts(s, USBSTS_ASS);
609 ehci_update_halt(s);
610 } else {
611 ehci_set_usbsts(s, USBSTS_ASS);
612 }
613 } else {
614 trace_usb_ehci_state("periodic", state2str(state));
615 s->pstate = state;
616 if (s->pstate == EST_INACTIVE) {
617 ehci_clear_usbsts(s, USBSTS_PSS);
618 ehci_update_halt(s);
619 } else {
620 ehci_set_usbsts(s, USBSTS_PSS);
621 }
622 }
623 }
624
625 static int ehci_get_state(EHCIState *s, int async)
626 {
627 return async ? s->astate : s->pstate;
628 }
629
630 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
631 {
632 if (async) {
633 s->a_fetch_addr = addr;
634 } else {
635 s->p_fetch_addr = addr;
636 }
637 }
638
639 static int ehci_get_fetch_addr(EHCIState *s, int async)
640 {
641 return async ? s->a_fetch_addr : s->p_fetch_addr;
642 }
643
644 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
645 {
646 /* need three here due to argument count limits */
647 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
648 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
649 trace_usb_ehci_qh_fields(addr,
650 get_field(qh->epchar, QH_EPCHAR_RL),
651 get_field(qh->epchar, QH_EPCHAR_MPLEN),
652 get_field(qh->epchar, QH_EPCHAR_EPS),
653 get_field(qh->epchar, QH_EPCHAR_EP),
654 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
655 trace_usb_ehci_qh_bits(addr,
656 (bool)(qh->epchar & QH_EPCHAR_C),
657 (bool)(qh->epchar & QH_EPCHAR_H),
658 (bool)(qh->epchar & QH_EPCHAR_DTC),
659 (bool)(qh->epchar & QH_EPCHAR_I));
660 }
661
662 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
663 {
664 /* need three here due to argument count limits */
665 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
666 trace_usb_ehci_qtd_fields(addr,
667 get_field(qtd->token, QTD_TOKEN_TBYTES),
668 get_field(qtd->token, QTD_TOKEN_CPAGE),
669 get_field(qtd->token, QTD_TOKEN_CERR),
670 get_field(qtd->token, QTD_TOKEN_PID));
671 trace_usb_ehci_qtd_bits(addr,
672 (bool)(qtd->token & QTD_TOKEN_IOC),
673 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
674 (bool)(qtd->token & QTD_TOKEN_HALT),
675 (bool)(qtd->token & QTD_TOKEN_BABBLE),
676 (bool)(qtd->token & QTD_TOKEN_XACTERR));
677 }
678
679 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
680 {
681 trace_usb_ehci_itd(addr, itd->next,
682 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
683 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
684 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
685 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
686 }
687
688 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
689 EHCIsitd *sitd)
690 {
691 trace_usb_ehci_sitd(addr, sitd->next,
692 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
693 }
694
695 static inline bool ehci_enabled(EHCIState *s)
696 {
697 return s->usbcmd & USBCMD_RUNSTOP;
698 }
699
700 static inline bool ehci_async_enabled(EHCIState *s)
701 {
702 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
703 }
704
705 static inline bool ehci_periodic_enabled(EHCIState *s)
706 {
707 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
708 }
709
710 /* packet management */
711
712 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
713 {
714 EHCIPacket *p;
715
716 p = g_new0(EHCIPacket, 1);
717 p->queue = q;
718 usb_packet_init(&p->packet);
719 QTAILQ_INSERT_TAIL(&q->packets, p, next);
720 trace_usb_ehci_packet_action(p->queue, p, "alloc");
721 return p;
722 }
723
724 static void ehci_free_packet(EHCIPacket *p)
725 {
726 trace_usb_ehci_packet_action(p->queue, p, "free");
727 if (p->async == EHCI_ASYNC_INFLIGHT) {
728 usb_cancel_packet(&p->packet);
729 }
730 QTAILQ_REMOVE(&p->queue->packets, p, next);
731 usb_packet_cleanup(&p->packet);
732 g_free(p);
733 }
734
735 /* queue management */
736
737 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
738 {
739 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
740 EHCIQueue *q;
741
742 q = g_malloc0(sizeof(*q));
743 q->ehci = ehci;
744 q->qhaddr = addr;
745 q->async = async;
746 QTAILQ_INIT(&q->packets);
747 QTAILQ_INSERT_HEAD(head, q, next);
748 trace_usb_ehci_queue_action(q, "alloc");
749 return q;
750 }
751
752 static void ehci_free_queue(EHCIQueue *q)
753 {
754 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
755 EHCIPacket *p;
756
757 trace_usb_ehci_queue_action(q, "free");
758 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
759 ehci_free_packet(p);
760 }
761 QTAILQ_REMOVE(head, q, next);
762 g_free(q);
763 }
764
765 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
766 int async)
767 {
768 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
769 EHCIQueue *q;
770
771 QTAILQ_FOREACH(q, head, next) {
772 if (addr == q->qhaddr) {
773 return q;
774 }
775 }
776 return NULL;
777 }
778
779 static void ehci_queues_tag_unused_async(EHCIState *ehci)
780 {
781 EHCIQueue *q;
782
783 QTAILQ_FOREACH(q, &ehci->aqueues, next) {
784 if (!q->seen) {
785 q->revalidate = 1;
786 }
787 }
788 }
789
790 static void ehci_queues_rip_unused(EHCIState *ehci, int async)
791 {
792 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
793 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
794 EHCIQueue *q, *tmp;
795
796 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
797 if (q->seen) {
798 q->seen = 0;
799 q->ts = ehci->last_run_ns;
800 continue;
801 }
802 if (ehci->last_run_ns < q->ts + maxage) {
803 continue;
804 }
805 ehci_free_queue(q);
806 }
807 }
808
809 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
810 {
811 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
812 EHCIQueue *q, *tmp;
813
814 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
815 if (q->dev != dev) {
816 continue;
817 }
818 ehci_free_queue(q);
819 }
820 }
821
822 static void ehci_queues_rip_all(EHCIState *ehci, int async)
823 {
824 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
825 EHCIQueue *q, *tmp;
826
827 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
828 ehci_free_queue(q);
829 }
830 }
831
832 /* Attach or detach a device on root hub */
833
834 static void ehci_attach(USBPort *port)
835 {
836 EHCIState *s = port->opaque;
837 uint32_t *portsc = &s->portsc[port->index];
838 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
839
840 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
841
842 if (*portsc & PORTSC_POWNER) {
843 USBPort *companion = s->companion_ports[port->index];
844 companion->dev = port->dev;
845 companion->ops->attach(companion);
846 return;
847 }
848
849 *portsc |= PORTSC_CONNECT;
850 *portsc |= PORTSC_CSC;
851
852 ehci_set_interrupt(s, USBSTS_PCD);
853 }
854
855 static void ehci_detach(USBPort *port)
856 {
857 EHCIState *s = port->opaque;
858 uint32_t *portsc = &s->portsc[port->index];
859 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
860
861 trace_usb_ehci_port_detach(port->index, owner);
862
863 if (*portsc & PORTSC_POWNER) {
864 USBPort *companion = s->companion_ports[port->index];
865 companion->ops->detach(companion);
866 companion->dev = NULL;
867 /*
868 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
869 * the port ownership is returned immediately to the EHCI controller."
870 */
871 *portsc &= ~PORTSC_POWNER;
872 return;
873 }
874
875 ehci_queues_rip_device(s, port->dev, 0);
876 ehci_queues_rip_device(s, port->dev, 1);
877
878 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
879 *portsc |= PORTSC_CSC;
880
881 ehci_set_interrupt(s, USBSTS_PCD);
882 }
883
884 static void ehci_child_detach(USBPort *port, USBDevice *child)
885 {
886 EHCIState *s = port->opaque;
887 uint32_t portsc = s->portsc[port->index];
888
889 if (portsc & PORTSC_POWNER) {
890 USBPort *companion = s->companion_ports[port->index];
891 companion->ops->child_detach(companion, child);
892 return;
893 }
894
895 ehci_queues_rip_device(s, child, 0);
896 ehci_queues_rip_device(s, child, 1);
897 }
898
899 static void ehci_wakeup(USBPort *port)
900 {
901 EHCIState *s = port->opaque;
902 uint32_t portsc = s->portsc[port->index];
903
904 if (portsc & PORTSC_POWNER) {
905 USBPort *companion = s->companion_ports[port->index];
906 if (companion->ops->wakeup) {
907 companion->ops->wakeup(companion);
908 }
909 return;
910 }
911
912 qemu_bh_schedule(s->async_bh);
913 }
914
915 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
916 uint32_t portcount, uint32_t firstport)
917 {
918 EHCIState *s = container_of(bus, EHCIState, bus);
919 uint32_t i;
920
921 if (firstport + portcount > NB_PORTS) {
922 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
923 "firstport on masterbus");
924 error_printf_unless_qmp(
925 "firstport value of %u makes companion take ports %u - %u, which "
926 "is outside of the valid range of 0 - %u\n", firstport, firstport,
927 firstport + portcount - 1, NB_PORTS - 1);
928 return -1;
929 }
930
931 for (i = 0; i < portcount; i++) {
932 if (s->companion_ports[firstport + i]) {
933 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
934 "an USB masterbus");
935 error_printf_unless_qmp(
936 "port %u on masterbus %s already has a companion assigned\n",
937 firstport + i, bus->qbus.name);
938 return -1;
939 }
940 }
941
942 for (i = 0; i < portcount; i++) {
943 s->companion_ports[firstport + i] = ports[i];
944 s->ports[firstport + i].speedmask |=
945 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
946 /* Ensure devs attached before the initial reset go to the companion */
947 s->portsc[firstport + i] = PORTSC_POWNER;
948 }
949
950 s->companion_count++;
951 s->mmio[0x05] = (s->companion_count << 4) | portcount;
952
953 return 0;
954 }
955
956 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
957 {
958 USBDevice *dev;
959 USBPort *port;
960 int i;
961
962 for (i = 0; i < NB_PORTS; i++) {
963 port = &ehci->ports[i];
964 if (!(ehci->portsc[i] & PORTSC_PED)) {
965 DPRINTF("Port %d not enabled\n", i);
966 continue;
967 }
968 dev = usb_find_device(port, addr);
969 if (dev != NULL) {
970 return dev;
971 }
972 }
973 return NULL;
974 }
975
976 /* 4.1 host controller initialization */
977 static void ehci_reset(void *opaque)
978 {
979 EHCIState *s = opaque;
980 int i;
981 USBDevice *devs[NB_PORTS];
982
983 trace_usb_ehci_reset();
984
985 /*
986 * Do the detach before touching portsc, so that it correctly gets send to
987 * us or to our companion based on PORTSC_POWNER before the reset.
988 */
989 for(i = 0; i < NB_PORTS; i++) {
990 devs[i] = s->ports[i].dev;
991 if (devs[i] && devs[i]->attached) {
992 usb_detach(&s->ports[i]);
993 }
994 }
995
996 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
997
998 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
999 s->usbsts = USBSTS_HALT;
1000
1001 s->astate = EST_INACTIVE;
1002 s->pstate = EST_INACTIVE;
1003
1004 for(i = 0; i < NB_PORTS; i++) {
1005 if (s->companion_ports[i]) {
1006 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
1007 } else {
1008 s->portsc[i] = PORTSC_PPOWER;
1009 }
1010 if (devs[i] && devs[i]->attached) {
1011 usb_attach(&s->ports[i]);
1012 usb_device_reset(devs[i]);
1013 }
1014 }
1015 ehci_queues_rip_all(s, 0);
1016 ehci_queues_rip_all(s, 1);
1017 qemu_del_timer(s->frame_timer);
1018 qemu_bh_cancel(s->async_bh);
1019 }
1020
1021 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
1022 {
1023 EHCIState *s = ptr;
1024 uint32_t val;
1025
1026 val = s->mmio[addr];
1027
1028 return val;
1029 }
1030
1031 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
1032 {
1033 EHCIState *s = ptr;
1034 uint32_t val;
1035
1036 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
1037
1038 return val;
1039 }
1040
1041 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
1042 {
1043 EHCIState *s = ptr;
1044 uint32_t val;
1045
1046 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
1047 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
1048
1049 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
1050 return val;
1051 }
1052
1053 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
1054 {
1055 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
1056 exit(1);
1057 }
1058
1059 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
1060 {
1061 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
1062 exit(1);
1063 }
1064
1065 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
1066 {
1067 USBDevice *dev = s->ports[port].dev;
1068 uint32_t *portsc = &s->portsc[port];
1069 uint32_t orig;
1070
1071 if (s->companion_ports[port] == NULL)
1072 return;
1073
1074 owner = owner & PORTSC_POWNER;
1075 orig = *portsc & PORTSC_POWNER;
1076
1077 if (!(owner ^ orig)) {
1078 return;
1079 }
1080
1081 if (dev && dev->attached) {
1082 usb_detach(&s->ports[port]);
1083 }
1084
1085 *portsc &= ~PORTSC_POWNER;
1086 *portsc |= owner;
1087
1088 if (dev && dev->attached) {
1089 usb_attach(&s->ports[port]);
1090 }
1091 }
1092
1093 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1094 {
1095 uint32_t *portsc = &s->portsc[port];
1096 USBDevice *dev = s->ports[port].dev;
1097
1098 /* Clear rwc bits */
1099 *portsc &= ~(val & PORTSC_RWC_MASK);
1100 /* The guest may clear, but not set the PED bit */
1101 *portsc &= val | ~PORTSC_PED;
1102 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1103 handle_port_owner_write(s, port, val);
1104 /* And finally apply RO_MASK */
1105 val &= PORTSC_RO_MASK;
1106
1107 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1108 trace_usb_ehci_port_reset(port, 1);
1109 }
1110
1111 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1112 trace_usb_ehci_port_reset(port, 0);
1113 if (dev && dev->attached) {
1114 usb_port_reset(&s->ports[port]);
1115 *portsc &= ~PORTSC_CSC;
1116 }
1117
1118 /*
1119 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1120 * to SW that this port has a high speed device attached
1121 */
1122 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1123 val |= PORTSC_PED;
1124 }
1125 }
1126
1127 *portsc &= ~PORTSC_RO_MASK;
1128 *portsc |= val;
1129 }
1130
1131 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1132 {
1133 EHCIState *s = ptr;
1134 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1135 uint32_t old = *mmio;
1136 int i;
1137
1138 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1139
1140 /* Only aligned reads are allowed on OHCI */
1141 if (addr & 3) {
1142 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1143 TARGET_FMT_plx "\n", addr);
1144 return;
1145 }
1146
1147 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1148 handle_port_status_write(s, (addr-PORTSC)/4, val);
1149 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1150 return;
1151 }
1152
1153 if (addr < OPREGBASE) {
1154 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1155 TARGET_FMT_plx "\n", addr);
1156 return;
1157 }
1158
1159
1160 /* Do any register specific pre-write processing here. */
1161 switch(addr) {
1162 case USBCMD:
1163 if (val & USBCMD_HCRESET) {
1164 ehci_reset(s);
1165 val = s->usbcmd;
1166 break;
1167 }
1168
1169 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1170 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1171 if (s->pstate == EST_INACTIVE) {
1172 SET_LAST_RUN_CLOCK(s);
1173 }
1174 ehci_update_halt(s);
1175 s->async_stepdown = 0;
1176 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1177 }
1178
1179 /* not supporting dynamic frame list size at the moment */
1180 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1181 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1182 val & USBCMD_FLS);
1183 val &= ~USBCMD_FLS;
1184 }
1185 break;
1186
1187 case USBSTS:
1188 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1189 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1190 val = s->usbsts;
1191 ehci_set_interrupt(s, 0);
1192 break;
1193
1194 case USBINTR:
1195 val &= USBINTR_MASK;
1196 break;
1197
1198 case FRINDEX:
1199 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1200 break;
1201
1202 case CONFIGFLAG:
1203 val &= 0x1;
1204 if (val) {
1205 for(i = 0; i < NB_PORTS; i++)
1206 handle_port_owner_write(s, i, 0);
1207 }
1208 break;
1209
1210 case PERIODICLISTBASE:
1211 if (ehci_periodic_enabled(s)) {
1212 fprintf(stderr,
1213 "ehci: PERIODIC list base register set while periodic schedule\n"
1214 " is enabled and HC is enabled\n");
1215 }
1216 break;
1217
1218 case ASYNCLISTADDR:
1219 if (ehci_async_enabled(s)) {
1220 fprintf(stderr,
1221 "ehci: ASYNC list address register set while async schedule\n"
1222 " is enabled and HC is enabled\n");
1223 }
1224 break;
1225 }
1226
1227 *mmio = val;
1228 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1229 }
1230
1231
1232 // TODO : Put in common header file, duplication from usb-ohci.c
1233
1234 /* Get an array of dwords from main memory */
1235 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1236 uint32_t *buf, int num)
1237 {
1238 int i;
1239
1240 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1241 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1242 *buf = le32_to_cpu(*buf);
1243 }
1244
1245 return 1;
1246 }
1247
1248 /* Put an array of dwords in to main memory */
1249 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1250 uint32_t *buf, int num)
1251 {
1252 int i;
1253
1254 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1255 uint32_t tmp = cpu_to_le32(*buf);
1256 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1257 }
1258
1259 return 1;
1260 }
1261
1262 /*
1263 * Write the qh back to guest physical memory. This step isn't
1264 * in the EHCI spec but we need to do it since we don't share
1265 * physical memory with our guest VM.
1266 *
1267 * The first three dwords are read-only for the EHCI, so skip them
1268 * when writing back the qh.
1269 */
1270 static void ehci_flush_qh(EHCIQueue *q)
1271 {
1272 uint32_t *qh = (uint32_t *) &q->qh;
1273 uint32_t dwords = sizeof(EHCIqh) >> 2;
1274 uint32_t addr = NLPTR_GET(q->qhaddr);
1275
1276 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1277 }
1278
1279 // 4.10.2
1280
1281 static int ehci_qh_do_overlay(EHCIQueue *q)
1282 {
1283 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1284 int i;
1285 int dtoggle;
1286 int ping;
1287 int eps;
1288 int reload;
1289
1290 assert(p != NULL);
1291 assert(p->qtdaddr == q->qtdaddr);
1292
1293 // remember values in fields to preserve in qh after overlay
1294
1295 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1296 ping = q->qh.token & QTD_TOKEN_PING;
1297
1298 q->qh.current_qtd = p->qtdaddr;
1299 q->qh.next_qtd = p->qtd.next;
1300 q->qh.altnext_qtd = p->qtd.altnext;
1301 q->qh.token = p->qtd.token;
1302
1303
1304 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1305 if (eps == EHCI_QH_EPS_HIGH) {
1306 q->qh.token &= ~QTD_TOKEN_PING;
1307 q->qh.token |= ping;
1308 }
1309
1310 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1311 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1312
1313 for (i = 0; i < 5; i++) {
1314 q->qh.bufptr[i] = p->qtd.bufptr[i];
1315 }
1316
1317 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1318 // preserve QH DT bit
1319 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1320 q->qh.token |= dtoggle;
1321 }
1322
1323 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1324 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1325
1326 ehci_flush_qh(q);
1327
1328 return 0;
1329 }
1330
1331 static int ehci_init_transfer(EHCIPacket *p)
1332 {
1333 uint32_t cpage, offset, bytes, plen;
1334 dma_addr_t page;
1335
1336 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1337 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1338 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1339 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
1340
1341 while (bytes > 0) {
1342 if (cpage > 4) {
1343 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1344 return USB_RET_PROCERR;
1345 }
1346
1347 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1348 page += offset;
1349 plen = bytes;
1350 if (plen > 4096 - offset) {
1351 plen = 4096 - offset;
1352 offset = 0;
1353 cpage++;
1354 }
1355
1356 qemu_sglist_add(&p->sgl, page, plen);
1357 bytes -= plen;
1358 }
1359 return 0;
1360 }
1361
1362 static void ehci_finish_transfer(EHCIQueue *q, int status)
1363 {
1364 uint32_t cpage, offset;
1365
1366 if (status > 0) {
1367 /* update cpage & offset */
1368 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1369 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1370
1371 offset += status;
1372 cpage += offset >> QTD_BUFPTR_SH;
1373 offset &= ~QTD_BUFPTR_MASK;
1374
1375 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1376 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1377 q->qh.bufptr[0] |= offset;
1378 }
1379 }
1380
1381 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1382 {
1383 EHCIPacket *p;
1384 EHCIState *s = port->opaque;
1385 uint32_t portsc = s->portsc[port->index];
1386
1387 if (portsc & PORTSC_POWNER) {
1388 USBPort *companion = s->companion_ports[port->index];
1389 companion->ops->complete(companion, packet);
1390 return;
1391 }
1392
1393 p = container_of(packet, EHCIPacket, packet);
1394 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1395 assert(p->async == EHCI_ASYNC_INFLIGHT);
1396 p->async = EHCI_ASYNC_FINISHED;
1397 p->usb_status = packet->result;
1398
1399 if (p->queue->async) {
1400 qemu_bh_schedule(p->queue->ehci->async_bh);
1401 }
1402 }
1403
1404 static void ehci_execute_complete(EHCIQueue *q)
1405 {
1406 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1407
1408 assert(p != NULL);
1409 assert(p->qtdaddr == q->qtdaddr);
1410 assert(p->async != EHCI_ASYNC_INFLIGHT);
1411 p->async = EHCI_ASYNC_NONE;
1412
1413 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1414 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1415
1416 if (p->usb_status < 0) {
1417 switch (p->usb_status) {
1418 case USB_RET_IOERROR:
1419 case USB_RET_NODEV:
1420 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1421 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1422 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1423 break;
1424 case USB_RET_STALL:
1425 q->qh.token |= QTD_TOKEN_HALT;
1426 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1427 break;
1428 case USB_RET_NAK:
1429 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1430 return; /* We're not done yet with this transaction */
1431 case USB_RET_BABBLE:
1432 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1433 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1434 break;
1435 default:
1436 /* should not be triggerable */
1437 fprintf(stderr, "USB invalid response %d\n", p->usb_status);
1438 assert(0);
1439 break;
1440 }
1441 } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) {
1442 p->usb_status = USB_RET_BABBLE;
1443 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1444 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1445 } else {
1446 // TODO check 4.12 for splits
1447
1448 if (p->tbytes && p->pid == USB_TOKEN_IN) {
1449 p->tbytes -= p->usb_status;
1450 } else {
1451 p->tbytes = 0;
1452 }
1453
1454 DPRINTF("updating tbytes to %d\n", p->tbytes);
1455 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES);
1456 }
1457 ehci_finish_transfer(q, p->usb_status);
1458 usb_packet_unmap(&p->packet, &p->sgl);
1459 qemu_sglist_destroy(&p->sgl);
1460
1461 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1462 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1463
1464 if (q->qh.token & QTD_TOKEN_IOC) {
1465 ehci_record_interrupt(q->ehci, USBSTS_INT);
1466 }
1467 }
1468
1469 // 4.10.3
1470
1471 static int ehci_execute(EHCIPacket *p, const char *action)
1472 {
1473 USBEndpoint *ep;
1474 int ret;
1475 int endp;
1476
1477 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1478 fprintf(stderr, "Attempting to execute inactive qtd\n");
1479 return USB_RET_PROCERR;
1480 }
1481
1482 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1483 if (p->tbytes > BUFF_SIZE) {
1484 fprintf(stderr, "Request for more bytes than allowed\n");
1485 return USB_RET_PROCERR;
1486 }
1487
1488 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1489 switch (p->pid) {
1490 case 0:
1491 p->pid = USB_TOKEN_OUT;
1492 break;
1493 case 1:
1494 p->pid = USB_TOKEN_IN;
1495 break;
1496 case 2:
1497 p->pid = USB_TOKEN_SETUP;
1498 break;
1499 default:
1500 fprintf(stderr, "bad token\n");
1501 break;
1502 }
1503
1504 if (ehci_init_transfer(p) != 0) {
1505 return USB_RET_PROCERR;
1506 }
1507
1508 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1509 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1510
1511 usb_packet_setup(&p->packet, p->pid, ep);
1512 usb_packet_map(&p->packet, &p->sgl);
1513
1514 trace_usb_ehci_packet_action(p->queue, p, action);
1515 ret = usb_handle_packet(p->queue->dev, &p->packet);
1516 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1517 "(total %d) endp %x ret %d\n",
1518 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1519 q->packet.iov.size, q->tbytes, endp, ret);
1520
1521 if (ret > BUFF_SIZE) {
1522 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1523 return USB_RET_PROCERR;
1524 }
1525
1526 return ret;
1527 }
1528
1529 /* 4.7.2
1530 */
1531
1532 static int ehci_process_itd(EHCIState *ehci,
1533 EHCIitd *itd)
1534 {
1535 USBDevice *dev;
1536 USBEndpoint *ep;
1537 int ret;
1538 uint32_t i, len, pid, dir, devaddr, endp;
1539 uint32_t pg, off, ptr1, ptr2, max, mult;
1540
1541 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1542 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1543 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1544 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1545 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1546
1547 for(i = 0; i < 8; i++) {
1548 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1549 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1550 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1551 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1552 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1553 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1554
1555 if (len > max * mult) {
1556 len = max * mult;
1557 }
1558
1559 if (len > BUFF_SIZE) {
1560 return USB_RET_PROCERR;
1561 }
1562
1563 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1564 if (off + len > 4096) {
1565 /* transfer crosses page border */
1566 uint32_t len2 = off + len - 4096;
1567 uint32_t len1 = len - len2;
1568 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1569 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1570 } else {
1571 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1572 }
1573
1574 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1575
1576 dev = ehci_find_device(ehci, devaddr);
1577 ep = usb_ep_get(dev, pid, endp);
1578 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1579 usb_packet_setup(&ehci->ipacket, pid, ep);
1580 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1581 ret = usb_handle_packet(dev, &ehci->ipacket);
1582 assert(ret != USB_RET_ASYNC);
1583 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1584 } else {
1585 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1586 ret = USB_RET_NAK;
1587 }
1588 qemu_sglist_destroy(&ehci->isgl);
1589
1590 if (ret < 0) {
1591 switch (ret) {
1592 default:
1593 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1594 /* Fall through */
1595 case USB_RET_IOERROR:
1596 case USB_RET_NODEV:
1597 /* 3.3.2: XACTERR is only allowed on IN transactions */
1598 if (dir) {
1599 itd->transact[i] |= ITD_XACT_XACTERR;
1600 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1601 }
1602 break;
1603 case USB_RET_BABBLE:
1604 itd->transact[i] |= ITD_XACT_BABBLE;
1605 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1606 break;
1607 case USB_RET_NAK:
1608 /* no data for us, so do a zero-length transfer */
1609 ret = 0;
1610 break;
1611 }
1612 }
1613 if (ret >= 0) {
1614 if (!dir) {
1615 /* OUT */
1616 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1617 } else {
1618 /* IN */
1619 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1620 }
1621 }
1622 if (itd->transact[i] & ITD_XACT_IOC) {
1623 ehci_record_interrupt(ehci, USBSTS_INT);
1624 }
1625 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1626 }
1627 }
1628 return 0;
1629 }
1630
1631
1632 /* This state is the entry point for asynchronous schedule
1633 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1634 */
1635 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1636 {
1637 EHCIqh qh;
1638 int i = 0;
1639 int again = 0;
1640 uint32_t entry = ehci->asynclistaddr;
1641
1642 /* set reclamation flag at start event (4.8.6) */
1643 if (async) {
1644 ehci_set_usbsts(ehci, USBSTS_REC);
1645 }
1646
1647 ehci_queues_rip_unused(ehci, async);
1648
1649 /* Find the head of the list (4.9.1.1) */
1650 for(i = 0; i < MAX_QH; i++) {
1651 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1652 sizeof(EHCIqh) >> 2);
1653 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1654
1655 if (qh.epchar & QH_EPCHAR_H) {
1656 if (async) {
1657 entry |= (NLPTR_TYPE_QH << 1);
1658 }
1659
1660 ehci_set_fetch_addr(ehci, async, entry);
1661 ehci_set_state(ehci, async, EST_FETCHENTRY);
1662 again = 1;
1663 goto out;
1664 }
1665
1666 entry = qh.next;
1667 if (entry == ehci->asynclistaddr) {
1668 break;
1669 }
1670 }
1671
1672 /* no head found for list. */
1673
1674 ehci_set_state(ehci, async, EST_ACTIVE);
1675
1676 out:
1677 return again;
1678 }
1679
1680
1681 /* This state is the entry point for periodic schedule processing as
1682 * well as being a continuation state for async processing.
1683 */
1684 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1685 {
1686 int again = 0;
1687 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1688
1689 if (NLPTR_TBIT(entry)) {
1690 ehci_set_state(ehci, async, EST_ACTIVE);
1691 goto out;
1692 }
1693
1694 /* section 4.8, only QH in async schedule */
1695 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1696 fprintf(stderr, "non queue head request in async schedule\n");
1697 return -1;
1698 }
1699
1700 switch (NLPTR_TYPE_GET(entry)) {
1701 case NLPTR_TYPE_QH:
1702 ehci_set_state(ehci, async, EST_FETCHQH);
1703 again = 1;
1704 break;
1705
1706 case NLPTR_TYPE_ITD:
1707 ehci_set_state(ehci, async, EST_FETCHITD);
1708 again = 1;
1709 break;
1710
1711 case NLPTR_TYPE_STITD:
1712 ehci_set_state(ehci, async, EST_FETCHSITD);
1713 again = 1;
1714 break;
1715
1716 default:
1717 /* TODO: handle FSTN type */
1718 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1719 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1720 return -1;
1721 }
1722
1723 out:
1724 return again;
1725 }
1726
1727 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1728 {
1729 EHCIPacket *p;
1730 uint32_t entry, devaddr;
1731 EHCIQueue *q;
1732 EHCIqh qh;
1733
1734 entry = ehci_get_fetch_addr(ehci, async);
1735 q = ehci_find_queue_by_qh(ehci, entry, async);
1736 if (NULL == q) {
1737 q = ehci_alloc_queue(ehci, entry, async);
1738 }
1739 p = QTAILQ_FIRST(&q->packets);
1740
1741 q->seen++;
1742 if (q->seen > 1) {
1743 /* we are going in circles -- stop processing */
1744 ehci_set_state(ehci, async, EST_ACTIVE);
1745 q = NULL;
1746 goto out;
1747 }
1748
1749 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1750 (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1751 if (q->revalidate && (q->qh.epchar != qh.epchar ||
1752 q->qh.epcap != qh.epcap ||
1753 q->qh.current_qtd != qh.current_qtd)) {
1754 ehci_free_queue(q);
1755 q = ehci_alloc_queue(ehci, entry, async);
1756 q->seen++;
1757 p = NULL;
1758 }
1759 q->qh = qh;
1760 q->revalidate = 0;
1761 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1762
1763 devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1764 if (q->dev != NULL && q->dev->addr != devaddr) {
1765 if (!QTAILQ_EMPTY(&q->packets)) {
1766 /* should not happen (guest bug) */
1767 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
1768 ehci_free_packet(p);
1769 }
1770 }
1771 q->dev = NULL;
1772 }
1773 if (q->dev == NULL) {
1774 q->dev = ehci_find_device(q->ehci, devaddr);
1775 }
1776
1777 if (p && p->async == EHCI_ASYNC_INFLIGHT) {
1778 /* I/O still in progress -- skip queue */
1779 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1780 goto out;
1781 }
1782 if (p && p->async == EHCI_ASYNC_FINISHED) {
1783 /* I/O finished -- continue processing queue */
1784 trace_usb_ehci_packet_action(p->queue, p, "complete");
1785 ehci_set_state(ehci, async, EST_EXECUTING);
1786 goto out;
1787 }
1788
1789 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1790
1791 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1792 if (ehci->usbsts & USBSTS_REC) {
1793 ehci_clear_usbsts(ehci, USBSTS_REC);
1794 } else {
1795 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1796 " - done processing\n", q->qhaddr);
1797 ehci_set_state(ehci, async, EST_ACTIVE);
1798 q = NULL;
1799 goto out;
1800 }
1801 }
1802
1803 #if EHCI_DEBUG
1804 if (q->qhaddr != q->qh.next) {
1805 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1806 q->qhaddr,
1807 q->qh.epchar & QH_EPCHAR_H,
1808 q->qh.token & QTD_TOKEN_HALT,
1809 q->qh.token & QTD_TOKEN_ACTIVE,
1810 q->qh.next);
1811 }
1812 #endif
1813
1814 if (q->qh.token & QTD_TOKEN_HALT) {
1815 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1816
1817 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1818 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1819 q->qtdaddr = q->qh.current_qtd;
1820 ehci_set_state(ehci, async, EST_FETCHQTD);
1821
1822 } else {
1823 /* EHCI spec version 1.0 Section 4.10.2 */
1824 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1825 }
1826
1827 out:
1828 return q;
1829 }
1830
1831 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1832 {
1833 uint32_t entry;
1834 EHCIitd itd;
1835
1836 assert(!async);
1837 entry = ehci_get_fetch_addr(ehci, async);
1838
1839 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1840 sizeof(EHCIitd) >> 2);
1841 ehci_trace_itd(ehci, entry, &itd);
1842
1843 if (ehci_process_itd(ehci, &itd) != 0) {
1844 return -1;
1845 }
1846
1847 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1848 sizeof(EHCIitd) >> 2);
1849 ehci_set_fetch_addr(ehci, async, itd.next);
1850 ehci_set_state(ehci, async, EST_FETCHENTRY);
1851
1852 return 1;
1853 }
1854
1855 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1856 {
1857 uint32_t entry;
1858 EHCIsitd sitd;
1859
1860 assert(!async);
1861 entry = ehci_get_fetch_addr(ehci, async);
1862
1863 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1864 sizeof(EHCIsitd) >> 2);
1865 ehci_trace_sitd(ehci, entry, &sitd);
1866
1867 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1868 /* siTD is not active, nothing to do */;
1869 } else {
1870 /* TODO: split transfers are not implemented */
1871 fprintf(stderr, "WARNING: Skipping active siTD\n");
1872 }
1873
1874 ehci_set_fetch_addr(ehci, async, sitd.next);
1875 ehci_set_state(ehci, async, EST_FETCHENTRY);
1876 return 1;
1877 }
1878
1879 /* Section 4.10.2 - paragraph 3 */
1880 static int ehci_state_advqueue(EHCIQueue *q)
1881 {
1882 #if 0
1883 /* TO-DO: 4.10.2 - paragraph 2
1884 * if I-bit is set to 1 and QH is not active
1885 * go to horizontal QH
1886 */
1887 if (I-bit set) {
1888 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1889 goto out;
1890 }
1891 #endif
1892
1893 /*
1894 * want data and alt-next qTD is valid
1895 */
1896 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1897 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1898 q->qtdaddr = q->qh.altnext_qtd;
1899 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1900
1901 /*
1902 * next qTD is valid
1903 */
1904 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1905 q->qtdaddr = q->qh.next_qtd;
1906 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1907
1908 /*
1909 * no valid qTD, try next QH
1910 */
1911 } else {
1912 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1913 }
1914
1915 return 1;
1916 }
1917
1918 /* Section 4.10.2 - paragraph 4 */
1919 static int ehci_state_fetchqtd(EHCIQueue *q)
1920 {
1921 EHCIqtd qtd;
1922 EHCIPacket *p;
1923 int again = 0;
1924
1925 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1926 sizeof(EHCIqtd) >> 2);
1927 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1928
1929 p = QTAILQ_FIRST(&q->packets);
1930 while (p != NULL && p->qtdaddr != q->qtdaddr) {
1931 /* should not happen (guest bug) */
1932 ehci_free_packet(p);
1933 p = QTAILQ_FIRST(&q->packets);
1934 }
1935 if (p != NULL) {
1936 ehci_qh_do_overlay(q);
1937 ehci_flush_qh(q);
1938 if (p->async == EHCI_ASYNC_INFLIGHT) {
1939 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1940 } else {
1941 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1942 }
1943 again = 1;
1944 } else if (qtd.token & QTD_TOKEN_ACTIVE) {
1945 p = ehci_alloc_packet(q);
1946 p->qtdaddr = q->qtdaddr;
1947 p->qtd = qtd;
1948 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1949 again = 1;
1950 } else {
1951 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1952 again = 1;
1953 }
1954
1955 return again;
1956 }
1957
1958 static int ehci_state_horizqh(EHCIQueue *q)
1959 {
1960 int again = 0;
1961
1962 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1963 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1964 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1965 again = 1;
1966 } else {
1967 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1968 }
1969
1970 return again;
1971 }
1972
1973 static void ehci_fill_queue(EHCIPacket *p)
1974 {
1975 EHCIQueue *q = p->queue;
1976 EHCIqtd qtd = p->qtd;
1977 uint32_t qtdaddr;
1978
1979 for (;;) {
1980 if (NLPTR_TBIT(qtd.altnext) == 0) {
1981 break;
1982 }
1983 if (NLPTR_TBIT(qtd.next) != 0) {
1984 break;
1985 }
1986 qtdaddr = qtd.next;
1987 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1988 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
1989 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1990 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1991 break;
1992 }
1993 p = ehci_alloc_packet(q);
1994 p->qtdaddr = qtdaddr;
1995 p->qtd = qtd;
1996 p->usb_status = ehci_execute(p, "queue");
1997 assert(p->usb_status = USB_RET_ASYNC);
1998 p->async = EHCI_ASYNC_INFLIGHT;
1999 }
2000 }
2001
2002 static int ehci_state_execute(EHCIQueue *q)
2003 {
2004 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2005 int again = 0;
2006
2007 assert(p != NULL);
2008 assert(p->qtdaddr == q->qtdaddr);
2009
2010 if (ehci_qh_do_overlay(q) != 0) {
2011 return -1;
2012 }
2013
2014 // TODO verify enough time remains in the uframe as in 4.4.1.1
2015 // TODO write back ptr to async list when done or out of time
2016 // TODO Windows does not seem to ever set the MULT field
2017
2018 if (!q->async) {
2019 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2020 if (!transactCtr) {
2021 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2022 again = 1;
2023 goto out;
2024 }
2025 }
2026
2027 if (q->async) {
2028 ehci_set_usbsts(q->ehci, USBSTS_REC);
2029 }
2030
2031 p->usb_status = ehci_execute(p, "process");
2032 if (p->usb_status == USB_RET_PROCERR) {
2033 again = -1;
2034 goto out;
2035 }
2036 if (p->usb_status == USB_RET_ASYNC) {
2037 ehci_flush_qh(q);
2038 trace_usb_ehci_packet_action(p->queue, p, "async");
2039 p->async = EHCI_ASYNC_INFLIGHT;
2040 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2041 again = 1;
2042 ehci_fill_queue(p);
2043 goto out;
2044 }
2045
2046 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
2047 again = 1;
2048
2049 out:
2050 return again;
2051 }
2052
2053 static int ehci_state_executing(EHCIQueue *q)
2054 {
2055 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2056 int again = 0;
2057
2058 assert(p != NULL);
2059 assert(p->qtdaddr == q->qtdaddr);
2060
2061 ehci_execute_complete(q);
2062 if (p->usb_status == USB_RET_ASYNC) {
2063 goto out;
2064 }
2065 if (p->usb_status == USB_RET_PROCERR) {
2066 again = -1;
2067 goto out;
2068 }
2069
2070 // 4.10.3
2071 if (!q->async) {
2072 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2073 transactCtr--;
2074 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
2075 // 4.10.3, bottom of page 82, should exit this state when transaction
2076 // counter decrements to 0
2077 }
2078
2079 /* 4.10.5 */
2080 if (p->usb_status == USB_RET_NAK) {
2081 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2082 } else {
2083 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
2084 }
2085
2086 again = 1;
2087
2088 out:
2089 ehci_flush_qh(q);
2090 return again;
2091 }
2092
2093
2094 static int ehci_state_writeback(EHCIQueue *q)
2095 {
2096 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2097 uint32_t *qtd, addr;
2098 int again = 0;
2099
2100 /* Write back the QTD from the QH area */
2101 assert(p != NULL);
2102 assert(p->qtdaddr == q->qtdaddr);
2103
2104 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2105 qtd = (uint32_t *) &q->qh.next_qtd;
2106 addr = NLPTR_GET(p->qtdaddr);
2107 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2);
2108 ehci_free_packet(p);
2109
2110 /*
2111 * EHCI specs say go horizontal here.
2112 *
2113 * We can also advance the queue here for performance reasons. We
2114 * need to take care to only take that shortcut in case we've
2115 * processed the qtd just written back without errors, i.e. halt
2116 * bit is clear.
2117 */
2118 if (q->qh.token & QTD_TOKEN_HALT) {
2119 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2120 again = 1;
2121 } else {
2122 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2123 again = 1;
2124 }
2125 return again;
2126 }
2127
2128 /*
2129 * This is the state machine that is common to both async and periodic
2130 */
2131
2132 static void ehci_advance_state(EHCIState *ehci, int async)
2133 {
2134 EHCIQueue *q = NULL;
2135 int again;
2136
2137 do {
2138 switch(ehci_get_state(ehci, async)) {
2139 case EST_WAITLISTHEAD:
2140 again = ehci_state_waitlisthead(ehci, async);
2141 break;
2142
2143 case EST_FETCHENTRY:
2144 again = ehci_state_fetchentry(ehci, async);
2145 break;
2146
2147 case EST_FETCHQH:
2148 q = ehci_state_fetchqh(ehci, async);
2149 if (q != NULL) {
2150 assert(q->async == async);
2151 again = 1;
2152 } else {
2153 again = 0;
2154 }
2155 break;
2156
2157 case EST_FETCHITD:
2158 again = ehci_state_fetchitd(ehci, async);
2159 break;
2160
2161 case EST_FETCHSITD:
2162 again = ehci_state_fetchsitd(ehci, async);
2163 break;
2164
2165 case EST_ADVANCEQUEUE:
2166 again = ehci_state_advqueue(q);
2167 break;
2168
2169 case EST_FETCHQTD:
2170 again = ehci_state_fetchqtd(q);
2171 break;
2172
2173 case EST_HORIZONTALQH:
2174 again = ehci_state_horizqh(q);
2175 break;
2176
2177 case EST_EXECUTE:
2178 again = ehci_state_execute(q);
2179 if (async) {
2180 ehci->async_stepdown = 0;
2181 }
2182 break;
2183
2184 case EST_EXECUTING:
2185 assert(q != NULL);
2186 if (async) {
2187 ehci->async_stepdown = 0;
2188 }
2189 again = ehci_state_executing(q);
2190 break;
2191
2192 case EST_WRITEBACK:
2193 assert(q != NULL);
2194 again = ehci_state_writeback(q);
2195 break;
2196
2197 default:
2198 fprintf(stderr, "Bad state!\n");
2199 again = -1;
2200 assert(0);
2201 break;
2202 }
2203
2204 if (again < 0) {
2205 fprintf(stderr, "processing error - resetting ehci HC\n");
2206 ehci_reset(ehci);
2207 again = 0;
2208 }
2209 }
2210 while (again);
2211
2212 ehci_commit_interrupt(ehci);
2213 }
2214
2215 static void ehci_advance_async_state(EHCIState *ehci)
2216 {
2217 const int async = 1;
2218
2219 switch(ehci_get_state(ehci, async)) {
2220 case EST_INACTIVE:
2221 if (!ehci_async_enabled(ehci)) {
2222 break;
2223 }
2224 ehci_set_state(ehci, async, EST_ACTIVE);
2225 // No break, fall through to ACTIVE
2226
2227 case EST_ACTIVE:
2228 if (!ehci_async_enabled(ehci)) {
2229 ehci_queues_rip_all(ehci, async);
2230 ehci_set_state(ehci, async, EST_INACTIVE);
2231 break;
2232 }
2233
2234 /* make sure guest has acknowledged the doorbell interrupt */
2235 /* TO-DO: is this really needed? */
2236 if (ehci->usbsts & USBSTS_IAA) {
2237 DPRINTF("IAA status bit still set.\n");
2238 break;
2239 }
2240
2241 /* check that address register has been set */
2242 if (ehci->asynclistaddr == 0) {
2243 break;
2244 }
2245
2246 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2247 ehci_advance_state(ehci, async);
2248
2249 /* If the doorbell is set, the guest wants to make a change to the
2250 * schedule. The host controller needs to release cached data.
2251 * (section 4.8.2)
2252 */
2253 if (ehci->usbcmd & USBCMD_IAAD) {
2254 /* Remove all unseen qhs from the async qhs queue */
2255 ehci_queues_tag_unused_async(ehci);
2256 DPRINTF("ASYNC: doorbell request acknowledged\n");
2257 ehci->usbcmd &= ~USBCMD_IAAD;
2258 ehci_set_interrupt(ehci, USBSTS_IAA);
2259 }
2260 break;
2261
2262 default:
2263 /* this should only be due to a developer mistake */
2264 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2265 "Resetting to active\n", ehci->astate);
2266 assert(0);
2267 }
2268 }
2269
2270 static void ehci_advance_periodic_state(EHCIState *ehci)
2271 {
2272 uint32_t entry;
2273 uint32_t list;
2274 const int async = 0;
2275
2276 // 4.6
2277
2278 switch(ehci_get_state(ehci, async)) {
2279 case EST_INACTIVE:
2280 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2281 ehci_set_state(ehci, async, EST_ACTIVE);
2282 // No break, fall through to ACTIVE
2283 } else
2284 break;
2285
2286 case EST_ACTIVE:
2287 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2288 ehci_queues_rip_all(ehci, async);
2289 ehci_set_state(ehci, async, EST_INACTIVE);
2290 break;
2291 }
2292
2293 list = ehci->periodiclistbase & 0xfffff000;
2294 /* check that register has been set */
2295 if (list == 0) {
2296 break;
2297 }
2298 list |= ((ehci->frindex & 0x1ff8) >> 1);
2299
2300 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2301 entry = le32_to_cpu(entry);
2302
2303 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2304 ehci->frindex / 8, list, entry);
2305 ehci_set_fetch_addr(ehci, async,entry);
2306 ehci_set_state(ehci, async, EST_FETCHENTRY);
2307 ehci_advance_state(ehci, async);
2308 ehci_queues_rip_unused(ehci, async);
2309 break;
2310
2311 default:
2312 /* this should only be due to a developer mistake */
2313 fprintf(stderr, "ehci: Bad periodic state %d. "
2314 "Resetting to active\n", ehci->pstate);
2315 assert(0);
2316 }
2317 }
2318
2319 static void ehci_update_frindex(EHCIState *ehci, int frames)
2320 {
2321 int i;
2322
2323 if (!ehci_enabled(ehci)) {
2324 return;
2325 }
2326
2327 for (i = 0; i < frames; i++) {
2328 ehci->frindex += 8;
2329
2330 if (ehci->frindex == 0x00002000) {
2331 ehci_set_interrupt(ehci, USBSTS_FLR);
2332 }
2333
2334 if (ehci->frindex == 0x00004000) {
2335 ehci_set_interrupt(ehci, USBSTS_FLR);
2336 ehci->frindex = 0;
2337 }
2338 }
2339 }
2340
2341 static void ehci_frame_timer(void *opaque)
2342 {
2343 EHCIState *ehci = opaque;
2344 int schedules = 0;
2345 int64_t expire_time, t_now;
2346 uint64_t ns_elapsed;
2347 int frames, skipped_frames;
2348 int i;
2349
2350 t_now = qemu_get_clock_ns(vm_clock);
2351 ns_elapsed = t_now - ehci->last_run_ns;
2352 frames = ns_elapsed / FRAME_TIMER_NS;
2353
2354 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2355 schedules++;
2356 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
2357
2358 if (frames > ehci->maxframes) {
2359 skipped_frames = frames - ehci->maxframes;
2360 ehci_update_frindex(ehci, skipped_frames);
2361 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2362 frames -= skipped_frames;
2363 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2364 }
2365
2366 for (i = 0; i < frames; i++) {
2367 ehci_update_frindex(ehci, 1);
2368 ehci_advance_periodic_state(ehci);
2369 ehci->last_run_ns += FRAME_TIMER_NS;
2370 }
2371 } else {
2372 if (ehci->async_stepdown < ehci->maxframes / 2) {
2373 ehci->async_stepdown++;
2374 }
2375 expire_time = t_now + (get_ticks_per_sec()
2376 * ehci->async_stepdown / FRAME_TIMER_FREQ);
2377 ehci_update_frindex(ehci, frames);
2378 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2379 }
2380
2381 /* Async is not inside loop since it executes everything it can once
2382 * called
2383 */
2384 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2385 schedules++;
2386 qemu_bh_schedule(ehci->async_bh);
2387 }
2388
2389 if (schedules) {
2390 qemu_mod_timer(ehci->frame_timer, expire_time);
2391 }
2392 }
2393
2394 static void ehci_async_bh(void *opaque)
2395 {
2396 EHCIState *ehci = opaque;
2397 ehci_advance_async_state(ehci);
2398 }
2399
2400 static const MemoryRegionOps ehci_mem_ops = {
2401 .old_mmio = {
2402 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2403 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2404 },
2405 .endianness = DEVICE_LITTLE_ENDIAN,
2406 };
2407
2408 static int usb_ehci_initfn(PCIDevice *dev);
2409
2410 static USBPortOps ehci_port_ops = {
2411 .attach = ehci_attach,
2412 .detach = ehci_detach,
2413 .child_detach = ehci_child_detach,
2414 .wakeup = ehci_wakeup,
2415 .complete = ehci_async_complete_packet,
2416 };
2417
2418 static USBBusOps ehci_bus_ops = {
2419 .register_companion = ehci_register_companion,
2420 };
2421
2422 static int usb_ehci_post_load(void *opaque, int version_id)
2423 {
2424 EHCIState *s = opaque;
2425 int i;
2426
2427 for (i = 0; i < NB_PORTS; i++) {
2428 USBPort *companion = s->companion_ports[i];
2429 if (companion == NULL) {
2430 continue;
2431 }
2432 if (s->portsc[i] & PORTSC_POWNER) {
2433 companion->dev = s->ports[i].dev;
2434 } else {
2435 companion->dev = NULL;
2436 }
2437 }
2438
2439 return 0;
2440 }
2441
2442 static const VMStateDescription vmstate_ehci = {
2443 .name = "ehci",
2444 .version_id = 1,
2445 .post_load = usb_ehci_post_load,
2446 .fields = (VMStateField[]) {
2447 VMSTATE_PCI_DEVICE(dev, EHCIState),
2448 /* mmio registers */
2449 VMSTATE_UINT32(usbcmd, EHCIState),
2450 VMSTATE_UINT32(usbsts, EHCIState),
2451 VMSTATE_UINT32(usbintr, EHCIState),
2452 VMSTATE_UINT32(frindex, EHCIState),
2453 VMSTATE_UINT32(ctrldssegment, EHCIState),
2454 VMSTATE_UINT32(periodiclistbase, EHCIState),
2455 VMSTATE_UINT32(asynclistaddr, EHCIState),
2456 VMSTATE_UINT32(configflag, EHCIState),
2457 VMSTATE_UINT32(portsc[0], EHCIState),
2458 VMSTATE_UINT32(portsc[1], EHCIState),
2459 VMSTATE_UINT32(portsc[2], EHCIState),
2460 VMSTATE_UINT32(portsc[3], EHCIState),
2461 VMSTATE_UINT32(portsc[4], EHCIState),
2462 VMSTATE_UINT32(portsc[5], EHCIState),
2463 /* frame timer */
2464 VMSTATE_TIMER(frame_timer, EHCIState),
2465 VMSTATE_UINT64(last_run_ns, EHCIState),
2466 VMSTATE_UINT32(async_stepdown, EHCIState),
2467 /* schedule state */
2468 VMSTATE_UINT32(astate, EHCIState),
2469 VMSTATE_UINT32(pstate, EHCIState),
2470 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2471 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2472 VMSTATE_END_OF_LIST()
2473 }
2474 };
2475
2476 static Property ehci_properties[] = {
2477 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2478 DEFINE_PROP_END_OF_LIST(),
2479 };
2480
2481 static void ehci_class_init(ObjectClass *klass, void *data)
2482 {
2483 DeviceClass *dc = DEVICE_CLASS(klass);
2484 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2485
2486 k->init = usb_ehci_initfn;
2487 k->vendor_id = PCI_VENDOR_ID_INTEL;
2488 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2489 k->revision = 0x10;
2490 k->class_id = PCI_CLASS_SERIAL_USB;
2491 dc->vmsd = &vmstate_ehci;
2492 dc->props = ehci_properties;
2493 }
2494
2495 static TypeInfo ehci_info = {
2496 .name = "usb-ehci",
2497 .parent = TYPE_PCI_DEVICE,
2498 .instance_size = sizeof(EHCIState),
2499 .class_init = ehci_class_init,
2500 };
2501
2502 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2503 {
2504 DeviceClass *dc = DEVICE_CLASS(klass);
2505 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2506
2507 k->init = usb_ehci_initfn;
2508 k->vendor_id = PCI_VENDOR_ID_INTEL;
2509 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2510 k->revision = 0x03;
2511 k->class_id = PCI_CLASS_SERIAL_USB;
2512 dc->vmsd = &vmstate_ehci;
2513 dc->props = ehci_properties;
2514 }
2515
2516 static TypeInfo ich9_ehci_info = {
2517 .name = "ich9-usb-ehci1",
2518 .parent = TYPE_PCI_DEVICE,
2519 .instance_size = sizeof(EHCIState),
2520 .class_init = ich9_ehci_class_init,
2521 };
2522
2523 static int usb_ehci_initfn(PCIDevice *dev)
2524 {
2525 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2526 uint8_t *pci_conf = s->dev.config;
2527 int i;
2528
2529 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2530
2531 /* capabilities pointer */
2532 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2533 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2534
2535 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2536 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2537 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2538
2539 // pci_conf[0x50] = 0x01; // power management caps
2540
2541 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2542 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2543 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2544
2545 pci_conf[0x64] = 0x00;
2546 pci_conf[0x65] = 0x00;
2547 pci_conf[0x66] = 0x00;
2548 pci_conf[0x67] = 0x00;
2549 pci_conf[0x68] = 0x01;
2550 pci_conf[0x69] = 0x00;
2551 pci_conf[0x6a] = 0x00;
2552 pci_conf[0x6b] = 0x00; // USBLEGSUP
2553 pci_conf[0x6c] = 0x00;
2554 pci_conf[0x6d] = 0x00;
2555 pci_conf[0x6e] = 0x00;
2556 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2557
2558 // 2.2 host controller interface version
2559 s->mmio[0x00] = (uint8_t) OPREGBASE;
2560 s->mmio[0x01] = 0x00;
2561 s->mmio[0x02] = 0x00;
2562 s->mmio[0x03] = 0x01; // HC version
2563 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2564 s->mmio[0x05] = 0x00; // No companion ports at present
2565 s->mmio[0x06] = 0x00;
2566 s->mmio[0x07] = 0x00;
2567 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2568 s->mmio[0x09] = 0x68; // EECP
2569 s->mmio[0x0a] = 0x00;
2570 s->mmio[0x0b] = 0x00;
2571
2572 s->irq = s->dev.irq[3];
2573
2574 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2575 for(i = 0; i < NB_PORTS; i++) {
2576 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2577 USB_SPEED_MASK_HIGH);
2578 s->ports[i].dev = 0;
2579 }
2580
2581 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2582 s->async_bh = qemu_bh_new(ehci_async_bh, s);
2583 QTAILQ_INIT(&s->aqueues);
2584 QTAILQ_INIT(&s->pqueues);
2585 usb_packet_init(&s->ipacket);
2586
2587 qemu_register_reset(ehci_reset, s);
2588
2589 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2590 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2591
2592 return 0;
2593 }
2594
2595 static void ehci_register_types(void)
2596 {
2597 type_register_static(&ehci_info);
2598 type_register_static(&ich9_ehci_info);
2599 }
2600
2601 type_init(ehci_register_types)
2602
2603 /*
2604 * vim: expandtab ts=4
2605 */
Qemu copy for testing