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Merge remote-tracking branch 'sstabellini/xen-pt' into staging
[qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw/hw.h"
26 #include "qemu-timer.h"
27 #include "hw/usb.h"
28 #include "hw/pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
137
138 /* Internal periodic / asynchronous schedule state machine states
139 */
140 typedef enum {
141 EST_INACTIVE = 1000,
142 EST_ACTIVE,
143 EST_EXECUTING,
144 EST_SLEEPING,
145 /* The following states are internal to the state machine function
146 */
147 EST_WAITLISTHEAD,
148 EST_FETCHENTRY,
149 EST_FETCHQH,
150 EST_FETCHITD,
151 EST_FETCHSITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIPacket EHCIPacket;
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIPacket {
348 EHCIQueue *queue;
349 QTAILQ_ENTRY(EHCIPacket) next;
350
351 EHCIqtd qtd; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr; /* address QTD read from */
353
354 USBPacket packet;
355 QEMUSGList sgl;
356 int pid;
357 uint32_t tbytes;
358 enum async_state async;
359 int usb_status;
360 };
361
362 struct EHCIQueue {
363 EHCIState *ehci;
364 QTAILQ_ENTRY(EHCIQueue) next;
365 uint32_t seen;
366 uint64_t ts;
367 int async;
368
369 /* cached data from guest - needs to be flushed
370 * when guest removes an entry (doorbell, handshake sequence)
371 */
372 EHCIqh qh; /* copy of current QH (being worked on) */
373 uint32_t qhaddr; /* address QH read from */
374 uint32_t qtdaddr; /* address QTD read from */
375 USBDevice *dev;
376 QTAILQ_HEAD(, EHCIPacket) packets;
377 };
378
379 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
380
381 struct EHCIState {
382 PCIDevice dev;
383 USBBus bus;
384 qemu_irq irq;
385 MemoryRegion mem;
386 int companion_count;
387
388 /* properties */
389 uint32_t maxframes;
390
391 /*
392 * EHCI spec version 1.0 Section 2.3
393 * Host Controller Operational Registers
394 */
395 union {
396 uint8_t mmio[MMIO_SIZE];
397 struct {
398 uint8_t cap[OPREGBASE];
399 uint32_t usbcmd;
400 uint32_t usbsts;
401 uint32_t usbintr;
402 uint32_t frindex;
403 uint32_t ctrldssegment;
404 uint32_t periodiclistbase;
405 uint32_t asynclistaddr;
406 uint32_t notused[9];
407 uint32_t configflag;
408 uint32_t portsc[NB_PORTS];
409 };
410 };
411
412 /*
413 * Internal states, shadow registers, etc
414 */
415 QEMUTimer *frame_timer;
416 QEMUBH *async_bh;
417 uint32_t astate; /* Current state in asynchronous schedule */
418 uint32_t pstate; /* Current state in periodic schedule */
419 USBPort ports[NB_PORTS];
420 USBPort *companion_ports[NB_PORTS];
421 uint32_t usbsts_pending;
422 EHCIQueueHead aqueues;
423 EHCIQueueHead pqueues;
424
425 /* which address to look at next */
426 uint32_t a_fetch_addr;
427 uint32_t p_fetch_addr;
428
429 USBPacket ipacket;
430 QEMUSGList isgl;
431
432 uint64_t last_run_ns;
433 uint32_t async_stepdown;
434 };
435
436 #define SET_LAST_RUN_CLOCK(s) \
437 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
438
439 /* nifty macros from Arnon's EHCI version */
440 #define get_field(data, field) \
441 (((data) & field##_MASK) >> field##_SH)
442
443 #define set_field(data, newval, field) do { \
444 uint32_t val = *data; \
445 val &= ~ field##_MASK; \
446 val |= ((newval) << field##_SH) & field##_MASK; \
447 *data = val; \
448 } while(0)
449
450 static const char *ehci_state_names[] = {
451 [EST_INACTIVE] = "INACTIVE",
452 [EST_ACTIVE] = "ACTIVE",
453 [EST_EXECUTING] = "EXECUTING",
454 [EST_SLEEPING] = "SLEEPING",
455 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
456 [EST_FETCHENTRY] = "FETCH ENTRY",
457 [EST_FETCHQH] = "FETCH QH",
458 [EST_FETCHITD] = "FETCH ITD",
459 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
460 [EST_FETCHQTD] = "FETCH QTD",
461 [EST_EXECUTE] = "EXECUTE",
462 [EST_WRITEBACK] = "WRITEBACK",
463 [EST_HORIZONTALQH] = "HORIZONTALQH",
464 };
465
466 static const char *ehci_mmio_names[] = {
467 [CAPLENGTH] = "CAPLENGTH",
468 [HCIVERSION] = "HCIVERSION",
469 [HCSPARAMS] = "HCSPARAMS",
470 [HCCPARAMS] = "HCCPARAMS",
471 [USBCMD] = "USBCMD",
472 [USBSTS] = "USBSTS",
473 [USBINTR] = "USBINTR",
474 [FRINDEX] = "FRINDEX",
475 [PERIODICLISTBASE] = "P-LIST BASE",
476 [ASYNCLISTADDR] = "A-LIST ADDR",
477 [PORTSC_BEGIN] = "PORTSC #0",
478 [PORTSC_BEGIN + 4] = "PORTSC #1",
479 [PORTSC_BEGIN + 8] = "PORTSC #2",
480 [PORTSC_BEGIN + 12] = "PORTSC #3",
481 [PORTSC_BEGIN + 16] = "PORTSC #4",
482 [PORTSC_BEGIN + 20] = "PORTSC #5",
483 [CONFIGFLAG] = "CONFIGFLAG",
484 };
485
486 static const char *nr2str(const char **n, size_t len, uint32_t nr)
487 {
488 if (nr < len && n[nr] != NULL) {
489 return n[nr];
490 } else {
491 return "unknown";
492 }
493 }
494
495 static const char *state2str(uint32_t state)
496 {
497 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
498 }
499
500 static const char *addr2str(target_phys_addr_t addr)
501 {
502 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
503 }
504
505 static void ehci_trace_usbsts(uint32_t mask, int state)
506 {
507 /* interrupts */
508 if (mask & USBSTS_INT) {
509 trace_usb_ehci_usbsts("INT", state);
510 }
511 if (mask & USBSTS_ERRINT) {
512 trace_usb_ehci_usbsts("ERRINT", state);
513 }
514 if (mask & USBSTS_PCD) {
515 trace_usb_ehci_usbsts("PCD", state);
516 }
517 if (mask & USBSTS_FLR) {
518 trace_usb_ehci_usbsts("FLR", state);
519 }
520 if (mask & USBSTS_HSE) {
521 trace_usb_ehci_usbsts("HSE", state);
522 }
523 if (mask & USBSTS_IAA) {
524 trace_usb_ehci_usbsts("IAA", state);
525 }
526
527 /* status */
528 if (mask & USBSTS_HALT) {
529 trace_usb_ehci_usbsts("HALT", state);
530 }
531 if (mask & USBSTS_REC) {
532 trace_usb_ehci_usbsts("REC", state);
533 }
534 if (mask & USBSTS_PSS) {
535 trace_usb_ehci_usbsts("PSS", state);
536 }
537 if (mask & USBSTS_ASS) {
538 trace_usb_ehci_usbsts("ASS", state);
539 }
540 }
541
542 static inline void ehci_set_usbsts(EHCIState *s, int mask)
543 {
544 if ((s->usbsts & mask) == mask) {
545 return;
546 }
547 ehci_trace_usbsts(mask, 1);
548 s->usbsts |= mask;
549 }
550
551 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
552 {
553 if ((s->usbsts & mask) == 0) {
554 return;
555 }
556 ehci_trace_usbsts(mask, 0);
557 s->usbsts &= ~mask;
558 }
559
560 static inline void ehci_set_interrupt(EHCIState *s, int intr)
561 {
562 int level = 0;
563
564 // TODO honour interrupt threshold requests
565
566 ehci_set_usbsts(s, intr);
567
568 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
569 level = 1;
570 }
571
572 trace_usb_ehci_interrupt(level, s->usbsts, s->usbintr);
573 qemu_set_irq(s->irq, level);
574 }
575
576 static inline void ehci_record_interrupt(EHCIState *s, int intr)
577 {
578 s->usbsts_pending |= intr;
579 }
580
581 static inline void ehci_commit_interrupt(EHCIState *s)
582 {
583 if (!s->usbsts_pending) {
584 return;
585 }
586 ehci_set_interrupt(s, s->usbsts_pending);
587 s->usbsts_pending = 0;
588 }
589
590 static void ehci_update_halt(EHCIState *s)
591 {
592 if (s->usbcmd & USBCMD_RUNSTOP) {
593 ehci_clear_usbsts(s, USBSTS_HALT);
594 } else {
595 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
596 ehci_set_usbsts(s, USBSTS_HALT);
597 }
598 }
599 }
600
601 static void ehci_set_state(EHCIState *s, int async, int state)
602 {
603 if (async) {
604 trace_usb_ehci_state("async", state2str(state));
605 s->astate = state;
606 if (s->astate == EST_INACTIVE) {
607 ehci_clear_usbsts(s, USBSTS_ASS);
608 ehci_update_halt(s);
609 } else {
610 ehci_set_usbsts(s, USBSTS_ASS);
611 }
612 } else {
613 trace_usb_ehci_state("periodic", state2str(state));
614 s->pstate = state;
615 if (s->pstate == EST_INACTIVE) {
616 ehci_clear_usbsts(s, USBSTS_PSS);
617 ehci_update_halt(s);
618 } else {
619 ehci_set_usbsts(s, USBSTS_PSS);
620 }
621 }
622 }
623
624 static int ehci_get_state(EHCIState *s, int async)
625 {
626 return async ? s->astate : s->pstate;
627 }
628
629 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
630 {
631 if (async) {
632 s->a_fetch_addr = addr;
633 } else {
634 s->p_fetch_addr = addr;
635 }
636 }
637
638 static int ehci_get_fetch_addr(EHCIState *s, int async)
639 {
640 return async ? s->a_fetch_addr : s->p_fetch_addr;
641 }
642
643 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
644 {
645 /* need three here due to argument count limits */
646 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
647 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
648 trace_usb_ehci_qh_fields(addr,
649 get_field(qh->epchar, QH_EPCHAR_RL),
650 get_field(qh->epchar, QH_EPCHAR_MPLEN),
651 get_field(qh->epchar, QH_EPCHAR_EPS),
652 get_field(qh->epchar, QH_EPCHAR_EP),
653 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
654 trace_usb_ehci_qh_bits(addr,
655 (bool)(qh->epchar & QH_EPCHAR_C),
656 (bool)(qh->epchar & QH_EPCHAR_H),
657 (bool)(qh->epchar & QH_EPCHAR_DTC),
658 (bool)(qh->epchar & QH_EPCHAR_I));
659 }
660
661 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
662 {
663 /* need three here due to argument count limits */
664 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
665 trace_usb_ehci_qtd_fields(addr,
666 get_field(qtd->token, QTD_TOKEN_TBYTES),
667 get_field(qtd->token, QTD_TOKEN_CPAGE),
668 get_field(qtd->token, QTD_TOKEN_CERR),
669 get_field(qtd->token, QTD_TOKEN_PID));
670 trace_usb_ehci_qtd_bits(addr,
671 (bool)(qtd->token & QTD_TOKEN_IOC),
672 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
673 (bool)(qtd->token & QTD_TOKEN_HALT),
674 (bool)(qtd->token & QTD_TOKEN_BABBLE),
675 (bool)(qtd->token & QTD_TOKEN_XACTERR));
676 }
677
678 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
679 {
680 trace_usb_ehci_itd(addr, itd->next,
681 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
682 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
683 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
684 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
685 }
686
687 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
688 EHCIsitd *sitd)
689 {
690 trace_usb_ehci_sitd(addr, sitd->next,
691 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
692 }
693
694 static inline bool ehci_enabled(EHCIState *s)
695 {
696 return s->usbcmd & USBCMD_RUNSTOP;
697 }
698
699 static inline bool ehci_async_enabled(EHCIState *s)
700 {
701 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
702 }
703
704 static inline bool ehci_periodic_enabled(EHCIState *s)
705 {
706 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
707 }
708
709 /* packet management */
710
711 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
712 {
713 EHCIPacket *p;
714
715 p = g_new0(EHCIPacket, 1);
716 p->queue = q;
717 usb_packet_init(&p->packet);
718 QTAILQ_INSERT_TAIL(&q->packets, p, next);
719 trace_usb_ehci_packet_action(p->queue, p, "alloc");
720 return p;
721 }
722
723 static void ehci_free_packet(EHCIPacket *p)
724 {
725 trace_usb_ehci_packet_action(p->queue, p, "free");
726 if (p->async == EHCI_ASYNC_INFLIGHT) {
727 usb_cancel_packet(&p->packet);
728 }
729 QTAILQ_REMOVE(&p->queue->packets, p, next);
730 usb_packet_cleanup(&p->packet);
731 g_free(p);
732 }
733
734 /* queue management */
735
736 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
737 {
738 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
739 EHCIQueue *q;
740
741 q = g_malloc0(sizeof(*q));
742 q->ehci = ehci;
743 q->qhaddr = addr;
744 q->async = async;
745 QTAILQ_INIT(&q->packets);
746 QTAILQ_INSERT_HEAD(head, q, next);
747 trace_usb_ehci_queue_action(q, "alloc");
748 return q;
749 }
750
751 static void ehci_free_queue(EHCIQueue *q)
752 {
753 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
754 EHCIPacket *p;
755
756 trace_usb_ehci_queue_action(q, "free");
757 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
758 ehci_free_packet(p);
759 }
760 QTAILQ_REMOVE(head, q, next);
761 g_free(q);
762 }
763
764 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
765 int async)
766 {
767 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
768 EHCIQueue *q;
769
770 QTAILQ_FOREACH(q, head, next) {
771 if (addr == q->qhaddr) {
772 return q;
773 }
774 }
775 return NULL;
776 }
777
778 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush)
779 {
780 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
781 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
782 EHCIQueue *q, *tmp;
783
784 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
785 if (q->seen) {
786 q->seen = 0;
787 q->ts = ehci->last_run_ns;
788 continue;
789 }
790 if (!flush && ehci->last_run_ns < q->ts + maxage) {
791 continue;
792 }
793 ehci_free_queue(q);
794 }
795 }
796
797 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
798 {
799 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
800 EHCIQueue *q, *tmp;
801
802 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
803 if (q->dev != dev) {
804 continue;
805 }
806 ehci_free_queue(q);
807 }
808 }
809
810 static void ehci_queues_rip_all(EHCIState *ehci, int async)
811 {
812 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
813 EHCIQueue *q, *tmp;
814
815 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
816 ehci_free_queue(q);
817 }
818 }
819
820 /* Attach or detach a device on root hub */
821
822 static void ehci_attach(USBPort *port)
823 {
824 EHCIState *s = port->opaque;
825 uint32_t *portsc = &s->portsc[port->index];
826 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
827
828 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
829
830 if (*portsc & PORTSC_POWNER) {
831 USBPort *companion = s->companion_ports[port->index];
832 companion->dev = port->dev;
833 companion->ops->attach(companion);
834 return;
835 }
836
837 *portsc |= PORTSC_CONNECT;
838 *portsc |= PORTSC_CSC;
839
840 ehci_set_interrupt(s, USBSTS_PCD);
841 }
842
843 static void ehci_detach(USBPort *port)
844 {
845 EHCIState *s = port->opaque;
846 uint32_t *portsc = &s->portsc[port->index];
847 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
848
849 trace_usb_ehci_port_detach(port->index, owner);
850
851 if (*portsc & PORTSC_POWNER) {
852 USBPort *companion = s->companion_ports[port->index];
853 companion->ops->detach(companion);
854 companion->dev = NULL;
855 /*
856 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
857 * the port ownership is returned immediately to the EHCI controller."
858 */
859 *portsc &= ~PORTSC_POWNER;
860 return;
861 }
862
863 ehci_queues_rip_device(s, port->dev, 0);
864 ehci_queues_rip_device(s, port->dev, 1);
865
866 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
867 *portsc |= PORTSC_CSC;
868
869 ehci_set_interrupt(s, USBSTS_PCD);
870 }
871
872 static void ehci_child_detach(USBPort *port, USBDevice *child)
873 {
874 EHCIState *s = port->opaque;
875 uint32_t portsc = s->portsc[port->index];
876
877 if (portsc & PORTSC_POWNER) {
878 USBPort *companion = s->companion_ports[port->index];
879 companion->ops->child_detach(companion, child);
880 return;
881 }
882
883 ehci_queues_rip_device(s, child, 0);
884 ehci_queues_rip_device(s, child, 1);
885 }
886
887 static void ehci_wakeup(USBPort *port)
888 {
889 EHCIState *s = port->opaque;
890 uint32_t portsc = s->portsc[port->index];
891
892 if (portsc & PORTSC_POWNER) {
893 USBPort *companion = s->companion_ports[port->index];
894 if (companion->ops->wakeup) {
895 companion->ops->wakeup(companion);
896 } else {
897 qemu_bh_schedule(s->async_bh);
898 }
899 }
900 }
901
902 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
903 uint32_t portcount, uint32_t firstport)
904 {
905 EHCIState *s = container_of(bus, EHCIState, bus);
906 uint32_t i;
907
908 if (firstport + portcount > NB_PORTS) {
909 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
910 "firstport on masterbus");
911 error_printf_unless_qmp(
912 "firstport value of %u makes companion take ports %u - %u, which "
913 "is outside of the valid range of 0 - %u\n", firstport, firstport,
914 firstport + portcount - 1, NB_PORTS - 1);
915 return -1;
916 }
917
918 for (i = 0; i < portcount; i++) {
919 if (s->companion_ports[firstport + i]) {
920 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
921 "an USB masterbus");
922 error_printf_unless_qmp(
923 "port %u on masterbus %s already has a companion assigned\n",
924 firstport + i, bus->qbus.name);
925 return -1;
926 }
927 }
928
929 for (i = 0; i < portcount; i++) {
930 s->companion_ports[firstport + i] = ports[i];
931 s->ports[firstport + i].speedmask |=
932 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
933 /* Ensure devs attached before the initial reset go to the companion */
934 s->portsc[firstport + i] = PORTSC_POWNER;
935 }
936
937 s->companion_count++;
938 s->mmio[0x05] = (s->companion_count << 4) | portcount;
939
940 return 0;
941 }
942
943 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
944 {
945 USBDevice *dev;
946 USBPort *port;
947 int i;
948
949 for (i = 0; i < NB_PORTS; i++) {
950 port = &ehci->ports[i];
951 if (!(ehci->portsc[i] & PORTSC_PED)) {
952 DPRINTF("Port %d not enabled\n", i);
953 continue;
954 }
955 dev = usb_find_device(port, addr);
956 if (dev != NULL) {
957 return dev;
958 }
959 }
960 return NULL;
961 }
962
963 /* 4.1 host controller initialization */
964 static void ehci_reset(void *opaque)
965 {
966 EHCIState *s = opaque;
967 int i;
968 USBDevice *devs[NB_PORTS];
969
970 trace_usb_ehci_reset();
971
972 /*
973 * Do the detach before touching portsc, so that it correctly gets send to
974 * us or to our companion based on PORTSC_POWNER before the reset.
975 */
976 for(i = 0; i < NB_PORTS; i++) {
977 devs[i] = s->ports[i].dev;
978 if (devs[i] && devs[i]->attached) {
979 usb_detach(&s->ports[i]);
980 }
981 }
982
983 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
984
985 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
986 s->usbsts = USBSTS_HALT;
987
988 s->astate = EST_INACTIVE;
989 s->pstate = EST_INACTIVE;
990
991 for(i = 0; i < NB_PORTS; i++) {
992 if (s->companion_ports[i]) {
993 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
994 } else {
995 s->portsc[i] = PORTSC_PPOWER;
996 }
997 if (devs[i] && devs[i]->attached) {
998 usb_attach(&s->ports[i]);
999 usb_device_reset(devs[i]);
1000 }
1001 }
1002 ehci_queues_rip_all(s, 0);
1003 ehci_queues_rip_all(s, 1);
1004 qemu_del_timer(s->frame_timer);
1005 qemu_bh_cancel(s->async_bh);
1006 }
1007
1008 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
1009 {
1010 EHCIState *s = ptr;
1011 uint32_t val;
1012
1013 val = s->mmio[addr];
1014
1015 return val;
1016 }
1017
1018 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
1019 {
1020 EHCIState *s = ptr;
1021 uint32_t val;
1022
1023 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
1024
1025 return val;
1026 }
1027
1028 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
1029 {
1030 EHCIState *s = ptr;
1031 uint32_t val;
1032
1033 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
1034 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
1035
1036 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
1037 return val;
1038 }
1039
1040 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
1041 {
1042 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
1043 exit(1);
1044 }
1045
1046 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
1047 {
1048 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
1049 exit(1);
1050 }
1051
1052 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
1053 {
1054 USBDevice *dev = s->ports[port].dev;
1055 uint32_t *portsc = &s->portsc[port];
1056 uint32_t orig;
1057
1058 if (s->companion_ports[port] == NULL)
1059 return;
1060
1061 owner = owner & PORTSC_POWNER;
1062 orig = *portsc & PORTSC_POWNER;
1063
1064 if (!(owner ^ orig)) {
1065 return;
1066 }
1067
1068 if (dev && dev->attached) {
1069 usb_detach(&s->ports[port]);
1070 }
1071
1072 *portsc &= ~PORTSC_POWNER;
1073 *portsc |= owner;
1074
1075 if (dev && dev->attached) {
1076 usb_attach(&s->ports[port]);
1077 }
1078 }
1079
1080 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1081 {
1082 uint32_t *portsc = &s->portsc[port];
1083 USBDevice *dev = s->ports[port].dev;
1084
1085 /* Clear rwc bits */
1086 *portsc &= ~(val & PORTSC_RWC_MASK);
1087 /* The guest may clear, but not set the PED bit */
1088 *portsc &= val | ~PORTSC_PED;
1089 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1090 handle_port_owner_write(s, port, val);
1091 /* And finally apply RO_MASK */
1092 val &= PORTSC_RO_MASK;
1093
1094 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1095 trace_usb_ehci_port_reset(port, 1);
1096 }
1097
1098 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1099 trace_usb_ehci_port_reset(port, 0);
1100 if (dev && dev->attached) {
1101 usb_port_reset(&s->ports[port]);
1102 *portsc &= ~PORTSC_CSC;
1103 }
1104
1105 /*
1106 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1107 * to SW that this port has a high speed device attached
1108 */
1109 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1110 val |= PORTSC_PED;
1111 }
1112 }
1113
1114 *portsc &= ~PORTSC_RO_MASK;
1115 *portsc |= val;
1116 }
1117
1118 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1119 {
1120 EHCIState *s = ptr;
1121 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1122 uint32_t old = *mmio;
1123 int i;
1124
1125 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1126
1127 /* Only aligned reads are allowed on OHCI */
1128 if (addr & 3) {
1129 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1130 TARGET_FMT_plx "\n", addr);
1131 return;
1132 }
1133
1134 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1135 handle_port_status_write(s, (addr-PORTSC)/4, val);
1136 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1137 return;
1138 }
1139
1140 if (addr < OPREGBASE) {
1141 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1142 TARGET_FMT_plx "\n", addr);
1143 return;
1144 }
1145
1146
1147 /* Do any register specific pre-write processing here. */
1148 switch(addr) {
1149 case USBCMD:
1150 if (val & USBCMD_HCRESET) {
1151 ehci_reset(s);
1152 val = s->usbcmd;
1153 break;
1154 }
1155
1156 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1157 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1158 if (s->pstate == EST_INACTIVE) {
1159 SET_LAST_RUN_CLOCK(s);
1160 }
1161 ehci_update_halt(s);
1162 s->async_stepdown = 0;
1163 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1164 }
1165
1166 /* not supporting dynamic frame list size at the moment */
1167 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1168 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1169 val & USBCMD_FLS);
1170 val &= ~USBCMD_FLS;
1171 }
1172 break;
1173
1174 case USBSTS:
1175 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1176 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1177 val = s->usbsts;
1178 ehci_set_interrupt(s, 0);
1179 break;
1180
1181 case USBINTR:
1182 val &= USBINTR_MASK;
1183 break;
1184
1185 case FRINDEX:
1186 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1187 break;
1188
1189 case CONFIGFLAG:
1190 val &= 0x1;
1191 if (val) {
1192 for(i = 0; i < NB_PORTS; i++)
1193 handle_port_owner_write(s, i, 0);
1194 }
1195 break;
1196
1197 case PERIODICLISTBASE:
1198 if (ehci_periodic_enabled(s)) {
1199 fprintf(stderr,
1200 "ehci: PERIODIC list base register set while periodic schedule\n"
1201 " is enabled and HC is enabled\n");
1202 }
1203 break;
1204
1205 case ASYNCLISTADDR:
1206 if (ehci_async_enabled(s)) {
1207 fprintf(stderr,
1208 "ehci: ASYNC list address register set while async schedule\n"
1209 " is enabled and HC is enabled\n");
1210 }
1211 break;
1212 }
1213
1214 *mmio = val;
1215 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1216 }
1217
1218
1219 // TODO : Put in common header file, duplication from usb-ohci.c
1220
1221 /* Get an array of dwords from main memory */
1222 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1223 uint32_t *buf, int num)
1224 {
1225 int i;
1226
1227 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1228 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1229 *buf = le32_to_cpu(*buf);
1230 }
1231
1232 return 1;
1233 }
1234
1235 /* Put an array of dwords in to main memory */
1236 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1237 uint32_t *buf, int num)
1238 {
1239 int i;
1240
1241 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1242 uint32_t tmp = cpu_to_le32(*buf);
1243 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1244 }
1245
1246 return 1;
1247 }
1248
1249 // 4.10.2
1250
1251 static int ehci_qh_do_overlay(EHCIQueue *q)
1252 {
1253 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1254 int i;
1255 int dtoggle;
1256 int ping;
1257 int eps;
1258 int reload;
1259
1260 assert(p != NULL);
1261 assert(p->qtdaddr == q->qtdaddr);
1262
1263 // remember values in fields to preserve in qh after overlay
1264
1265 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1266 ping = q->qh.token & QTD_TOKEN_PING;
1267
1268 q->qh.current_qtd = p->qtdaddr;
1269 q->qh.next_qtd = p->qtd.next;
1270 q->qh.altnext_qtd = p->qtd.altnext;
1271 q->qh.token = p->qtd.token;
1272
1273
1274 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1275 if (eps == EHCI_QH_EPS_HIGH) {
1276 q->qh.token &= ~QTD_TOKEN_PING;
1277 q->qh.token |= ping;
1278 }
1279
1280 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1281 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1282
1283 for (i = 0; i < 5; i++) {
1284 q->qh.bufptr[i] = p->qtd.bufptr[i];
1285 }
1286
1287 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1288 // preserve QH DT bit
1289 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1290 q->qh.token |= dtoggle;
1291 }
1292
1293 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1294 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1295
1296 put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh,
1297 sizeof(EHCIqh) >> 2);
1298
1299 return 0;
1300 }
1301
1302 static int ehci_init_transfer(EHCIPacket *p)
1303 {
1304 uint32_t cpage, offset, bytes, plen;
1305 dma_addr_t page;
1306
1307 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1308 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1309 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1310 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
1311
1312 while (bytes > 0) {
1313 if (cpage > 4) {
1314 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1315 return USB_RET_PROCERR;
1316 }
1317
1318 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1319 page += offset;
1320 plen = bytes;
1321 if (plen > 4096 - offset) {
1322 plen = 4096 - offset;
1323 offset = 0;
1324 cpage++;
1325 }
1326
1327 qemu_sglist_add(&p->sgl, page, plen);
1328 bytes -= plen;
1329 }
1330 return 0;
1331 }
1332
1333 static void ehci_finish_transfer(EHCIQueue *q, int status)
1334 {
1335 uint32_t cpage, offset;
1336
1337 if (status > 0) {
1338 /* update cpage & offset */
1339 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1340 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1341
1342 offset += status;
1343 cpage += offset >> QTD_BUFPTR_SH;
1344 offset &= ~QTD_BUFPTR_MASK;
1345
1346 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1347 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1348 q->qh.bufptr[0] |= offset;
1349 }
1350 }
1351
1352 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1353 {
1354 EHCIPacket *p;
1355 EHCIState *s = port->opaque;
1356 uint32_t portsc = s->portsc[port->index];
1357
1358 if (portsc & PORTSC_POWNER) {
1359 USBPort *companion = s->companion_ports[port->index];
1360 companion->ops->complete(companion, packet);
1361 return;
1362 }
1363
1364 p = container_of(packet, EHCIPacket, packet);
1365 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1366 assert(p->async == EHCI_ASYNC_INFLIGHT);
1367 p->async = EHCI_ASYNC_FINISHED;
1368 p->usb_status = packet->result;
1369
1370 if (p->queue->async) {
1371 qemu_bh_schedule(p->queue->ehci->async_bh);
1372 }
1373 }
1374
1375 static void ehci_execute_complete(EHCIQueue *q)
1376 {
1377 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1378
1379 assert(p != NULL);
1380 assert(p->qtdaddr == q->qtdaddr);
1381 assert(p->async != EHCI_ASYNC_INFLIGHT);
1382 p->async = EHCI_ASYNC_NONE;
1383
1384 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1385 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1386
1387 if (p->usb_status < 0) {
1388 switch (p->usb_status) {
1389 case USB_RET_IOERROR:
1390 case USB_RET_NODEV:
1391 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1392 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1393 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1394 break;
1395 case USB_RET_STALL:
1396 q->qh.token |= QTD_TOKEN_HALT;
1397 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1398 break;
1399 case USB_RET_NAK:
1400 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1401 return; /* We're not done yet with this transaction */
1402 case USB_RET_BABBLE:
1403 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1404 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1405 break;
1406 default:
1407 /* should not be triggerable */
1408 fprintf(stderr, "USB invalid response %d\n", p->usb_status);
1409 assert(0);
1410 break;
1411 }
1412 } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) {
1413 p->usb_status = USB_RET_BABBLE;
1414 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1415 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1416 } else {
1417 // TODO check 4.12 for splits
1418
1419 if (p->tbytes && p->pid == USB_TOKEN_IN) {
1420 p->tbytes -= p->usb_status;
1421 } else {
1422 p->tbytes = 0;
1423 }
1424
1425 DPRINTF("updating tbytes to %d\n", p->tbytes);
1426 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES);
1427 }
1428 ehci_finish_transfer(q, p->usb_status);
1429 qemu_sglist_destroy(&p->sgl);
1430 usb_packet_unmap(&p->packet);
1431
1432 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1433 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1434
1435 if (q->qh.token & QTD_TOKEN_IOC) {
1436 ehci_record_interrupt(q->ehci, USBSTS_INT);
1437 }
1438 }
1439
1440 // 4.10.3
1441
1442 static int ehci_execute(EHCIPacket *p, const char *action)
1443 {
1444 USBEndpoint *ep;
1445 int ret;
1446 int endp;
1447
1448 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1449 fprintf(stderr, "Attempting to execute inactive qtd\n");
1450 return USB_RET_PROCERR;
1451 }
1452
1453 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1454 if (p->tbytes > BUFF_SIZE) {
1455 fprintf(stderr, "Request for more bytes than allowed\n");
1456 return USB_RET_PROCERR;
1457 }
1458
1459 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1460 switch (p->pid) {
1461 case 0:
1462 p->pid = USB_TOKEN_OUT;
1463 break;
1464 case 1:
1465 p->pid = USB_TOKEN_IN;
1466 break;
1467 case 2:
1468 p->pid = USB_TOKEN_SETUP;
1469 break;
1470 default:
1471 fprintf(stderr, "bad token\n");
1472 break;
1473 }
1474
1475 if (ehci_init_transfer(p) != 0) {
1476 return USB_RET_PROCERR;
1477 }
1478
1479 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1480 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1481
1482 usb_packet_setup(&p->packet, p->pid, ep);
1483 usb_packet_map(&p->packet, &p->sgl);
1484
1485 trace_usb_ehci_packet_action(p->queue, p, action);
1486 ret = usb_handle_packet(p->queue->dev, &p->packet);
1487 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1488 "(total %d) endp %x ret %d\n",
1489 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1490 q->packet.iov.size, q->tbytes, endp, ret);
1491
1492 if (ret > BUFF_SIZE) {
1493 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1494 return USB_RET_PROCERR;
1495 }
1496
1497 return ret;
1498 }
1499
1500 /* 4.7.2
1501 */
1502
1503 static int ehci_process_itd(EHCIState *ehci,
1504 EHCIitd *itd)
1505 {
1506 USBDevice *dev;
1507 USBEndpoint *ep;
1508 int ret;
1509 uint32_t i, len, pid, dir, devaddr, endp;
1510 uint32_t pg, off, ptr1, ptr2, max, mult;
1511
1512 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1513 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1514 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1515 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1516 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1517
1518 for(i = 0; i < 8; i++) {
1519 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1520 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1521 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1522 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1523 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1524 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1525
1526 if (len > max * mult) {
1527 len = max * mult;
1528 }
1529
1530 if (len > BUFF_SIZE) {
1531 return USB_RET_PROCERR;
1532 }
1533
1534 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1535 if (off + len > 4096) {
1536 /* transfer crosses page border */
1537 uint32_t len2 = off + len - 4096;
1538 uint32_t len1 = len - len2;
1539 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1540 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1541 } else {
1542 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1543 }
1544
1545 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1546
1547 dev = ehci_find_device(ehci, devaddr);
1548 ep = usb_ep_get(dev, pid, endp);
1549 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1550 usb_packet_setup(&ehci->ipacket, pid, ep);
1551 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1552 ret = usb_handle_packet(dev, &ehci->ipacket);
1553 assert(ret != USB_RET_ASYNC);
1554 usb_packet_unmap(&ehci->ipacket);
1555 } else {
1556 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1557 ret = USB_RET_NAK;
1558 }
1559 qemu_sglist_destroy(&ehci->isgl);
1560
1561 if (ret < 0) {
1562 switch (ret) {
1563 default:
1564 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1565 /* Fall through */
1566 case USB_RET_IOERROR:
1567 case USB_RET_NODEV:
1568 /* 3.3.2: XACTERR is only allowed on IN transactions */
1569 if (dir) {
1570 itd->transact[i] |= ITD_XACT_XACTERR;
1571 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1572 }
1573 break;
1574 case USB_RET_BABBLE:
1575 itd->transact[i] |= ITD_XACT_BABBLE;
1576 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1577 break;
1578 case USB_RET_NAK:
1579 /* no data for us, so do a zero-length transfer */
1580 ret = 0;
1581 break;
1582 }
1583 }
1584 if (ret >= 0) {
1585 if (!dir) {
1586 /* OUT */
1587 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1588 } else {
1589 /* IN */
1590 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1591 }
1592 }
1593 if (itd->transact[i] & ITD_XACT_IOC) {
1594 ehci_record_interrupt(ehci, USBSTS_INT);
1595 }
1596 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1597 }
1598 }
1599 return 0;
1600 }
1601
1602
1603 /*
1604 * Write the qh back to guest physical memory. This step isn't
1605 * in the EHCI spec but we need to do it since we don't share
1606 * physical memory with our guest VM.
1607 *
1608 * The first three dwords are read-only for the EHCI, so skip them
1609 * when writing back the qh.
1610 */
1611 static void ehci_flush_qh(EHCIQueue *q)
1612 {
1613 uint32_t *qh = (uint32_t *) &q->qh;
1614 uint32_t dwords = sizeof(EHCIqh) >> 2;
1615 uint32_t addr = NLPTR_GET(q->qhaddr);
1616
1617 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1618 }
1619
1620 /* This state is the entry point for asynchronous schedule
1621 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1622 */
1623 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1624 {
1625 EHCIqh qh;
1626 int i = 0;
1627 int again = 0;
1628 uint32_t entry = ehci->asynclistaddr;
1629
1630 /* set reclamation flag at start event (4.8.6) */
1631 if (async) {
1632 ehci_set_usbsts(ehci, USBSTS_REC);
1633 }
1634
1635 ehci_queues_rip_unused(ehci, async, 0);
1636
1637 /* Find the head of the list (4.9.1.1) */
1638 for(i = 0; i < MAX_QH; i++) {
1639 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1640 sizeof(EHCIqh) >> 2);
1641 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1642
1643 if (qh.epchar & QH_EPCHAR_H) {
1644 if (async) {
1645 entry |= (NLPTR_TYPE_QH << 1);
1646 }
1647
1648 ehci_set_fetch_addr(ehci, async, entry);
1649 ehci_set_state(ehci, async, EST_FETCHENTRY);
1650 again = 1;
1651 goto out;
1652 }
1653
1654 entry = qh.next;
1655 if (entry == ehci->asynclistaddr) {
1656 break;
1657 }
1658 }
1659
1660 /* no head found for list. */
1661
1662 ehci_set_state(ehci, async, EST_ACTIVE);
1663
1664 out:
1665 return again;
1666 }
1667
1668
1669 /* This state is the entry point for periodic schedule processing as
1670 * well as being a continuation state for async processing.
1671 */
1672 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1673 {
1674 int again = 0;
1675 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1676
1677 if (NLPTR_TBIT(entry)) {
1678 ehci_set_state(ehci, async, EST_ACTIVE);
1679 goto out;
1680 }
1681
1682 /* section 4.8, only QH in async schedule */
1683 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1684 fprintf(stderr, "non queue head request in async schedule\n");
1685 return -1;
1686 }
1687
1688 switch (NLPTR_TYPE_GET(entry)) {
1689 case NLPTR_TYPE_QH:
1690 ehci_set_state(ehci, async, EST_FETCHQH);
1691 again = 1;
1692 break;
1693
1694 case NLPTR_TYPE_ITD:
1695 ehci_set_state(ehci, async, EST_FETCHITD);
1696 again = 1;
1697 break;
1698
1699 case NLPTR_TYPE_STITD:
1700 ehci_set_state(ehci, async, EST_FETCHSITD);
1701 again = 1;
1702 break;
1703
1704 default:
1705 /* TODO: handle FSTN type */
1706 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1707 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1708 return -1;
1709 }
1710
1711 out:
1712 return again;
1713 }
1714
1715 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1716 {
1717 EHCIPacket *p;
1718 uint32_t entry, devaddr;
1719 EHCIQueue *q;
1720
1721 entry = ehci_get_fetch_addr(ehci, async);
1722 q = ehci_find_queue_by_qh(ehci, entry, async);
1723 if (NULL == q) {
1724 q = ehci_alloc_queue(ehci, entry, async);
1725 }
1726 p = QTAILQ_FIRST(&q->packets);
1727
1728 q->seen++;
1729 if (q->seen > 1) {
1730 /* we are going in circles -- stop processing */
1731 ehci_set_state(ehci, async, EST_ACTIVE);
1732 q = NULL;
1733 goto out;
1734 }
1735
1736 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1737 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1738 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1739
1740 devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1741 if (q->dev != NULL && q->dev->addr != devaddr) {
1742 if (!QTAILQ_EMPTY(&q->packets)) {
1743 /* should not happen (guest bug) */
1744 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
1745 ehci_free_packet(p);
1746 }
1747 }
1748 q->dev = NULL;
1749 }
1750 if (q->dev == NULL) {
1751 q->dev = ehci_find_device(q->ehci, devaddr);
1752 }
1753
1754 if (p && p->async == EHCI_ASYNC_INFLIGHT) {
1755 /* I/O still in progress -- skip queue */
1756 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1757 goto out;
1758 }
1759 if (p && p->async == EHCI_ASYNC_FINISHED) {
1760 /* I/O finished -- continue processing queue */
1761 trace_usb_ehci_packet_action(p->queue, p, "complete");
1762 ehci_set_state(ehci, async, EST_EXECUTING);
1763 goto out;
1764 }
1765
1766 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1767
1768 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1769 if (ehci->usbsts & USBSTS_REC) {
1770 ehci_clear_usbsts(ehci, USBSTS_REC);
1771 } else {
1772 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1773 " - done processing\n", q->qhaddr);
1774 ehci_set_state(ehci, async, EST_ACTIVE);
1775 q = NULL;
1776 goto out;
1777 }
1778 }
1779
1780 #if EHCI_DEBUG
1781 if (q->qhaddr != q->qh.next) {
1782 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1783 q->qhaddr,
1784 q->qh.epchar & QH_EPCHAR_H,
1785 q->qh.token & QTD_TOKEN_HALT,
1786 q->qh.token & QTD_TOKEN_ACTIVE,
1787 q->qh.next);
1788 }
1789 #endif
1790
1791 if (q->qh.token & QTD_TOKEN_HALT) {
1792 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1793
1794 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1795 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1796 q->qtdaddr = q->qh.current_qtd;
1797 ehci_set_state(ehci, async, EST_FETCHQTD);
1798
1799 } else {
1800 /* EHCI spec version 1.0 Section 4.10.2 */
1801 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1802 }
1803
1804 out:
1805 return q;
1806 }
1807
1808 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1809 {
1810 uint32_t entry;
1811 EHCIitd itd;
1812
1813 assert(!async);
1814 entry = ehci_get_fetch_addr(ehci, async);
1815
1816 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1817 sizeof(EHCIitd) >> 2);
1818 ehci_trace_itd(ehci, entry, &itd);
1819
1820 if (ehci_process_itd(ehci, &itd) != 0) {
1821 return -1;
1822 }
1823
1824 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1825 sizeof(EHCIitd) >> 2);
1826 ehci_set_fetch_addr(ehci, async, itd.next);
1827 ehci_set_state(ehci, async, EST_FETCHENTRY);
1828
1829 return 1;
1830 }
1831
1832 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1833 {
1834 uint32_t entry;
1835 EHCIsitd sitd;
1836
1837 assert(!async);
1838 entry = ehci_get_fetch_addr(ehci, async);
1839
1840 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1841 sizeof(EHCIsitd) >> 2);
1842 ehci_trace_sitd(ehci, entry, &sitd);
1843
1844 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1845 /* siTD is not active, nothing to do */;
1846 } else {
1847 /* TODO: split transfers are not implemented */
1848 fprintf(stderr, "WARNING: Skipping active siTD\n");
1849 }
1850
1851 ehci_set_fetch_addr(ehci, async, sitd.next);
1852 ehci_set_state(ehci, async, EST_FETCHENTRY);
1853 return 1;
1854 }
1855
1856 /* Section 4.10.2 - paragraph 3 */
1857 static int ehci_state_advqueue(EHCIQueue *q)
1858 {
1859 #if 0
1860 /* TO-DO: 4.10.2 - paragraph 2
1861 * if I-bit is set to 1 and QH is not active
1862 * go to horizontal QH
1863 */
1864 if (I-bit set) {
1865 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1866 goto out;
1867 }
1868 #endif
1869
1870 /*
1871 * want data and alt-next qTD is valid
1872 */
1873 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1874 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1875 q->qtdaddr = q->qh.altnext_qtd;
1876 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1877
1878 /*
1879 * next qTD is valid
1880 */
1881 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1882 q->qtdaddr = q->qh.next_qtd;
1883 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1884
1885 /*
1886 * no valid qTD, try next QH
1887 */
1888 } else {
1889 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1890 }
1891
1892 return 1;
1893 }
1894
1895 /* Section 4.10.2 - paragraph 4 */
1896 static int ehci_state_fetchqtd(EHCIQueue *q)
1897 {
1898 EHCIqtd qtd;
1899 EHCIPacket *p;
1900 int again = 0;
1901
1902 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1903 sizeof(EHCIqtd) >> 2);
1904 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1905
1906 p = QTAILQ_FIRST(&q->packets);
1907 while (p != NULL && p->qtdaddr != q->qtdaddr) {
1908 /* should not happen (guest bug) */
1909 ehci_free_packet(p);
1910 p = QTAILQ_FIRST(&q->packets);
1911 }
1912 if (p != NULL) {
1913 ehci_qh_do_overlay(q);
1914 ehci_flush_qh(q);
1915 if (p->async == EHCI_ASYNC_INFLIGHT) {
1916 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1917 } else {
1918 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1919 }
1920 again = 1;
1921 } else if (qtd.token & QTD_TOKEN_ACTIVE) {
1922 p = ehci_alloc_packet(q);
1923 p->qtdaddr = q->qtdaddr;
1924 p->qtd = qtd;
1925 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1926 again = 1;
1927 } else {
1928 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1929 again = 1;
1930 }
1931
1932 return again;
1933 }
1934
1935 static int ehci_state_horizqh(EHCIQueue *q)
1936 {
1937 int again = 0;
1938
1939 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1940 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1941 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1942 again = 1;
1943 } else {
1944 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1945 }
1946
1947 return again;
1948 }
1949
1950 static void ehci_fill_queue(EHCIPacket *p)
1951 {
1952 EHCIQueue *q = p->queue;
1953 EHCIqtd qtd = p->qtd;
1954 uint32_t qtdaddr;
1955
1956 for (;;) {
1957 if (NLPTR_TBIT(qtd.altnext) == 0) {
1958 break;
1959 }
1960 if (NLPTR_TBIT(qtd.next) != 0) {
1961 break;
1962 }
1963 qtdaddr = qtd.next;
1964 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1965 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
1966 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1967 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1968 break;
1969 }
1970 p = ehci_alloc_packet(q);
1971 p->qtdaddr = qtdaddr;
1972 p->qtd = qtd;
1973 p->usb_status = ehci_execute(p, "queue");
1974 assert(p->usb_status = USB_RET_ASYNC);
1975 p->async = EHCI_ASYNC_INFLIGHT;
1976 }
1977 }
1978
1979 static int ehci_state_execute(EHCIQueue *q)
1980 {
1981 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1982 int again = 0;
1983
1984 assert(p != NULL);
1985 assert(p->qtdaddr == q->qtdaddr);
1986
1987 if (ehci_qh_do_overlay(q) != 0) {
1988 return -1;
1989 }
1990
1991 // TODO verify enough time remains in the uframe as in 4.4.1.1
1992 // TODO write back ptr to async list when done or out of time
1993 // TODO Windows does not seem to ever set the MULT field
1994
1995 if (!q->async) {
1996 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1997 if (!transactCtr) {
1998 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1999 again = 1;
2000 goto out;
2001 }
2002 }
2003
2004 if (q->async) {
2005 ehci_set_usbsts(q->ehci, USBSTS_REC);
2006 }
2007
2008 p->usb_status = ehci_execute(p, "process");
2009 if (p->usb_status == USB_RET_PROCERR) {
2010 again = -1;
2011 goto out;
2012 }
2013 if (p->usb_status == USB_RET_ASYNC) {
2014 ehci_flush_qh(q);
2015 trace_usb_ehci_packet_action(p->queue, p, "async");
2016 p->async = EHCI_ASYNC_INFLIGHT;
2017 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2018 again = 1;
2019 ehci_fill_queue(p);
2020 goto out;
2021 }
2022
2023 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
2024 again = 1;
2025
2026 out:
2027 return again;
2028 }
2029
2030 static int ehci_state_executing(EHCIQueue *q)
2031 {
2032 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2033 int again = 0;
2034
2035 assert(p != NULL);
2036 assert(p->qtdaddr == q->qtdaddr);
2037
2038 ehci_execute_complete(q);
2039 if (p->usb_status == USB_RET_ASYNC) {
2040 goto out;
2041 }
2042 if (p->usb_status == USB_RET_PROCERR) {
2043 again = -1;
2044 goto out;
2045 }
2046
2047 // 4.10.3
2048 if (!q->async) {
2049 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2050 transactCtr--;
2051 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
2052 // 4.10.3, bottom of page 82, should exit this state when transaction
2053 // counter decrements to 0
2054 }
2055
2056 /* 4.10.5 */
2057 if (p->usb_status == USB_RET_NAK) {
2058 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2059 } else {
2060 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
2061 }
2062
2063 again = 1;
2064
2065 out:
2066 ehci_flush_qh(q);
2067 return again;
2068 }
2069
2070
2071 static int ehci_state_writeback(EHCIQueue *q)
2072 {
2073 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2074 int again = 0;
2075
2076 /* Write back the QTD from the QH area */
2077 assert(p != NULL);
2078 assert(p->qtdaddr == q->qtdaddr);
2079
2080 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2081 put_dwords(q->ehci, NLPTR_GET(p->qtdaddr), (uint32_t *) &q->qh.next_qtd,
2082 sizeof(EHCIqtd) >> 2);
2083 ehci_free_packet(p);
2084
2085 /*
2086 * EHCI specs say go horizontal here.
2087 *
2088 * We can also advance the queue here for performance reasons. We
2089 * need to take care to only take that shortcut in case we've
2090 * processed the qtd just written back without errors, i.e. halt
2091 * bit is clear.
2092 */
2093 if (q->qh.token & QTD_TOKEN_HALT) {
2094 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2095 again = 1;
2096 } else {
2097 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2098 again = 1;
2099 }
2100 return again;
2101 }
2102
2103 /*
2104 * This is the state machine that is common to both async and periodic
2105 */
2106
2107 static void ehci_advance_state(EHCIState *ehci, int async)
2108 {
2109 EHCIQueue *q = NULL;
2110 int again;
2111
2112 do {
2113 switch(ehci_get_state(ehci, async)) {
2114 case EST_WAITLISTHEAD:
2115 again = ehci_state_waitlisthead(ehci, async);
2116 break;
2117
2118 case EST_FETCHENTRY:
2119 again = ehci_state_fetchentry(ehci, async);
2120 break;
2121
2122 case EST_FETCHQH:
2123 q = ehci_state_fetchqh(ehci, async);
2124 if (q != NULL) {
2125 assert(q->async == async);
2126 again = 1;
2127 } else {
2128 again = 0;
2129 }
2130 break;
2131
2132 case EST_FETCHITD:
2133 again = ehci_state_fetchitd(ehci, async);
2134 break;
2135
2136 case EST_FETCHSITD:
2137 again = ehci_state_fetchsitd(ehci, async);
2138 break;
2139
2140 case EST_ADVANCEQUEUE:
2141 again = ehci_state_advqueue(q);
2142 break;
2143
2144 case EST_FETCHQTD:
2145 again = ehci_state_fetchqtd(q);
2146 break;
2147
2148 case EST_HORIZONTALQH:
2149 again = ehci_state_horizqh(q);
2150 break;
2151
2152 case EST_EXECUTE:
2153 again = ehci_state_execute(q);
2154 if (async) {
2155 ehci->async_stepdown = 0;
2156 }
2157 break;
2158
2159 case EST_EXECUTING:
2160 assert(q != NULL);
2161 if (async) {
2162 ehci->async_stepdown = 0;
2163 }
2164 again = ehci_state_executing(q);
2165 break;
2166
2167 case EST_WRITEBACK:
2168 assert(q != NULL);
2169 again = ehci_state_writeback(q);
2170 break;
2171
2172 default:
2173 fprintf(stderr, "Bad state!\n");
2174 again = -1;
2175 assert(0);
2176 break;
2177 }
2178
2179 if (again < 0) {
2180 fprintf(stderr, "processing error - resetting ehci HC\n");
2181 ehci_reset(ehci);
2182 again = 0;
2183 }
2184 }
2185 while (again);
2186
2187 ehci_commit_interrupt(ehci);
2188 }
2189
2190 static void ehci_advance_async_state(EHCIState *ehci)
2191 {
2192 const int async = 1;
2193
2194 switch(ehci_get_state(ehci, async)) {
2195 case EST_INACTIVE:
2196 if (!ehci_async_enabled(ehci)) {
2197 break;
2198 }
2199 ehci_set_state(ehci, async, EST_ACTIVE);
2200 // No break, fall through to ACTIVE
2201
2202 case EST_ACTIVE:
2203 if (!ehci_async_enabled(ehci)) {
2204 ehci_queues_rip_all(ehci, async);
2205 ehci_set_state(ehci, async, EST_INACTIVE);
2206 break;
2207 }
2208
2209 /* make sure guest has acknowledged the doorbell interrupt */
2210 /* TO-DO: is this really needed? */
2211 if (ehci->usbsts & USBSTS_IAA) {
2212 DPRINTF("IAA status bit still set.\n");
2213 break;
2214 }
2215
2216 /* check that address register has been set */
2217 if (ehci->asynclistaddr == 0) {
2218 break;
2219 }
2220
2221 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2222 ehci_advance_state(ehci, async);
2223
2224 /* If the doorbell is set, the guest wants to make a change to the
2225 * schedule. The host controller needs to release cached data.
2226 * (section 4.8.2)
2227 */
2228 if (ehci->usbcmd & USBCMD_IAAD) {
2229 /* Remove all unseen qhs from the async qhs queue */
2230 ehci_queues_rip_unused(ehci, async, 1);
2231 DPRINTF("ASYNC: doorbell request acknowledged\n");
2232 ehci->usbcmd &= ~USBCMD_IAAD;
2233 ehci_set_interrupt(ehci, USBSTS_IAA);
2234 }
2235 break;
2236
2237 default:
2238 /* this should only be due to a developer mistake */
2239 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2240 "Resetting to active\n", ehci->astate);
2241 assert(0);
2242 }
2243 }
2244
2245 static void ehci_advance_periodic_state(EHCIState *ehci)
2246 {
2247 uint32_t entry;
2248 uint32_t list;
2249 const int async = 0;
2250
2251 // 4.6
2252
2253 switch(ehci_get_state(ehci, async)) {
2254 case EST_INACTIVE:
2255 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2256 ehci_set_state(ehci, async, EST_ACTIVE);
2257 // No break, fall through to ACTIVE
2258 } else
2259 break;
2260
2261 case EST_ACTIVE:
2262 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2263 ehci_queues_rip_all(ehci, async);
2264 ehci_set_state(ehci, async, EST_INACTIVE);
2265 break;
2266 }
2267
2268 list = ehci->periodiclistbase & 0xfffff000;
2269 /* check that register has been set */
2270 if (list == 0) {
2271 break;
2272 }
2273 list |= ((ehci->frindex & 0x1ff8) >> 1);
2274
2275 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2276 entry = le32_to_cpu(entry);
2277
2278 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2279 ehci->frindex / 8, list, entry);
2280 ehci_set_fetch_addr(ehci, async,entry);
2281 ehci_set_state(ehci, async, EST_FETCHENTRY);
2282 ehci_advance_state(ehci, async);
2283 ehci_queues_rip_unused(ehci, async, 0);
2284 break;
2285
2286 default:
2287 /* this should only be due to a developer mistake */
2288 fprintf(stderr, "ehci: Bad periodic state %d. "
2289 "Resetting to active\n", ehci->pstate);
2290 assert(0);
2291 }
2292 }
2293
2294 static void ehci_update_frindex(EHCIState *ehci, int frames)
2295 {
2296 int i;
2297
2298 if (!ehci_enabled(ehci)) {
2299 return;
2300 }
2301
2302 for (i = 0; i < frames; i++) {
2303 ehci->frindex += 8;
2304
2305 if (ehci->frindex == 0x00002000) {
2306 ehci_set_interrupt(ehci, USBSTS_FLR);
2307 }
2308
2309 if (ehci->frindex == 0x00004000) {
2310 ehci_set_interrupt(ehci, USBSTS_FLR);
2311 ehci->frindex = 0;
2312 }
2313 }
2314 }
2315
2316 static void ehci_frame_timer(void *opaque)
2317 {
2318 EHCIState *ehci = opaque;
2319 int schedules = 0;
2320 int64_t expire_time, t_now;
2321 uint64_t ns_elapsed;
2322 int frames, skipped_frames;
2323 int i;
2324
2325 t_now = qemu_get_clock_ns(vm_clock);
2326 ns_elapsed = t_now - ehci->last_run_ns;
2327 frames = ns_elapsed / FRAME_TIMER_NS;
2328
2329 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2330 schedules++;
2331 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
2332
2333 if (frames > ehci->maxframes) {
2334 skipped_frames = frames - ehci->maxframes;
2335 ehci_update_frindex(ehci, skipped_frames);
2336 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2337 frames -= skipped_frames;
2338 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2339 }
2340
2341 for (i = 0; i < frames; i++) {
2342 ehci_update_frindex(ehci, 1);
2343 ehci_advance_periodic_state(ehci);
2344 ehci->last_run_ns += FRAME_TIMER_NS;
2345 }
2346 } else {
2347 if (ehci->async_stepdown < ehci->maxframes / 2) {
2348 ehci->async_stepdown++;
2349 }
2350 expire_time = t_now + (get_ticks_per_sec()
2351 * ehci->async_stepdown / FRAME_TIMER_FREQ);
2352 ehci_update_frindex(ehci, frames);
2353 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2354 }
2355
2356 /* Async is not inside loop since it executes everything it can once
2357 * called
2358 */
2359 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2360 schedules++;
2361 qemu_bh_schedule(ehci->async_bh);
2362 }
2363
2364 if (schedules) {
2365 qemu_mod_timer(ehci->frame_timer, expire_time);
2366 }
2367 }
2368
2369 static void ehci_async_bh(void *opaque)
2370 {
2371 EHCIState *ehci = opaque;
2372 ehci_advance_async_state(ehci);
2373 }
2374
2375 static const MemoryRegionOps ehci_mem_ops = {
2376 .old_mmio = {
2377 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2378 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2379 },
2380 .endianness = DEVICE_LITTLE_ENDIAN,
2381 };
2382
2383 static int usb_ehci_initfn(PCIDevice *dev);
2384
2385 static USBPortOps ehci_port_ops = {
2386 .attach = ehci_attach,
2387 .detach = ehci_detach,
2388 .child_detach = ehci_child_detach,
2389 .wakeup = ehci_wakeup,
2390 .complete = ehci_async_complete_packet,
2391 };
2392
2393 static USBBusOps ehci_bus_ops = {
2394 .register_companion = ehci_register_companion,
2395 };
2396
2397 static int usb_ehci_post_load(void *opaque, int version_id)
2398 {
2399 EHCIState *s = opaque;
2400 int i;
2401
2402 for (i = 0; i < NB_PORTS; i++) {
2403 USBPort *companion = s->companion_ports[i];
2404 if (companion == NULL) {
2405 continue;
2406 }
2407 if (s->portsc[i] & PORTSC_POWNER) {
2408 companion->dev = s->ports[i].dev;
2409 } else {
2410 companion->dev = NULL;
2411 }
2412 }
2413
2414 return 0;
2415 }
2416
2417 static const VMStateDescription vmstate_ehci = {
2418 .name = "ehci",
2419 .version_id = 1,
2420 .post_load = usb_ehci_post_load,
2421 .fields = (VMStateField[]) {
2422 VMSTATE_PCI_DEVICE(dev, EHCIState),
2423 /* mmio registers */
2424 VMSTATE_UINT32(usbcmd, EHCIState),
2425 VMSTATE_UINT32(usbsts, EHCIState),
2426 VMSTATE_UINT32(usbintr, EHCIState),
2427 VMSTATE_UINT32(frindex, EHCIState),
2428 VMSTATE_UINT32(ctrldssegment, EHCIState),
2429 VMSTATE_UINT32(periodiclistbase, EHCIState),
2430 VMSTATE_UINT32(asynclistaddr, EHCIState),
2431 VMSTATE_UINT32(configflag, EHCIState),
2432 VMSTATE_UINT32(portsc[0], EHCIState),
2433 VMSTATE_UINT32(portsc[1], EHCIState),
2434 VMSTATE_UINT32(portsc[2], EHCIState),
2435 VMSTATE_UINT32(portsc[3], EHCIState),
2436 VMSTATE_UINT32(portsc[4], EHCIState),
2437 VMSTATE_UINT32(portsc[5], EHCIState),
2438 /* frame timer */
2439 VMSTATE_TIMER(frame_timer, EHCIState),
2440 VMSTATE_UINT64(last_run_ns, EHCIState),
2441 VMSTATE_UINT32(async_stepdown, EHCIState),
2442 /* schedule state */
2443 VMSTATE_UINT32(astate, EHCIState),
2444 VMSTATE_UINT32(pstate, EHCIState),
2445 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2446 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2447 VMSTATE_END_OF_LIST()
2448 }
2449 };
2450
2451 static Property ehci_properties[] = {
2452 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2453 DEFINE_PROP_END_OF_LIST(),
2454 };
2455
2456 static void ehci_class_init(ObjectClass *klass, void *data)
2457 {
2458 DeviceClass *dc = DEVICE_CLASS(klass);
2459 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2460
2461 k->init = usb_ehci_initfn;
2462 k->vendor_id = PCI_VENDOR_ID_INTEL;
2463 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2464 k->revision = 0x10;
2465 k->class_id = PCI_CLASS_SERIAL_USB;
2466 dc->vmsd = &vmstate_ehci;
2467 dc->props = ehci_properties;
2468 }
2469
2470 static TypeInfo ehci_info = {
2471 .name = "usb-ehci",
2472 .parent = TYPE_PCI_DEVICE,
2473 .instance_size = sizeof(EHCIState),
2474 .class_init = ehci_class_init,
2475 };
2476
2477 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2478 {
2479 DeviceClass *dc = DEVICE_CLASS(klass);
2480 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2481
2482 k->init = usb_ehci_initfn;
2483 k->vendor_id = PCI_VENDOR_ID_INTEL;
2484 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2485 k->revision = 0x03;
2486 k->class_id = PCI_CLASS_SERIAL_USB;
2487 dc->vmsd = &vmstate_ehci;
2488 dc->props = ehci_properties;
2489 }
2490
2491 static TypeInfo ich9_ehci_info = {
2492 .name = "ich9-usb-ehci1",
2493 .parent = TYPE_PCI_DEVICE,
2494 .instance_size = sizeof(EHCIState),
2495 .class_init = ich9_ehci_class_init,
2496 };
2497
2498 static int usb_ehci_initfn(PCIDevice *dev)
2499 {
2500 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2501 uint8_t *pci_conf = s->dev.config;
2502 int i;
2503
2504 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2505
2506 /* capabilities pointer */
2507 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2508 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2509
2510 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2511 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2512 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2513
2514 // pci_conf[0x50] = 0x01; // power management caps
2515
2516 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2517 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2518 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2519
2520 pci_conf[0x64] = 0x00;
2521 pci_conf[0x65] = 0x00;
2522 pci_conf[0x66] = 0x00;
2523 pci_conf[0x67] = 0x00;
2524 pci_conf[0x68] = 0x01;
2525 pci_conf[0x69] = 0x00;
2526 pci_conf[0x6a] = 0x00;
2527 pci_conf[0x6b] = 0x00; // USBLEGSUP
2528 pci_conf[0x6c] = 0x00;
2529 pci_conf[0x6d] = 0x00;
2530 pci_conf[0x6e] = 0x00;
2531 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2532
2533 // 2.2 host controller interface version
2534 s->mmio[0x00] = (uint8_t) OPREGBASE;
2535 s->mmio[0x01] = 0x00;
2536 s->mmio[0x02] = 0x00;
2537 s->mmio[0x03] = 0x01; // HC version
2538 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2539 s->mmio[0x05] = 0x00; // No companion ports at present
2540 s->mmio[0x06] = 0x00;
2541 s->mmio[0x07] = 0x00;
2542 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2543 s->mmio[0x09] = 0x68; // EECP
2544 s->mmio[0x0a] = 0x00;
2545 s->mmio[0x0b] = 0x00;
2546
2547 s->irq = s->dev.irq[3];
2548
2549 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2550 for(i = 0; i < NB_PORTS; i++) {
2551 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2552 USB_SPEED_MASK_HIGH);
2553 s->ports[i].dev = 0;
2554 }
2555
2556 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2557 s->async_bh = qemu_bh_new(ehci_async_bh, s);
2558 QTAILQ_INIT(&s->aqueues);
2559 QTAILQ_INIT(&s->pqueues);
2560
2561 qemu_register_reset(ehci_reset, s);
2562
2563 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2564 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2565
2566 return 0;
2567 }
2568
2569 static void ehci_register_types(void)
2570 {
2571 type_register_static(&ehci_info);
2572 type_register_static(&ich9_ehci_info);
2573 }
2574
2575 type_init(ehci_register_types)
2576
2577 /*
2578 * vim: expandtab ts=4
2579 */
Qemu copy for testing