2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
16 * This library is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU Lesser General Public
18 * License as published by the Free Software Foundation; either
19 * version 2 of the License, or(at your option) any later version.
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * Lesser General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
31 #include "qemu-timer.h"
41 #define DPRINTF printf
46 /* internal processing - reset HC to try and recover */
47 #define USB_RET_PROCERR (-99)
49 #define MMIO_SIZE 0x1000
51 /* Capability Registers Base Address - section 2.2 */
52 #define CAPREGBASE 0x0000
53 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
54 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
55 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
56 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
57 #define EECP HCCPARAMS + 1
58 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
59 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
61 #define OPREGBASE 0x0020 // Operational Registers Base Address
63 #define USBCMD OPREGBASE + 0x0000
64 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
65 #define USBCMD_HCRESET (1 << 1) // HC Reset
66 #define USBCMD_FLS (3 << 2) // Frame List Size
67 #define USBCMD_FLS_SH 2 // Frame List Size Shift
68 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
69 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
70 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
71 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
72 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
73 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
74 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
75 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
77 #define USBSTS OPREGBASE + 0x0004
78 #define USBSTS_RO_MASK 0x0000003f
79 #define USBSTS_INT (1 << 0) // USB Interrupt
80 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
81 #define USBSTS_PCD (1 << 2) // Port Change Detect
82 #define USBSTS_FLR (1 << 3) // Frame List Rollover
83 #define USBSTS_HSE (1 << 4) // Host System Error
84 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
85 #define USBSTS_HALT (1 << 12) // HC Halted
86 #define USBSTS_REC (1 << 13) // Reclamation
87 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
88 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
91 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
92 * so no need to redefine here.
94 #define USBINTR OPREGBASE + 0x0008
95 #define USBINTR_MASK 0x0000003f
97 #define FRINDEX OPREGBASE + 0x000c
98 #define CTRLDSSEGMENT OPREGBASE + 0x0010
99 #define PERIODICLISTBASE OPREGBASE + 0x0014
100 #define ASYNCLISTADDR OPREGBASE + 0x0018
101 #define ASYNCLISTADDR_MASK 0xffffffe0
103 #define CONFIGFLAG OPREGBASE + 0x0040
105 #define PORTSC (OPREGBASE + 0x0044)
106 #define PORTSC_BEGIN PORTSC
107 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
109 * Bits that are reserved or are read-only are masked out of values
110 * written to us by software
112 #define PORTSC_RO_MASK 0x007001c0
113 #define PORTSC_RWC_MASK 0x0000002a
114 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
115 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
116 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
117 #define PORTSC_PTC (15 << 16) // Port Test Control
118 #define PORTSC_PTC_SH 16 // Port Test Control shift
119 #define PORTSC_PIC (3 << 14) // Port Indicator Control
120 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
121 #define PORTSC_POWNER (1 << 13) // Port Owner
122 #define PORTSC_PPOWER (1 << 12) // Port Power
123 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
124 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
125 #define PORTSC_PRESET (1 << 8) // Port Reset
126 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
127 #define PORTSC_FPRES (1 << 6) // Force Port Resume
128 #define PORTSC_OCC (1 << 5) // Over Current Change
129 #define PORTSC_OCA (1 << 4) // Over Current Active
130 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
131 #define PORTSC_PED (1 << 2) // Port Enable/Disable
132 #define PORTSC_CSC (1 << 1) // Connect Status Change
133 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
135 #define FRAME_TIMER_FREQ 1000
136 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
138 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
139 #define NB_PORTS 6 // Number of downstream ports
140 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
141 #define MAX_QH 100 // Max allowable queue heads in a chain
142 #define MIN_FR_PER_TICK 3 // Min frames to process when catching up
144 /* Internal periodic / asynchronous schedule state machine states
151 /* The following states are internal to the state machine function
165 /* macros for accessing fields within next link pointer entry */
166 #define NLPTR_GET(x) ((x) & 0xffffffe0)
167 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
168 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
170 /* link pointer types */
171 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
172 #define NLPTR_TYPE_QH 1 // queue head
173 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
174 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
177 /* EHCI spec version 1.0 Section 3.3
179 typedef struct EHCIitd
{
182 uint32_t transact
[8];
183 #define ITD_XACT_ACTIVE (1 << 31)
184 #define ITD_XACT_DBERROR (1 << 30)
185 #define ITD_XACT_BABBLE (1 << 29)
186 #define ITD_XACT_XACTERR (1 << 28)
187 #define ITD_XACT_LENGTH_MASK 0x0fff0000
188 #define ITD_XACT_LENGTH_SH 16
189 #define ITD_XACT_IOC (1 << 15)
190 #define ITD_XACT_PGSEL_MASK 0x00007000
191 #define ITD_XACT_PGSEL_SH 12
192 #define ITD_XACT_OFFSET_MASK 0x00000fff
195 #define ITD_BUFPTR_MASK 0xfffff000
196 #define ITD_BUFPTR_SH 12
197 #define ITD_BUFPTR_EP_MASK 0x00000f00
198 #define ITD_BUFPTR_EP_SH 8
199 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
200 #define ITD_BUFPTR_DEVADDR_SH 0
201 #define ITD_BUFPTR_DIRECTION (1 << 11)
202 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
203 #define ITD_BUFPTR_MAXPKT_SH 0
204 #define ITD_BUFPTR_MULT_MASK 0x00000003
205 #define ITD_BUFPTR_MULT_SH 0
208 /* EHCI spec version 1.0 Section 3.4
210 typedef struct EHCIsitd
{
211 uint32_t next
; // Standard next link pointer
213 #define SITD_EPCHAR_IO (1 << 31)
214 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
215 #define SITD_EPCHAR_PORTNUM_SH 24
216 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
217 #define SITD_EPCHAR_HUBADDR_SH 16
218 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
219 #define SITD_EPCHAR_EPNUM_SH 8
220 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
223 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
224 #define SITD_UFRAME_CMASK_SH 8
225 #define SITD_UFRAME_SMASK_MASK 0x000000ff
228 #define SITD_RESULTS_IOC (1 << 31)
229 #define SITD_RESULTS_PGSEL (1 << 30)
230 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
231 #define SITD_RESULTS_TYBYTES_SH 16
232 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
233 #define SITD_RESULTS_CPROGMASK_SH 8
234 #define SITD_RESULTS_ACTIVE (1 << 7)
235 #define SITD_RESULTS_ERR (1 << 6)
236 #define SITD_RESULTS_DBERR (1 << 5)
237 #define SITD_RESULTS_BABBLE (1 << 4)
238 #define SITD_RESULTS_XACTERR (1 << 3)
239 #define SITD_RESULTS_MISSEDUF (1 << 2)
240 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
243 #define SITD_BUFPTR_MASK 0xfffff000
244 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
245 #define SITD_BUFPTR_TPOS_MASK 0x00000018
246 #define SITD_BUFPTR_TPOS_SH 3
247 #define SITD_BUFPTR_TCNT_MASK 0x00000007
249 uint32_t backptr
; // Standard next link pointer
252 /* EHCI spec version 1.0 Section 3.5
254 typedef struct EHCIqtd
{
255 uint32_t next
; // Standard next link pointer
256 uint32_t altnext
; // Standard next link pointer
258 #define QTD_TOKEN_DTOGGLE (1 << 31)
259 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
260 #define QTD_TOKEN_TBYTES_SH 16
261 #define QTD_TOKEN_IOC (1 << 15)
262 #define QTD_TOKEN_CPAGE_MASK 0x00007000
263 #define QTD_TOKEN_CPAGE_SH 12
264 #define QTD_TOKEN_CERR_MASK 0x00000c00
265 #define QTD_TOKEN_CERR_SH 10
266 #define QTD_TOKEN_PID_MASK 0x00000300
267 #define QTD_TOKEN_PID_SH 8
268 #define QTD_TOKEN_ACTIVE (1 << 7)
269 #define QTD_TOKEN_HALT (1 << 6)
270 #define QTD_TOKEN_DBERR (1 << 5)
271 #define QTD_TOKEN_BABBLE (1 << 4)
272 #define QTD_TOKEN_XACTERR (1 << 3)
273 #define QTD_TOKEN_MISSEDUF (1 << 2)
274 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
275 #define QTD_TOKEN_PING (1 << 0)
277 uint32_t bufptr
[5]; // Standard buffer pointer
278 #define QTD_BUFPTR_MASK 0xfffff000
279 #define QTD_BUFPTR_SH 12
282 /* EHCI spec version 1.0 Section 3.6
284 typedef struct EHCIqh
{
285 uint32_t next
; // Standard next link pointer
287 /* endpoint characteristics */
289 #define QH_EPCHAR_RL_MASK 0xf0000000
290 #define QH_EPCHAR_RL_SH 28
291 #define QH_EPCHAR_C (1 << 27)
292 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
293 #define QH_EPCHAR_MPLEN_SH 16
294 #define QH_EPCHAR_H (1 << 15)
295 #define QH_EPCHAR_DTC (1 << 14)
296 #define QH_EPCHAR_EPS_MASK 0x00003000
297 #define QH_EPCHAR_EPS_SH 12
298 #define EHCI_QH_EPS_FULL 0
299 #define EHCI_QH_EPS_LOW 1
300 #define EHCI_QH_EPS_HIGH 2
301 #define EHCI_QH_EPS_RESERVED 3
303 #define QH_EPCHAR_EP_MASK 0x00000f00
304 #define QH_EPCHAR_EP_SH 8
305 #define QH_EPCHAR_I (1 << 7)
306 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
307 #define QH_EPCHAR_DEVADDR_SH 0
309 /* endpoint capabilities */
311 #define QH_EPCAP_MULT_MASK 0xc0000000
312 #define QH_EPCAP_MULT_SH 30
313 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
314 #define QH_EPCAP_PORTNUM_SH 23
315 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
316 #define QH_EPCAP_HUBADDR_SH 16
317 #define QH_EPCAP_CMASK_MASK 0x0000ff00
318 #define QH_EPCAP_CMASK_SH 8
319 #define QH_EPCAP_SMASK_MASK 0x000000ff
320 #define QH_EPCAP_SMASK_SH 0
322 uint32_t current_qtd
; // Standard next link pointer
323 uint32_t next_qtd
; // Standard next link pointer
324 uint32_t altnext_qtd
;
325 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
326 #define QH_ALTNEXT_NAKCNT_SH 1
328 uint32_t token
; // Same as QTD token
329 uint32_t bufptr
[5]; // Standard buffer pointer
330 #define BUFPTR_CPROGMASK_MASK 0x000000ff
331 #define BUFPTR_FRAMETAG_MASK 0x0000001f
332 #define BUFPTR_SBYTES_MASK 0x00000fe0
333 #define BUFPTR_SBYTES_SH 5
336 /* EHCI spec version 1.0 Section 3.7
338 typedef struct EHCIfstn
{
339 uint32_t next
; // Standard next link pointer
340 uint32_t backptr
; // Standard next link pointer
343 typedef struct EHCIPacket EHCIPacket
;
344 typedef struct EHCIQueue EHCIQueue
;
345 typedef struct EHCIState EHCIState
;
349 EHCI_ASYNC_INITIALIZED
,
356 QTAILQ_ENTRY(EHCIPacket
) next
;
358 EHCIqtd qtd
; /* copy of current QTD (being worked on) */
359 uint32_t qtdaddr
; /* address QTD read from */
365 enum async_state async
;
371 QTAILQ_ENTRY(EHCIQueue
) next
;
376 /* cached data from guest - needs to be flushed
377 * when guest removes an entry (doorbell, handshake sequence)
379 EHCIqh qh
; /* copy of current QH (being worked on) */
380 uint32_t qhaddr
; /* address QH read from */
381 uint32_t qtdaddr
; /* address QTD read from */
383 QTAILQ_HEAD(, EHCIPacket
) packets
;
386 typedef QTAILQ_HEAD(EHCIQueueHead
, EHCIQueue
) EHCIQueueHead
;
393 MemoryRegion mem_caps
;
394 MemoryRegion mem_opreg
;
395 MemoryRegion mem_ports
;
402 * EHCI spec version 1.0 Section 2.3
403 * Host Controller Operational Registers
405 uint8_t caps
[OPREGBASE
];
407 uint32_t opreg
[(PORTSC_BEGIN
-OPREGBASE
)/sizeof(uint32_t)];
413 uint32_t ctrldssegment
;
414 uint32_t periodiclistbase
;
415 uint32_t asynclistaddr
;
420 uint32_t portsc
[NB_PORTS
];
423 * Internal states, shadow registers, etc
425 QEMUTimer
*frame_timer
;
427 uint32_t astate
; /* Current state in asynchronous schedule */
428 uint32_t pstate
; /* Current state in periodic schedule */
429 USBPort ports
[NB_PORTS
];
430 USBPort
*companion_ports
[NB_PORTS
];
431 uint32_t usbsts_pending
;
432 uint32_t usbsts_frindex
;
433 EHCIQueueHead aqueues
;
434 EHCIQueueHead pqueues
;
436 /* which address to look at next */
437 uint32_t a_fetch_addr
;
438 uint32_t p_fetch_addr
;
443 uint64_t last_run_ns
;
444 uint32_t async_stepdown
;
447 #define SET_LAST_RUN_CLOCK(s) \
448 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
450 /* nifty macros from Arnon's EHCI version */
451 #define get_field(data, field) \
452 (((data) & field##_MASK) >> field##_SH)
454 #define set_field(data, newval, field) do { \
455 uint32_t val = *data; \
456 val &= ~ field##_MASK; \
457 val |= ((newval) << field##_SH) & field##_MASK; \
461 static const char *ehci_state_names
[] = {
462 [EST_INACTIVE
] = "INACTIVE",
463 [EST_ACTIVE
] = "ACTIVE",
464 [EST_EXECUTING
] = "EXECUTING",
465 [EST_SLEEPING
] = "SLEEPING",
466 [EST_WAITLISTHEAD
] = "WAITLISTHEAD",
467 [EST_FETCHENTRY
] = "FETCH ENTRY",
468 [EST_FETCHQH
] = "FETCH QH",
469 [EST_FETCHITD
] = "FETCH ITD",
470 [EST_ADVANCEQUEUE
] = "ADVANCEQUEUE",
471 [EST_FETCHQTD
] = "FETCH QTD",
472 [EST_EXECUTE
] = "EXECUTE",
473 [EST_WRITEBACK
] = "WRITEBACK",
474 [EST_HORIZONTALQH
] = "HORIZONTALQH",
477 static const char *ehci_mmio_names
[] = {
480 [USBINTR
] = "USBINTR",
481 [FRINDEX
] = "FRINDEX",
482 [PERIODICLISTBASE
] = "P-LIST BASE",
483 [ASYNCLISTADDR
] = "A-LIST ADDR",
484 [CONFIGFLAG
] = "CONFIGFLAG",
487 static int ehci_state_executing(EHCIQueue
*q
);
488 static int ehci_state_writeback(EHCIQueue
*q
);
490 static const char *nr2str(const char **n
, size_t len
, uint32_t nr
)
492 if (nr
< len
&& n
[nr
] != NULL
) {
499 static const char *state2str(uint32_t state
)
501 return nr2str(ehci_state_names
, ARRAY_SIZE(ehci_state_names
), state
);
504 static const char *addr2str(target_phys_addr_t addr
)
506 return nr2str(ehci_mmio_names
, ARRAY_SIZE(ehci_mmio_names
),
510 static void ehci_trace_usbsts(uint32_t mask
, int state
)
513 if (mask
& USBSTS_INT
) {
514 trace_usb_ehci_usbsts("INT", state
);
516 if (mask
& USBSTS_ERRINT
) {
517 trace_usb_ehci_usbsts("ERRINT", state
);
519 if (mask
& USBSTS_PCD
) {
520 trace_usb_ehci_usbsts("PCD", state
);
522 if (mask
& USBSTS_FLR
) {
523 trace_usb_ehci_usbsts("FLR", state
);
525 if (mask
& USBSTS_HSE
) {
526 trace_usb_ehci_usbsts("HSE", state
);
528 if (mask
& USBSTS_IAA
) {
529 trace_usb_ehci_usbsts("IAA", state
);
533 if (mask
& USBSTS_HALT
) {
534 trace_usb_ehci_usbsts("HALT", state
);
536 if (mask
& USBSTS_REC
) {
537 trace_usb_ehci_usbsts("REC", state
);
539 if (mask
& USBSTS_PSS
) {
540 trace_usb_ehci_usbsts("PSS", state
);
542 if (mask
& USBSTS_ASS
) {
543 trace_usb_ehci_usbsts("ASS", state
);
547 static inline void ehci_set_usbsts(EHCIState
*s
, int mask
)
549 if ((s
->usbsts
& mask
) == mask
) {
552 ehci_trace_usbsts(mask
, 1);
556 static inline void ehci_clear_usbsts(EHCIState
*s
, int mask
)
558 if ((s
->usbsts
& mask
) == 0) {
561 ehci_trace_usbsts(mask
, 0);
565 /* update irq line */
566 static inline void ehci_update_irq(EHCIState
*s
)
570 if ((s
->usbsts
& USBINTR_MASK
) & s
->usbintr
) {
574 trace_usb_ehci_irq(level
, s
->frindex
, s
->usbsts
, s
->usbintr
);
575 qemu_set_irq(s
->irq
, level
);
578 /* flag interrupt condition */
579 static inline void ehci_raise_irq(EHCIState
*s
, int intr
)
581 if (intr
& (USBSTS_PCD
| USBSTS_FLR
| USBSTS_HSE
)) {
585 s
->usbsts_pending
|= intr
;
590 * Commit pending interrupts (added via ehci_raise_irq),
591 * at the rate allowed by "Interrupt Threshold Control".
593 static inline void ehci_commit_irq(EHCIState
*s
)
597 if (!s
->usbsts_pending
) {
600 if (s
->usbsts_frindex
> s
->frindex
) {
604 itc
= (s
->usbcmd
>> 16) & 0xff;
605 s
->usbsts
|= s
->usbsts_pending
;
606 s
->usbsts_pending
= 0;
607 s
->usbsts_frindex
= s
->frindex
+ itc
;
611 static void ehci_update_halt(EHCIState
*s
)
613 if (s
->usbcmd
& USBCMD_RUNSTOP
) {
614 ehci_clear_usbsts(s
, USBSTS_HALT
);
616 if (s
->astate
== EST_INACTIVE
&& s
->pstate
== EST_INACTIVE
) {
617 ehci_set_usbsts(s
, USBSTS_HALT
);
622 static void ehci_set_state(EHCIState
*s
, int async
, int state
)
625 trace_usb_ehci_state("async", state2str(state
));
627 if (s
->astate
== EST_INACTIVE
) {
628 ehci_clear_usbsts(s
, USBSTS_ASS
);
631 ehci_set_usbsts(s
, USBSTS_ASS
);
634 trace_usb_ehci_state("periodic", state2str(state
));
636 if (s
->pstate
== EST_INACTIVE
) {
637 ehci_clear_usbsts(s
, USBSTS_PSS
);
640 ehci_set_usbsts(s
, USBSTS_PSS
);
645 static int ehci_get_state(EHCIState
*s
, int async
)
647 return async
? s
->astate
: s
->pstate
;
650 static void ehci_set_fetch_addr(EHCIState
*s
, int async
, uint32_t addr
)
653 s
->a_fetch_addr
= addr
;
655 s
->p_fetch_addr
= addr
;
659 static int ehci_get_fetch_addr(EHCIState
*s
, int async
)
661 return async
? s
->a_fetch_addr
: s
->p_fetch_addr
;
664 static void ehci_trace_qh(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqh
*qh
)
666 /* need three here due to argument count limits */
667 trace_usb_ehci_qh_ptrs(q
, addr
, qh
->next
,
668 qh
->current_qtd
, qh
->next_qtd
, qh
->altnext_qtd
);
669 trace_usb_ehci_qh_fields(addr
,
670 get_field(qh
->epchar
, QH_EPCHAR_RL
),
671 get_field(qh
->epchar
, QH_EPCHAR_MPLEN
),
672 get_field(qh
->epchar
, QH_EPCHAR_EPS
),
673 get_field(qh
->epchar
, QH_EPCHAR_EP
),
674 get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
));
675 trace_usb_ehci_qh_bits(addr
,
676 (bool)(qh
->epchar
& QH_EPCHAR_C
),
677 (bool)(qh
->epchar
& QH_EPCHAR_H
),
678 (bool)(qh
->epchar
& QH_EPCHAR_DTC
),
679 (bool)(qh
->epchar
& QH_EPCHAR_I
));
682 static void ehci_trace_qtd(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqtd
*qtd
)
684 /* need three here due to argument count limits */
685 trace_usb_ehci_qtd_ptrs(q
, addr
, qtd
->next
, qtd
->altnext
);
686 trace_usb_ehci_qtd_fields(addr
,
687 get_field(qtd
->token
, QTD_TOKEN_TBYTES
),
688 get_field(qtd
->token
, QTD_TOKEN_CPAGE
),
689 get_field(qtd
->token
, QTD_TOKEN_CERR
),
690 get_field(qtd
->token
, QTD_TOKEN_PID
));
691 trace_usb_ehci_qtd_bits(addr
,
692 (bool)(qtd
->token
& QTD_TOKEN_IOC
),
693 (bool)(qtd
->token
& QTD_TOKEN_ACTIVE
),
694 (bool)(qtd
->token
& QTD_TOKEN_HALT
),
695 (bool)(qtd
->token
& QTD_TOKEN_BABBLE
),
696 (bool)(qtd
->token
& QTD_TOKEN_XACTERR
));
699 static void ehci_trace_itd(EHCIState
*s
, target_phys_addr_t addr
, EHCIitd
*itd
)
701 trace_usb_ehci_itd(addr
, itd
->next
,
702 get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
),
703 get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
),
704 get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
),
705 get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
));
708 static void ehci_trace_sitd(EHCIState
*s
, target_phys_addr_t addr
,
711 trace_usb_ehci_sitd(addr
, sitd
->next
,
712 (bool)(sitd
->results
& SITD_RESULTS_ACTIVE
));
715 static void ehci_trace_guest_bug(EHCIState
*s
, const char *message
)
717 trace_usb_ehci_guest_bug(message
);
718 fprintf(stderr
, "ehci warning: %s\n", message
);
721 static inline bool ehci_enabled(EHCIState
*s
)
723 return s
->usbcmd
& USBCMD_RUNSTOP
;
726 static inline bool ehci_async_enabled(EHCIState
*s
)
728 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_ASE
);
731 static inline bool ehci_periodic_enabled(EHCIState
*s
)
733 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_PSE
);
736 /* packet management */
738 static EHCIPacket
*ehci_alloc_packet(EHCIQueue
*q
)
742 p
= g_new0(EHCIPacket
, 1);
744 usb_packet_init(&p
->packet
);
745 QTAILQ_INSERT_TAIL(&q
->packets
, p
, next
);
746 trace_usb_ehci_packet_action(p
->queue
, p
, "alloc");
750 static void ehci_free_packet(EHCIPacket
*p
)
752 if (p
->async
== EHCI_ASYNC_FINISHED
) {
753 int state
= ehci_get_state(p
->queue
->ehci
, p
->queue
->async
);
754 /* This is a normal, but rare condition (cancel racing completion) */
755 fprintf(stderr
, "EHCI: Warning packet completed but not processed\n");
756 ehci_state_executing(p
->queue
);
757 ehci_state_writeback(p
->queue
);
758 ehci_set_state(p
->queue
->ehci
, p
->queue
->async
, state
);
759 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
762 trace_usb_ehci_packet_action(p
->queue
, p
, "free");
763 if (p
->async
== EHCI_ASYNC_INITIALIZED
) {
764 usb_packet_unmap(&p
->packet
, &p
->sgl
);
765 qemu_sglist_destroy(&p
->sgl
);
767 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
768 usb_cancel_packet(&p
->packet
);
769 usb_packet_unmap(&p
->packet
, &p
->sgl
);
770 qemu_sglist_destroy(&p
->sgl
);
772 QTAILQ_REMOVE(&p
->queue
->packets
, p
, next
);
773 usb_packet_cleanup(&p
->packet
);
777 /* queue management */
779 static EHCIQueue
*ehci_alloc_queue(EHCIState
*ehci
, uint32_t addr
, int async
)
781 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
784 q
= g_malloc0(sizeof(*q
));
788 QTAILQ_INIT(&q
->packets
);
789 QTAILQ_INSERT_HEAD(head
, q
, next
);
790 trace_usb_ehci_queue_action(q
, "alloc");
794 static int ehci_cancel_queue(EHCIQueue
*q
)
799 p
= QTAILQ_FIRST(&q
->packets
);
804 trace_usb_ehci_queue_action(q
, "cancel");
808 } while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
);
812 static int ehci_reset_queue(EHCIQueue
*q
)
816 trace_usb_ehci_queue_action(q
, "reset");
817 packets
= ehci_cancel_queue(q
);
823 static void ehci_free_queue(EHCIQueue
*q
, const char *warn
)
825 EHCIQueueHead
*head
= q
->async
? &q
->ehci
->aqueues
: &q
->ehci
->pqueues
;
828 trace_usb_ehci_queue_action(q
, "free");
829 cancelled
= ehci_cancel_queue(q
);
830 if (warn
&& cancelled
> 0) {
831 ehci_trace_guest_bug(q
->ehci
, warn
);
833 QTAILQ_REMOVE(head
, q
, next
);
837 static EHCIQueue
*ehci_find_queue_by_qh(EHCIState
*ehci
, uint32_t addr
,
840 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
843 QTAILQ_FOREACH(q
, head
, next
) {
844 if (addr
== q
->qhaddr
) {
851 static void ehci_queues_rip_unused(EHCIState
*ehci
, int async
, int flush
)
853 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
854 const char *warn
= (async
&& !flush
) ? "guest unlinked busy QH" : NULL
;
855 uint64_t maxage
= FRAME_TIMER_NS
* ehci
->maxframes
* 4;
858 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
861 q
->ts
= ehci
->last_run_ns
;
864 if (!flush
&& ehci
->last_run_ns
< q
->ts
+ maxage
) {
867 ehci_free_queue(q
, warn
);
871 static void ehci_queues_rip_device(EHCIState
*ehci
, USBDevice
*dev
, int async
)
873 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
876 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
880 ehci_free_queue(q
, NULL
);
884 static void ehci_queues_rip_all(EHCIState
*ehci
, int async
)
886 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
887 const char *warn
= async
? "guest stopped busy async schedule" : NULL
;
890 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
891 ehci_free_queue(q
, warn
);
895 /* Attach or detach a device on root hub */
897 static void ehci_attach(USBPort
*port
)
899 EHCIState
*s
= port
->opaque
;
900 uint32_t *portsc
= &s
->portsc
[port
->index
];
901 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
903 trace_usb_ehci_port_attach(port
->index
, owner
, port
->dev
->product_desc
);
905 if (*portsc
& PORTSC_POWNER
) {
906 USBPort
*companion
= s
->companion_ports
[port
->index
];
907 companion
->dev
= port
->dev
;
908 companion
->ops
->attach(companion
);
912 *portsc
|= PORTSC_CONNECT
;
913 *portsc
|= PORTSC_CSC
;
915 ehci_raise_irq(s
, USBSTS_PCD
);
919 static void ehci_detach(USBPort
*port
)
921 EHCIState
*s
= port
->opaque
;
922 uint32_t *portsc
= &s
->portsc
[port
->index
];
923 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
925 trace_usb_ehci_port_detach(port
->index
, owner
);
927 if (*portsc
& PORTSC_POWNER
) {
928 USBPort
*companion
= s
->companion_ports
[port
->index
];
929 companion
->ops
->detach(companion
);
930 companion
->dev
= NULL
;
932 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
933 * the port ownership is returned immediately to the EHCI controller."
935 *portsc
&= ~PORTSC_POWNER
;
939 ehci_queues_rip_device(s
, port
->dev
, 0);
940 ehci_queues_rip_device(s
, port
->dev
, 1);
942 *portsc
&= ~(PORTSC_CONNECT
|PORTSC_PED
);
943 *portsc
|= PORTSC_CSC
;
945 ehci_raise_irq(s
, USBSTS_PCD
);
949 static void ehci_child_detach(USBPort
*port
, USBDevice
*child
)
951 EHCIState
*s
= port
->opaque
;
952 uint32_t portsc
= s
->portsc
[port
->index
];
954 if (portsc
& PORTSC_POWNER
) {
955 USBPort
*companion
= s
->companion_ports
[port
->index
];
956 companion
->ops
->child_detach(companion
, child
);
960 ehci_queues_rip_device(s
, child
, 0);
961 ehci_queues_rip_device(s
, child
, 1);
964 static void ehci_wakeup(USBPort
*port
)
966 EHCIState
*s
= port
->opaque
;
967 uint32_t portsc
= s
->portsc
[port
->index
];
969 if (portsc
& PORTSC_POWNER
) {
970 USBPort
*companion
= s
->companion_ports
[port
->index
];
971 if (companion
->ops
->wakeup
) {
972 companion
->ops
->wakeup(companion
);
977 qemu_bh_schedule(s
->async_bh
);
980 static int ehci_register_companion(USBBus
*bus
, USBPort
*ports
[],
981 uint32_t portcount
, uint32_t firstport
)
983 EHCIState
*s
= container_of(bus
, EHCIState
, bus
);
986 if (firstport
+ portcount
> NB_PORTS
) {
987 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "firstport",
988 "firstport on masterbus");
989 error_printf_unless_qmp(
990 "firstport value of %u makes companion take ports %u - %u, which "
991 "is outside of the valid range of 0 - %u\n", firstport
, firstport
,
992 firstport
+ portcount
- 1, NB_PORTS
- 1);
996 for (i
= 0; i
< portcount
; i
++) {
997 if (s
->companion_ports
[firstport
+ i
]) {
998 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "masterbus",
1000 error_printf_unless_qmp(
1001 "port %u on masterbus %s already has a companion assigned\n",
1002 firstport
+ i
, bus
->qbus
.name
);
1007 for (i
= 0; i
< portcount
; i
++) {
1008 s
->companion_ports
[firstport
+ i
] = ports
[i
];
1009 s
->ports
[firstport
+ i
].speedmask
|=
1010 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
;
1011 /* Ensure devs attached before the initial reset go to the companion */
1012 s
->portsc
[firstport
+ i
] = PORTSC_POWNER
;
1015 s
->companion_count
++;
1016 s
->caps
[0x05] = (s
->companion_count
<< 4) | portcount
;
1021 static USBDevice
*ehci_find_device(EHCIState
*ehci
, uint8_t addr
)
1027 for (i
= 0; i
< NB_PORTS
; i
++) {
1028 port
= &ehci
->ports
[i
];
1029 if (!(ehci
->portsc
[i
] & PORTSC_PED
)) {
1030 DPRINTF("Port %d not enabled\n", i
);
1033 dev
= usb_find_device(port
, addr
);
1041 /* 4.1 host controller initialization */
1042 static void ehci_reset(void *opaque
)
1044 EHCIState
*s
= opaque
;
1046 USBDevice
*devs
[NB_PORTS
];
1048 trace_usb_ehci_reset();
1051 * Do the detach before touching portsc, so that it correctly gets send to
1052 * us or to our companion based on PORTSC_POWNER before the reset.
1054 for(i
= 0; i
< NB_PORTS
; i
++) {
1055 devs
[i
] = s
->ports
[i
].dev
;
1056 if (devs
[i
] && devs
[i
]->attached
) {
1057 usb_detach(&s
->ports
[i
]);
1061 memset(&s
->opreg
, 0x00, sizeof(s
->opreg
));
1062 memset(&s
->portsc
, 0x00, sizeof(s
->portsc
));
1064 s
->usbcmd
= NB_MAXINTRATE
<< USBCMD_ITC_SH
;
1065 s
->usbsts
= USBSTS_HALT
;
1066 s
->usbsts_pending
= 0;
1067 s
->usbsts_frindex
= 0;
1069 s
->astate
= EST_INACTIVE
;
1070 s
->pstate
= EST_INACTIVE
;
1072 for(i
= 0; i
< NB_PORTS
; i
++) {
1073 if (s
->companion_ports
[i
]) {
1074 s
->portsc
[i
] = PORTSC_POWNER
| PORTSC_PPOWER
;
1076 s
->portsc
[i
] = PORTSC_PPOWER
;
1078 if (devs
[i
] && devs
[i
]->attached
) {
1079 usb_attach(&s
->ports
[i
]);
1080 usb_device_reset(devs
[i
]);
1083 ehci_queues_rip_all(s
, 0);
1084 ehci_queues_rip_all(s
, 1);
1085 qemu_del_timer(s
->frame_timer
);
1086 qemu_bh_cancel(s
->async_bh
);
1089 static uint64_t ehci_caps_read(void *ptr
, target_phys_addr_t addr
,
1093 return s
->caps
[addr
];
1096 static uint64_t ehci_opreg_read(void *ptr
, target_phys_addr_t addr
,
1102 val
= s
->opreg
[addr
>> 2];
1103 trace_usb_ehci_opreg_read(addr
+ OPREGBASE
, addr2str(addr
), val
);
1107 static uint64_t ehci_port_read(void *ptr
, target_phys_addr_t addr
,
1113 val
= s
->portsc
[addr
>> 2];
1114 trace_usb_ehci_portsc_read(addr
+ PORTSC_BEGIN
, addr
>> 2, val
);
1118 static void handle_port_owner_write(EHCIState
*s
, int port
, uint32_t owner
)
1120 USBDevice
*dev
= s
->ports
[port
].dev
;
1121 uint32_t *portsc
= &s
->portsc
[port
];
1124 if (s
->companion_ports
[port
] == NULL
)
1127 owner
= owner
& PORTSC_POWNER
;
1128 orig
= *portsc
& PORTSC_POWNER
;
1130 if (!(owner
^ orig
)) {
1134 if (dev
&& dev
->attached
) {
1135 usb_detach(&s
->ports
[port
]);
1138 *portsc
&= ~PORTSC_POWNER
;
1141 if (dev
&& dev
->attached
) {
1142 usb_attach(&s
->ports
[port
]);
1146 static void ehci_port_write(void *ptr
, target_phys_addr_t addr
,
1147 uint64_t val
, unsigned size
)
1150 int port
= addr
>> 2;
1151 uint32_t *portsc
= &s
->portsc
[port
];
1152 uint32_t old
= *portsc
;
1153 USBDevice
*dev
= s
->ports
[port
].dev
;
1155 trace_usb_ehci_portsc_write(addr
+ PORTSC_BEGIN
, addr
>> 2, val
);
1157 /* Clear rwc bits */
1158 *portsc
&= ~(val
& PORTSC_RWC_MASK
);
1159 /* The guest may clear, but not set the PED bit */
1160 *portsc
&= val
| ~PORTSC_PED
;
1161 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1162 handle_port_owner_write(s
, port
, val
);
1163 /* And finally apply RO_MASK */
1164 val
&= PORTSC_RO_MASK
;
1166 if ((val
& PORTSC_PRESET
) && !(*portsc
& PORTSC_PRESET
)) {
1167 trace_usb_ehci_port_reset(port
, 1);
1170 if (!(val
& PORTSC_PRESET
) &&(*portsc
& PORTSC_PRESET
)) {
1171 trace_usb_ehci_port_reset(port
, 0);
1172 if (dev
&& dev
->attached
) {
1173 usb_port_reset(&s
->ports
[port
]);
1174 *portsc
&= ~PORTSC_CSC
;
1178 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1179 * to SW that this port has a high speed device attached
1181 if (dev
&& dev
->attached
&& (dev
->speedmask
& USB_SPEED_MASK_HIGH
)) {
1186 *portsc
&= ~PORTSC_RO_MASK
;
1188 trace_usb_ehci_portsc_change(addr
+ PORTSC_BEGIN
, addr
>> 2, *portsc
, old
);
1191 static void ehci_opreg_write(void *ptr
, target_phys_addr_t addr
,
1192 uint64_t val
, unsigned size
)
1195 uint32_t *mmio
= s
->opreg
+ (addr
>> 2);
1196 uint32_t old
= *mmio
;
1199 trace_usb_ehci_opreg_write(addr
+ OPREGBASE
, addr2str(addr
), val
);
1201 switch (addr
+ OPREGBASE
) {
1203 if (val
& USBCMD_HCRESET
) {
1209 /* not supporting dynamic frame list size at the moment */
1210 if ((val
& USBCMD_FLS
) && !(s
->usbcmd
& USBCMD_FLS
)) {
1211 fprintf(stderr
, "attempt to set frame list size -- value %d\n",
1212 (int)val
& USBCMD_FLS
);
1216 if (val
& USBCMD_IAAD
) {
1218 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1219 * trigger and re-use a qh without us seeing the unlink.
1221 s
->async_stepdown
= 0;
1222 qemu_bh_schedule(s
->async_bh
);
1223 trace_usb_ehci_doorbell_ring();
1226 if (((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & val
) !=
1227 ((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & s
->usbcmd
)) {
1228 if (s
->pstate
== EST_INACTIVE
) {
1229 SET_LAST_RUN_CLOCK(s
);
1231 s
->usbcmd
= val
; /* Set usbcmd for ehci_update_halt() */
1232 ehci_update_halt(s
);
1233 s
->async_stepdown
= 0;
1234 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
1239 val
&= USBSTS_RO_MASK
; // bits 6 through 31 are RO
1240 ehci_clear_usbsts(s
, val
); // bits 0 through 5 are R/WC
1246 val
&= USBINTR_MASK
;
1250 val
&= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1256 for(i
= 0; i
< NB_PORTS
; i
++)
1257 handle_port_owner_write(s
, i
, 0);
1261 case PERIODICLISTBASE
:
1262 if (ehci_periodic_enabled(s
)) {
1264 "ehci: PERIODIC list base register set while periodic schedule\n"
1265 " is enabled and HC is enabled\n");
1270 if (ehci_async_enabled(s
)) {
1272 "ehci: ASYNC list address register set while async schedule\n"
1273 " is enabled and HC is enabled\n");
1279 trace_usb_ehci_opreg_change(addr
+ OPREGBASE
, addr2str(addr
), *mmio
, old
);
1283 // TODO : Put in common header file, duplication from usb-ohci.c
1285 /* Get an array of dwords from main memory */
1286 static inline int get_dwords(EHCIState
*ehci
, uint32_t addr
,
1287 uint32_t *buf
, int num
)
1291 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1292 pci_dma_read(&ehci
->dev
, addr
, buf
, sizeof(*buf
));
1293 *buf
= le32_to_cpu(*buf
);
1299 /* Put an array of dwords in to main memory */
1300 static inline int put_dwords(EHCIState
*ehci
, uint32_t addr
,
1301 uint32_t *buf
, int num
)
1305 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1306 uint32_t tmp
= cpu_to_le32(*buf
);
1307 pci_dma_write(&ehci
->dev
, addr
, &tmp
, sizeof(tmp
));
1314 * Write the qh back to guest physical memory. This step isn't
1315 * in the EHCI spec but we need to do it since we don't share
1316 * physical memory with our guest VM.
1318 * The first three dwords are read-only for the EHCI, so skip them
1319 * when writing back the qh.
1321 static void ehci_flush_qh(EHCIQueue
*q
)
1323 uint32_t *qh
= (uint32_t *) &q
->qh
;
1324 uint32_t dwords
= sizeof(EHCIqh
) >> 2;
1325 uint32_t addr
= NLPTR_GET(q
->qhaddr
);
1327 put_dwords(q
->ehci
, addr
+ 3 * sizeof(uint32_t), qh
+ 3, dwords
- 3);
1332 static int ehci_qh_do_overlay(EHCIQueue
*q
)
1334 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1342 assert(p
->qtdaddr
== q
->qtdaddr
);
1344 // remember values in fields to preserve in qh after overlay
1346 dtoggle
= q
->qh
.token
& QTD_TOKEN_DTOGGLE
;
1347 ping
= q
->qh
.token
& QTD_TOKEN_PING
;
1349 q
->qh
.current_qtd
= p
->qtdaddr
;
1350 q
->qh
.next_qtd
= p
->qtd
.next
;
1351 q
->qh
.altnext_qtd
= p
->qtd
.altnext
;
1352 q
->qh
.token
= p
->qtd
.token
;
1355 eps
= get_field(q
->qh
.epchar
, QH_EPCHAR_EPS
);
1356 if (eps
== EHCI_QH_EPS_HIGH
) {
1357 q
->qh
.token
&= ~QTD_TOKEN_PING
;
1358 q
->qh
.token
|= ping
;
1361 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1362 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1364 for (i
= 0; i
< 5; i
++) {
1365 q
->qh
.bufptr
[i
] = p
->qtd
.bufptr
[i
];
1368 if (!(q
->qh
.epchar
& QH_EPCHAR_DTC
)) {
1369 // preserve QH DT bit
1370 q
->qh
.token
&= ~QTD_TOKEN_DTOGGLE
;
1371 q
->qh
.token
|= dtoggle
;
1374 q
->qh
.bufptr
[1] &= ~BUFPTR_CPROGMASK_MASK
;
1375 q
->qh
.bufptr
[2] &= ~BUFPTR_FRAMETAG_MASK
;
1382 static int ehci_init_transfer(EHCIPacket
*p
)
1384 uint32_t cpage
, offset
, bytes
, plen
;
1387 cpage
= get_field(p
->qtd
.token
, QTD_TOKEN_CPAGE
);
1388 bytes
= get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
);
1389 offset
= p
->qtd
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1390 pci_dma_sglist_init(&p
->sgl
, &p
->queue
->ehci
->dev
, 5);
1394 fprintf(stderr
, "cpage out of range (%d)\n", cpage
);
1395 return USB_RET_PROCERR
;
1398 page
= p
->qtd
.bufptr
[cpage
] & QTD_BUFPTR_MASK
;
1401 if (plen
> 4096 - offset
) {
1402 plen
= 4096 - offset
;
1407 qemu_sglist_add(&p
->sgl
, page
, plen
);
1413 static void ehci_finish_transfer(EHCIQueue
*q
, int status
)
1415 uint32_t cpage
, offset
;
1418 /* update cpage & offset */
1419 cpage
= get_field(q
->qh
.token
, QTD_TOKEN_CPAGE
);
1420 offset
= q
->qh
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1423 cpage
+= offset
>> QTD_BUFPTR_SH
;
1424 offset
&= ~QTD_BUFPTR_MASK
;
1426 set_field(&q
->qh
.token
, cpage
, QTD_TOKEN_CPAGE
);
1427 q
->qh
.bufptr
[0] &= QTD_BUFPTR_MASK
;
1428 q
->qh
.bufptr
[0] |= offset
;
1432 static void ehci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
1435 EHCIState
*s
= port
->opaque
;
1436 uint32_t portsc
= s
->portsc
[port
->index
];
1438 if (portsc
& PORTSC_POWNER
) {
1439 USBPort
*companion
= s
->companion_ports
[port
->index
];
1440 companion
->ops
->complete(companion
, packet
);
1444 p
= container_of(packet
, EHCIPacket
, packet
);
1445 trace_usb_ehci_packet_action(p
->queue
, p
, "wakeup");
1446 assert(p
->async
== EHCI_ASYNC_INFLIGHT
);
1447 p
->async
= EHCI_ASYNC_FINISHED
;
1448 p
->usb_status
= packet
->result
;
1450 if (p
->queue
->async
) {
1451 qemu_bh_schedule(p
->queue
->ehci
->async_bh
);
1455 static void ehci_execute_complete(EHCIQueue
*q
)
1457 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1460 assert(p
->qtdaddr
== q
->qtdaddr
);
1461 assert(p
->async
== EHCI_ASYNC_INITIALIZED
||
1462 p
->async
== EHCI_ASYNC_FINISHED
);
1464 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1465 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->usb_status
);
1467 if (p
->usb_status
< 0) {
1468 switch (p
->usb_status
) {
1469 case USB_RET_IOERROR
:
1471 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_XACTERR
);
1472 set_field(&q
->qh
.token
, 0, QTD_TOKEN_CERR
);
1473 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1476 q
->qh
.token
|= QTD_TOKEN_HALT
;
1477 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1480 set_field(&q
->qh
.altnext_qtd
, 0, QH_ALTNEXT_NAKCNT
);
1481 return; /* We're not done yet with this transaction */
1482 case USB_RET_BABBLE
:
1483 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1484 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1487 /* should not be triggerable */
1488 fprintf(stderr
, "USB invalid response %d\n", p
->usb_status
);
1493 // TODO check 4.12 for splits
1495 if (p
->tbytes
&& p
->pid
== USB_TOKEN_IN
) {
1496 p
->tbytes
-= p
->usb_status
;
1501 DPRINTF("updating tbytes to %d\n", p
->tbytes
);
1502 set_field(&q
->qh
.token
, p
->tbytes
, QTD_TOKEN_TBYTES
);
1504 ehci_finish_transfer(q
, p
->usb_status
);
1505 usb_packet_unmap(&p
->packet
, &p
->sgl
);
1506 qemu_sglist_destroy(&p
->sgl
);
1507 p
->async
= EHCI_ASYNC_NONE
;
1509 q
->qh
.token
^= QTD_TOKEN_DTOGGLE
;
1510 q
->qh
.token
&= ~QTD_TOKEN_ACTIVE
;
1512 if (q
->qh
.token
& QTD_TOKEN_IOC
) {
1513 ehci_raise_irq(q
->ehci
, USBSTS_INT
);
1519 static int ehci_execute(EHCIPacket
*p
, const char *action
)
1525 assert(p
->async
== EHCI_ASYNC_NONE
||
1526 p
->async
== EHCI_ASYNC_INITIALIZED
);
1528 if (!(p
->qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1529 fprintf(stderr
, "Attempting to execute inactive qtd\n");
1530 return USB_RET_PROCERR
;
1533 p
->tbytes
= (p
->qtd
.token
& QTD_TOKEN_TBYTES_MASK
) >> QTD_TOKEN_TBYTES_SH
;
1534 if (p
->tbytes
> BUFF_SIZE
) {
1535 ehci_trace_guest_bug(p
->queue
->ehci
,
1536 "guest requested more bytes than allowed");
1537 return USB_RET_PROCERR
;
1540 p
->pid
= (p
->qtd
.token
& QTD_TOKEN_PID_MASK
) >> QTD_TOKEN_PID_SH
;
1543 p
->pid
= USB_TOKEN_OUT
;
1546 p
->pid
= USB_TOKEN_IN
;
1549 p
->pid
= USB_TOKEN_SETUP
;
1552 fprintf(stderr
, "bad token\n");
1556 endp
= get_field(p
->queue
->qh
.epchar
, QH_EPCHAR_EP
);
1557 ep
= usb_ep_get(p
->queue
->dev
, p
->pid
, endp
);
1559 if (p
->async
== EHCI_ASYNC_NONE
) {
1560 if (ehci_init_transfer(p
) != 0) {
1561 return USB_RET_PROCERR
;
1564 usb_packet_setup(&p
->packet
, p
->pid
, ep
, p
->qtdaddr
);
1565 usb_packet_map(&p
->packet
, &p
->sgl
);
1566 p
->async
= EHCI_ASYNC_INITIALIZED
;
1569 trace_usb_ehci_packet_action(p
->queue
, p
, action
);
1570 ret
= usb_handle_packet(p
->queue
->dev
, &p
->packet
);
1571 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1572 "(total %d) endp %x ret %d\n",
1573 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->pid
,
1574 q
->packet
.iov
.size
, q
->tbytes
, endp
, ret
);
1576 if (ret
> BUFF_SIZE
) {
1577 fprintf(stderr
, "ret from usb_handle_packet > BUFF_SIZE\n");
1578 return USB_RET_PROCERR
;
1587 static int ehci_process_itd(EHCIState
*ehci
,
1594 uint32_t i
, len
, pid
, dir
, devaddr
, endp
;
1595 uint32_t pg
, off
, ptr1
, ptr2
, max
, mult
;
1597 dir
=(itd
->bufptr
[1] & ITD_BUFPTR_DIRECTION
);
1598 devaddr
= get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
);
1599 endp
= get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
);
1600 max
= get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
);
1601 mult
= get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
);
1603 for(i
= 0; i
< 8; i
++) {
1604 if (itd
->transact
[i
] & ITD_XACT_ACTIVE
) {
1605 pg
= get_field(itd
->transact
[i
], ITD_XACT_PGSEL
);
1606 off
= itd
->transact
[i
] & ITD_XACT_OFFSET_MASK
;
1607 ptr1
= (itd
->bufptr
[pg
] & ITD_BUFPTR_MASK
);
1608 ptr2
= (itd
->bufptr
[pg
+1] & ITD_BUFPTR_MASK
);
1609 len
= get_field(itd
->transact
[i
], ITD_XACT_LENGTH
);
1611 if (len
> max
* mult
) {
1615 if (len
> BUFF_SIZE
) {
1616 return USB_RET_PROCERR
;
1619 pci_dma_sglist_init(&ehci
->isgl
, &ehci
->dev
, 2);
1620 if (off
+ len
> 4096) {
1621 /* transfer crosses page border */
1622 uint32_t len2
= off
+ len
- 4096;
1623 uint32_t len1
= len
- len2
;
1624 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len1
);
1625 qemu_sglist_add(&ehci
->isgl
, ptr2
, len2
);
1627 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len
);
1630 pid
= dir
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1632 dev
= ehci_find_device(ehci
, devaddr
);
1633 ep
= usb_ep_get(dev
, pid
, endp
);
1634 if (ep
&& ep
->type
== USB_ENDPOINT_XFER_ISOC
) {
1635 usb_packet_setup(&ehci
->ipacket
, pid
, ep
, addr
);
1636 usb_packet_map(&ehci
->ipacket
, &ehci
->isgl
);
1637 ret
= usb_handle_packet(dev
, &ehci
->ipacket
);
1638 assert(ret
!= USB_RET_ASYNC
);
1639 usb_packet_unmap(&ehci
->ipacket
, &ehci
->isgl
);
1641 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1644 qemu_sglist_destroy(&ehci
->isgl
);
1649 fprintf(stderr
, "Unexpected iso usb result: %d\n", ret
);
1651 case USB_RET_IOERROR
:
1653 /* 3.3.2: XACTERR is only allowed on IN transactions */
1655 itd
->transact
[i
] |= ITD_XACT_XACTERR
;
1656 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1659 case USB_RET_BABBLE
:
1660 itd
->transact
[i
] |= ITD_XACT_BABBLE
;
1661 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1664 /* no data for us, so do a zero-length transfer */
1672 set_field(&itd
->transact
[i
], len
- ret
, ITD_XACT_LENGTH
);
1675 set_field(&itd
->transact
[i
], ret
, ITD_XACT_LENGTH
);
1678 if (itd
->transact
[i
] & ITD_XACT_IOC
) {
1679 ehci_raise_irq(ehci
, USBSTS_INT
);
1681 itd
->transact
[i
] &= ~ITD_XACT_ACTIVE
;
1688 /* This state is the entry point for asynchronous schedule
1689 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1691 static int ehci_state_waitlisthead(EHCIState
*ehci
, int async
)
1696 uint32_t entry
= ehci
->asynclistaddr
;
1698 /* set reclamation flag at start event (4.8.6) */
1700 ehci_set_usbsts(ehci
, USBSTS_REC
);
1703 ehci_queues_rip_unused(ehci
, async
, 0);
1705 /* Find the head of the list (4.9.1.1) */
1706 for(i
= 0; i
< MAX_QH
; i
++) {
1707 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &qh
,
1708 sizeof(EHCIqh
) >> 2);
1709 ehci_trace_qh(NULL
, NLPTR_GET(entry
), &qh
);
1711 if (qh
.epchar
& QH_EPCHAR_H
) {
1713 entry
|= (NLPTR_TYPE_QH
<< 1);
1716 ehci_set_fetch_addr(ehci
, async
, entry
);
1717 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1723 if (entry
== ehci
->asynclistaddr
) {
1728 /* no head found for list. */
1730 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1737 /* This state is the entry point for periodic schedule processing as
1738 * well as being a continuation state for async processing.
1740 static int ehci_state_fetchentry(EHCIState
*ehci
, int async
)
1743 uint32_t entry
= ehci_get_fetch_addr(ehci
, async
);
1745 if (NLPTR_TBIT(entry
)) {
1746 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1750 /* section 4.8, only QH in async schedule */
1751 if (async
&& (NLPTR_TYPE_GET(entry
) != NLPTR_TYPE_QH
)) {
1752 fprintf(stderr
, "non queue head request in async schedule\n");
1756 switch (NLPTR_TYPE_GET(entry
)) {
1758 ehci_set_state(ehci
, async
, EST_FETCHQH
);
1762 case NLPTR_TYPE_ITD
:
1763 ehci_set_state(ehci
, async
, EST_FETCHITD
);
1767 case NLPTR_TYPE_STITD
:
1768 ehci_set_state(ehci
, async
, EST_FETCHSITD
);
1773 /* TODO: handle FSTN type */
1774 fprintf(stderr
, "FETCHENTRY: entry at %X is of type %d "
1775 "which is not supported yet\n", entry
, NLPTR_TYPE_GET(entry
));
1783 static EHCIQueue
*ehci_state_fetchqh(EHCIState
*ehci
, int async
)
1786 uint32_t entry
, devaddr
, endp
;
1790 entry
= ehci_get_fetch_addr(ehci
, async
);
1791 q
= ehci_find_queue_by_qh(ehci
, entry
, async
);
1793 q
= ehci_alloc_queue(ehci
, entry
, async
);
1795 p
= QTAILQ_FIRST(&q
->packets
);
1799 /* we are going in circles -- stop processing */
1800 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1805 get_dwords(ehci
, NLPTR_GET(q
->qhaddr
),
1806 (uint32_t *) &qh
, sizeof(EHCIqh
) >> 2);
1807 ehci_trace_qh(q
, NLPTR_GET(q
->qhaddr
), &qh
);
1810 * The overlay area of the qh should never be changed by the guest,
1811 * except when idle, in which case the reset is a nop.
1813 devaddr
= get_field(qh
.epchar
, QH_EPCHAR_DEVADDR
);
1814 endp
= get_field(qh
.epchar
, QH_EPCHAR_EP
);
1815 if ((devaddr
!= get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
)) ||
1816 (endp
!= get_field(q
->qh
.epchar
, QH_EPCHAR_EP
)) ||
1817 (memcmp(&qh
.current_qtd
, &q
->qh
.current_qtd
,
1818 9 * sizeof(uint32_t)) != 0) ||
1819 (q
->dev
!= NULL
&& q
->dev
->addr
!= devaddr
)) {
1820 if (ehci_reset_queue(q
) > 0) {
1821 ehci_trace_guest_bug(ehci
, "guest updated active QH");
1827 if (q
->dev
== NULL
) {
1828 q
->dev
= ehci_find_device(q
->ehci
, devaddr
);
1831 if (p
&& p
->async
== EHCI_ASYNC_FINISHED
) {
1832 /* I/O finished -- continue processing queue */
1833 trace_usb_ehci_packet_action(p
->queue
, p
, "complete");
1834 ehci_set_state(ehci
, async
, EST_EXECUTING
);
1838 if (async
&& (q
->qh
.epchar
& QH_EPCHAR_H
)) {
1840 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1841 if (ehci
->usbsts
& USBSTS_REC
) {
1842 ehci_clear_usbsts(ehci
, USBSTS_REC
);
1844 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1845 " - done processing\n", q
->qhaddr
);
1846 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1853 if (q
->qhaddr
!= q
->qh
.next
) {
1854 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1856 q
->qh
.epchar
& QH_EPCHAR_H
,
1857 q
->qh
.token
& QTD_TOKEN_HALT
,
1858 q
->qh
.token
& QTD_TOKEN_ACTIVE
,
1863 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1864 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1866 } else if ((q
->qh
.token
& QTD_TOKEN_ACTIVE
) &&
1867 (NLPTR_TBIT(q
->qh
.current_qtd
) == 0)) {
1868 q
->qtdaddr
= q
->qh
.current_qtd
;
1869 ehci_set_state(ehci
, async
, EST_FETCHQTD
);
1872 /* EHCI spec version 1.0 Section 4.10.2 */
1873 ehci_set_state(ehci
, async
, EST_ADVANCEQUEUE
);
1880 static int ehci_state_fetchitd(EHCIState
*ehci
, int async
)
1886 entry
= ehci_get_fetch_addr(ehci
, async
);
1888 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1889 sizeof(EHCIitd
) >> 2);
1890 ehci_trace_itd(ehci
, entry
, &itd
);
1892 if (ehci_process_itd(ehci
, &itd
, entry
) != 0) {
1896 put_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1897 sizeof(EHCIitd
) >> 2);
1898 ehci_set_fetch_addr(ehci
, async
, itd
.next
);
1899 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1904 static int ehci_state_fetchsitd(EHCIState
*ehci
, int async
)
1910 entry
= ehci_get_fetch_addr(ehci
, async
);
1912 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *)&sitd
,
1913 sizeof(EHCIsitd
) >> 2);
1914 ehci_trace_sitd(ehci
, entry
, &sitd
);
1916 if (!(sitd
.results
& SITD_RESULTS_ACTIVE
)) {
1917 /* siTD is not active, nothing to do */;
1919 /* TODO: split transfers are not implemented */
1920 fprintf(stderr
, "WARNING: Skipping active siTD\n");
1923 ehci_set_fetch_addr(ehci
, async
, sitd
.next
);
1924 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1928 /* Section 4.10.2 - paragraph 3 */
1929 static int ehci_state_advqueue(EHCIQueue
*q
)
1932 /* TO-DO: 4.10.2 - paragraph 2
1933 * if I-bit is set to 1 and QH is not active
1934 * go to horizontal QH
1937 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1943 * want data and alt-next qTD is valid
1945 if (((q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) != 0) &&
1946 (NLPTR_TBIT(q
->qh
.altnext_qtd
) == 0)) {
1947 q
->qtdaddr
= q
->qh
.altnext_qtd
;
1948 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1953 } else if (NLPTR_TBIT(q
->qh
.next_qtd
) == 0) {
1954 q
->qtdaddr
= q
->qh
.next_qtd
;
1955 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1958 * no valid qTD, try next QH
1961 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1967 /* Section 4.10.2 - paragraph 4 */
1968 static int ehci_state_fetchqtd(EHCIQueue
*q
)
1974 get_dwords(q
->ehci
, NLPTR_GET(q
->qtdaddr
), (uint32_t *) &qtd
,
1975 sizeof(EHCIqtd
) >> 2);
1976 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), &qtd
);
1978 p
= QTAILQ_FIRST(&q
->packets
);
1980 if (p
->qtdaddr
!= q
->qtdaddr
||
1981 (!NLPTR_TBIT(p
->qtd
.next
) && (p
->qtd
.next
!= qtd
.next
)) ||
1982 (!NLPTR_TBIT(p
->qtd
.altnext
) && (p
->qtd
.altnext
!= qtd
.altnext
)) ||
1983 p
->qtd
.bufptr
[0] != qtd
.bufptr
[0]) {
1984 ehci_cancel_queue(q
);
1985 ehci_trace_guest_bug(q
->ehci
, "guest updated active QH or qTD");
1989 ehci_qh_do_overlay(q
);
1993 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1995 /* transfer canceled by guest (clear active) */
1996 ehci_cancel_queue(q
);
1999 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2001 } else if (p
!= NULL
) {
2003 case EHCI_ASYNC_NONE
:
2004 /* Should never happen packet should at least be initialized */
2007 case EHCI_ASYNC_INITIALIZED
:
2008 /* Previously nacked packet (likely interrupt ep) */
2009 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
2011 case EHCI_ASYNC_INFLIGHT
:
2012 /* Unfinished async handled packet, go horizontal */
2013 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2015 case EHCI_ASYNC_FINISHED
:
2017 * We get here when advqueue moves to a packet which is already
2018 * finished, which can happen with packets queued up by fill_queue
2020 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2025 p
= ehci_alloc_packet(q
);
2026 p
->qtdaddr
= q
->qtdaddr
;
2028 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
2035 static int ehci_state_horizqh(EHCIQueue
*q
)
2039 if (ehci_get_fetch_addr(q
->ehci
, q
->async
) != q
->qh
.next
) {
2040 ehci_set_fetch_addr(q
->ehci
, q
->async
, q
->qh
.next
);
2041 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHENTRY
);
2044 ehci_set_state(q
->ehci
, q
->async
, EST_ACTIVE
);
2050 static int ehci_fill_queue(EHCIPacket
*p
)
2052 EHCIQueue
*q
= p
->queue
;
2053 EHCIqtd qtd
= p
->qtd
;
2057 if (NLPTR_TBIT(qtd
.altnext
) == 0) {
2060 if (NLPTR_TBIT(qtd
.next
) != 0) {
2064 get_dwords(q
->ehci
, NLPTR_GET(qtdaddr
),
2065 (uint32_t *) &qtd
, sizeof(EHCIqtd
) >> 2);
2066 ehci_trace_qtd(q
, NLPTR_GET(qtdaddr
), &qtd
);
2067 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
2070 p
= ehci_alloc_packet(q
);
2071 p
->qtdaddr
= qtdaddr
;
2073 p
->usb_status
= ehci_execute(p
, "queue");
2074 if (p
->usb_status
== USB_RET_PROCERR
) {
2077 assert(p
->usb_status
== USB_RET_ASYNC
);
2078 p
->async
= EHCI_ASYNC_INFLIGHT
;
2080 return p
->usb_status
;
2083 static int ehci_state_execute(EHCIQueue
*q
)
2085 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2089 assert(p
->qtdaddr
== q
->qtdaddr
);
2091 if (ehci_qh_do_overlay(q
) != 0) {
2095 // TODO verify enough time remains in the uframe as in 4.4.1.1
2096 // TODO write back ptr to async list when done or out of time
2097 // TODO Windows does not seem to ever set the MULT field
2100 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
2102 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2109 ehci_set_usbsts(q
->ehci
, USBSTS_REC
);
2112 p
->usb_status
= ehci_execute(p
, "process");
2113 if (p
->usb_status
== USB_RET_PROCERR
) {
2117 if (p
->usb_status
== USB_RET_ASYNC
) {
2119 trace_usb_ehci_packet_action(p
->queue
, p
, "async");
2120 p
->async
= EHCI_ASYNC_INFLIGHT
;
2121 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2122 again
= (ehci_fill_queue(p
) == USB_RET_PROCERR
) ? -1 : 1;
2126 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2133 static int ehci_state_executing(EHCIQueue
*q
)
2135 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2138 assert(p
->qtdaddr
== q
->qtdaddr
);
2140 ehci_execute_complete(q
);
2144 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
2146 set_field(&q
->qh
.epcap
, transactCtr
, QH_EPCAP_MULT
);
2147 // 4.10.3, bottom of page 82, should exit this state when transaction
2148 // counter decrements to 0
2152 if (p
->usb_status
== USB_RET_NAK
) {
2153 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2155 ehci_set_state(q
->ehci
, q
->async
, EST_WRITEBACK
);
2163 static int ehci_state_writeback(EHCIQueue
*q
)
2165 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2166 uint32_t *qtd
, addr
;
2169 /* Write back the QTD from the QH area */
2171 assert(p
->qtdaddr
== q
->qtdaddr
);
2173 ehci_trace_qtd(q
, NLPTR_GET(p
->qtdaddr
), (EHCIqtd
*) &q
->qh
.next_qtd
);
2174 qtd
= (uint32_t *) &q
->qh
.next_qtd
;
2175 addr
= NLPTR_GET(p
->qtdaddr
);
2176 put_dwords(q
->ehci
, addr
+ 2 * sizeof(uint32_t), qtd
+ 2, 2);
2177 ehci_free_packet(p
);
2180 * EHCI specs say go horizontal here.
2182 * We can also advance the queue here for performance reasons. We
2183 * need to take care to only take that shortcut in case we've
2184 * processed the qtd just written back without errors, i.e. halt
2187 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
2189 * We should not do any further processing on a halted queue!
2190 * This is esp. important for bulk endpoints with pipelining enabled
2191 * (redirection to a real USB device), where we must cancel all the
2192 * transfers after this one so that:
2193 * 1) If they've completed already, they are not processed further
2194 * causing more stalls, originating from the same failed transfer
2195 * 2) If still in flight, they are cancelled before the guest does
2196 * a clear stall, otherwise the guest and device can loose sync!
2198 while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
) {
2199 ehci_free_packet(p
);
2201 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2204 ehci_set_state(q
->ehci
, q
->async
, EST_ADVANCEQUEUE
);
2211 * This is the state machine that is common to both async and periodic
2214 static void ehci_advance_state(EHCIState
*ehci
, int async
)
2216 EHCIQueue
*q
= NULL
;
2220 switch(ehci_get_state(ehci
, async
)) {
2221 case EST_WAITLISTHEAD
:
2222 again
= ehci_state_waitlisthead(ehci
, async
);
2225 case EST_FETCHENTRY
:
2226 again
= ehci_state_fetchentry(ehci
, async
);
2230 q
= ehci_state_fetchqh(ehci
, async
);
2232 assert(q
->async
== async
);
2240 again
= ehci_state_fetchitd(ehci
, async
);
2244 again
= ehci_state_fetchsitd(ehci
, async
);
2247 case EST_ADVANCEQUEUE
:
2248 again
= ehci_state_advqueue(q
);
2252 again
= ehci_state_fetchqtd(q
);
2255 case EST_HORIZONTALQH
:
2256 again
= ehci_state_horizqh(q
);
2260 again
= ehci_state_execute(q
);
2262 ehci
->async_stepdown
= 0;
2269 ehci
->async_stepdown
= 0;
2271 again
= ehci_state_executing(q
);
2276 again
= ehci_state_writeback(q
);
2280 fprintf(stderr
, "Bad state!\n");
2287 fprintf(stderr
, "processing error - resetting ehci HC\n");
2295 static void ehci_advance_async_state(EHCIState
*ehci
)
2297 const int async
= 1;
2299 switch(ehci_get_state(ehci
, async
)) {
2301 if (!ehci_async_enabled(ehci
)) {
2304 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2305 // No break, fall through to ACTIVE
2308 if (!ehci_async_enabled(ehci
)) {
2309 ehci_queues_rip_all(ehci
, async
);
2310 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2314 /* make sure guest has acknowledged the doorbell interrupt */
2315 /* TO-DO: is this really needed? */
2316 if (ehci
->usbsts
& USBSTS_IAA
) {
2317 DPRINTF("IAA status bit still set.\n");
2321 /* check that address register has been set */
2322 if (ehci
->asynclistaddr
== 0) {
2326 ehci_set_state(ehci
, async
, EST_WAITLISTHEAD
);
2327 ehci_advance_state(ehci
, async
);
2329 /* If the doorbell is set, the guest wants to make a change to the
2330 * schedule. The host controller needs to release cached data.
2333 if (ehci
->usbcmd
& USBCMD_IAAD
) {
2334 /* Remove all unseen qhs from the async qhs queue */
2335 ehci_queues_rip_unused(ehci
, async
, 1);
2336 trace_usb_ehci_doorbell_ack();
2337 ehci
->usbcmd
&= ~USBCMD_IAAD
;
2338 ehci_raise_irq(ehci
, USBSTS_IAA
);
2343 /* this should only be due to a developer mistake */
2344 fprintf(stderr
, "ehci: Bad asynchronous state %d. "
2345 "Resetting to active\n", ehci
->astate
);
2350 static void ehci_advance_periodic_state(EHCIState
*ehci
)
2354 const int async
= 0;
2358 switch(ehci_get_state(ehci
, async
)) {
2360 if (!(ehci
->frindex
& 7) && ehci_periodic_enabled(ehci
)) {
2361 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2362 // No break, fall through to ACTIVE
2367 if (!(ehci
->frindex
& 7) && !ehci_periodic_enabled(ehci
)) {
2368 ehci_queues_rip_all(ehci
, async
);
2369 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2373 list
= ehci
->periodiclistbase
& 0xfffff000;
2374 /* check that register has been set */
2378 list
|= ((ehci
->frindex
& 0x1ff8) >> 1);
2380 pci_dma_read(&ehci
->dev
, list
, &entry
, sizeof entry
);
2381 entry
= le32_to_cpu(entry
);
2383 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2384 ehci
->frindex
/ 8, list
, entry
);
2385 ehci_set_fetch_addr(ehci
, async
,entry
);
2386 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
2387 ehci_advance_state(ehci
, async
);
2388 ehci_queues_rip_unused(ehci
, async
, 0);
2392 /* this should only be due to a developer mistake */
2393 fprintf(stderr
, "ehci: Bad periodic state %d. "
2394 "Resetting to active\n", ehci
->pstate
);
2399 static void ehci_update_frindex(EHCIState
*ehci
, int frames
)
2403 if (!ehci_enabled(ehci
)) {
2407 for (i
= 0; i
< frames
; i
++) {
2410 if (ehci
->frindex
== 0x00002000) {
2411 ehci_raise_irq(ehci
, USBSTS_FLR
);
2414 if (ehci
->frindex
== 0x00004000) {
2415 ehci_raise_irq(ehci
, USBSTS_FLR
);
2417 if (ehci
->usbsts_frindex
>= 0x00004000) {
2418 ehci
->usbsts_frindex
-= 0x00004000;
2420 ehci
->usbsts_frindex
= 0;
2426 static void ehci_frame_timer(void *opaque
)
2428 EHCIState
*ehci
= opaque
;
2430 int64_t expire_time
, t_now
;
2431 uint64_t ns_elapsed
;
2432 int frames
, skipped_frames
;
2435 t_now
= qemu_get_clock_ns(vm_clock
);
2436 ns_elapsed
= t_now
- ehci
->last_run_ns
;
2437 frames
= ns_elapsed
/ FRAME_TIMER_NS
;
2439 if (ehci_periodic_enabled(ehci
) || ehci
->pstate
!= EST_INACTIVE
) {
2441 ehci
->async_stepdown
= 0;
2443 if (frames
> ehci
->maxframes
) {
2444 skipped_frames
= frames
- ehci
->maxframes
;
2445 ehci_update_frindex(ehci
, skipped_frames
);
2446 ehci
->last_run_ns
+= FRAME_TIMER_NS
* skipped_frames
;
2447 frames
-= skipped_frames
;
2448 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames
);
2451 for (i
= 0; i
< frames
; i
++) {
2453 * If we're running behind schedule, we should not catch up
2454 * too fast, as that will make some guests unhappy:
2455 * 1) We must process a minimum of MIN_FR_PER_TICK frames,
2456 * otherwise we will never catch up
2457 * 2) Process frames until the guest has requested an irq (IOC)
2459 if (i
>= MIN_FR_PER_TICK
) {
2460 ehci_commit_irq(ehci
);
2461 if ((ehci
->usbsts
& USBINTR_MASK
) & ehci
->usbintr
) {
2465 ehci_update_frindex(ehci
, 1);
2466 ehci_advance_periodic_state(ehci
);
2467 ehci
->last_run_ns
+= FRAME_TIMER_NS
;
2470 if (ehci
->async_stepdown
< ehci
->maxframes
/ 2) {
2471 ehci
->async_stepdown
++;
2473 ehci_update_frindex(ehci
, frames
);
2474 ehci
->last_run_ns
+= FRAME_TIMER_NS
* frames
;
2477 /* Async is not inside loop since it executes everything it can once
2480 if (ehci_async_enabled(ehci
) || ehci
->astate
!= EST_INACTIVE
) {
2482 ehci_advance_async_state(ehci
);
2485 ehci_commit_irq(ehci
);
2486 if (ehci
->usbsts_pending
) {
2488 ehci
->async_stepdown
= 0;
2492 expire_time
= t_now
+ (get_ticks_per_sec()
2493 * (ehci
->async_stepdown
+1) / FRAME_TIMER_FREQ
);
2494 qemu_mod_timer(ehci
->frame_timer
, expire_time
);
2498 static void ehci_async_bh(void *opaque
)
2500 EHCIState
*ehci
= opaque
;
2501 ehci_advance_async_state(ehci
);
2504 static const MemoryRegionOps ehci_mmio_caps_ops
= {
2505 .read
= ehci_caps_read
,
2506 .valid
.min_access_size
= 1,
2507 .valid
.max_access_size
= 4,
2508 .impl
.min_access_size
= 1,
2509 .impl
.max_access_size
= 1,
2510 .endianness
= DEVICE_LITTLE_ENDIAN
,
2513 static const MemoryRegionOps ehci_mmio_opreg_ops
= {
2514 .read
= ehci_opreg_read
,
2515 .write
= ehci_opreg_write
,
2516 .valid
.min_access_size
= 4,
2517 .valid
.max_access_size
= 4,
2518 .endianness
= DEVICE_LITTLE_ENDIAN
,
2521 static const MemoryRegionOps ehci_mmio_port_ops
= {
2522 .read
= ehci_port_read
,
2523 .write
= ehci_port_write
,
2524 .valid
.min_access_size
= 4,
2525 .valid
.max_access_size
= 4,
2526 .endianness
= DEVICE_LITTLE_ENDIAN
,
2529 static int usb_ehci_initfn(PCIDevice
*dev
);
2531 static USBPortOps ehci_port_ops
= {
2532 .attach
= ehci_attach
,
2533 .detach
= ehci_detach
,
2534 .child_detach
= ehci_child_detach
,
2535 .wakeup
= ehci_wakeup
,
2536 .complete
= ehci_async_complete_packet
,
2539 static USBBusOps ehci_bus_ops
= {
2540 .register_companion
= ehci_register_companion
,
2543 static int usb_ehci_post_load(void *opaque
, int version_id
)
2545 EHCIState
*s
= opaque
;
2548 for (i
= 0; i
< NB_PORTS
; i
++) {
2549 USBPort
*companion
= s
->companion_ports
[i
];
2550 if (companion
== NULL
) {
2553 if (s
->portsc
[i
] & PORTSC_POWNER
) {
2554 companion
->dev
= s
->ports
[i
].dev
;
2556 companion
->dev
= NULL
;
2563 static const VMStateDescription vmstate_ehci
= {
2566 .minimum_version_id
= 1,
2567 .post_load
= usb_ehci_post_load
,
2568 .fields
= (VMStateField
[]) {
2569 VMSTATE_PCI_DEVICE(dev
, EHCIState
),
2570 /* mmio registers */
2571 VMSTATE_UINT32(usbcmd
, EHCIState
),
2572 VMSTATE_UINT32(usbsts
, EHCIState
),
2573 VMSTATE_UINT32_V(usbsts_pending
, EHCIState
, 2),
2574 VMSTATE_UINT32_V(usbsts_frindex
, EHCIState
, 2),
2575 VMSTATE_UINT32(usbintr
, EHCIState
),
2576 VMSTATE_UINT32(frindex
, EHCIState
),
2577 VMSTATE_UINT32(ctrldssegment
, EHCIState
),
2578 VMSTATE_UINT32(periodiclistbase
, EHCIState
),
2579 VMSTATE_UINT32(asynclistaddr
, EHCIState
),
2580 VMSTATE_UINT32(configflag
, EHCIState
),
2581 VMSTATE_UINT32(portsc
[0], EHCIState
),
2582 VMSTATE_UINT32(portsc
[1], EHCIState
),
2583 VMSTATE_UINT32(portsc
[2], EHCIState
),
2584 VMSTATE_UINT32(portsc
[3], EHCIState
),
2585 VMSTATE_UINT32(portsc
[4], EHCIState
),
2586 VMSTATE_UINT32(portsc
[5], EHCIState
),
2588 VMSTATE_TIMER(frame_timer
, EHCIState
),
2589 VMSTATE_UINT64(last_run_ns
, EHCIState
),
2590 VMSTATE_UINT32(async_stepdown
, EHCIState
),
2591 /* schedule state */
2592 VMSTATE_UINT32(astate
, EHCIState
),
2593 VMSTATE_UINT32(pstate
, EHCIState
),
2594 VMSTATE_UINT32(a_fetch_addr
, EHCIState
),
2595 VMSTATE_UINT32(p_fetch_addr
, EHCIState
),
2596 VMSTATE_END_OF_LIST()
2600 static Property ehci_properties
[] = {
2601 DEFINE_PROP_UINT32("maxframes", EHCIState
, maxframes
, 128),
2602 DEFINE_PROP_END_OF_LIST(),
2605 static void ehci_class_init(ObjectClass
*klass
, void *data
)
2607 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2608 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2610 k
->init
= usb_ehci_initfn
;
2611 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2612 k
->device_id
= PCI_DEVICE_ID_INTEL_82801D
; /* ich4 */
2614 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2615 dc
->vmsd
= &vmstate_ehci
;
2616 dc
->props
= ehci_properties
;
2619 static TypeInfo ehci_info
= {
2621 .parent
= TYPE_PCI_DEVICE
,
2622 .instance_size
= sizeof(EHCIState
),
2623 .class_init
= ehci_class_init
,
2626 static void ich9_ehci_class_init(ObjectClass
*klass
, void *data
)
2628 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2629 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2631 k
->init
= usb_ehci_initfn
;
2632 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2633 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_EHCI1
;
2635 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2636 dc
->vmsd
= &vmstate_ehci
;
2637 dc
->props
= ehci_properties
;
2640 static TypeInfo ich9_ehci_info
= {
2641 .name
= "ich9-usb-ehci1",
2642 .parent
= TYPE_PCI_DEVICE
,
2643 .instance_size
= sizeof(EHCIState
),
2644 .class_init
= ich9_ehci_class_init
,
2647 static int usb_ehci_initfn(PCIDevice
*dev
)
2649 EHCIState
*s
= DO_UPCAST(EHCIState
, dev
, dev
);
2650 uint8_t *pci_conf
= s
->dev
.config
;
2653 pci_set_byte(&pci_conf
[PCI_CLASS_PROG
], 0x20);
2655 /* capabilities pointer */
2656 pci_set_byte(&pci_conf
[PCI_CAPABILITY_LIST
], 0x00);
2657 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2659 pci_set_byte(&pci_conf
[PCI_INTERRUPT_PIN
], 4); /* interrupt pin D */
2660 pci_set_byte(&pci_conf
[PCI_MIN_GNT
], 0);
2661 pci_set_byte(&pci_conf
[PCI_MAX_LAT
], 0);
2663 // pci_conf[0x50] = 0x01; // power management caps
2665 pci_set_byte(&pci_conf
[USB_SBRN
], USB_RELEASE_2
); // release number (2.1.4)
2666 pci_set_byte(&pci_conf
[0x61], 0x20); // frame length adjustment (2.1.5)
2667 pci_set_word(&pci_conf
[0x62], 0x00); // port wake up capability (2.1.6)
2669 pci_conf
[0x64] = 0x00;
2670 pci_conf
[0x65] = 0x00;
2671 pci_conf
[0x66] = 0x00;
2672 pci_conf
[0x67] = 0x00;
2673 pci_conf
[0x68] = 0x01;
2674 pci_conf
[0x69] = 0x00;
2675 pci_conf
[0x6a] = 0x00;
2676 pci_conf
[0x6b] = 0x00; // USBLEGSUP
2677 pci_conf
[0x6c] = 0x00;
2678 pci_conf
[0x6d] = 0x00;
2679 pci_conf
[0x6e] = 0x00;
2680 pci_conf
[0x6f] = 0xc0; // USBLEFCTLSTS
2682 /* 2.2 host controller interface version */
2683 s
->caps
[0x00] = (uint8_t) OPREGBASE
;
2684 s
->caps
[0x01] = 0x00;
2685 s
->caps
[0x02] = 0x00;
2686 s
->caps
[0x03] = 0x01; /* HC version */
2687 s
->caps
[0x04] = NB_PORTS
; /* Number of downstream ports */
2688 s
->caps
[0x05] = 0x00; /* No companion ports at present */
2689 s
->caps
[0x06] = 0x00;
2690 s
->caps
[0x07] = 0x00;
2691 s
->caps
[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2692 s
->caps
[0x09] = 0x68; /* EECP */
2693 s
->caps
[0x0a] = 0x00;
2694 s
->caps
[0x0b] = 0x00;
2696 s
->irq
= s
->dev
.irq
[3];
2698 usb_bus_new(&s
->bus
, &ehci_bus_ops
, &s
->dev
.qdev
);
2699 for(i
= 0; i
< NB_PORTS
; i
++) {
2700 usb_register_port(&s
->bus
, &s
->ports
[i
], s
, i
, &ehci_port_ops
,
2701 USB_SPEED_MASK_HIGH
);
2702 s
->ports
[i
].dev
= 0;
2705 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, ehci_frame_timer
, s
);
2706 s
->async_bh
= qemu_bh_new(ehci_async_bh
, s
);
2707 QTAILQ_INIT(&s
->aqueues
);
2708 QTAILQ_INIT(&s
->pqueues
);
2709 usb_packet_init(&s
->ipacket
);
2711 qemu_register_reset(ehci_reset
, s
);
2713 memory_region_init(&s
->mem
, "ehci", MMIO_SIZE
);
2714 memory_region_init_io(&s
->mem_caps
, &ehci_mmio_caps_ops
, s
,
2715 "capabilities", OPREGBASE
);
2716 memory_region_init_io(&s
->mem_opreg
, &ehci_mmio_opreg_ops
, s
,
2717 "operational", PORTSC_BEGIN
- OPREGBASE
);
2718 memory_region_init_io(&s
->mem_ports
, &ehci_mmio_port_ops
, s
,
2719 "ports", PORTSC_END
- PORTSC_BEGIN
);
2721 memory_region_add_subregion(&s
->mem
, 0, &s
->mem_caps
);
2722 memory_region_add_subregion(&s
->mem
, OPREGBASE
, &s
->mem_opreg
);
2723 memory_region_add_subregion(&s
->mem
, PORTSC_BEGIN
, &s
->mem_ports
);
2725 pci_register_bar(&s
->dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mem
);
2730 static void ehci_register_types(void)
2732 type_register_static(&ehci_info
);
2733 type_register_static(&ich9_ehci_info
);
2736 type_init(ehci_register_types
)
2739 * vim: expandtab ts=4