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ehci: add async field to EHCIQueue
[qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw/hw.h"
26 #include "qemu-timer.h"
27 #include "hw/usb.h"
28 #include "hw/pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
137
138 /* Internal periodic / asynchronous schedule state machine states
139 */
140 typedef enum {
141 EST_INACTIVE = 1000,
142 EST_ACTIVE,
143 EST_EXECUTING,
144 EST_SLEEPING,
145 /* The following states are internal to the state machine function
146 */
147 EST_WAITLISTHEAD,
148 EST_FETCHENTRY,
149 EST_FETCHQH,
150 EST_FETCHITD,
151 EST_FETCHSITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIPacket EHCIPacket;
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIPacket {
348 EHCIQueue *queue;
349 QTAILQ_ENTRY(EHCIPacket) next;
350
351 EHCIqtd qtd; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr; /* address QTD read from */
353
354 USBPacket packet;
355 QEMUSGList sgl;
356 int pid;
357 uint32_t tbytes;
358 enum async_state async;
359 int usb_status;
360 };
361
362 struct EHCIQueue {
363 EHCIState *ehci;
364 QTAILQ_ENTRY(EHCIQueue) next;
365 uint32_t seen;
366 uint64_t ts;
367 int async;
368
369 /* cached data from guest - needs to be flushed
370 * when guest removes an entry (doorbell, handshake sequence)
371 */
372 EHCIqh qh; /* copy of current QH (being worked on) */
373 uint32_t qhaddr; /* address QH read from */
374 uint32_t qtdaddr; /* address QTD read from */
375 USBDevice *dev;
376 QTAILQ_HEAD(, EHCIPacket) packets;
377 };
378
379 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
380
381 struct EHCIState {
382 PCIDevice dev;
383 USBBus bus;
384 qemu_irq irq;
385 MemoryRegion mem;
386 int companion_count;
387
388 /* properties */
389 uint32_t freq;
390 uint32_t maxframes;
391
392 /*
393 * EHCI spec version 1.0 Section 2.3
394 * Host Controller Operational Registers
395 */
396 union {
397 uint8_t mmio[MMIO_SIZE];
398 struct {
399 uint8_t cap[OPREGBASE];
400 uint32_t usbcmd;
401 uint32_t usbsts;
402 uint32_t usbintr;
403 uint32_t frindex;
404 uint32_t ctrldssegment;
405 uint32_t periodiclistbase;
406 uint32_t asynclistaddr;
407 uint32_t notused[9];
408 uint32_t configflag;
409 uint32_t portsc[NB_PORTS];
410 };
411 };
412
413 /*
414 * Internal states, shadow registers, etc
415 */
416 QEMUTimer *frame_timer;
417 int attach_poll_counter;
418 int astate; // Current state in asynchronous schedule
419 int pstate; // Current state in periodic schedule
420 USBPort ports[NB_PORTS];
421 USBPort *companion_ports[NB_PORTS];
422 uint32_t usbsts_pending;
423 EHCIQueueHead aqueues;
424 EHCIQueueHead pqueues;
425
426 uint32_t a_fetch_addr; // which address to look at next
427 uint32_t p_fetch_addr; // which address to look at next
428
429 USBPacket ipacket;
430 QEMUSGList isgl;
431
432 uint64_t last_run_ns;
433 };
434
435 #define SET_LAST_RUN_CLOCK(s) \
436 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
437
438 /* nifty macros from Arnon's EHCI version */
439 #define get_field(data, field) \
440 (((data) & field##_MASK) >> field##_SH)
441
442 #define set_field(data, newval, field) do { \
443 uint32_t val = *data; \
444 val &= ~ field##_MASK; \
445 val |= ((newval) << field##_SH) & field##_MASK; \
446 *data = val; \
447 } while(0)
448
449 static const char *ehci_state_names[] = {
450 [EST_INACTIVE] = "INACTIVE",
451 [EST_ACTIVE] = "ACTIVE",
452 [EST_EXECUTING] = "EXECUTING",
453 [EST_SLEEPING] = "SLEEPING",
454 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
455 [EST_FETCHENTRY] = "FETCH ENTRY",
456 [EST_FETCHQH] = "FETCH QH",
457 [EST_FETCHITD] = "FETCH ITD",
458 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
459 [EST_FETCHQTD] = "FETCH QTD",
460 [EST_EXECUTE] = "EXECUTE",
461 [EST_WRITEBACK] = "WRITEBACK",
462 [EST_HORIZONTALQH] = "HORIZONTALQH",
463 };
464
465 static const char *ehci_mmio_names[] = {
466 [CAPLENGTH] = "CAPLENGTH",
467 [HCIVERSION] = "HCIVERSION",
468 [HCSPARAMS] = "HCSPARAMS",
469 [HCCPARAMS] = "HCCPARAMS",
470 [USBCMD] = "USBCMD",
471 [USBSTS] = "USBSTS",
472 [USBINTR] = "USBINTR",
473 [FRINDEX] = "FRINDEX",
474 [PERIODICLISTBASE] = "P-LIST BASE",
475 [ASYNCLISTADDR] = "A-LIST ADDR",
476 [PORTSC_BEGIN] = "PORTSC #0",
477 [PORTSC_BEGIN + 4] = "PORTSC #1",
478 [PORTSC_BEGIN + 8] = "PORTSC #2",
479 [PORTSC_BEGIN + 12] = "PORTSC #3",
480 [PORTSC_BEGIN + 16] = "PORTSC #4",
481 [PORTSC_BEGIN + 20] = "PORTSC #5",
482 [CONFIGFLAG] = "CONFIGFLAG",
483 };
484
485 static const char *nr2str(const char **n, size_t len, uint32_t nr)
486 {
487 if (nr < len && n[nr] != NULL) {
488 return n[nr];
489 } else {
490 return "unknown";
491 }
492 }
493
494 static const char *state2str(uint32_t state)
495 {
496 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
497 }
498
499 static const char *addr2str(target_phys_addr_t addr)
500 {
501 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
502 }
503
504 static void ehci_trace_usbsts(uint32_t mask, int state)
505 {
506 /* interrupts */
507 if (mask & USBSTS_INT) {
508 trace_usb_ehci_usbsts("INT", state);
509 }
510 if (mask & USBSTS_ERRINT) {
511 trace_usb_ehci_usbsts("ERRINT", state);
512 }
513 if (mask & USBSTS_PCD) {
514 trace_usb_ehci_usbsts("PCD", state);
515 }
516 if (mask & USBSTS_FLR) {
517 trace_usb_ehci_usbsts("FLR", state);
518 }
519 if (mask & USBSTS_HSE) {
520 trace_usb_ehci_usbsts("HSE", state);
521 }
522 if (mask & USBSTS_IAA) {
523 trace_usb_ehci_usbsts("IAA", state);
524 }
525
526 /* status */
527 if (mask & USBSTS_HALT) {
528 trace_usb_ehci_usbsts("HALT", state);
529 }
530 if (mask & USBSTS_REC) {
531 trace_usb_ehci_usbsts("REC", state);
532 }
533 if (mask & USBSTS_PSS) {
534 trace_usb_ehci_usbsts("PSS", state);
535 }
536 if (mask & USBSTS_ASS) {
537 trace_usb_ehci_usbsts("ASS", state);
538 }
539 }
540
541 static inline void ehci_set_usbsts(EHCIState *s, int mask)
542 {
543 if ((s->usbsts & mask) == mask) {
544 return;
545 }
546 ehci_trace_usbsts(mask, 1);
547 s->usbsts |= mask;
548 }
549
550 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
551 {
552 if ((s->usbsts & mask) == 0) {
553 return;
554 }
555 ehci_trace_usbsts(mask, 0);
556 s->usbsts &= ~mask;
557 }
558
559 static inline void ehci_set_interrupt(EHCIState *s, int intr)
560 {
561 int level = 0;
562
563 // TODO honour interrupt threshold requests
564
565 ehci_set_usbsts(s, intr);
566
567 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
568 level = 1;
569 }
570
571 qemu_set_irq(s->irq, level);
572 }
573
574 static inline void ehci_record_interrupt(EHCIState *s, int intr)
575 {
576 s->usbsts_pending |= intr;
577 }
578
579 static inline void ehci_commit_interrupt(EHCIState *s)
580 {
581 if (!s->usbsts_pending) {
582 return;
583 }
584 ehci_set_interrupt(s, s->usbsts_pending);
585 s->usbsts_pending = 0;
586 }
587
588 static void ehci_set_state(EHCIState *s, int async, int state)
589 {
590 if (async) {
591 trace_usb_ehci_state("async", state2str(state));
592 s->astate = state;
593 } else {
594 trace_usb_ehci_state("periodic", state2str(state));
595 s->pstate = state;
596 }
597 }
598
599 static int ehci_get_state(EHCIState *s, int async)
600 {
601 return async ? s->astate : s->pstate;
602 }
603
604 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
605 {
606 if (async) {
607 s->a_fetch_addr = addr;
608 } else {
609 s->p_fetch_addr = addr;
610 }
611 }
612
613 static int ehci_get_fetch_addr(EHCIState *s, int async)
614 {
615 return async ? s->a_fetch_addr : s->p_fetch_addr;
616 }
617
618 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
619 {
620 /* need three here due to argument count limits */
621 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
622 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
623 trace_usb_ehci_qh_fields(addr,
624 get_field(qh->epchar, QH_EPCHAR_RL),
625 get_field(qh->epchar, QH_EPCHAR_MPLEN),
626 get_field(qh->epchar, QH_EPCHAR_EPS),
627 get_field(qh->epchar, QH_EPCHAR_EP),
628 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
629 trace_usb_ehci_qh_bits(addr,
630 (bool)(qh->epchar & QH_EPCHAR_C),
631 (bool)(qh->epchar & QH_EPCHAR_H),
632 (bool)(qh->epchar & QH_EPCHAR_DTC),
633 (bool)(qh->epchar & QH_EPCHAR_I));
634 }
635
636 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
637 {
638 /* need three here due to argument count limits */
639 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
640 trace_usb_ehci_qtd_fields(addr,
641 get_field(qtd->token, QTD_TOKEN_TBYTES),
642 get_field(qtd->token, QTD_TOKEN_CPAGE),
643 get_field(qtd->token, QTD_TOKEN_CERR),
644 get_field(qtd->token, QTD_TOKEN_PID));
645 trace_usb_ehci_qtd_bits(addr,
646 (bool)(qtd->token & QTD_TOKEN_IOC),
647 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
648 (bool)(qtd->token & QTD_TOKEN_HALT),
649 (bool)(qtd->token & QTD_TOKEN_BABBLE),
650 (bool)(qtd->token & QTD_TOKEN_XACTERR));
651 }
652
653 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
654 {
655 trace_usb_ehci_itd(addr, itd->next,
656 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
657 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
658 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
659 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
660 }
661
662 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
663 EHCIsitd *sitd)
664 {
665 trace_usb_ehci_sitd(addr, sitd->next,
666 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
667 }
668
669 /* packet management */
670
671 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
672 {
673 EHCIPacket *p;
674
675 p = g_new0(EHCIPacket, 1);
676 p->queue = q;
677 usb_packet_init(&p->packet);
678 QTAILQ_INSERT_TAIL(&q->packets, p, next);
679 trace_usb_ehci_packet_action(p->queue, p, "alloc");
680 return p;
681 }
682
683 static void ehci_free_packet(EHCIPacket *p)
684 {
685 trace_usb_ehci_packet_action(p->queue, p, "free");
686 if (p->async == EHCI_ASYNC_INFLIGHT) {
687 usb_cancel_packet(&p->packet);
688 }
689 QTAILQ_REMOVE(&p->queue->packets, p, next);
690 usb_packet_cleanup(&p->packet);
691 g_free(p);
692 }
693
694 /* queue management */
695
696 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
697 {
698 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
699 EHCIQueue *q;
700
701 q = g_malloc0(sizeof(*q));
702 q->ehci = ehci;
703 q->qhaddr = addr;
704 q->async = async;
705 QTAILQ_INIT(&q->packets);
706 QTAILQ_INSERT_HEAD(head, q, next);
707 trace_usb_ehci_queue_action(q, "alloc");
708 return q;
709 }
710
711 static void ehci_free_queue(EHCIQueue *q)
712 {
713 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
714 EHCIPacket *p;
715
716 trace_usb_ehci_queue_action(q, "free");
717 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
718 ehci_free_packet(p);
719 }
720 QTAILQ_REMOVE(head, q, next);
721 g_free(q);
722 }
723
724 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
725 int async)
726 {
727 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
728 EHCIQueue *q;
729
730 QTAILQ_FOREACH(q, head, next) {
731 if (addr == q->qhaddr) {
732 return q;
733 }
734 }
735 return NULL;
736 }
737
738 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush)
739 {
740 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
741 EHCIQueue *q, *tmp;
742
743 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
744 if (q->seen) {
745 q->seen = 0;
746 q->ts = ehci->last_run_ns;
747 continue;
748 }
749 if (!flush && ehci->last_run_ns < q->ts + 250000000) {
750 /* allow 0.25 sec idle */
751 continue;
752 }
753 ehci_free_queue(q);
754 }
755 }
756
757 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
758 {
759 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
760 EHCIQueue *q, *tmp;
761
762 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
763 if (q->dev != dev) {
764 continue;
765 }
766 ehci_free_queue(q);
767 }
768 }
769
770 static void ehci_queues_rip_all(EHCIState *ehci, int async)
771 {
772 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
773 EHCIQueue *q, *tmp;
774
775 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
776 ehci_free_queue(q);
777 }
778 }
779
780 /* Attach or detach a device on root hub */
781
782 static void ehci_attach(USBPort *port)
783 {
784 EHCIState *s = port->opaque;
785 uint32_t *portsc = &s->portsc[port->index];
786
787 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
788
789 if (*portsc & PORTSC_POWNER) {
790 USBPort *companion = s->companion_ports[port->index];
791 companion->dev = port->dev;
792 companion->ops->attach(companion);
793 return;
794 }
795
796 *portsc |= PORTSC_CONNECT;
797 *portsc |= PORTSC_CSC;
798
799 ehci_set_interrupt(s, USBSTS_PCD);
800 }
801
802 static void ehci_detach(USBPort *port)
803 {
804 EHCIState *s = port->opaque;
805 uint32_t *portsc = &s->portsc[port->index];
806
807 trace_usb_ehci_port_detach(port->index);
808
809 if (*portsc & PORTSC_POWNER) {
810 USBPort *companion = s->companion_ports[port->index];
811 companion->ops->detach(companion);
812 companion->dev = NULL;
813 /*
814 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
815 * the port ownership is returned immediately to the EHCI controller."
816 */
817 *portsc &= ~PORTSC_POWNER;
818 return;
819 }
820
821 ehci_queues_rip_device(s, port->dev, 0);
822 ehci_queues_rip_device(s, port->dev, 1);
823
824 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
825 *portsc |= PORTSC_CSC;
826
827 ehci_set_interrupt(s, USBSTS_PCD);
828 }
829
830 static void ehci_child_detach(USBPort *port, USBDevice *child)
831 {
832 EHCIState *s = port->opaque;
833 uint32_t portsc = s->portsc[port->index];
834
835 if (portsc & PORTSC_POWNER) {
836 USBPort *companion = s->companion_ports[port->index];
837 companion->ops->child_detach(companion, child);
838 return;
839 }
840
841 ehci_queues_rip_device(s, child, 0);
842 ehci_queues_rip_device(s, child, 1);
843 }
844
845 static void ehci_wakeup(USBPort *port)
846 {
847 EHCIState *s = port->opaque;
848 uint32_t portsc = s->portsc[port->index];
849
850 if (portsc & PORTSC_POWNER) {
851 USBPort *companion = s->companion_ports[port->index];
852 if (companion->ops->wakeup) {
853 companion->ops->wakeup(companion);
854 }
855 }
856 }
857
858 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
859 uint32_t portcount, uint32_t firstport)
860 {
861 EHCIState *s = container_of(bus, EHCIState, bus);
862 uint32_t i;
863
864 if (firstport + portcount > NB_PORTS) {
865 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
866 "firstport on masterbus");
867 error_printf_unless_qmp(
868 "firstport value of %u makes companion take ports %u - %u, which "
869 "is outside of the valid range of 0 - %u\n", firstport, firstport,
870 firstport + portcount - 1, NB_PORTS - 1);
871 return -1;
872 }
873
874 for (i = 0; i < portcount; i++) {
875 if (s->companion_ports[firstport + i]) {
876 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
877 "an USB masterbus");
878 error_printf_unless_qmp(
879 "port %u on masterbus %s already has a companion assigned\n",
880 firstport + i, bus->qbus.name);
881 return -1;
882 }
883 }
884
885 for (i = 0; i < portcount; i++) {
886 s->companion_ports[firstport + i] = ports[i];
887 s->ports[firstport + i].speedmask |=
888 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
889 /* Ensure devs attached before the initial reset go to the companion */
890 s->portsc[firstport + i] = PORTSC_POWNER;
891 }
892
893 s->companion_count++;
894 s->mmio[0x05] = (s->companion_count << 4) | portcount;
895
896 return 0;
897 }
898
899 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
900 {
901 USBDevice *dev;
902 USBPort *port;
903 int i;
904
905 for (i = 0; i < NB_PORTS; i++) {
906 port = &ehci->ports[i];
907 if (!(ehci->portsc[i] & PORTSC_PED)) {
908 DPRINTF("Port %d not enabled\n", i);
909 continue;
910 }
911 dev = usb_find_device(port, addr);
912 if (dev != NULL) {
913 return dev;
914 }
915 }
916 return NULL;
917 }
918
919 /* 4.1 host controller initialization */
920 static void ehci_reset(void *opaque)
921 {
922 EHCIState *s = opaque;
923 int i;
924 USBDevice *devs[NB_PORTS];
925
926 trace_usb_ehci_reset();
927
928 /*
929 * Do the detach before touching portsc, so that it correctly gets send to
930 * us or to our companion based on PORTSC_POWNER before the reset.
931 */
932 for(i = 0; i < NB_PORTS; i++) {
933 devs[i] = s->ports[i].dev;
934 if (devs[i] && devs[i]->attached) {
935 usb_detach(&s->ports[i]);
936 }
937 }
938
939 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
940
941 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
942 s->usbsts = USBSTS_HALT;
943
944 s->astate = EST_INACTIVE;
945 s->pstate = EST_INACTIVE;
946 s->attach_poll_counter = 0;
947
948 for(i = 0; i < NB_PORTS; i++) {
949 if (s->companion_ports[i]) {
950 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
951 } else {
952 s->portsc[i] = PORTSC_PPOWER;
953 }
954 if (devs[i] && devs[i]->attached) {
955 usb_attach(&s->ports[i]);
956 usb_device_reset(devs[i]);
957 }
958 }
959 ehci_queues_rip_all(s, 0);
960 ehci_queues_rip_all(s, 1);
961 qemu_del_timer(s->frame_timer);
962 }
963
964 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
965 {
966 EHCIState *s = ptr;
967 uint32_t val;
968
969 val = s->mmio[addr];
970
971 return val;
972 }
973
974 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
975 {
976 EHCIState *s = ptr;
977 uint32_t val;
978
979 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
980
981 return val;
982 }
983
984 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
985 {
986 EHCIState *s = ptr;
987 uint32_t val;
988
989 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
990 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
991
992 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
993 return val;
994 }
995
996 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
997 {
998 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
999 exit(1);
1000 }
1001
1002 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
1003 {
1004 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
1005 exit(1);
1006 }
1007
1008 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
1009 {
1010 USBDevice *dev = s->ports[port].dev;
1011 uint32_t *portsc = &s->portsc[port];
1012 uint32_t orig;
1013
1014 if (s->companion_ports[port] == NULL)
1015 return;
1016
1017 owner = owner & PORTSC_POWNER;
1018 orig = *portsc & PORTSC_POWNER;
1019
1020 if (!(owner ^ orig)) {
1021 return;
1022 }
1023
1024 if (dev && dev->attached) {
1025 usb_detach(&s->ports[port]);
1026 }
1027
1028 *portsc &= ~PORTSC_POWNER;
1029 *portsc |= owner;
1030
1031 if (dev && dev->attached) {
1032 usb_attach(&s->ports[port]);
1033 }
1034 }
1035
1036 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1037 {
1038 uint32_t *portsc = &s->portsc[port];
1039 USBDevice *dev = s->ports[port].dev;
1040
1041 /* Clear rwc bits */
1042 *portsc &= ~(val & PORTSC_RWC_MASK);
1043 /* The guest may clear, but not set the PED bit */
1044 *portsc &= val | ~PORTSC_PED;
1045 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1046 handle_port_owner_write(s, port, val);
1047 /* And finally apply RO_MASK */
1048 val &= PORTSC_RO_MASK;
1049
1050 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1051 trace_usb_ehci_port_reset(port, 1);
1052 }
1053
1054 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1055 trace_usb_ehci_port_reset(port, 0);
1056 if (dev && dev->attached) {
1057 usb_port_reset(&s->ports[port]);
1058 *portsc &= ~PORTSC_CSC;
1059 }
1060
1061 /*
1062 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1063 * to SW that this port has a high speed device attached
1064 */
1065 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1066 val |= PORTSC_PED;
1067 }
1068 }
1069
1070 *portsc &= ~PORTSC_RO_MASK;
1071 *portsc |= val;
1072 }
1073
1074 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1075 {
1076 EHCIState *s = ptr;
1077 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1078 uint32_t old = *mmio;
1079 int i;
1080
1081 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1082
1083 /* Only aligned reads are allowed on OHCI */
1084 if (addr & 3) {
1085 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1086 TARGET_FMT_plx "\n", addr);
1087 return;
1088 }
1089
1090 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1091 handle_port_status_write(s, (addr-PORTSC)/4, val);
1092 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1093 return;
1094 }
1095
1096 if (addr < OPREGBASE) {
1097 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1098 TARGET_FMT_plx "\n", addr);
1099 return;
1100 }
1101
1102
1103 /* Do any register specific pre-write processing here. */
1104 switch(addr) {
1105 case USBCMD:
1106 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
1107 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1108 SET_LAST_RUN_CLOCK(s);
1109 ehci_clear_usbsts(s, USBSTS_HALT);
1110 }
1111
1112 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
1113 qemu_del_timer(s->frame_timer);
1114 ehci_queues_rip_all(s, 0);
1115 ehci_queues_rip_all(s, 1);
1116 ehci_set_usbsts(s, USBSTS_HALT);
1117 }
1118
1119 if (val & USBCMD_HCRESET) {
1120 ehci_reset(s);
1121 val = s->usbcmd;
1122 }
1123
1124 /* not supporting dynamic frame list size at the moment */
1125 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1126 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1127 val & USBCMD_FLS);
1128 val &= ~USBCMD_FLS;
1129 }
1130 break;
1131
1132 case USBSTS:
1133 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1134 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1135 val = s->usbsts;
1136 ehci_set_interrupt(s, 0);
1137 break;
1138
1139 case USBINTR:
1140 val &= USBINTR_MASK;
1141 break;
1142
1143 case FRINDEX:
1144 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1145 break;
1146
1147 case CONFIGFLAG:
1148 val &= 0x1;
1149 if (val) {
1150 for(i = 0; i < NB_PORTS; i++)
1151 handle_port_owner_write(s, i, 0);
1152 }
1153 break;
1154
1155 case PERIODICLISTBASE:
1156 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1157 fprintf(stderr,
1158 "ehci: PERIODIC list base register set while periodic schedule\n"
1159 " is enabled and HC is enabled\n");
1160 }
1161 break;
1162
1163 case ASYNCLISTADDR:
1164 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1165 fprintf(stderr,
1166 "ehci: ASYNC list address register set while async schedule\n"
1167 " is enabled and HC is enabled\n");
1168 }
1169 break;
1170 }
1171
1172 *mmio = val;
1173 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1174 }
1175
1176
1177 // TODO : Put in common header file, duplication from usb-ohci.c
1178
1179 /* Get an array of dwords from main memory */
1180 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1181 uint32_t *buf, int num)
1182 {
1183 int i;
1184
1185 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1186 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1187 *buf = le32_to_cpu(*buf);
1188 }
1189
1190 return 1;
1191 }
1192
1193 /* Put an array of dwords in to main memory */
1194 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1195 uint32_t *buf, int num)
1196 {
1197 int i;
1198
1199 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1200 uint32_t tmp = cpu_to_le32(*buf);
1201 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1202 }
1203
1204 return 1;
1205 }
1206
1207 // 4.10.2
1208
1209 static int ehci_qh_do_overlay(EHCIQueue *q)
1210 {
1211 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1212 int i;
1213 int dtoggle;
1214 int ping;
1215 int eps;
1216 int reload;
1217
1218 assert(p != NULL);
1219 assert(p->qtdaddr == q->qtdaddr);
1220
1221 // remember values in fields to preserve in qh after overlay
1222
1223 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1224 ping = q->qh.token & QTD_TOKEN_PING;
1225
1226 q->qh.current_qtd = p->qtdaddr;
1227 q->qh.next_qtd = p->qtd.next;
1228 q->qh.altnext_qtd = p->qtd.altnext;
1229 q->qh.token = p->qtd.token;
1230
1231
1232 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1233 if (eps == EHCI_QH_EPS_HIGH) {
1234 q->qh.token &= ~QTD_TOKEN_PING;
1235 q->qh.token |= ping;
1236 }
1237
1238 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1239 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1240
1241 for (i = 0; i < 5; i++) {
1242 q->qh.bufptr[i] = p->qtd.bufptr[i];
1243 }
1244
1245 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1246 // preserve QH DT bit
1247 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1248 q->qh.token |= dtoggle;
1249 }
1250
1251 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1252 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1253
1254 put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh,
1255 sizeof(EHCIqh) >> 2);
1256
1257 return 0;
1258 }
1259
1260 static int ehci_init_transfer(EHCIPacket *p)
1261 {
1262 uint32_t cpage, offset, bytes, plen;
1263 dma_addr_t page;
1264
1265 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1266 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1267 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1268 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
1269
1270 while (bytes > 0) {
1271 if (cpage > 4) {
1272 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1273 return USB_RET_PROCERR;
1274 }
1275
1276 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1277 page += offset;
1278 plen = bytes;
1279 if (plen > 4096 - offset) {
1280 plen = 4096 - offset;
1281 offset = 0;
1282 cpage++;
1283 }
1284
1285 qemu_sglist_add(&p->sgl, page, plen);
1286 bytes -= plen;
1287 }
1288 return 0;
1289 }
1290
1291 static void ehci_finish_transfer(EHCIQueue *q, int status)
1292 {
1293 uint32_t cpage, offset;
1294
1295 if (status > 0) {
1296 /* update cpage & offset */
1297 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1298 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1299
1300 offset += status;
1301 cpage += offset >> QTD_BUFPTR_SH;
1302 offset &= ~QTD_BUFPTR_MASK;
1303
1304 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1305 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1306 q->qh.bufptr[0] |= offset;
1307 }
1308 }
1309
1310 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1311 {
1312 EHCIPacket *p;
1313 EHCIState *s = port->opaque;
1314 uint32_t portsc = s->portsc[port->index];
1315
1316 if (portsc & PORTSC_POWNER) {
1317 USBPort *companion = s->companion_ports[port->index];
1318 companion->ops->complete(companion, packet);
1319 return;
1320 }
1321
1322 p = container_of(packet, EHCIPacket, packet);
1323 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1324 assert(p->async == EHCI_ASYNC_INFLIGHT);
1325 p->async = EHCI_ASYNC_FINISHED;
1326 p->usb_status = packet->result;
1327 }
1328
1329 static void ehci_execute_complete(EHCIQueue *q)
1330 {
1331 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1332
1333 assert(p != NULL);
1334 assert(p->qtdaddr == q->qtdaddr);
1335 assert(p->async != EHCI_ASYNC_INFLIGHT);
1336 p->async = EHCI_ASYNC_NONE;
1337
1338 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1339 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1340
1341 if (p->usb_status < 0) {
1342 switch (p->usb_status) {
1343 case USB_RET_IOERROR:
1344 case USB_RET_NODEV:
1345 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1346 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1347 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1348 break;
1349 case USB_RET_STALL:
1350 q->qh.token |= QTD_TOKEN_HALT;
1351 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1352 break;
1353 case USB_RET_NAK:
1354 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1355 return; /* We're not done yet with this transaction */
1356 case USB_RET_BABBLE:
1357 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1358 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1359 break;
1360 default:
1361 /* should not be triggerable */
1362 fprintf(stderr, "USB invalid response %d\n", p->usb_status);
1363 assert(0);
1364 break;
1365 }
1366 } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) {
1367 p->usb_status = USB_RET_BABBLE;
1368 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1369 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1370 } else {
1371 // TODO check 4.12 for splits
1372
1373 if (p->tbytes && p->pid == USB_TOKEN_IN) {
1374 p->tbytes -= p->usb_status;
1375 } else {
1376 p->tbytes = 0;
1377 }
1378
1379 DPRINTF("updating tbytes to %d\n", p->tbytes);
1380 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES);
1381 }
1382 ehci_finish_transfer(q, p->usb_status);
1383 qemu_sglist_destroy(&p->sgl);
1384 usb_packet_unmap(&p->packet);
1385
1386 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1387 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1388
1389 if (q->qh.token & QTD_TOKEN_IOC) {
1390 ehci_record_interrupt(q->ehci, USBSTS_INT);
1391 }
1392 }
1393
1394 // 4.10.3
1395
1396 static int ehci_execute(EHCIPacket *p, const char *action)
1397 {
1398 USBEndpoint *ep;
1399 int ret;
1400 int endp;
1401
1402 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1403 fprintf(stderr, "Attempting to execute inactive qtd\n");
1404 return USB_RET_PROCERR;
1405 }
1406
1407 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1408 if (p->tbytes > BUFF_SIZE) {
1409 fprintf(stderr, "Request for more bytes than allowed\n");
1410 return USB_RET_PROCERR;
1411 }
1412
1413 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1414 switch (p->pid) {
1415 case 0:
1416 p->pid = USB_TOKEN_OUT;
1417 break;
1418 case 1:
1419 p->pid = USB_TOKEN_IN;
1420 break;
1421 case 2:
1422 p->pid = USB_TOKEN_SETUP;
1423 break;
1424 default:
1425 fprintf(stderr, "bad token\n");
1426 break;
1427 }
1428
1429 if (ehci_init_transfer(p) != 0) {
1430 return USB_RET_PROCERR;
1431 }
1432
1433 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1434 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1435
1436 usb_packet_setup(&p->packet, p->pid, ep);
1437 usb_packet_map(&p->packet, &p->sgl);
1438
1439 trace_usb_ehci_packet_action(p->queue, p, action);
1440 ret = usb_handle_packet(p->queue->dev, &p->packet);
1441 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1442 "(total %d) endp %x ret %d\n",
1443 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1444 q->packet.iov.size, q->tbytes, endp, ret);
1445
1446 if (ret > BUFF_SIZE) {
1447 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1448 return USB_RET_PROCERR;
1449 }
1450
1451 return ret;
1452 }
1453
1454 /* 4.7.2
1455 */
1456
1457 static int ehci_process_itd(EHCIState *ehci,
1458 EHCIitd *itd)
1459 {
1460 USBDevice *dev;
1461 USBEndpoint *ep;
1462 int ret;
1463 uint32_t i, len, pid, dir, devaddr, endp;
1464 uint32_t pg, off, ptr1, ptr2, max, mult;
1465
1466 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1467 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1468 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1469 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1470 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1471
1472 for(i = 0; i < 8; i++) {
1473 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1474 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1475 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1476 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1477 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1478 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1479
1480 if (len > max * mult) {
1481 len = max * mult;
1482 }
1483
1484 if (len > BUFF_SIZE) {
1485 return USB_RET_PROCERR;
1486 }
1487
1488 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1489 if (off + len > 4096) {
1490 /* transfer crosses page border */
1491 uint32_t len2 = off + len - 4096;
1492 uint32_t len1 = len - len2;
1493 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1494 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1495 } else {
1496 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1497 }
1498
1499 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1500
1501 dev = ehci_find_device(ehci, devaddr);
1502 ep = usb_ep_get(dev, pid, endp);
1503 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1504 usb_packet_setup(&ehci->ipacket, pid, ep);
1505 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1506 ret = usb_handle_packet(dev, &ehci->ipacket);
1507 assert(ret != USB_RET_ASYNC);
1508 usb_packet_unmap(&ehci->ipacket);
1509 } else {
1510 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1511 ret = USB_RET_NAK;
1512 }
1513 qemu_sglist_destroy(&ehci->isgl);
1514
1515 if (ret < 0) {
1516 switch (ret) {
1517 default:
1518 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1519 /* Fall through */
1520 case USB_RET_IOERROR:
1521 case USB_RET_NODEV:
1522 /* 3.3.2: XACTERR is only allowed on IN transactions */
1523 if (dir) {
1524 itd->transact[i] |= ITD_XACT_XACTERR;
1525 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1526 }
1527 break;
1528 case USB_RET_BABBLE:
1529 itd->transact[i] |= ITD_XACT_BABBLE;
1530 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1531 break;
1532 case USB_RET_NAK:
1533 /* no data for us, so do a zero-length transfer */
1534 ret = 0;
1535 break;
1536 }
1537 }
1538 if (ret >= 0) {
1539 if (!dir) {
1540 /* OUT */
1541 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1542 } else {
1543 /* IN */
1544 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1545 }
1546 }
1547 if (itd->transact[i] & ITD_XACT_IOC) {
1548 ehci_record_interrupt(ehci, USBSTS_INT);
1549 }
1550 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1551 }
1552 }
1553 return 0;
1554 }
1555
1556
1557 /*
1558 * Write the qh back to guest physical memory. This step isn't
1559 * in the EHCI spec but we need to do it since we don't share
1560 * physical memory with our guest VM.
1561 *
1562 * The first three dwords are read-only for the EHCI, so skip them
1563 * when writing back the qh.
1564 */
1565 static void ehci_flush_qh(EHCIQueue *q)
1566 {
1567 uint32_t *qh = (uint32_t *) &q->qh;
1568 uint32_t dwords = sizeof(EHCIqh) >> 2;
1569 uint32_t addr = NLPTR_GET(q->qhaddr);
1570
1571 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1572 }
1573
1574 /* This state is the entry point for asynchronous schedule
1575 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1576 */
1577 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1578 {
1579 EHCIqh qh;
1580 int i = 0;
1581 int again = 0;
1582 uint32_t entry = ehci->asynclistaddr;
1583
1584 /* set reclamation flag at start event (4.8.6) */
1585 if (async) {
1586 ehci_set_usbsts(ehci, USBSTS_REC);
1587 }
1588
1589 ehci_queues_rip_unused(ehci, async, 0);
1590
1591 /* Find the head of the list (4.9.1.1) */
1592 for(i = 0; i < MAX_QH; i++) {
1593 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1594 sizeof(EHCIqh) >> 2);
1595 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1596
1597 if (qh.epchar & QH_EPCHAR_H) {
1598 if (async) {
1599 entry |= (NLPTR_TYPE_QH << 1);
1600 }
1601
1602 ehci_set_fetch_addr(ehci, async, entry);
1603 ehci_set_state(ehci, async, EST_FETCHENTRY);
1604 again = 1;
1605 goto out;
1606 }
1607
1608 entry = qh.next;
1609 if (entry == ehci->asynclistaddr) {
1610 break;
1611 }
1612 }
1613
1614 /* no head found for list. */
1615
1616 ehci_set_state(ehci, async, EST_ACTIVE);
1617
1618 out:
1619 return again;
1620 }
1621
1622
1623 /* This state is the entry point for periodic schedule processing as
1624 * well as being a continuation state for async processing.
1625 */
1626 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1627 {
1628 int again = 0;
1629 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1630
1631 if (NLPTR_TBIT(entry)) {
1632 ehci_set_state(ehci, async, EST_ACTIVE);
1633 goto out;
1634 }
1635
1636 /* section 4.8, only QH in async schedule */
1637 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1638 fprintf(stderr, "non queue head request in async schedule\n");
1639 return -1;
1640 }
1641
1642 switch (NLPTR_TYPE_GET(entry)) {
1643 case NLPTR_TYPE_QH:
1644 ehci_set_state(ehci, async, EST_FETCHQH);
1645 again = 1;
1646 break;
1647
1648 case NLPTR_TYPE_ITD:
1649 ehci_set_state(ehci, async, EST_FETCHITD);
1650 again = 1;
1651 break;
1652
1653 case NLPTR_TYPE_STITD:
1654 ehci_set_state(ehci, async, EST_FETCHSITD);
1655 again = 1;
1656 break;
1657
1658 default:
1659 /* TODO: handle FSTN type */
1660 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1661 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1662 return -1;
1663 }
1664
1665 out:
1666 return again;
1667 }
1668
1669 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1670 {
1671 EHCIPacket *p;
1672 uint32_t entry, devaddr;
1673 EHCIQueue *q;
1674
1675 entry = ehci_get_fetch_addr(ehci, async);
1676 q = ehci_find_queue_by_qh(ehci, entry, async);
1677 if (NULL == q) {
1678 q = ehci_alloc_queue(ehci, entry, async);
1679 }
1680 p = QTAILQ_FIRST(&q->packets);
1681
1682 q->seen++;
1683 if (q->seen > 1) {
1684 /* we are going in circles -- stop processing */
1685 ehci_set_state(ehci, async, EST_ACTIVE);
1686 q = NULL;
1687 goto out;
1688 }
1689
1690 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1691 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1692 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1693
1694 devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1695 if (q->dev != NULL && q->dev->addr != devaddr) {
1696 if (!QTAILQ_EMPTY(&q->packets)) {
1697 /* should not happen (guest bug) */
1698 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
1699 ehci_free_packet(p);
1700 }
1701 }
1702 q->dev = NULL;
1703 }
1704 if (q->dev == NULL) {
1705 q->dev = ehci_find_device(q->ehci, devaddr);
1706 }
1707
1708 if (p && p->async == EHCI_ASYNC_INFLIGHT) {
1709 /* I/O still in progress -- skip queue */
1710 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1711 goto out;
1712 }
1713 if (p && p->async == EHCI_ASYNC_FINISHED) {
1714 /* I/O finished -- continue processing queue */
1715 trace_usb_ehci_packet_action(p->queue, p, "complete");
1716 ehci_set_state(ehci, async, EST_EXECUTING);
1717 goto out;
1718 }
1719
1720 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1721
1722 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1723 if (ehci->usbsts & USBSTS_REC) {
1724 ehci_clear_usbsts(ehci, USBSTS_REC);
1725 } else {
1726 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1727 " - done processing\n", q->qhaddr);
1728 ehci_set_state(ehci, async, EST_ACTIVE);
1729 q = NULL;
1730 goto out;
1731 }
1732 }
1733
1734 #if EHCI_DEBUG
1735 if (q->qhaddr != q->qh.next) {
1736 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1737 q->qhaddr,
1738 q->qh.epchar & QH_EPCHAR_H,
1739 q->qh.token & QTD_TOKEN_HALT,
1740 q->qh.token & QTD_TOKEN_ACTIVE,
1741 q->qh.next);
1742 }
1743 #endif
1744
1745 if (q->qh.token & QTD_TOKEN_HALT) {
1746 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1747
1748 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1749 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1750 q->qtdaddr = q->qh.current_qtd;
1751 ehci_set_state(ehci, async, EST_FETCHQTD);
1752
1753 } else {
1754 /* EHCI spec version 1.0 Section 4.10.2 */
1755 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1756 }
1757
1758 out:
1759 return q;
1760 }
1761
1762 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1763 {
1764 uint32_t entry;
1765 EHCIitd itd;
1766
1767 assert(!async);
1768 entry = ehci_get_fetch_addr(ehci, async);
1769
1770 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1771 sizeof(EHCIitd) >> 2);
1772 ehci_trace_itd(ehci, entry, &itd);
1773
1774 if (ehci_process_itd(ehci, &itd) != 0) {
1775 return -1;
1776 }
1777
1778 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1779 sizeof(EHCIitd) >> 2);
1780 ehci_set_fetch_addr(ehci, async, itd.next);
1781 ehci_set_state(ehci, async, EST_FETCHENTRY);
1782
1783 return 1;
1784 }
1785
1786 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1787 {
1788 uint32_t entry;
1789 EHCIsitd sitd;
1790
1791 assert(!async);
1792 entry = ehci_get_fetch_addr(ehci, async);
1793
1794 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1795 sizeof(EHCIsitd) >> 2);
1796 ehci_trace_sitd(ehci, entry, &sitd);
1797
1798 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1799 /* siTD is not active, nothing to do */;
1800 } else {
1801 /* TODO: split transfers are not implemented */
1802 fprintf(stderr, "WARNING: Skipping active siTD\n");
1803 }
1804
1805 ehci_set_fetch_addr(ehci, async, sitd.next);
1806 ehci_set_state(ehci, async, EST_FETCHENTRY);
1807 return 1;
1808 }
1809
1810 /* Section 4.10.2 - paragraph 3 */
1811 static int ehci_state_advqueue(EHCIQueue *q)
1812 {
1813 #if 0
1814 /* TO-DO: 4.10.2 - paragraph 2
1815 * if I-bit is set to 1 and QH is not active
1816 * go to horizontal QH
1817 */
1818 if (I-bit set) {
1819 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1820 goto out;
1821 }
1822 #endif
1823
1824 /*
1825 * want data and alt-next qTD is valid
1826 */
1827 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1828 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1829 q->qtdaddr = q->qh.altnext_qtd;
1830 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1831
1832 /*
1833 * next qTD is valid
1834 */
1835 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1836 q->qtdaddr = q->qh.next_qtd;
1837 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1838
1839 /*
1840 * no valid qTD, try next QH
1841 */
1842 } else {
1843 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1844 }
1845
1846 return 1;
1847 }
1848
1849 /* Section 4.10.2 - paragraph 4 */
1850 static int ehci_state_fetchqtd(EHCIQueue *q)
1851 {
1852 EHCIqtd qtd;
1853 EHCIPacket *p;
1854 int again = 0;
1855
1856 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1857 sizeof(EHCIqtd) >> 2);
1858 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1859
1860 p = QTAILQ_FIRST(&q->packets);
1861 while (p != NULL && p->qtdaddr != q->qtdaddr) {
1862 /* should not happen (guest bug) */
1863 ehci_free_packet(p);
1864 p = QTAILQ_FIRST(&q->packets);
1865 }
1866 if (p != NULL) {
1867 ehci_qh_do_overlay(q);
1868 ehci_flush_qh(q);
1869 if (p->async == EHCI_ASYNC_INFLIGHT) {
1870 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1871 } else {
1872 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1873 }
1874 again = 1;
1875 } else if (qtd.token & QTD_TOKEN_ACTIVE) {
1876 p = ehci_alloc_packet(q);
1877 p->qtdaddr = q->qtdaddr;
1878 p->qtd = qtd;
1879 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1880 again = 1;
1881 } else {
1882 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1883 again = 1;
1884 }
1885
1886 return again;
1887 }
1888
1889 static int ehci_state_horizqh(EHCIQueue *q)
1890 {
1891 int again = 0;
1892
1893 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1894 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1895 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1896 again = 1;
1897 } else {
1898 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1899 }
1900
1901 return again;
1902 }
1903
1904 static void ehci_fill_queue(EHCIPacket *p)
1905 {
1906 EHCIQueue *q = p->queue;
1907 EHCIqtd qtd = p->qtd;
1908 uint32_t qtdaddr;
1909
1910 for (;;) {
1911 if (NLPTR_TBIT(qtd.altnext) == 0) {
1912 break;
1913 }
1914 if (NLPTR_TBIT(qtd.next) != 0) {
1915 break;
1916 }
1917 qtdaddr = qtd.next;
1918 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1919 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
1920 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1921 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1922 break;
1923 }
1924 p = ehci_alloc_packet(q);
1925 p->qtdaddr = qtdaddr;
1926 p->qtd = qtd;
1927 p->usb_status = ehci_execute(p, "queue");
1928 assert(p->usb_status = USB_RET_ASYNC);
1929 p->async = EHCI_ASYNC_INFLIGHT;
1930 }
1931 }
1932
1933 static int ehci_state_execute(EHCIQueue *q)
1934 {
1935 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1936 int again = 0;
1937
1938 assert(p != NULL);
1939 assert(p->qtdaddr == q->qtdaddr);
1940
1941 if (ehci_qh_do_overlay(q) != 0) {
1942 return -1;
1943 }
1944
1945 // TODO verify enough time remains in the uframe as in 4.4.1.1
1946 // TODO write back ptr to async list when done or out of time
1947 // TODO Windows does not seem to ever set the MULT field
1948
1949 if (!q->async) {
1950 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1951 if (!transactCtr) {
1952 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1953 again = 1;
1954 goto out;
1955 }
1956 }
1957
1958 if (q->async) {
1959 ehci_set_usbsts(q->ehci, USBSTS_REC);
1960 }
1961
1962 p->usb_status = ehci_execute(p, "process");
1963 if (p->usb_status == USB_RET_PROCERR) {
1964 again = -1;
1965 goto out;
1966 }
1967 if (p->usb_status == USB_RET_ASYNC) {
1968 ehci_flush_qh(q);
1969 trace_usb_ehci_packet_action(p->queue, p, "async");
1970 p->async = EHCI_ASYNC_INFLIGHT;
1971 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1972 again = 1;
1973 ehci_fill_queue(p);
1974 goto out;
1975 }
1976
1977 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1978 again = 1;
1979
1980 out:
1981 return again;
1982 }
1983
1984 static int ehci_state_executing(EHCIQueue *q)
1985 {
1986 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1987 int again = 0;
1988
1989 assert(p != NULL);
1990 assert(p->qtdaddr == q->qtdaddr);
1991
1992 ehci_execute_complete(q);
1993 if (p->usb_status == USB_RET_ASYNC) {
1994 goto out;
1995 }
1996 if (p->usb_status == USB_RET_PROCERR) {
1997 again = -1;
1998 goto out;
1999 }
2000
2001 // 4.10.3
2002 if (!q->async) {
2003 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2004 transactCtr--;
2005 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
2006 // 4.10.3, bottom of page 82, should exit this state when transaction
2007 // counter decrements to 0
2008 }
2009
2010 /* 4.10.5 */
2011 if (p->usb_status == USB_RET_NAK) {
2012 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2013 } else {
2014 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
2015 }
2016
2017 again = 1;
2018
2019 out:
2020 ehci_flush_qh(q);
2021 return again;
2022 }
2023
2024
2025 static int ehci_state_writeback(EHCIQueue *q)
2026 {
2027 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2028 int again = 0;
2029
2030 /* Write back the QTD from the QH area */
2031 assert(p != NULL);
2032 assert(p->qtdaddr == q->qtdaddr);
2033
2034 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2035 put_dwords(q->ehci, NLPTR_GET(p->qtdaddr), (uint32_t *) &q->qh.next_qtd,
2036 sizeof(EHCIqtd) >> 2);
2037 ehci_free_packet(p);
2038
2039 /*
2040 * EHCI specs say go horizontal here.
2041 *
2042 * We can also advance the queue here for performance reasons. We
2043 * need to take care to only take that shortcut in case we've
2044 * processed the qtd just written back without errors, i.e. halt
2045 * bit is clear.
2046 */
2047 if (q->qh.token & QTD_TOKEN_HALT) {
2048 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2049 again = 1;
2050 } else {
2051 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2052 again = 1;
2053 }
2054 return again;
2055 }
2056
2057 /*
2058 * This is the state machine that is common to both async and periodic
2059 */
2060
2061 static void ehci_advance_state(EHCIState *ehci, int async)
2062 {
2063 EHCIQueue *q = NULL;
2064 int again;
2065
2066 do {
2067 switch(ehci_get_state(ehci, async)) {
2068 case EST_WAITLISTHEAD:
2069 again = ehci_state_waitlisthead(ehci, async);
2070 break;
2071
2072 case EST_FETCHENTRY:
2073 again = ehci_state_fetchentry(ehci, async);
2074 break;
2075
2076 case EST_FETCHQH:
2077 q = ehci_state_fetchqh(ehci, async);
2078 if (q != NULL) {
2079 assert(q->async == async);
2080 again = 1;
2081 } else {
2082 again = 0;
2083 }
2084 break;
2085
2086 case EST_FETCHITD:
2087 again = ehci_state_fetchitd(ehci, async);
2088 break;
2089
2090 case EST_FETCHSITD:
2091 again = ehci_state_fetchsitd(ehci, async);
2092 break;
2093
2094 case EST_ADVANCEQUEUE:
2095 again = ehci_state_advqueue(q);
2096 break;
2097
2098 case EST_FETCHQTD:
2099 again = ehci_state_fetchqtd(q);
2100 break;
2101
2102 case EST_HORIZONTALQH:
2103 again = ehci_state_horizqh(q);
2104 break;
2105
2106 case EST_EXECUTE:
2107 again = ehci_state_execute(q);
2108 break;
2109
2110 case EST_EXECUTING:
2111 assert(q != NULL);
2112 again = ehci_state_executing(q);
2113 break;
2114
2115 case EST_WRITEBACK:
2116 assert(q != NULL);
2117 again = ehci_state_writeback(q);
2118 break;
2119
2120 default:
2121 fprintf(stderr, "Bad state!\n");
2122 again = -1;
2123 assert(0);
2124 break;
2125 }
2126
2127 if (again < 0) {
2128 fprintf(stderr, "processing error - resetting ehci HC\n");
2129 ehci_reset(ehci);
2130 again = 0;
2131 }
2132 }
2133 while (again);
2134
2135 ehci_commit_interrupt(ehci);
2136 }
2137
2138 static void ehci_advance_async_state(EHCIState *ehci)
2139 {
2140 const int async = 1;
2141
2142 switch(ehci_get_state(ehci, async)) {
2143 case EST_INACTIVE:
2144 if (!(ehci->usbcmd & USBCMD_ASE)) {
2145 break;
2146 }
2147 ehci_set_usbsts(ehci, USBSTS_ASS);
2148 ehci_set_state(ehci, async, EST_ACTIVE);
2149 // No break, fall through to ACTIVE
2150
2151 case EST_ACTIVE:
2152 if ( !(ehci->usbcmd & USBCMD_ASE)) {
2153 ehci_queues_rip_all(ehci, async);
2154 ehci_clear_usbsts(ehci, USBSTS_ASS);
2155 ehci_set_state(ehci, async, EST_INACTIVE);
2156 break;
2157 }
2158
2159 /* make sure guest has acknowledged the doorbell interrupt */
2160 /* TO-DO: is this really needed? */
2161 if (ehci->usbsts & USBSTS_IAA) {
2162 DPRINTF("IAA status bit still set.\n");
2163 break;
2164 }
2165
2166 /* check that address register has been set */
2167 if (ehci->asynclistaddr == 0) {
2168 break;
2169 }
2170
2171 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2172 ehci_advance_state(ehci, async);
2173
2174 /* If the doorbell is set, the guest wants to make a change to the
2175 * schedule. The host controller needs to release cached data.
2176 * (section 4.8.2)
2177 */
2178 if (ehci->usbcmd & USBCMD_IAAD) {
2179 /* Remove all unseen qhs from the async qhs queue */
2180 ehci_queues_rip_unused(ehci, async, 1);
2181 DPRINTF("ASYNC: doorbell request acknowledged\n");
2182 ehci->usbcmd &= ~USBCMD_IAAD;
2183 ehci_set_interrupt(ehci, USBSTS_IAA);
2184 }
2185 break;
2186
2187 default:
2188 /* this should only be due to a developer mistake */
2189 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2190 "Resetting to active\n", ehci->astate);
2191 assert(0);
2192 }
2193 }
2194
2195 static void ehci_advance_periodic_state(EHCIState *ehci)
2196 {
2197 uint32_t entry;
2198 uint32_t list;
2199 const int async = 0;
2200
2201 // 4.6
2202
2203 switch(ehci_get_state(ehci, async)) {
2204 case EST_INACTIVE:
2205 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2206 ehci_set_usbsts(ehci, USBSTS_PSS);
2207 ehci_set_state(ehci, async, EST_ACTIVE);
2208 // No break, fall through to ACTIVE
2209 } else
2210 break;
2211
2212 case EST_ACTIVE:
2213 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2214 ehci_queues_rip_all(ehci, async);
2215 ehci_clear_usbsts(ehci, USBSTS_PSS);
2216 ehci_set_state(ehci, async, EST_INACTIVE);
2217 break;
2218 }
2219
2220 list = ehci->periodiclistbase & 0xfffff000;
2221 /* check that register has been set */
2222 if (list == 0) {
2223 break;
2224 }
2225 list |= ((ehci->frindex & 0x1ff8) >> 1);
2226
2227 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2228 entry = le32_to_cpu(entry);
2229
2230 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2231 ehci->frindex / 8, list, entry);
2232 ehci_set_fetch_addr(ehci, async,entry);
2233 ehci_set_state(ehci, async, EST_FETCHENTRY);
2234 ehci_advance_state(ehci, async);
2235 ehci_queues_rip_unused(ehci, async, 0);
2236 break;
2237
2238 default:
2239 /* this should only be due to a developer mistake */
2240 fprintf(stderr, "ehci: Bad periodic state %d. "
2241 "Resetting to active\n", ehci->pstate);
2242 assert(0);
2243 }
2244 }
2245
2246 static void ehci_frame_timer(void *opaque)
2247 {
2248 EHCIState *ehci = opaque;
2249 int64_t expire_time, t_now;
2250 uint64_t ns_elapsed;
2251 int frames;
2252 int i;
2253 int skipped_frames = 0;
2254
2255 t_now = qemu_get_clock_ns(vm_clock);
2256 expire_time = t_now + (get_ticks_per_sec() / ehci->freq);
2257
2258 ns_elapsed = t_now - ehci->last_run_ns;
2259 frames = ns_elapsed / FRAME_TIMER_NS;
2260
2261 for (i = 0; i < frames; i++) {
2262 if ( !(ehci->usbsts & USBSTS_HALT)) {
2263 ehci->frindex += 8;
2264
2265 if (ehci->frindex == 0x00002000) {
2266 ehci_set_interrupt(ehci, USBSTS_FLR);
2267 }
2268
2269 if (ehci->frindex == 0x00004000) {
2270 ehci_set_interrupt(ehci, USBSTS_FLR);
2271 ehci->frindex = 0;
2272 }
2273 }
2274
2275 if (frames - i > ehci->maxframes) {
2276 skipped_frames++;
2277 } else {
2278 ehci_advance_periodic_state(ehci);
2279 }
2280
2281 ehci->last_run_ns += FRAME_TIMER_NS;
2282 }
2283
2284 #if 0
2285 if (skipped_frames) {
2286 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2287 }
2288 #endif
2289
2290 /* Async is not inside loop since it executes everything it can once
2291 * called
2292 */
2293 ehci_advance_async_state(ehci);
2294
2295 qemu_mod_timer(ehci->frame_timer, expire_time);
2296 }
2297
2298
2299 static const MemoryRegionOps ehci_mem_ops = {
2300 .old_mmio = {
2301 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2302 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2303 },
2304 .endianness = DEVICE_LITTLE_ENDIAN,
2305 };
2306
2307 static int usb_ehci_initfn(PCIDevice *dev);
2308
2309 static USBPortOps ehci_port_ops = {
2310 .attach = ehci_attach,
2311 .detach = ehci_detach,
2312 .child_detach = ehci_child_detach,
2313 .wakeup = ehci_wakeup,
2314 .complete = ehci_async_complete_packet,
2315 };
2316
2317 static USBBusOps ehci_bus_ops = {
2318 .register_companion = ehci_register_companion,
2319 };
2320
2321 static const VMStateDescription vmstate_ehci = {
2322 .name = "ehci",
2323 .unmigratable = 1,
2324 };
2325
2326 static Property ehci_properties[] = {
2327 DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ),
2328 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2329 DEFINE_PROP_END_OF_LIST(),
2330 };
2331
2332 static void ehci_class_init(ObjectClass *klass, void *data)
2333 {
2334 DeviceClass *dc = DEVICE_CLASS(klass);
2335 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2336
2337 k->init = usb_ehci_initfn;
2338 k->vendor_id = PCI_VENDOR_ID_INTEL;
2339 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2340 k->revision = 0x10;
2341 k->class_id = PCI_CLASS_SERIAL_USB;
2342 dc->vmsd = &vmstate_ehci;
2343 dc->props = ehci_properties;
2344 }
2345
2346 static TypeInfo ehci_info = {
2347 .name = "usb-ehci",
2348 .parent = TYPE_PCI_DEVICE,
2349 .instance_size = sizeof(EHCIState),
2350 .class_init = ehci_class_init,
2351 };
2352
2353 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2354 {
2355 DeviceClass *dc = DEVICE_CLASS(klass);
2356 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2357
2358 k->init = usb_ehci_initfn;
2359 k->vendor_id = PCI_VENDOR_ID_INTEL;
2360 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2361 k->revision = 0x03;
2362 k->class_id = PCI_CLASS_SERIAL_USB;
2363 dc->vmsd = &vmstate_ehci;
2364 dc->props = ehci_properties;
2365 }
2366
2367 static TypeInfo ich9_ehci_info = {
2368 .name = "ich9-usb-ehci1",
2369 .parent = TYPE_PCI_DEVICE,
2370 .instance_size = sizeof(EHCIState),
2371 .class_init = ich9_ehci_class_init,
2372 };
2373
2374 static int usb_ehci_initfn(PCIDevice *dev)
2375 {
2376 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2377 uint8_t *pci_conf = s->dev.config;
2378 int i;
2379
2380 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2381
2382 /* capabilities pointer */
2383 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2384 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2385
2386 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2387 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2388 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2389
2390 // pci_conf[0x50] = 0x01; // power management caps
2391
2392 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2393 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2394 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2395
2396 pci_conf[0x64] = 0x00;
2397 pci_conf[0x65] = 0x00;
2398 pci_conf[0x66] = 0x00;
2399 pci_conf[0x67] = 0x00;
2400 pci_conf[0x68] = 0x01;
2401 pci_conf[0x69] = 0x00;
2402 pci_conf[0x6a] = 0x00;
2403 pci_conf[0x6b] = 0x00; // USBLEGSUP
2404 pci_conf[0x6c] = 0x00;
2405 pci_conf[0x6d] = 0x00;
2406 pci_conf[0x6e] = 0x00;
2407 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2408
2409 // 2.2 host controller interface version
2410 s->mmio[0x00] = (uint8_t) OPREGBASE;
2411 s->mmio[0x01] = 0x00;
2412 s->mmio[0x02] = 0x00;
2413 s->mmio[0x03] = 0x01; // HC version
2414 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2415 s->mmio[0x05] = 0x00; // No companion ports at present
2416 s->mmio[0x06] = 0x00;
2417 s->mmio[0x07] = 0x00;
2418 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2419 s->mmio[0x09] = 0x68; // EECP
2420 s->mmio[0x0a] = 0x00;
2421 s->mmio[0x0b] = 0x00;
2422
2423 s->irq = s->dev.irq[3];
2424
2425 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2426 for(i = 0; i < NB_PORTS; i++) {
2427 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2428 USB_SPEED_MASK_HIGH);
2429 s->ports[i].dev = 0;
2430 }
2431
2432 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2433 QTAILQ_INIT(&s->aqueues);
2434 QTAILQ_INIT(&s->pqueues);
2435
2436 qemu_register_reset(ehci_reset, s);
2437
2438 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2439 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2440
2441 return 0;
2442 }
2443
2444 static void ehci_register_types(void)
2445 {
2446 type_register_static(&ehci_info);
2447 type_register_static(&ich9_ehci_info);
2448 }
2449
2450 type_init(ehci_register_types)
2451
2452 /*
2453 * vim: expandtab ts=4
2454 */