2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu-timer.h"
36 #define DPRINTF printf
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
44 #define MMIO_SIZE 0x1000
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
98 #define CONFIGFLAG OPREGBASE + 0x0040
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
138 /* Internal periodic / asynchronous schedule state machine states
145 /* The following states are internal to the state machine function
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171 /* EHCI spec version 1.0 Section 3.3
173 typedef struct EHCIitd
{
176 uint32_t transact
[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
202 /* EHCI spec version 1.0 Section 3.4
204 typedef struct EHCIsitd
{
205 uint32_t next
; // Standard next link pointer
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243 uint32_t backptr
; // Standard next link pointer
246 /* EHCI spec version 1.0 Section 3.5
248 typedef struct EHCIqtd
{
249 uint32_t next
; // Standard next link pointer
250 uint32_t altnext
; // Standard next link pointer
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
271 uint32_t bufptr
[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
276 /* EHCI spec version 1.0 Section 3.6
278 typedef struct EHCIqh
{
279 uint32_t next
; // Standard next link pointer
281 /* endpoint characteristics */
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
303 /* endpoint capabilities */
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
316 uint32_t current_qtd
; // Standard next link pointer
317 uint32_t next_qtd
; // Standard next link pointer
318 uint32_t altnext_qtd
;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
322 uint32_t token
; // Same as QTD token
323 uint32_t bufptr
[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
330 /* EHCI spec version 1.0 Section 3.7
332 typedef struct EHCIfstn
{
333 uint32_t next
; // Standard next link pointer
334 uint32_t backptr
; // Standard next link pointer
337 typedef struct EHCIPacket EHCIPacket
;
338 typedef struct EHCIQueue EHCIQueue
;
339 typedef struct EHCIState EHCIState
;
349 QTAILQ_ENTRY(EHCIPacket
) next
;
351 EHCIqtd qtd
; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr
; /* address QTD read from */
358 enum async_state async
;
364 QTAILQ_ENTRY(EHCIQueue
) next
;
369 /* cached data from guest - needs to be flushed
370 * when guest removes an entry (doorbell, handshake sequence)
372 EHCIqh qh
; /* copy of current QH (being worked on) */
373 uint32_t qhaddr
; /* address QH read from */
374 uint32_t qtdaddr
; /* address QTD read from */
376 QTAILQ_HEAD(, EHCIPacket
) packets
;
379 typedef QTAILQ_HEAD(EHCIQueueHead
, EHCIQueue
) EHCIQueueHead
;
393 * EHCI spec version 1.0 Section 2.3
394 * Host Controller Operational Registers
397 uint8_t mmio
[MMIO_SIZE
];
399 uint8_t cap
[OPREGBASE
];
404 uint32_t ctrldssegment
;
405 uint32_t periodiclistbase
;
406 uint32_t asynclistaddr
;
409 uint32_t portsc
[NB_PORTS
];
414 * Internal states, shadow registers, etc
416 QEMUTimer
*frame_timer
;
418 int attach_poll_counter
;
419 int astate
; // Current state in asynchronous schedule
420 int pstate
; // Current state in periodic schedule
421 USBPort ports
[NB_PORTS
];
422 USBPort
*companion_ports
[NB_PORTS
];
423 uint32_t usbsts_pending
;
424 EHCIQueueHead aqueues
;
425 EHCIQueueHead pqueues
;
427 uint32_t a_fetch_addr
; // which address to look at next
428 uint32_t p_fetch_addr
; // which address to look at next
433 uint64_t last_run_ns
;
436 #define SET_LAST_RUN_CLOCK(s) \
437 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
439 /* nifty macros from Arnon's EHCI version */
440 #define get_field(data, field) \
441 (((data) & field##_MASK) >> field##_SH)
443 #define set_field(data, newval, field) do { \
444 uint32_t val = *data; \
445 val &= ~ field##_MASK; \
446 val |= ((newval) << field##_SH) & field##_MASK; \
450 static const char *ehci_state_names
[] = {
451 [EST_INACTIVE
] = "INACTIVE",
452 [EST_ACTIVE
] = "ACTIVE",
453 [EST_EXECUTING
] = "EXECUTING",
454 [EST_SLEEPING
] = "SLEEPING",
455 [EST_WAITLISTHEAD
] = "WAITLISTHEAD",
456 [EST_FETCHENTRY
] = "FETCH ENTRY",
457 [EST_FETCHQH
] = "FETCH QH",
458 [EST_FETCHITD
] = "FETCH ITD",
459 [EST_ADVANCEQUEUE
] = "ADVANCEQUEUE",
460 [EST_FETCHQTD
] = "FETCH QTD",
461 [EST_EXECUTE
] = "EXECUTE",
462 [EST_WRITEBACK
] = "WRITEBACK",
463 [EST_HORIZONTALQH
] = "HORIZONTALQH",
466 static const char *ehci_mmio_names
[] = {
467 [CAPLENGTH
] = "CAPLENGTH",
468 [HCIVERSION
] = "HCIVERSION",
469 [HCSPARAMS
] = "HCSPARAMS",
470 [HCCPARAMS
] = "HCCPARAMS",
473 [USBINTR
] = "USBINTR",
474 [FRINDEX
] = "FRINDEX",
475 [PERIODICLISTBASE
] = "P-LIST BASE",
476 [ASYNCLISTADDR
] = "A-LIST ADDR",
477 [PORTSC_BEGIN
] = "PORTSC #0",
478 [PORTSC_BEGIN
+ 4] = "PORTSC #1",
479 [PORTSC_BEGIN
+ 8] = "PORTSC #2",
480 [PORTSC_BEGIN
+ 12] = "PORTSC #3",
481 [PORTSC_BEGIN
+ 16] = "PORTSC #4",
482 [PORTSC_BEGIN
+ 20] = "PORTSC #5",
483 [CONFIGFLAG
] = "CONFIGFLAG",
486 static const char *nr2str(const char **n
, size_t len
, uint32_t nr
)
488 if (nr
< len
&& n
[nr
] != NULL
) {
495 static const char *state2str(uint32_t state
)
497 return nr2str(ehci_state_names
, ARRAY_SIZE(ehci_state_names
), state
);
500 static const char *addr2str(target_phys_addr_t addr
)
502 return nr2str(ehci_mmio_names
, ARRAY_SIZE(ehci_mmio_names
), addr
);
505 static void ehci_trace_usbsts(uint32_t mask
, int state
)
508 if (mask
& USBSTS_INT
) {
509 trace_usb_ehci_usbsts("INT", state
);
511 if (mask
& USBSTS_ERRINT
) {
512 trace_usb_ehci_usbsts("ERRINT", state
);
514 if (mask
& USBSTS_PCD
) {
515 trace_usb_ehci_usbsts("PCD", state
);
517 if (mask
& USBSTS_FLR
) {
518 trace_usb_ehci_usbsts("FLR", state
);
520 if (mask
& USBSTS_HSE
) {
521 trace_usb_ehci_usbsts("HSE", state
);
523 if (mask
& USBSTS_IAA
) {
524 trace_usb_ehci_usbsts("IAA", state
);
528 if (mask
& USBSTS_HALT
) {
529 trace_usb_ehci_usbsts("HALT", state
);
531 if (mask
& USBSTS_REC
) {
532 trace_usb_ehci_usbsts("REC", state
);
534 if (mask
& USBSTS_PSS
) {
535 trace_usb_ehci_usbsts("PSS", state
);
537 if (mask
& USBSTS_ASS
) {
538 trace_usb_ehci_usbsts("ASS", state
);
542 static inline void ehci_set_usbsts(EHCIState
*s
, int mask
)
544 if ((s
->usbsts
& mask
) == mask
) {
547 ehci_trace_usbsts(mask
, 1);
551 static inline void ehci_clear_usbsts(EHCIState
*s
, int mask
)
553 if ((s
->usbsts
& mask
) == 0) {
556 ehci_trace_usbsts(mask
, 0);
560 static inline void ehci_set_interrupt(EHCIState
*s
, int intr
)
564 // TODO honour interrupt threshold requests
566 ehci_set_usbsts(s
, intr
);
568 if ((s
->usbsts
& USBINTR_MASK
) & s
->usbintr
) {
572 qemu_set_irq(s
->irq
, level
);
575 static inline void ehci_record_interrupt(EHCIState
*s
, int intr
)
577 s
->usbsts_pending
|= intr
;
580 static inline void ehci_commit_interrupt(EHCIState
*s
)
582 if (!s
->usbsts_pending
) {
585 ehci_set_interrupt(s
, s
->usbsts_pending
);
586 s
->usbsts_pending
= 0;
589 static void ehci_set_state(EHCIState
*s
, int async
, int state
)
592 trace_usb_ehci_state("async", state2str(state
));
595 trace_usb_ehci_state("periodic", state2str(state
));
600 static int ehci_get_state(EHCIState
*s
, int async
)
602 return async
? s
->astate
: s
->pstate
;
605 static void ehci_set_fetch_addr(EHCIState
*s
, int async
, uint32_t addr
)
608 s
->a_fetch_addr
= addr
;
610 s
->p_fetch_addr
= addr
;
614 static int ehci_get_fetch_addr(EHCIState
*s
, int async
)
616 return async
? s
->a_fetch_addr
: s
->p_fetch_addr
;
619 static void ehci_trace_qh(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqh
*qh
)
621 /* need three here due to argument count limits */
622 trace_usb_ehci_qh_ptrs(q
, addr
, qh
->next
,
623 qh
->current_qtd
, qh
->next_qtd
, qh
->altnext_qtd
);
624 trace_usb_ehci_qh_fields(addr
,
625 get_field(qh
->epchar
, QH_EPCHAR_RL
),
626 get_field(qh
->epchar
, QH_EPCHAR_MPLEN
),
627 get_field(qh
->epchar
, QH_EPCHAR_EPS
),
628 get_field(qh
->epchar
, QH_EPCHAR_EP
),
629 get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
));
630 trace_usb_ehci_qh_bits(addr
,
631 (bool)(qh
->epchar
& QH_EPCHAR_C
),
632 (bool)(qh
->epchar
& QH_EPCHAR_H
),
633 (bool)(qh
->epchar
& QH_EPCHAR_DTC
),
634 (bool)(qh
->epchar
& QH_EPCHAR_I
));
637 static void ehci_trace_qtd(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqtd
*qtd
)
639 /* need three here due to argument count limits */
640 trace_usb_ehci_qtd_ptrs(q
, addr
, qtd
->next
, qtd
->altnext
);
641 trace_usb_ehci_qtd_fields(addr
,
642 get_field(qtd
->token
, QTD_TOKEN_TBYTES
),
643 get_field(qtd
->token
, QTD_TOKEN_CPAGE
),
644 get_field(qtd
->token
, QTD_TOKEN_CERR
),
645 get_field(qtd
->token
, QTD_TOKEN_PID
));
646 trace_usb_ehci_qtd_bits(addr
,
647 (bool)(qtd
->token
& QTD_TOKEN_IOC
),
648 (bool)(qtd
->token
& QTD_TOKEN_ACTIVE
),
649 (bool)(qtd
->token
& QTD_TOKEN_HALT
),
650 (bool)(qtd
->token
& QTD_TOKEN_BABBLE
),
651 (bool)(qtd
->token
& QTD_TOKEN_XACTERR
));
654 static void ehci_trace_itd(EHCIState
*s
, target_phys_addr_t addr
, EHCIitd
*itd
)
656 trace_usb_ehci_itd(addr
, itd
->next
,
657 get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
),
658 get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
),
659 get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
),
660 get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
));
663 static void ehci_trace_sitd(EHCIState
*s
, target_phys_addr_t addr
,
666 trace_usb_ehci_sitd(addr
, sitd
->next
,
667 (bool)(sitd
->results
& SITD_RESULTS_ACTIVE
));
670 static inline bool ehci_enabled(EHCIState
*s
)
672 return s
->usbcmd
& USBCMD_RUNSTOP
;
675 static inline bool ehci_async_enabled(EHCIState
*s
)
677 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_ASE
);
680 static inline bool ehci_periodic_enabled(EHCIState
*s
)
682 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_PSE
);
685 /* packet management */
687 static EHCIPacket
*ehci_alloc_packet(EHCIQueue
*q
)
691 p
= g_new0(EHCIPacket
, 1);
693 usb_packet_init(&p
->packet
);
694 QTAILQ_INSERT_TAIL(&q
->packets
, p
, next
);
695 trace_usb_ehci_packet_action(p
->queue
, p
, "alloc");
699 static void ehci_free_packet(EHCIPacket
*p
)
701 trace_usb_ehci_packet_action(p
->queue
, p
, "free");
702 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
703 usb_cancel_packet(&p
->packet
);
705 QTAILQ_REMOVE(&p
->queue
->packets
, p
, next
);
706 usb_packet_cleanup(&p
->packet
);
710 /* queue management */
712 static EHCIQueue
*ehci_alloc_queue(EHCIState
*ehci
, uint32_t addr
, int async
)
714 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
717 q
= g_malloc0(sizeof(*q
));
721 QTAILQ_INIT(&q
->packets
);
722 QTAILQ_INSERT_HEAD(head
, q
, next
);
723 trace_usb_ehci_queue_action(q
, "alloc");
727 static void ehci_free_queue(EHCIQueue
*q
)
729 EHCIQueueHead
*head
= q
->async
? &q
->ehci
->aqueues
: &q
->ehci
->pqueues
;
732 trace_usb_ehci_queue_action(q
, "free");
733 while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
) {
736 QTAILQ_REMOVE(head
, q
, next
);
740 static EHCIQueue
*ehci_find_queue_by_qh(EHCIState
*ehci
, uint32_t addr
,
743 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
746 QTAILQ_FOREACH(q
, head
, next
) {
747 if (addr
== q
->qhaddr
) {
754 static void ehci_queues_rip_unused(EHCIState
*ehci
, int async
, int flush
)
756 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
759 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
762 q
->ts
= ehci
->last_run_ns
;
765 if (!flush
&& ehci
->last_run_ns
< q
->ts
+ 250000000) {
766 /* allow 0.25 sec idle */
773 static void ehci_queues_rip_device(EHCIState
*ehci
, USBDevice
*dev
, int async
)
775 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
778 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
786 static void ehci_queues_rip_all(EHCIState
*ehci
, int async
)
788 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
791 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
796 /* Attach or detach a device on root hub */
798 static void ehci_attach(USBPort
*port
)
800 EHCIState
*s
= port
->opaque
;
801 uint32_t *portsc
= &s
->portsc
[port
->index
];
803 trace_usb_ehci_port_attach(port
->index
, port
->dev
->product_desc
);
805 if (*portsc
& PORTSC_POWNER
) {
806 USBPort
*companion
= s
->companion_ports
[port
->index
];
807 companion
->dev
= port
->dev
;
808 companion
->ops
->attach(companion
);
812 *portsc
|= PORTSC_CONNECT
;
813 *portsc
|= PORTSC_CSC
;
815 ehci_set_interrupt(s
, USBSTS_PCD
);
818 static void ehci_detach(USBPort
*port
)
820 EHCIState
*s
= port
->opaque
;
821 uint32_t *portsc
= &s
->portsc
[port
->index
];
823 trace_usb_ehci_port_detach(port
->index
);
825 if (*portsc
& PORTSC_POWNER
) {
826 USBPort
*companion
= s
->companion_ports
[port
->index
];
827 companion
->ops
->detach(companion
);
828 companion
->dev
= NULL
;
830 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
831 * the port ownership is returned immediately to the EHCI controller."
833 *portsc
&= ~PORTSC_POWNER
;
837 ehci_queues_rip_device(s
, port
->dev
, 0);
838 ehci_queues_rip_device(s
, port
->dev
, 1);
840 *portsc
&= ~(PORTSC_CONNECT
|PORTSC_PED
);
841 *portsc
|= PORTSC_CSC
;
843 ehci_set_interrupt(s
, USBSTS_PCD
);
846 static void ehci_child_detach(USBPort
*port
, USBDevice
*child
)
848 EHCIState
*s
= port
->opaque
;
849 uint32_t portsc
= s
->portsc
[port
->index
];
851 if (portsc
& PORTSC_POWNER
) {
852 USBPort
*companion
= s
->companion_ports
[port
->index
];
853 companion
->ops
->child_detach(companion
, child
);
857 ehci_queues_rip_device(s
, child
, 0);
858 ehci_queues_rip_device(s
, child
, 1);
861 static void ehci_wakeup(USBPort
*port
)
863 EHCIState
*s
= port
->opaque
;
864 uint32_t portsc
= s
->portsc
[port
->index
];
866 if (portsc
& PORTSC_POWNER
) {
867 USBPort
*companion
= s
->companion_ports
[port
->index
];
868 if (companion
->ops
->wakeup
) {
869 companion
->ops
->wakeup(companion
);
871 qemu_bh_schedule(s
->async_bh
);
876 static int ehci_register_companion(USBBus
*bus
, USBPort
*ports
[],
877 uint32_t portcount
, uint32_t firstport
)
879 EHCIState
*s
= container_of(bus
, EHCIState
, bus
);
882 if (firstport
+ portcount
> NB_PORTS
) {
883 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "firstport",
884 "firstport on masterbus");
885 error_printf_unless_qmp(
886 "firstport value of %u makes companion take ports %u - %u, which "
887 "is outside of the valid range of 0 - %u\n", firstport
, firstport
,
888 firstport
+ portcount
- 1, NB_PORTS
- 1);
892 for (i
= 0; i
< portcount
; i
++) {
893 if (s
->companion_ports
[firstport
+ i
]) {
894 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "masterbus",
896 error_printf_unless_qmp(
897 "port %u on masterbus %s already has a companion assigned\n",
898 firstport
+ i
, bus
->qbus
.name
);
903 for (i
= 0; i
< portcount
; i
++) {
904 s
->companion_ports
[firstport
+ i
] = ports
[i
];
905 s
->ports
[firstport
+ i
].speedmask
|=
906 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
;
907 /* Ensure devs attached before the initial reset go to the companion */
908 s
->portsc
[firstport
+ i
] = PORTSC_POWNER
;
911 s
->companion_count
++;
912 s
->mmio
[0x05] = (s
->companion_count
<< 4) | portcount
;
917 static USBDevice
*ehci_find_device(EHCIState
*ehci
, uint8_t addr
)
923 for (i
= 0; i
< NB_PORTS
; i
++) {
924 port
= &ehci
->ports
[i
];
925 if (!(ehci
->portsc
[i
] & PORTSC_PED
)) {
926 DPRINTF("Port %d not enabled\n", i
);
929 dev
= usb_find_device(port
, addr
);
937 /* 4.1 host controller initialization */
938 static void ehci_reset(void *opaque
)
940 EHCIState
*s
= opaque
;
942 USBDevice
*devs
[NB_PORTS
];
944 trace_usb_ehci_reset();
947 * Do the detach before touching portsc, so that it correctly gets send to
948 * us or to our companion based on PORTSC_POWNER before the reset.
950 for(i
= 0; i
< NB_PORTS
; i
++) {
951 devs
[i
] = s
->ports
[i
].dev
;
952 if (devs
[i
] && devs
[i
]->attached
) {
953 usb_detach(&s
->ports
[i
]);
957 memset(&s
->mmio
[OPREGBASE
], 0x00, MMIO_SIZE
- OPREGBASE
);
959 s
->usbcmd
= NB_MAXINTRATE
<< USBCMD_ITC_SH
;
960 s
->usbsts
= USBSTS_HALT
;
962 s
->astate
= EST_INACTIVE
;
963 s
->pstate
= EST_INACTIVE
;
964 s
->attach_poll_counter
= 0;
966 for(i
= 0; i
< NB_PORTS
; i
++) {
967 if (s
->companion_ports
[i
]) {
968 s
->portsc
[i
] = PORTSC_POWNER
| PORTSC_PPOWER
;
970 s
->portsc
[i
] = PORTSC_PPOWER
;
972 if (devs
[i
] && devs
[i
]->attached
) {
973 usb_attach(&s
->ports
[i
]);
974 usb_device_reset(devs
[i
]);
977 ehci_queues_rip_all(s
, 0);
978 ehci_queues_rip_all(s
, 1);
979 qemu_del_timer(s
->frame_timer
);
980 qemu_bh_cancel(s
->async_bh
);
983 static uint32_t ehci_mem_readb(void *ptr
, target_phys_addr_t addr
)
993 static uint32_t ehci_mem_readw(void *ptr
, target_phys_addr_t addr
)
998 val
= s
->mmio
[addr
] | (s
->mmio
[addr
+1] << 8);
1003 static uint32_t ehci_mem_readl(void *ptr
, target_phys_addr_t addr
)
1008 val
= s
->mmio
[addr
] | (s
->mmio
[addr
+1] << 8) |
1009 (s
->mmio
[addr
+2] << 16) | (s
->mmio
[addr
+3] << 24);
1011 trace_usb_ehci_mmio_readl(addr
, addr2str(addr
), val
);
1015 static void ehci_mem_writeb(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1017 fprintf(stderr
, "EHCI doesn't handle byte writes to MMIO\n");
1021 static void ehci_mem_writew(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1023 fprintf(stderr
, "EHCI doesn't handle 16-bit writes to MMIO\n");
1027 static void handle_port_owner_write(EHCIState
*s
, int port
, uint32_t owner
)
1029 USBDevice
*dev
= s
->ports
[port
].dev
;
1030 uint32_t *portsc
= &s
->portsc
[port
];
1033 if (s
->companion_ports
[port
] == NULL
)
1036 owner
= owner
& PORTSC_POWNER
;
1037 orig
= *portsc
& PORTSC_POWNER
;
1039 if (!(owner
^ orig
)) {
1043 if (dev
&& dev
->attached
) {
1044 usb_detach(&s
->ports
[port
]);
1047 *portsc
&= ~PORTSC_POWNER
;
1050 if (dev
&& dev
->attached
) {
1051 usb_attach(&s
->ports
[port
]);
1055 static void handle_port_status_write(EHCIState
*s
, int port
, uint32_t val
)
1057 uint32_t *portsc
= &s
->portsc
[port
];
1058 USBDevice
*dev
= s
->ports
[port
].dev
;
1060 /* Clear rwc bits */
1061 *portsc
&= ~(val
& PORTSC_RWC_MASK
);
1062 /* The guest may clear, but not set the PED bit */
1063 *portsc
&= val
| ~PORTSC_PED
;
1064 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1065 handle_port_owner_write(s
, port
, val
);
1066 /* And finally apply RO_MASK */
1067 val
&= PORTSC_RO_MASK
;
1069 if ((val
& PORTSC_PRESET
) && !(*portsc
& PORTSC_PRESET
)) {
1070 trace_usb_ehci_port_reset(port
, 1);
1073 if (!(val
& PORTSC_PRESET
) &&(*portsc
& PORTSC_PRESET
)) {
1074 trace_usb_ehci_port_reset(port
, 0);
1075 if (dev
&& dev
->attached
) {
1076 usb_port_reset(&s
->ports
[port
]);
1077 *portsc
&= ~PORTSC_CSC
;
1081 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1082 * to SW that this port has a high speed device attached
1084 if (dev
&& dev
->attached
&& (dev
->speedmask
& USB_SPEED_MASK_HIGH
)) {
1089 *portsc
&= ~PORTSC_RO_MASK
;
1093 static void ehci_mem_writel(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1096 uint32_t *mmio
= (uint32_t *)(&s
->mmio
[addr
]);
1097 uint32_t old
= *mmio
;
1100 trace_usb_ehci_mmio_writel(addr
, addr2str(addr
), val
);
1102 /* Only aligned reads are allowed on OHCI */
1104 fprintf(stderr
, "usb-ehci: Mis-aligned write to addr 0x"
1105 TARGET_FMT_plx
"\n", addr
);
1109 if (addr
>= PORTSC
&& addr
< PORTSC
+ 4 * NB_PORTS
) {
1110 handle_port_status_write(s
, (addr
-PORTSC
)/4, val
);
1111 trace_usb_ehci_mmio_change(addr
, addr2str(addr
), *mmio
, old
);
1115 if (addr
< OPREGBASE
) {
1116 fprintf(stderr
, "usb-ehci: write attempt to read-only register"
1117 TARGET_FMT_plx
"\n", addr
);
1122 /* Do any register specific pre-write processing here. */
1125 if (val
& USBCMD_HCRESET
) {
1131 if ((val
& USBCMD_RUNSTOP
) && !(s
->usbcmd
& USBCMD_RUNSTOP
)) {
1132 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
1133 SET_LAST_RUN_CLOCK(s
);
1134 ehci_clear_usbsts(s
, USBSTS_HALT
);
1137 if (!(val
& USBCMD_RUNSTOP
) && (s
->usbcmd
& USBCMD_RUNSTOP
)) {
1138 qemu_del_timer(s
->frame_timer
);
1139 qemu_bh_cancel(s
->async_bh
);
1140 ehci_queues_rip_all(s
, 0);
1141 ehci_queues_rip_all(s
, 1);
1142 ehci_set_usbsts(s
, USBSTS_HALT
);
1146 /* not supporting dynamic frame list size at the moment */
1147 if ((val
& USBCMD_FLS
) && !(s
->usbcmd
& USBCMD_FLS
)) {
1148 fprintf(stderr
, "attempt to set frame list size -- value %d\n",
1155 val
&= USBSTS_RO_MASK
; // bits 6 through 31 are RO
1156 ehci_clear_usbsts(s
, val
); // bits 0 through 5 are R/WC
1158 ehci_set_interrupt(s
, 0);
1162 val
&= USBINTR_MASK
;
1166 val
&= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1172 for(i
= 0; i
< NB_PORTS
; i
++)
1173 handle_port_owner_write(s
, i
, 0);
1177 case PERIODICLISTBASE
:
1178 if (ehci_periodic_enabled(s
)) {
1180 "ehci: PERIODIC list base register set while periodic schedule\n"
1181 " is enabled and HC is enabled\n");
1186 if (ehci_async_enabled(s
)) {
1188 "ehci: ASYNC list address register set while async schedule\n"
1189 " is enabled and HC is enabled\n");
1195 trace_usb_ehci_mmio_change(addr
, addr2str(addr
), *mmio
, old
);
1199 // TODO : Put in common header file, duplication from usb-ohci.c
1201 /* Get an array of dwords from main memory */
1202 static inline int get_dwords(EHCIState
*ehci
, uint32_t addr
,
1203 uint32_t *buf
, int num
)
1207 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1208 pci_dma_read(&ehci
->dev
, addr
, buf
, sizeof(*buf
));
1209 *buf
= le32_to_cpu(*buf
);
1215 /* Put an array of dwords in to main memory */
1216 static inline int put_dwords(EHCIState
*ehci
, uint32_t addr
,
1217 uint32_t *buf
, int num
)
1221 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1222 uint32_t tmp
= cpu_to_le32(*buf
);
1223 pci_dma_write(&ehci
->dev
, addr
, &tmp
, sizeof(tmp
));
1231 static int ehci_qh_do_overlay(EHCIQueue
*q
)
1233 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1241 assert(p
->qtdaddr
== q
->qtdaddr
);
1243 // remember values in fields to preserve in qh after overlay
1245 dtoggle
= q
->qh
.token
& QTD_TOKEN_DTOGGLE
;
1246 ping
= q
->qh
.token
& QTD_TOKEN_PING
;
1248 q
->qh
.current_qtd
= p
->qtdaddr
;
1249 q
->qh
.next_qtd
= p
->qtd
.next
;
1250 q
->qh
.altnext_qtd
= p
->qtd
.altnext
;
1251 q
->qh
.token
= p
->qtd
.token
;
1254 eps
= get_field(q
->qh
.epchar
, QH_EPCHAR_EPS
);
1255 if (eps
== EHCI_QH_EPS_HIGH
) {
1256 q
->qh
.token
&= ~QTD_TOKEN_PING
;
1257 q
->qh
.token
|= ping
;
1260 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1261 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1263 for (i
= 0; i
< 5; i
++) {
1264 q
->qh
.bufptr
[i
] = p
->qtd
.bufptr
[i
];
1267 if (!(q
->qh
.epchar
& QH_EPCHAR_DTC
)) {
1268 // preserve QH DT bit
1269 q
->qh
.token
&= ~QTD_TOKEN_DTOGGLE
;
1270 q
->qh
.token
|= dtoggle
;
1273 q
->qh
.bufptr
[1] &= ~BUFPTR_CPROGMASK_MASK
;
1274 q
->qh
.bufptr
[2] &= ~BUFPTR_FRAMETAG_MASK
;
1276 put_dwords(q
->ehci
, NLPTR_GET(q
->qhaddr
), (uint32_t *) &q
->qh
,
1277 sizeof(EHCIqh
) >> 2);
1282 static int ehci_init_transfer(EHCIPacket
*p
)
1284 uint32_t cpage
, offset
, bytes
, plen
;
1287 cpage
= get_field(p
->qtd
.token
, QTD_TOKEN_CPAGE
);
1288 bytes
= get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
);
1289 offset
= p
->qtd
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1290 pci_dma_sglist_init(&p
->sgl
, &p
->queue
->ehci
->dev
, 5);
1294 fprintf(stderr
, "cpage out of range (%d)\n", cpage
);
1295 return USB_RET_PROCERR
;
1298 page
= p
->qtd
.bufptr
[cpage
] & QTD_BUFPTR_MASK
;
1301 if (plen
> 4096 - offset
) {
1302 plen
= 4096 - offset
;
1307 qemu_sglist_add(&p
->sgl
, page
, plen
);
1313 static void ehci_finish_transfer(EHCIQueue
*q
, int status
)
1315 uint32_t cpage
, offset
;
1318 /* update cpage & offset */
1319 cpage
= get_field(q
->qh
.token
, QTD_TOKEN_CPAGE
);
1320 offset
= q
->qh
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1323 cpage
+= offset
>> QTD_BUFPTR_SH
;
1324 offset
&= ~QTD_BUFPTR_MASK
;
1326 set_field(&q
->qh
.token
, cpage
, QTD_TOKEN_CPAGE
);
1327 q
->qh
.bufptr
[0] &= QTD_BUFPTR_MASK
;
1328 q
->qh
.bufptr
[0] |= offset
;
1332 static void ehci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
1335 EHCIState
*s
= port
->opaque
;
1336 uint32_t portsc
= s
->portsc
[port
->index
];
1338 if (portsc
& PORTSC_POWNER
) {
1339 USBPort
*companion
= s
->companion_ports
[port
->index
];
1340 companion
->ops
->complete(companion
, packet
);
1344 p
= container_of(packet
, EHCIPacket
, packet
);
1345 trace_usb_ehci_packet_action(p
->queue
, p
, "wakeup");
1346 assert(p
->async
== EHCI_ASYNC_INFLIGHT
);
1347 p
->async
= EHCI_ASYNC_FINISHED
;
1348 p
->usb_status
= packet
->result
;
1350 if (p
->queue
->async
) {
1351 qemu_bh_schedule(p
->queue
->ehci
->async_bh
);
1355 static void ehci_execute_complete(EHCIQueue
*q
)
1357 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1360 assert(p
->qtdaddr
== q
->qtdaddr
);
1361 assert(p
->async
!= EHCI_ASYNC_INFLIGHT
);
1362 p
->async
= EHCI_ASYNC_NONE
;
1364 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1365 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->usb_status
);
1367 if (p
->usb_status
< 0) {
1368 switch (p
->usb_status
) {
1369 case USB_RET_IOERROR
:
1371 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_XACTERR
);
1372 set_field(&q
->qh
.token
, 0, QTD_TOKEN_CERR
);
1373 ehci_record_interrupt(q
->ehci
, USBSTS_ERRINT
);
1376 q
->qh
.token
|= QTD_TOKEN_HALT
;
1377 ehci_record_interrupt(q
->ehci
, USBSTS_ERRINT
);
1380 set_field(&q
->qh
.altnext_qtd
, 0, QH_ALTNEXT_NAKCNT
);
1381 return; /* We're not done yet with this transaction */
1382 case USB_RET_BABBLE
:
1383 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1384 ehci_record_interrupt(q
->ehci
, USBSTS_ERRINT
);
1387 /* should not be triggerable */
1388 fprintf(stderr
, "USB invalid response %d\n", p
->usb_status
);
1392 } else if ((p
->usb_status
> p
->tbytes
) && (p
->pid
== USB_TOKEN_IN
)) {
1393 p
->usb_status
= USB_RET_BABBLE
;
1394 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1395 ehci_record_interrupt(q
->ehci
, USBSTS_ERRINT
);
1397 // TODO check 4.12 for splits
1399 if (p
->tbytes
&& p
->pid
== USB_TOKEN_IN
) {
1400 p
->tbytes
-= p
->usb_status
;
1405 DPRINTF("updating tbytes to %d\n", p
->tbytes
);
1406 set_field(&q
->qh
.token
, p
->tbytes
, QTD_TOKEN_TBYTES
);
1408 ehci_finish_transfer(q
, p
->usb_status
);
1409 qemu_sglist_destroy(&p
->sgl
);
1410 usb_packet_unmap(&p
->packet
);
1412 q
->qh
.token
^= QTD_TOKEN_DTOGGLE
;
1413 q
->qh
.token
&= ~QTD_TOKEN_ACTIVE
;
1415 if (q
->qh
.token
& QTD_TOKEN_IOC
) {
1416 ehci_record_interrupt(q
->ehci
, USBSTS_INT
);
1422 static int ehci_execute(EHCIPacket
*p
, const char *action
)
1428 if (!(p
->qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1429 fprintf(stderr
, "Attempting to execute inactive qtd\n");
1430 return USB_RET_PROCERR
;
1433 p
->tbytes
= (p
->qtd
.token
& QTD_TOKEN_TBYTES_MASK
) >> QTD_TOKEN_TBYTES_SH
;
1434 if (p
->tbytes
> BUFF_SIZE
) {
1435 fprintf(stderr
, "Request for more bytes than allowed\n");
1436 return USB_RET_PROCERR
;
1439 p
->pid
= (p
->qtd
.token
& QTD_TOKEN_PID_MASK
) >> QTD_TOKEN_PID_SH
;
1442 p
->pid
= USB_TOKEN_OUT
;
1445 p
->pid
= USB_TOKEN_IN
;
1448 p
->pid
= USB_TOKEN_SETUP
;
1451 fprintf(stderr
, "bad token\n");
1455 if (ehci_init_transfer(p
) != 0) {
1456 return USB_RET_PROCERR
;
1459 endp
= get_field(p
->queue
->qh
.epchar
, QH_EPCHAR_EP
);
1460 ep
= usb_ep_get(p
->queue
->dev
, p
->pid
, endp
);
1462 usb_packet_setup(&p
->packet
, p
->pid
, ep
);
1463 usb_packet_map(&p
->packet
, &p
->sgl
);
1465 trace_usb_ehci_packet_action(p
->queue
, p
, action
);
1466 ret
= usb_handle_packet(p
->queue
->dev
, &p
->packet
);
1467 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1468 "(total %d) endp %x ret %d\n",
1469 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->pid
,
1470 q
->packet
.iov
.size
, q
->tbytes
, endp
, ret
);
1472 if (ret
> BUFF_SIZE
) {
1473 fprintf(stderr
, "ret from usb_handle_packet > BUFF_SIZE\n");
1474 return USB_RET_PROCERR
;
1483 static int ehci_process_itd(EHCIState
*ehci
,
1489 uint32_t i
, len
, pid
, dir
, devaddr
, endp
;
1490 uint32_t pg
, off
, ptr1
, ptr2
, max
, mult
;
1492 dir
=(itd
->bufptr
[1] & ITD_BUFPTR_DIRECTION
);
1493 devaddr
= get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
);
1494 endp
= get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
);
1495 max
= get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
);
1496 mult
= get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
);
1498 for(i
= 0; i
< 8; i
++) {
1499 if (itd
->transact
[i
] & ITD_XACT_ACTIVE
) {
1500 pg
= get_field(itd
->transact
[i
], ITD_XACT_PGSEL
);
1501 off
= itd
->transact
[i
] & ITD_XACT_OFFSET_MASK
;
1502 ptr1
= (itd
->bufptr
[pg
] & ITD_BUFPTR_MASK
);
1503 ptr2
= (itd
->bufptr
[pg
+1] & ITD_BUFPTR_MASK
);
1504 len
= get_field(itd
->transact
[i
], ITD_XACT_LENGTH
);
1506 if (len
> max
* mult
) {
1510 if (len
> BUFF_SIZE
) {
1511 return USB_RET_PROCERR
;
1514 pci_dma_sglist_init(&ehci
->isgl
, &ehci
->dev
, 2);
1515 if (off
+ len
> 4096) {
1516 /* transfer crosses page border */
1517 uint32_t len2
= off
+ len
- 4096;
1518 uint32_t len1
= len
- len2
;
1519 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len1
);
1520 qemu_sglist_add(&ehci
->isgl
, ptr2
, len2
);
1522 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len
);
1525 pid
= dir
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1527 dev
= ehci_find_device(ehci
, devaddr
);
1528 ep
= usb_ep_get(dev
, pid
, endp
);
1529 if (ep
->type
== USB_ENDPOINT_XFER_ISOC
) {
1530 usb_packet_setup(&ehci
->ipacket
, pid
, ep
);
1531 usb_packet_map(&ehci
->ipacket
, &ehci
->isgl
);
1532 ret
= usb_handle_packet(dev
, &ehci
->ipacket
);
1533 assert(ret
!= USB_RET_ASYNC
);
1534 usb_packet_unmap(&ehci
->ipacket
);
1536 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1539 qemu_sglist_destroy(&ehci
->isgl
);
1544 fprintf(stderr
, "Unexpected iso usb result: %d\n", ret
);
1546 case USB_RET_IOERROR
:
1548 /* 3.3.2: XACTERR is only allowed on IN transactions */
1550 itd
->transact
[i
] |= ITD_XACT_XACTERR
;
1551 ehci_record_interrupt(ehci
, USBSTS_ERRINT
);
1554 case USB_RET_BABBLE
:
1555 itd
->transact
[i
] |= ITD_XACT_BABBLE
;
1556 ehci_record_interrupt(ehci
, USBSTS_ERRINT
);
1559 /* no data for us, so do a zero-length transfer */
1567 set_field(&itd
->transact
[i
], len
- ret
, ITD_XACT_LENGTH
);
1570 set_field(&itd
->transact
[i
], ret
, ITD_XACT_LENGTH
);
1573 if (itd
->transact
[i
] & ITD_XACT_IOC
) {
1574 ehci_record_interrupt(ehci
, USBSTS_INT
);
1576 itd
->transact
[i
] &= ~ITD_XACT_ACTIVE
;
1584 * Write the qh back to guest physical memory. This step isn't
1585 * in the EHCI spec but we need to do it since we don't share
1586 * physical memory with our guest VM.
1588 * The first three dwords are read-only for the EHCI, so skip them
1589 * when writing back the qh.
1591 static void ehci_flush_qh(EHCIQueue
*q
)
1593 uint32_t *qh
= (uint32_t *) &q
->qh
;
1594 uint32_t dwords
= sizeof(EHCIqh
) >> 2;
1595 uint32_t addr
= NLPTR_GET(q
->qhaddr
);
1597 put_dwords(q
->ehci
, addr
+ 3 * sizeof(uint32_t), qh
+ 3, dwords
- 3);
1600 /* This state is the entry point for asynchronous schedule
1601 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1603 static int ehci_state_waitlisthead(EHCIState
*ehci
, int async
)
1608 uint32_t entry
= ehci
->asynclistaddr
;
1610 /* set reclamation flag at start event (4.8.6) */
1612 ehci_set_usbsts(ehci
, USBSTS_REC
);
1615 ehci_queues_rip_unused(ehci
, async
, 0);
1617 /* Find the head of the list (4.9.1.1) */
1618 for(i
= 0; i
< MAX_QH
; i
++) {
1619 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &qh
,
1620 sizeof(EHCIqh
) >> 2);
1621 ehci_trace_qh(NULL
, NLPTR_GET(entry
), &qh
);
1623 if (qh
.epchar
& QH_EPCHAR_H
) {
1625 entry
|= (NLPTR_TYPE_QH
<< 1);
1628 ehci_set_fetch_addr(ehci
, async
, entry
);
1629 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1635 if (entry
== ehci
->asynclistaddr
) {
1640 /* no head found for list. */
1642 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1649 /* This state is the entry point for periodic schedule processing as
1650 * well as being a continuation state for async processing.
1652 static int ehci_state_fetchentry(EHCIState
*ehci
, int async
)
1655 uint32_t entry
= ehci_get_fetch_addr(ehci
, async
);
1657 if (NLPTR_TBIT(entry
)) {
1658 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1662 /* section 4.8, only QH in async schedule */
1663 if (async
&& (NLPTR_TYPE_GET(entry
) != NLPTR_TYPE_QH
)) {
1664 fprintf(stderr
, "non queue head request in async schedule\n");
1668 switch (NLPTR_TYPE_GET(entry
)) {
1670 ehci_set_state(ehci
, async
, EST_FETCHQH
);
1674 case NLPTR_TYPE_ITD
:
1675 ehci_set_state(ehci
, async
, EST_FETCHITD
);
1679 case NLPTR_TYPE_STITD
:
1680 ehci_set_state(ehci
, async
, EST_FETCHSITD
);
1685 /* TODO: handle FSTN type */
1686 fprintf(stderr
, "FETCHENTRY: entry at %X is of type %d "
1687 "which is not supported yet\n", entry
, NLPTR_TYPE_GET(entry
));
1695 static EHCIQueue
*ehci_state_fetchqh(EHCIState
*ehci
, int async
)
1698 uint32_t entry
, devaddr
;
1701 entry
= ehci_get_fetch_addr(ehci
, async
);
1702 q
= ehci_find_queue_by_qh(ehci
, entry
, async
);
1704 q
= ehci_alloc_queue(ehci
, entry
, async
);
1706 p
= QTAILQ_FIRST(&q
->packets
);
1710 /* we are going in circles -- stop processing */
1711 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1716 get_dwords(ehci
, NLPTR_GET(q
->qhaddr
),
1717 (uint32_t *) &q
->qh
, sizeof(EHCIqh
) >> 2);
1718 ehci_trace_qh(q
, NLPTR_GET(q
->qhaddr
), &q
->qh
);
1720 devaddr
= get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
);
1721 if (q
->dev
!= NULL
&& q
->dev
->addr
!= devaddr
) {
1722 if (!QTAILQ_EMPTY(&q
->packets
)) {
1723 /* should not happen (guest bug) */
1724 while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
) {
1725 ehci_free_packet(p
);
1730 if (q
->dev
== NULL
) {
1731 q
->dev
= ehci_find_device(q
->ehci
, devaddr
);
1734 if (p
&& p
->async
== EHCI_ASYNC_INFLIGHT
) {
1735 /* I/O still in progress -- skip queue */
1736 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1739 if (p
&& p
->async
== EHCI_ASYNC_FINISHED
) {
1740 /* I/O finished -- continue processing queue */
1741 trace_usb_ehci_packet_action(p
->queue
, p
, "complete");
1742 ehci_set_state(ehci
, async
, EST_EXECUTING
);
1746 if (async
&& (q
->qh
.epchar
& QH_EPCHAR_H
)) {
1748 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1749 if (ehci
->usbsts
& USBSTS_REC
) {
1750 ehci_clear_usbsts(ehci
, USBSTS_REC
);
1752 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1753 " - done processing\n", q
->qhaddr
);
1754 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1761 if (q
->qhaddr
!= q
->qh
.next
) {
1762 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1764 q
->qh
.epchar
& QH_EPCHAR_H
,
1765 q
->qh
.token
& QTD_TOKEN_HALT
,
1766 q
->qh
.token
& QTD_TOKEN_ACTIVE
,
1771 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1772 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1774 } else if ((q
->qh
.token
& QTD_TOKEN_ACTIVE
) &&
1775 (NLPTR_TBIT(q
->qh
.current_qtd
) == 0)) {
1776 q
->qtdaddr
= q
->qh
.current_qtd
;
1777 ehci_set_state(ehci
, async
, EST_FETCHQTD
);
1780 /* EHCI spec version 1.0 Section 4.10.2 */
1781 ehci_set_state(ehci
, async
, EST_ADVANCEQUEUE
);
1788 static int ehci_state_fetchitd(EHCIState
*ehci
, int async
)
1794 entry
= ehci_get_fetch_addr(ehci
, async
);
1796 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1797 sizeof(EHCIitd
) >> 2);
1798 ehci_trace_itd(ehci
, entry
, &itd
);
1800 if (ehci_process_itd(ehci
, &itd
) != 0) {
1804 put_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1805 sizeof(EHCIitd
) >> 2);
1806 ehci_set_fetch_addr(ehci
, async
, itd
.next
);
1807 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1812 static int ehci_state_fetchsitd(EHCIState
*ehci
, int async
)
1818 entry
= ehci_get_fetch_addr(ehci
, async
);
1820 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *)&sitd
,
1821 sizeof(EHCIsitd
) >> 2);
1822 ehci_trace_sitd(ehci
, entry
, &sitd
);
1824 if (!(sitd
.results
& SITD_RESULTS_ACTIVE
)) {
1825 /* siTD is not active, nothing to do */;
1827 /* TODO: split transfers are not implemented */
1828 fprintf(stderr
, "WARNING: Skipping active siTD\n");
1831 ehci_set_fetch_addr(ehci
, async
, sitd
.next
);
1832 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1836 /* Section 4.10.2 - paragraph 3 */
1837 static int ehci_state_advqueue(EHCIQueue
*q
)
1840 /* TO-DO: 4.10.2 - paragraph 2
1841 * if I-bit is set to 1 and QH is not active
1842 * go to horizontal QH
1845 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1851 * want data and alt-next qTD is valid
1853 if (((q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) != 0) &&
1854 (NLPTR_TBIT(q
->qh
.altnext_qtd
) == 0)) {
1855 q
->qtdaddr
= q
->qh
.altnext_qtd
;
1856 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1861 } else if (NLPTR_TBIT(q
->qh
.next_qtd
) == 0) {
1862 q
->qtdaddr
= q
->qh
.next_qtd
;
1863 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1866 * no valid qTD, try next QH
1869 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1875 /* Section 4.10.2 - paragraph 4 */
1876 static int ehci_state_fetchqtd(EHCIQueue
*q
)
1882 get_dwords(q
->ehci
, NLPTR_GET(q
->qtdaddr
), (uint32_t *) &qtd
,
1883 sizeof(EHCIqtd
) >> 2);
1884 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), &qtd
);
1886 p
= QTAILQ_FIRST(&q
->packets
);
1887 while (p
!= NULL
&& p
->qtdaddr
!= q
->qtdaddr
) {
1888 /* should not happen (guest bug) */
1889 ehci_free_packet(p
);
1890 p
= QTAILQ_FIRST(&q
->packets
);
1893 ehci_qh_do_overlay(q
);
1895 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
1896 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1898 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
1901 } else if (qtd
.token
& QTD_TOKEN_ACTIVE
) {
1902 p
= ehci_alloc_packet(q
);
1903 p
->qtdaddr
= q
->qtdaddr
;
1905 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
1908 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1915 static int ehci_state_horizqh(EHCIQueue
*q
)
1919 if (ehci_get_fetch_addr(q
->ehci
, q
->async
) != q
->qh
.next
) {
1920 ehci_set_fetch_addr(q
->ehci
, q
->async
, q
->qh
.next
);
1921 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHENTRY
);
1924 ehci_set_state(q
->ehci
, q
->async
, EST_ACTIVE
);
1930 static void ehci_fill_queue(EHCIPacket
*p
)
1932 EHCIQueue
*q
= p
->queue
;
1933 EHCIqtd qtd
= p
->qtd
;
1937 if (NLPTR_TBIT(qtd
.altnext
) == 0) {
1940 if (NLPTR_TBIT(qtd
.next
) != 0) {
1944 get_dwords(q
->ehci
, NLPTR_GET(qtdaddr
),
1945 (uint32_t *) &qtd
, sizeof(EHCIqtd
) >> 2);
1946 ehci_trace_qtd(q
, NLPTR_GET(qtdaddr
), &qtd
);
1947 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1950 p
= ehci_alloc_packet(q
);
1951 p
->qtdaddr
= qtdaddr
;
1953 p
->usb_status
= ehci_execute(p
, "queue");
1954 assert(p
->usb_status
= USB_RET_ASYNC
);
1955 p
->async
= EHCI_ASYNC_INFLIGHT
;
1959 static int ehci_state_execute(EHCIQueue
*q
)
1961 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1965 assert(p
->qtdaddr
== q
->qtdaddr
);
1967 if (ehci_qh_do_overlay(q
) != 0) {
1971 // TODO verify enough time remains in the uframe as in 4.4.1.1
1972 // TODO write back ptr to async list when done or out of time
1973 // TODO Windows does not seem to ever set the MULT field
1976 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
1978 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1985 ehci_set_usbsts(q
->ehci
, USBSTS_REC
);
1988 p
->usb_status
= ehci_execute(p
, "process");
1989 if (p
->usb_status
== USB_RET_PROCERR
) {
1993 if (p
->usb_status
== USB_RET_ASYNC
) {
1995 trace_usb_ehci_packet_action(p
->queue
, p
, "async");
1996 p
->async
= EHCI_ASYNC_INFLIGHT
;
1997 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2003 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2010 static int ehci_state_executing(EHCIQueue
*q
)
2012 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2016 assert(p
->qtdaddr
== q
->qtdaddr
);
2018 ehci_execute_complete(q
);
2019 if (p
->usb_status
== USB_RET_ASYNC
) {
2022 if (p
->usb_status
== USB_RET_PROCERR
) {
2029 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
2031 set_field(&q
->qh
.epcap
, transactCtr
, QH_EPCAP_MULT
);
2032 // 4.10.3, bottom of page 82, should exit this state when transaction
2033 // counter decrements to 0
2037 if (p
->usb_status
== USB_RET_NAK
) {
2038 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2040 ehci_set_state(q
->ehci
, q
->async
, EST_WRITEBACK
);
2051 static int ehci_state_writeback(EHCIQueue
*q
)
2053 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2056 /* Write back the QTD from the QH area */
2058 assert(p
->qtdaddr
== q
->qtdaddr
);
2060 ehci_trace_qtd(q
, NLPTR_GET(p
->qtdaddr
), (EHCIqtd
*) &q
->qh
.next_qtd
);
2061 put_dwords(q
->ehci
, NLPTR_GET(p
->qtdaddr
), (uint32_t *) &q
->qh
.next_qtd
,
2062 sizeof(EHCIqtd
) >> 2);
2063 ehci_free_packet(p
);
2066 * EHCI specs say go horizontal here.
2068 * We can also advance the queue here for performance reasons. We
2069 * need to take care to only take that shortcut in case we've
2070 * processed the qtd just written back without errors, i.e. halt
2073 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
2074 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2077 ehci_set_state(q
->ehci
, q
->async
, EST_ADVANCEQUEUE
);
2084 * This is the state machine that is common to both async and periodic
2087 static void ehci_advance_state(EHCIState
*ehci
, int async
)
2089 EHCIQueue
*q
= NULL
;
2093 switch(ehci_get_state(ehci
, async
)) {
2094 case EST_WAITLISTHEAD
:
2095 again
= ehci_state_waitlisthead(ehci
, async
);
2098 case EST_FETCHENTRY
:
2099 again
= ehci_state_fetchentry(ehci
, async
);
2103 q
= ehci_state_fetchqh(ehci
, async
);
2105 assert(q
->async
== async
);
2113 again
= ehci_state_fetchitd(ehci
, async
);
2117 again
= ehci_state_fetchsitd(ehci
, async
);
2120 case EST_ADVANCEQUEUE
:
2121 again
= ehci_state_advqueue(q
);
2125 again
= ehci_state_fetchqtd(q
);
2128 case EST_HORIZONTALQH
:
2129 again
= ehci_state_horizqh(q
);
2133 again
= ehci_state_execute(q
);
2138 again
= ehci_state_executing(q
);
2143 again
= ehci_state_writeback(q
);
2147 fprintf(stderr
, "Bad state!\n");
2154 fprintf(stderr
, "processing error - resetting ehci HC\n");
2161 ehci_commit_interrupt(ehci
);
2164 static void ehci_advance_async_state(EHCIState
*ehci
)
2166 const int async
= 1;
2168 switch(ehci_get_state(ehci
, async
)) {
2170 if (!ehci_async_enabled(ehci
)) {
2173 ehci_set_usbsts(ehci
, USBSTS_ASS
);
2174 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2175 // No break, fall through to ACTIVE
2178 if (!ehci_async_enabled(ehci
)) {
2179 ehci_queues_rip_all(ehci
, async
);
2180 ehci_clear_usbsts(ehci
, USBSTS_ASS
);
2181 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2185 /* make sure guest has acknowledged the doorbell interrupt */
2186 /* TO-DO: is this really needed? */
2187 if (ehci
->usbsts
& USBSTS_IAA
) {
2188 DPRINTF("IAA status bit still set.\n");
2192 /* check that address register has been set */
2193 if (ehci
->asynclistaddr
== 0) {
2197 ehci_set_state(ehci
, async
, EST_WAITLISTHEAD
);
2198 ehci_advance_state(ehci
, async
);
2200 /* If the doorbell is set, the guest wants to make a change to the
2201 * schedule. The host controller needs to release cached data.
2204 if (ehci
->usbcmd
& USBCMD_IAAD
) {
2205 /* Remove all unseen qhs from the async qhs queue */
2206 ehci_queues_rip_unused(ehci
, async
, 1);
2207 DPRINTF("ASYNC: doorbell request acknowledged\n");
2208 ehci
->usbcmd
&= ~USBCMD_IAAD
;
2209 ehci_set_interrupt(ehci
, USBSTS_IAA
);
2214 /* this should only be due to a developer mistake */
2215 fprintf(stderr
, "ehci: Bad asynchronous state %d. "
2216 "Resetting to active\n", ehci
->astate
);
2221 static void ehci_advance_periodic_state(EHCIState
*ehci
)
2225 const int async
= 0;
2229 switch(ehci_get_state(ehci
, async
)) {
2231 if (!(ehci
->frindex
& 7) && ehci_periodic_enabled(ehci
)) {
2232 ehci_set_usbsts(ehci
, USBSTS_PSS
);
2233 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2234 // No break, fall through to ACTIVE
2239 if (!(ehci
->frindex
& 7) && !ehci_periodic_enabled(ehci
)) {
2240 ehci_queues_rip_all(ehci
, async
);
2241 ehci_clear_usbsts(ehci
, USBSTS_PSS
);
2242 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2246 list
= ehci
->periodiclistbase
& 0xfffff000;
2247 /* check that register has been set */
2251 list
|= ((ehci
->frindex
& 0x1ff8) >> 1);
2253 pci_dma_read(&ehci
->dev
, list
, &entry
, sizeof entry
);
2254 entry
= le32_to_cpu(entry
);
2256 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2257 ehci
->frindex
/ 8, list
, entry
);
2258 ehci_set_fetch_addr(ehci
, async
,entry
);
2259 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
2260 ehci_advance_state(ehci
, async
);
2261 ehci_queues_rip_unused(ehci
, async
, 0);
2265 /* this should only be due to a developer mistake */
2266 fprintf(stderr
, "ehci: Bad periodic state %d. "
2267 "Resetting to active\n", ehci
->pstate
);
2272 static void ehci_frame_timer(void *opaque
)
2274 EHCIState
*ehci
= opaque
;
2275 int64_t expire_time
, t_now
;
2276 uint64_t ns_elapsed
;
2279 int skipped_frames
= 0;
2281 t_now
= qemu_get_clock_ns(vm_clock
);
2282 expire_time
= t_now
+ (get_ticks_per_sec() / ehci
->freq
);
2284 ns_elapsed
= t_now
- ehci
->last_run_ns
;
2285 frames
= ns_elapsed
/ FRAME_TIMER_NS
;
2287 for (i
= 0; i
< frames
; i
++) {
2288 if ( !(ehci
->usbsts
& USBSTS_HALT
)) {
2291 if (ehci
->frindex
== 0x00002000) {
2292 ehci_set_interrupt(ehci
, USBSTS_FLR
);
2295 if (ehci
->frindex
== 0x00004000) {
2296 ehci_set_interrupt(ehci
, USBSTS_FLR
);
2301 if (frames
- i
> ehci
->maxframes
) {
2304 ehci_advance_periodic_state(ehci
);
2307 ehci
->last_run_ns
+= FRAME_TIMER_NS
;
2311 if (skipped_frames
) {
2312 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames
);
2316 /* Async is not inside loop since it executes everything it can once
2319 qemu_bh_schedule(ehci
->async_bh
);
2321 qemu_mod_timer(ehci
->frame_timer
, expire_time
);
2324 static void ehci_async_bh(void *opaque
)
2326 EHCIState
*ehci
= opaque
;
2327 ehci_advance_async_state(ehci
);
2330 static const MemoryRegionOps ehci_mem_ops
= {
2332 .read
= { ehci_mem_readb
, ehci_mem_readw
, ehci_mem_readl
},
2333 .write
= { ehci_mem_writeb
, ehci_mem_writew
, ehci_mem_writel
},
2335 .endianness
= DEVICE_LITTLE_ENDIAN
,
2338 static int usb_ehci_initfn(PCIDevice
*dev
);
2340 static USBPortOps ehci_port_ops
= {
2341 .attach
= ehci_attach
,
2342 .detach
= ehci_detach
,
2343 .child_detach
= ehci_child_detach
,
2344 .wakeup
= ehci_wakeup
,
2345 .complete
= ehci_async_complete_packet
,
2348 static USBBusOps ehci_bus_ops
= {
2349 .register_companion
= ehci_register_companion
,
2352 static const VMStateDescription vmstate_ehci
= {
2357 static Property ehci_properties
[] = {
2358 DEFINE_PROP_UINT32("freq", EHCIState
, freq
, FRAME_TIMER_FREQ
),
2359 DEFINE_PROP_UINT32("maxframes", EHCIState
, maxframes
, 128),
2360 DEFINE_PROP_END_OF_LIST(),
2363 static void ehci_class_init(ObjectClass
*klass
, void *data
)
2365 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2366 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2368 k
->init
= usb_ehci_initfn
;
2369 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2370 k
->device_id
= PCI_DEVICE_ID_INTEL_82801D
; /* ich4 */
2372 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2373 dc
->vmsd
= &vmstate_ehci
;
2374 dc
->props
= ehci_properties
;
2377 static TypeInfo ehci_info
= {
2379 .parent
= TYPE_PCI_DEVICE
,
2380 .instance_size
= sizeof(EHCIState
),
2381 .class_init
= ehci_class_init
,
2384 static void ich9_ehci_class_init(ObjectClass
*klass
, void *data
)
2386 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2387 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2389 k
->init
= usb_ehci_initfn
;
2390 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2391 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_EHCI1
;
2393 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2394 dc
->vmsd
= &vmstate_ehci
;
2395 dc
->props
= ehci_properties
;
2398 static TypeInfo ich9_ehci_info
= {
2399 .name
= "ich9-usb-ehci1",
2400 .parent
= TYPE_PCI_DEVICE
,
2401 .instance_size
= sizeof(EHCIState
),
2402 .class_init
= ich9_ehci_class_init
,
2405 static int usb_ehci_initfn(PCIDevice
*dev
)
2407 EHCIState
*s
= DO_UPCAST(EHCIState
, dev
, dev
);
2408 uint8_t *pci_conf
= s
->dev
.config
;
2411 pci_set_byte(&pci_conf
[PCI_CLASS_PROG
], 0x20);
2413 /* capabilities pointer */
2414 pci_set_byte(&pci_conf
[PCI_CAPABILITY_LIST
], 0x00);
2415 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2417 pci_set_byte(&pci_conf
[PCI_INTERRUPT_PIN
], 4); /* interrupt pin D */
2418 pci_set_byte(&pci_conf
[PCI_MIN_GNT
], 0);
2419 pci_set_byte(&pci_conf
[PCI_MAX_LAT
], 0);
2421 // pci_conf[0x50] = 0x01; // power management caps
2423 pci_set_byte(&pci_conf
[USB_SBRN
], USB_RELEASE_2
); // release number (2.1.4)
2424 pci_set_byte(&pci_conf
[0x61], 0x20); // frame length adjustment (2.1.5)
2425 pci_set_word(&pci_conf
[0x62], 0x00); // port wake up capability (2.1.6)
2427 pci_conf
[0x64] = 0x00;
2428 pci_conf
[0x65] = 0x00;
2429 pci_conf
[0x66] = 0x00;
2430 pci_conf
[0x67] = 0x00;
2431 pci_conf
[0x68] = 0x01;
2432 pci_conf
[0x69] = 0x00;
2433 pci_conf
[0x6a] = 0x00;
2434 pci_conf
[0x6b] = 0x00; // USBLEGSUP
2435 pci_conf
[0x6c] = 0x00;
2436 pci_conf
[0x6d] = 0x00;
2437 pci_conf
[0x6e] = 0x00;
2438 pci_conf
[0x6f] = 0xc0; // USBLEFCTLSTS
2440 // 2.2 host controller interface version
2441 s
->mmio
[0x00] = (uint8_t) OPREGBASE
;
2442 s
->mmio
[0x01] = 0x00;
2443 s
->mmio
[0x02] = 0x00;
2444 s
->mmio
[0x03] = 0x01; // HC version
2445 s
->mmio
[0x04] = NB_PORTS
; // Number of downstream ports
2446 s
->mmio
[0x05] = 0x00; // No companion ports at present
2447 s
->mmio
[0x06] = 0x00;
2448 s
->mmio
[0x07] = 0x00;
2449 s
->mmio
[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2450 s
->mmio
[0x09] = 0x68; // EECP
2451 s
->mmio
[0x0a] = 0x00;
2452 s
->mmio
[0x0b] = 0x00;
2454 s
->irq
= s
->dev
.irq
[3];
2456 usb_bus_new(&s
->bus
, &ehci_bus_ops
, &s
->dev
.qdev
);
2457 for(i
= 0; i
< NB_PORTS
; i
++) {
2458 usb_register_port(&s
->bus
, &s
->ports
[i
], s
, i
, &ehci_port_ops
,
2459 USB_SPEED_MASK_HIGH
);
2460 s
->ports
[i
].dev
= 0;
2463 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, ehci_frame_timer
, s
);
2464 s
->async_bh
= qemu_bh_new(ehci_async_bh
, s
);
2465 QTAILQ_INIT(&s
->aqueues
);
2466 QTAILQ_INIT(&s
->pqueues
);
2468 qemu_register_reset(ehci_reset
, s
);
2470 memory_region_init_io(&s
->mem
, &ehci_mem_ops
, s
, "ehci", MMIO_SIZE
);
2471 pci_register_bar(&s
->dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mem
);
2476 static void ehci_register_types(void)
2478 type_register_static(&ehci_info
);
2479 type_register_static(&ich9_ehci_info
);
2482 type_init(ehci_register_types
)
2485 * vim: expandtab ts=4