2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
30 #include "qemu-timer.h"
33 #include "hw/sysbus.h"
34 #include "hw/qdev-addr.h"
37 /* Dump packet contents. */
38 //#define DEBUG_PACKET
40 /* This causes frames to occur 1000x slower */
41 //#define OHCI_TIME_WARP 1
44 #define DPRINTF printf
49 /* Number of Downstream Ports on the root hub. */
51 #define OHCI_MAX_PORTS 15
53 static int64_t usb_frame_time
;
54 static int64_t usb_bit_time
;
56 typedef struct OHCIPort
{
72 /* Control partition */
77 /* memory pointer partition */
79 uint32_t ctrl_head
, ctrl_cur
;
80 uint32_t bulk_head
, bulk_cur
;
85 /* Frame counter partition */
90 uint16_t frame_number
;
95 /* Root Hub partition */
96 uint32_t rhdesc_a
, rhdesc_b
;
98 OHCIPort rhport
[OHCI_MAX_PORTS
];
100 /* PXA27x Non-OHCI events */
106 /* SM501 local memory offset */
107 target_phys_addr_t localmem_base
;
109 /* Active packets. */
111 USBPacket usb_packet
;
112 uint8_t usb_buf
[8192];
118 /* Host Controller Communications Area */
125 static void ohci_bus_stop(OHCIState
*ohci
);
126 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
);
128 /* Bitfields for the first word of an Endpoint Desciptor. */
129 #define OHCI_ED_FA_SHIFT 0
130 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
131 #define OHCI_ED_EN_SHIFT 7
132 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
133 #define OHCI_ED_D_SHIFT 11
134 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
135 #define OHCI_ED_S (1<<13)
136 #define OHCI_ED_K (1<<14)
137 #define OHCI_ED_F (1<<15)
138 #define OHCI_ED_MPS_SHIFT 16
139 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
141 /* Flags in the head field of an Endpoint Desciptor. */
145 /* Bitfields for the first word of a Transfer Desciptor. */
146 #define OHCI_TD_R (1<<18)
147 #define OHCI_TD_DP_SHIFT 19
148 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
149 #define OHCI_TD_DI_SHIFT 21
150 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
151 #define OHCI_TD_T0 (1<<24)
152 #define OHCI_TD_T1 (1<<25)
153 #define OHCI_TD_EC_SHIFT 26
154 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
155 #define OHCI_TD_CC_SHIFT 28
156 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
158 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
159 /* CC & DI - same as in the General Transfer Desciptor */
160 #define OHCI_TD_SF_SHIFT 0
161 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
162 #define OHCI_TD_FC_SHIFT 24
163 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
165 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
166 #define OHCI_TD_PSW_CC_SHIFT 12
167 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
168 #define OHCI_TD_PSW_SIZE_SHIFT 0
169 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
171 #define OHCI_PAGE_MASK 0xfffff000
172 #define OHCI_OFFSET_MASK 0xfff
174 #define OHCI_DPTR_MASK 0xfffffff0
176 #define OHCI_BM(val, field) \
177 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
179 #define OHCI_SET_BM(val, field, newval) do { \
180 val &= ~OHCI_##field##_MASK; \
181 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
184 /* endpoint descriptor */
192 /* General transfer descriptor */
200 /* Isochronous transfer descriptor */
209 #define USB_HZ 12000000
211 /* OHCI Local stuff */
212 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
213 #define OHCI_CTL_PLE (1<<2)
214 #define OHCI_CTL_IE (1<<3)
215 #define OHCI_CTL_CLE (1<<4)
216 #define OHCI_CTL_BLE (1<<5)
217 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
218 #define OHCI_USB_RESET 0x00
219 #define OHCI_USB_RESUME 0x40
220 #define OHCI_USB_OPERATIONAL 0x80
221 #define OHCI_USB_SUSPEND 0xc0
222 #define OHCI_CTL_IR (1<<8)
223 #define OHCI_CTL_RWC (1<<9)
224 #define OHCI_CTL_RWE (1<<10)
226 #define OHCI_STATUS_HCR (1<<0)
227 #define OHCI_STATUS_CLF (1<<1)
228 #define OHCI_STATUS_BLF (1<<2)
229 #define OHCI_STATUS_OCR (1<<3)
230 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
232 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
233 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
234 #define OHCI_INTR_SF (1<<2) /* Start of frame */
235 #define OHCI_INTR_RD (1<<3) /* Resume detect */
236 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
237 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
238 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
239 #define OHCI_INTR_OC (1<<30) /* Ownership change */
240 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
242 #define OHCI_HCCA_SIZE 0x100
243 #define OHCI_HCCA_MASK 0xffffff00
245 #define OHCI_EDPTR_MASK 0xfffffff0
247 #define OHCI_FMI_FI 0x00003fff
248 #define OHCI_FMI_FSMPS 0xffff0000
249 #define OHCI_FMI_FIT 0x80000000
251 #define OHCI_FR_RT (1<<31)
253 #define OHCI_LS_THRESH 0x628
255 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
256 #define OHCI_RHA_PSM (1<<8)
257 #define OHCI_RHA_NPS (1<<9)
258 #define OHCI_RHA_DT (1<<10)
259 #define OHCI_RHA_OCPM (1<<11)
260 #define OHCI_RHA_NOCP (1<<12)
261 #define OHCI_RHA_POTPGT_MASK 0xff000000
263 #define OHCI_RHS_LPS (1<<0)
264 #define OHCI_RHS_OCI (1<<1)
265 #define OHCI_RHS_DRWE (1<<15)
266 #define OHCI_RHS_LPSC (1<<16)
267 #define OHCI_RHS_OCIC (1<<17)
268 #define OHCI_RHS_CRWE (1<<31)
270 #define OHCI_PORT_CCS (1<<0)
271 #define OHCI_PORT_PES (1<<1)
272 #define OHCI_PORT_PSS (1<<2)
273 #define OHCI_PORT_POCI (1<<3)
274 #define OHCI_PORT_PRS (1<<4)
275 #define OHCI_PORT_PPS (1<<8)
276 #define OHCI_PORT_LSDA (1<<9)
277 #define OHCI_PORT_CSC (1<<16)
278 #define OHCI_PORT_PESC (1<<17)
279 #define OHCI_PORT_PSSC (1<<18)
280 #define OHCI_PORT_OCIC (1<<19)
281 #define OHCI_PORT_PRSC (1<<20)
282 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
283 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
285 #define OHCI_TD_DIR_SETUP 0x0
286 #define OHCI_TD_DIR_OUT 0x1
287 #define OHCI_TD_DIR_IN 0x2
288 #define OHCI_TD_DIR_RESERVED 0x3
290 #define OHCI_CC_NOERROR 0x0
291 #define OHCI_CC_CRC 0x1
292 #define OHCI_CC_BITSTUFFING 0x2
293 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
294 #define OHCI_CC_STALL 0x4
295 #define OHCI_CC_DEVICENOTRESPONDING 0x5
296 #define OHCI_CC_PIDCHECKFAILURE 0x6
297 #define OHCI_CC_UNDEXPETEDPID 0x7
298 #define OHCI_CC_DATAOVERRUN 0x8
299 #define OHCI_CC_DATAUNDERRUN 0x9
300 #define OHCI_CC_BUFFEROVERRUN 0xc
301 #define OHCI_CC_BUFFERUNDERRUN 0xd
303 #define OHCI_HRESET_FSBIR (1 << 0)
305 /* Update IRQ levels */
306 static inline void ohci_intr_update(OHCIState
*ohci
)
310 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
311 (ohci
->intr_status
& ohci
->intr
))
314 qemu_set_irq(ohci
->irq
, level
);
317 /* Set an interrupt */
318 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
320 ohci
->intr_status
|= intr
;
321 ohci_intr_update(ohci
);
324 /* Attach or detach a device on a root hub port. */
325 static void ohci_attach(USBPort
*port1
)
327 OHCIState
*s
= port1
->opaque
;
328 OHCIPort
*port
= &s
->rhport
[port1
->index
];
329 uint32_t old_state
= port
->ctrl
;
331 /* set connect status */
332 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
335 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
336 port
->ctrl
|= OHCI_PORT_LSDA
;
338 port
->ctrl
&= ~OHCI_PORT_LSDA
;
341 /* notify of remote-wakeup */
342 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
343 ohci_set_interrupt(s
, OHCI_INTR_RD
);
346 DPRINTF("usb-ohci: Attached port %d\n", port1
->index
);
348 if (old_state
!= port
->ctrl
) {
349 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
353 static void ohci_detach(USBPort
*port1
)
355 OHCIState
*s
= port1
->opaque
;
356 OHCIPort
*port
= &s
->rhport
[port1
->index
];
357 uint32_t old_state
= port
->ctrl
;
359 ohci_async_cancel_device(s
, port1
->dev
);
361 /* set connect status */
362 if (port
->ctrl
& OHCI_PORT_CCS
) {
363 port
->ctrl
&= ~OHCI_PORT_CCS
;
364 port
->ctrl
|= OHCI_PORT_CSC
;
367 if (port
->ctrl
& OHCI_PORT_PES
) {
368 port
->ctrl
&= ~OHCI_PORT_PES
;
369 port
->ctrl
|= OHCI_PORT_PESC
;
371 DPRINTF("usb-ohci: Detached port %d\n", port1
->index
);
373 if (old_state
!= port
->ctrl
) {
374 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
378 static void ohci_wakeup(USBPort
*port1
)
380 OHCIState
*s
= port1
->opaque
;
381 OHCIPort
*port
= &s
->rhport
[port1
->index
];
383 if (port
->ctrl
& OHCI_PORT_PSS
) {
384 DPRINTF("usb-ohci: port %d: wakeup\n", port1
->index
);
385 port
->ctrl
|= OHCI_PORT_PSSC
;
386 port
->ctrl
&= ~OHCI_PORT_PSS
;
387 intr
= OHCI_INTR_RHSC
;
389 /* Note that the controller can be suspended even if this port is not */
390 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
) {
391 DPRINTF("usb-ohci: remote-wakeup: SUSPEND->RESUME\n");
392 /* This is the one state transition the controller can do by itself */
393 s
->ctl
&= ~OHCI_CTL_HCFS
;
394 s
->ctl
|= OHCI_USB_RESUME
;
395 /* In suspend mode only ResumeDetected is possible, not RHSC:
396 * see the OHCI spec 5.1.2.3.
400 ohci_set_interrupt(s
, intr
);
403 static void ohci_child_detach(USBPort
*port1
, USBDevice
*child
)
405 OHCIState
*s
= port1
->opaque
;
407 ohci_async_cancel_device(s
, child
);
410 static USBDevice
*ohci_find_device(OHCIState
*ohci
, uint8_t addr
)
415 for (i
= 0; i
< ohci
->num_ports
; i
++) {
416 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0) {
419 dev
= usb_find_device(&ohci
->rhport
[i
].port
, addr
);
427 /* Reset the controller */
428 static void ohci_reset(void *opaque
)
430 OHCIState
*ohci
= opaque
;
438 ohci
->intr_status
= 0;
439 ohci
->intr
= OHCI_INTR_MIE
;
442 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
443 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
446 ohci
->done_count
= 7;
448 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
449 * I took the value linux sets ...
451 ohci
->fsmps
= 0x2778;
455 ohci
->frame_number
= 0;
457 ohci
->lst
= OHCI_LS_THRESH
;
459 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
460 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
463 for (i
= 0; i
< ohci
->num_ports
; i
++)
465 port
= &ohci
->rhport
[i
];
467 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
468 usb_port_reset(&port
->port
);
471 if (ohci
->async_td
) {
472 usb_cancel_packet(&ohci
->usb_packet
);
475 DPRINTF("usb-ohci: Reset %s\n", ohci
->name
);
478 /* Get an array of dwords from main memory */
479 static inline int get_dwords(OHCIState
*ohci
,
480 uint32_t addr
, uint32_t *buf
, int num
)
484 addr
+= ohci
->localmem_base
;
486 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
487 cpu_physical_memory_read(addr
, buf
, sizeof(*buf
));
488 *buf
= le32_to_cpu(*buf
);
494 /* Put an array of dwords in to main memory */
495 static inline int put_dwords(OHCIState
*ohci
,
496 uint32_t addr
, uint32_t *buf
, int num
)
500 addr
+= ohci
->localmem_base
;
502 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
503 uint32_t tmp
= cpu_to_le32(*buf
);
504 cpu_physical_memory_write(addr
, &tmp
, sizeof(tmp
));
510 /* Get an array of words from main memory */
511 static inline int get_words(OHCIState
*ohci
,
512 uint32_t addr
, uint16_t *buf
, int num
)
516 addr
+= ohci
->localmem_base
;
518 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
519 cpu_physical_memory_read(addr
, buf
, sizeof(*buf
));
520 *buf
= le16_to_cpu(*buf
);
526 /* Put an array of words in to main memory */
527 static inline int put_words(OHCIState
*ohci
,
528 uint32_t addr
, uint16_t *buf
, int num
)
532 addr
+= ohci
->localmem_base
;
534 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
535 uint16_t tmp
= cpu_to_le16(*buf
);
536 cpu_physical_memory_write(addr
, &tmp
, sizeof(tmp
));
542 static inline int ohci_read_ed(OHCIState
*ohci
,
543 uint32_t addr
, struct ohci_ed
*ed
)
545 return get_dwords(ohci
, addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
548 static inline int ohci_read_td(OHCIState
*ohci
,
549 uint32_t addr
, struct ohci_td
*td
)
551 return get_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
554 static inline int ohci_read_iso_td(OHCIState
*ohci
,
555 uint32_t addr
, struct ohci_iso_td
*td
)
557 return (get_dwords(ohci
, addr
, (uint32_t *)td
, 4) &&
558 get_words(ohci
, addr
+ 16, td
->offset
, 8));
561 static inline int ohci_read_hcca(OHCIState
*ohci
,
562 uint32_t addr
, struct ohci_hcca
*hcca
)
564 cpu_physical_memory_read(addr
+ ohci
->localmem_base
, hcca
, sizeof(*hcca
));
568 static inline int ohci_put_ed(OHCIState
*ohci
,
569 uint32_t addr
, struct ohci_ed
*ed
)
571 return put_dwords(ohci
, addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
574 static inline int ohci_put_td(OHCIState
*ohci
,
575 uint32_t addr
, struct ohci_td
*td
)
577 return put_dwords(ohci
, addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
580 static inline int ohci_put_iso_td(OHCIState
*ohci
,
581 uint32_t addr
, struct ohci_iso_td
*td
)
583 return (put_dwords(ohci
, addr
, (uint32_t *)td
, 4) &&
584 put_words(ohci
, addr
+ 16, td
->offset
, 8));
587 static inline int ohci_put_hcca(OHCIState
*ohci
,
588 uint32_t addr
, struct ohci_hcca
*hcca
)
590 cpu_physical_memory_write(addr
+ ohci
->localmem_base
, hcca
, sizeof(*hcca
));
594 /* Read/Write the contents of a TD from/to main memory. */
595 static void ohci_copy_td(OHCIState
*ohci
, struct ohci_td
*td
,
596 uint8_t *buf
, int len
, int write
)
602 n
= 0x1000 - (ptr
& 0xfff);
605 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, n
, write
);
608 ptr
= td
->be
& ~0xfffu
;
610 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, len
- n
, write
);
613 /* Read/Write the contents of an ISO TD from/to main memory. */
614 static void ohci_copy_iso_td(OHCIState
*ohci
,
615 uint32_t start_addr
, uint32_t end_addr
,
616 uint8_t *buf
, int len
, int write
)
622 n
= 0x1000 - (ptr
& 0xfff);
625 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, n
, write
);
628 ptr
= end_addr
& ~0xfffu
;
630 cpu_physical_memory_rw(ptr
+ ohci
->localmem_base
, buf
, len
- n
, write
);
633 static void ohci_process_lists(OHCIState
*ohci
, int completion
);
635 static void ohci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
637 OHCIState
*ohci
= container_of(packet
, OHCIState
, usb_packet
);
639 DPRINTF("Async packet complete\n");
641 ohci
->async_complete
= 1;
642 ohci_process_lists(ohci
, 1);
645 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
647 static int ohci_service_iso_td(OHCIState
*ohci
, struct ohci_ed
*ed
,
653 const char *str
= NULL
;
660 struct ohci_iso_td iso_td
;
662 uint16_t starting_frame
;
663 int16_t relative_frame_number
;
665 uint32_t start_offset
, next_offset
, end_offset
= 0;
666 uint32_t start_addr
, end_addr
;
668 addr
= ed
->head
& OHCI_DPTR_MASK
;
670 if (!ohci_read_iso_td(ohci
, addr
, &iso_td
)) {
671 printf("usb-ohci: ISO_TD read error at %x\n", addr
);
675 starting_frame
= OHCI_BM(iso_td
.flags
, TD_SF
);
676 frame_count
= OHCI_BM(iso_td
.flags
, TD_FC
);
677 relative_frame_number
= USUB(ohci
->frame_number
, starting_frame
);
680 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
681 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
682 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
683 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
684 "frame_number 0x%.8x starting_frame 0x%.8x\n"
685 "frame_count 0x%.8x relative %d\n"
686 "di 0x%.8x cc 0x%.8x\n",
687 ed
->head
& OHCI_DPTR_MASK
, ed
->tail
& OHCI_DPTR_MASK
,
688 iso_td
.flags
, iso_td
.bp
, iso_td
.next
, iso_td
.be
,
689 iso_td
.offset
[0], iso_td
.offset
[1], iso_td
.offset
[2], iso_td
.offset
[3],
690 iso_td
.offset
[4], iso_td
.offset
[5], iso_td
.offset
[6], iso_td
.offset
[7],
691 ohci
->frame_number
, starting_frame
,
692 frame_count
, relative_frame_number
,
693 OHCI_BM(iso_td
.flags
, TD_DI
), OHCI_BM(iso_td
.flags
, TD_CC
));
696 if (relative_frame_number
< 0) {
697 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number
);
699 } else if (relative_frame_number
> frame_count
) {
700 /* ISO TD expired - retire the TD to the Done Queue and continue with
701 the next ISO TD of the same ED */
702 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number
,
704 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
705 ed
->head
&= ~OHCI_DPTR_MASK
;
706 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
707 iso_td
.next
= ohci
->done
;
709 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
710 if (i
< ohci
->done_count
)
711 ohci
->done_count
= i
;
712 ohci_put_iso_td(ohci
, addr
, &iso_td
);
716 dir
= OHCI_BM(ed
->flags
, ED_D
);
724 case OHCI_TD_DIR_OUT
:
730 case OHCI_TD_DIR_SETUP
:
734 pid
= USB_TOKEN_SETUP
;
737 printf("usb-ohci: Bad direction %d\n", dir
);
741 if (!iso_td
.bp
|| !iso_td
.be
) {
742 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td
.bp
, iso_td
.be
);
746 start_offset
= iso_td
.offset
[relative_frame_number
];
747 next_offset
= iso_td
.offset
[relative_frame_number
+ 1];
749 if (!(OHCI_BM(start_offset
, TD_PSW_CC
) & 0xe) ||
750 ((relative_frame_number
< frame_count
) &&
751 !(OHCI_BM(next_offset
, TD_PSW_CC
) & 0xe))) {
752 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
753 start_offset
, next_offset
);
757 if ((relative_frame_number
< frame_count
) && (start_offset
> next_offset
)) {
758 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
759 start_offset
, next_offset
);
763 if ((start_offset
& 0x1000) == 0) {
764 start_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
765 (start_offset
& OHCI_OFFSET_MASK
);
767 start_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
768 (start_offset
& OHCI_OFFSET_MASK
);
771 if (relative_frame_number
< frame_count
) {
772 end_offset
= next_offset
- 1;
773 if ((end_offset
& 0x1000) == 0) {
774 end_addr
= (iso_td
.bp
& OHCI_PAGE_MASK
) |
775 (end_offset
& OHCI_OFFSET_MASK
);
777 end_addr
= (iso_td
.be
& OHCI_PAGE_MASK
) |
778 (end_offset
& OHCI_OFFSET_MASK
);
781 /* Last packet in the ISO TD */
782 end_addr
= iso_td
.be
;
785 if ((start_addr
& OHCI_PAGE_MASK
) != (end_addr
& OHCI_PAGE_MASK
)) {
786 len
= (end_addr
& OHCI_OFFSET_MASK
) + 0x1001
787 - (start_addr
& OHCI_OFFSET_MASK
);
789 len
= end_addr
- start_addr
+ 1;
792 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
793 ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, len
, 0);
797 ret
= ohci
->usb_packet
.result
;
799 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
800 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
801 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
);
802 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, len
);
803 ret
= usb_handle_packet(dev
, &ohci
->usb_packet
);
804 if (ret
== USB_RET_ASYNC
) {
810 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
811 start_offset
, end_offset
, start_addr
, end_addr
, str
, len
, ret
);
815 if (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && ret
<= len
) {
816 /* IN transfer succeeded */
817 ohci_copy_iso_td(ohci
, start_addr
, end_addr
, ohci
->usb_buf
, ret
, 1);
818 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
820 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, ret
);
821 } else if (dir
== OHCI_TD_DIR_OUT
&& ret
== len
) {
822 /* OUT transfer succeeded */
823 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
825 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
, 0);
827 if (ret
> (ssize_t
) len
) {
828 printf("usb-ohci: DataOverrun %d > %zu\n", ret
, len
);
829 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
830 OHCI_CC_DATAOVERRUN
);
831 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
833 } else if (ret
>= 0) {
834 printf("usb-ohci: DataUnderrun %d\n", ret
);
835 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
836 OHCI_CC_DATAUNDERRUN
);
839 case USB_RET_IOERROR
:
841 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
842 OHCI_CC_DEVICENOTRESPONDING
);
843 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
848 printf("usb-ohci: got NAK/STALL %d\n", ret
);
849 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
851 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_SIZE
,
855 printf("usb-ohci: Bad device response %d\n", ret
);
856 OHCI_SET_BM(iso_td
.offset
[relative_frame_number
], TD_PSW_CC
,
857 OHCI_CC_UNDEXPETEDPID
);
863 if (relative_frame_number
== frame_count
) {
864 /* Last data packet of ISO TD - retire the TD to the Done Queue */
865 OHCI_SET_BM(iso_td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
866 ed
->head
&= ~OHCI_DPTR_MASK
;
867 ed
->head
|= (iso_td
.next
& OHCI_DPTR_MASK
);
868 iso_td
.next
= ohci
->done
;
870 i
= OHCI_BM(iso_td
.flags
, TD_DI
);
871 if (i
< ohci
->done_count
)
872 ohci
->done_count
= i
;
874 ohci_put_iso_td(ohci
, addr
, &iso_td
);
878 /* Service a transport descriptor.
879 Returns nonzero to terminate processing of this endpoint. */
881 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
884 size_t len
= 0, pktlen
= 0;
886 const char *str
= NULL
;
898 addr
= ed
->head
& OHCI_DPTR_MASK
;
899 /* See if this TD has already been submitted to the device. */
900 completion
= (addr
== ohci
->async_td
);
901 if (completion
&& !ohci
->async_complete
) {
903 DPRINTF("Skipping async TD\n");
907 if (!ohci_read_td(ohci
, addr
, &td
)) {
908 fprintf(stderr
, "usb-ohci: TD read error at %x\n", addr
);
912 dir
= OHCI_BM(ed
->flags
, ED_D
);
914 case OHCI_TD_DIR_OUT
:
919 dir
= OHCI_BM(td
.flags
, TD_DP
);
930 case OHCI_TD_DIR_OUT
:
936 case OHCI_TD_DIR_SETUP
:
940 pid
= USB_TOKEN_SETUP
;
943 fprintf(stderr
, "usb-ohci: Bad direction\n");
946 if (td
.cbp
&& td
.be
) {
947 if ((td
.cbp
& 0xfffff000) != (td
.be
& 0xfffff000)) {
948 len
= (td
.be
& 0xfff) + 0x1001 - (td
.cbp
& 0xfff);
950 len
= (td
.be
- td
.cbp
) + 1;
954 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
955 /* The endpoint may not allow us to transfer it all now */
956 pktlen
= (ed
->flags
& OHCI_ED_MPS_MASK
) >> OHCI_ED_MPS_SHIFT
;
961 ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, pktlen
, 0);
966 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
968 DPRINTF(" TD @ 0x%.8x %" PRId64
" of %" PRId64
969 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
970 addr
, (int64_t)pktlen
, (int64_t)len
, str
, flag_r
, td
.cbp
, td
.be
);
972 if (pktlen
> 0 && dir
!= OHCI_TD_DIR_IN
) {
974 for (i
= 0; i
< pktlen
; i
++) {
975 printf(" %.2x", ohci
->usb_buf
[i
]);
981 ret
= ohci
->usb_packet
.result
;
983 ohci
->async_complete
= 0;
985 if (ohci
->async_td
) {
986 /* ??? The hardware should allow one active packet per
987 endpoint. We only allow one active packet per controller.
988 This should be sufficient as long as devices respond in a
992 DPRINTF("Too many pending packets\n");
996 dev
= ohci_find_device(ohci
, OHCI_BM(ed
->flags
, ED_FA
));
997 ep
= usb_ep_get(dev
, pid
, OHCI_BM(ed
->flags
, ED_EN
));
998 usb_packet_setup(&ohci
->usb_packet
, pid
, ep
);
999 usb_packet_addbuf(&ohci
->usb_packet
, ohci
->usb_buf
, pktlen
);
1000 ret
= usb_handle_packet(dev
, &ohci
->usb_packet
);
1002 DPRINTF("ret=%d\n", ret
);
1004 if (ret
== USB_RET_ASYNC
) {
1005 ohci
->async_td
= addr
;
1010 if (dir
== OHCI_TD_DIR_IN
) {
1011 ohci_copy_td(ohci
, &td
, ohci
->usb_buf
, ret
, 1);
1014 for (i
= 0; i
< ret
; i
++)
1015 printf(" %.2x", ohci
->usb_buf
[i
]);
1024 if (ret
== pktlen
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
1025 /* Transmission succeeded. */
1029 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
1030 td
.cbp
= (td
.be
& ~0xfff) + ((td
.cbp
+ ret
) & 0xfff);
1035 td
.flags
|= OHCI_TD_T1
;
1036 td
.flags
^= OHCI_TD_T0
;
1037 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
1038 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
1040 if ((dir
!= OHCI_TD_DIR_IN
) && (ret
!= len
)) {
1041 /* Partial packet transfer: TD not ready to retire yet */
1042 goto exit_no_retire
;
1045 /* Setting ED_C is part of the TD retirement process */
1046 ed
->head
&= ~OHCI_ED_C
;
1047 if (td
.flags
& OHCI_TD_T0
)
1048 ed
->head
|= OHCI_ED_C
;
1051 DPRINTF("usb-ohci: Underrun\n");
1052 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
1055 case USB_RET_IOERROR
:
1057 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
1059 DPRINTF("usb-ohci: got NAK\n");
1062 DPRINTF("usb-ohci: got STALL\n");
1063 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
1065 case USB_RET_BABBLE
:
1066 DPRINTF("usb-ohci: got BABBLE\n");
1067 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
1070 fprintf(stderr
, "usb-ohci: Bad device response %d\n", ret
);
1071 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
1072 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
1076 ed
->head
|= OHCI_ED_H
;
1079 /* Retire this TD */
1080 ed
->head
&= ~OHCI_DPTR_MASK
;
1081 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
1082 td
.next
= ohci
->done
;
1084 i
= OHCI_BM(td
.flags
, TD_DI
);
1085 if (i
< ohci
->done_count
)
1086 ohci
->done_count
= i
;
1088 ohci_put_td(ohci
, addr
, &td
);
1089 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
1092 /* Service an endpoint list. Returns nonzero if active TD were found. */
1093 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
, int completion
)
1105 for (cur
= head
; cur
; cur
= next_ed
) {
1106 if (!ohci_read_ed(ohci
, cur
, &ed
)) {
1107 fprintf(stderr
, "usb-ohci: ED read error at %x\n", cur
);
1111 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
1113 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
)) {
1115 /* Cancel pending packets for ED that have been paused. */
1116 addr
= ed
.head
& OHCI_DPTR_MASK
;
1117 if (ohci
->async_td
&& addr
== ohci
->async_td
) {
1118 usb_cancel_packet(&ohci
->usb_packet
);
1124 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
1126 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1127 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur
,
1128 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
1129 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
1130 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
1131 OHCI_BM(ed
.flags
, ED_MPS
), (ed
.head
& OHCI_ED_H
) != 0,
1132 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
1133 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
1137 if ((ed
.flags
& OHCI_ED_F
) == 0) {
1138 if (ohci_service_td(ohci
, &ed
))
1141 /* Handle isochronous endpoints */
1142 if (ohci_service_iso_td(ohci
, &ed
, completion
))
1147 ohci_put_ed(ohci
, cur
, &ed
);
1153 /* Generate a SOF event, and set a timer for EOF */
1154 static void ohci_sof(OHCIState
*ohci
)
1156 ohci
->sof_time
= qemu_get_clock_ns(vm_clock
);
1157 qemu_mod_timer(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
1158 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
1161 /* Process Control and Bulk lists. */
1162 static void ohci_process_lists(OHCIState
*ohci
, int completion
)
1164 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
1165 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
) {
1166 DPRINTF("usb-ohci: head %x, cur %x\n",
1167 ohci
->ctrl_head
, ohci
->ctrl_cur
);
1169 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
, completion
)) {
1171 ohci
->status
&= ~OHCI_STATUS_CLF
;
1175 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
1176 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
, completion
)) {
1178 ohci
->status
&= ~OHCI_STATUS_BLF
;
1183 /* Do frame processing on frame boundary */
1184 static void ohci_frame_boundary(void *opaque
)
1186 OHCIState
*ohci
= opaque
;
1187 struct ohci_hcca hcca
;
1189 ohci_read_hcca(ohci
, ohci
->hcca
, &hcca
);
1191 /* Process all the lists at the end of the frame */
1192 if (ohci
->ctl
& OHCI_CTL_PLE
) {
1195 n
= ohci
->frame_number
& 0x1f;
1196 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]), 0);
1199 /* Cancel all pending packets if either of the lists has been disabled. */
1200 if (ohci
->async_td
&&
1201 ohci
->old_ctl
& (~ohci
->ctl
) & (OHCI_CTL_BLE
| OHCI_CTL_CLE
)) {
1202 usb_cancel_packet(&ohci
->usb_packet
);
1205 ohci
->old_ctl
= ohci
->ctl
;
1206 ohci_process_lists(ohci
, 0);
1208 /* Frame boundary, so do EOF stuf here */
1209 ohci
->frt
= ohci
->fit
;
1211 /* Increment frame number and take care of endianness. */
1212 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
1213 hcca
.frame
= cpu_to_le16(ohci
->frame_number
);
1215 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
1218 if (ohci
->intr
& ohci
->intr_status
)
1220 hcca
.done
= cpu_to_le32(ohci
->done
);
1222 ohci
->done_count
= 7;
1223 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
1226 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
1229 /* Do SOF stuff here */
1232 /* Writeback HCCA */
1233 ohci_put_hcca(ohci
, ohci
->hcca
, &hcca
);
1236 /* Start sending SOF tokens across the USB bus, lists are processed in
1239 static int ohci_bus_start(OHCIState
*ohci
)
1241 ohci
->eof_timer
= qemu_new_timer_ns(vm_clock
,
1242 ohci_frame_boundary
,
1245 if (ohci
->eof_timer
== NULL
) {
1246 fprintf(stderr
, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci
->name
);
1247 /* TODO: Signal unrecoverable error */
1251 DPRINTF("usb-ohci: %s: USB Operational\n", ohci
->name
);
1258 /* Stop sending SOF tokens on the bus */
1259 static void ohci_bus_stop(OHCIState
*ohci
)
1261 if (ohci
->eof_timer
)
1262 qemu_del_timer(ohci
->eof_timer
);
1263 ohci
->eof_timer
= NULL
;
1266 /* Sets a flag in a port status register but only set it if the port is
1267 * connected, if not set ConnectStatusChange flag. If flag is enabled
1270 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
1274 /* writing a 0 has no effect */
1278 /* If CurrentConnectStatus is cleared we set
1279 * ConnectStatusChange
1281 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
1282 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
1283 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
1284 /* TODO: CSC is a wakeup event */
1289 if (ohci
->rhport
[i
].ctrl
& val
)
1293 ohci
->rhport
[i
].ctrl
|= val
;
1298 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1299 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
1303 if (val
!= ohci
->fi
) {
1304 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1305 ohci
->name
, ohci
->fi
, ohci
->fi
);
1311 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
1314 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
1316 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
1323 /* Set HcControlRegister */
1324 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
1329 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1331 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
1333 /* no state change */
1334 if (old_state
== new_state
)
1337 switch (new_state
) {
1338 case OHCI_USB_OPERATIONAL
:
1339 ohci_bus_start(ohci
);
1341 case OHCI_USB_SUSPEND
:
1342 ohci_bus_stop(ohci
);
1343 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci
->name
);
1345 case OHCI_USB_RESUME
:
1346 DPRINTF("usb-ohci: %s: USB Resume\n", ohci
->name
);
1348 case OHCI_USB_RESET
:
1350 DPRINTF("usb-ohci: %s: USB Reset\n", ohci
->name
);
1355 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
1360 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
1361 return (ohci
->frt
<< 31);
1363 /* Being in USB operational state guarnatees sof_time was
1366 tks
= qemu_get_clock_ns(vm_clock
) - ohci
->sof_time
;
1368 /* avoid muldiv if possible */
1369 if (tks
>= usb_frame_time
)
1370 return (ohci
->frt
<< 31);
1372 tks
= muldiv64(1, tks
, usb_bit_time
);
1373 fr
= (uint16_t)(ohci
->fi
- tks
);
1375 return (ohci
->frt
<< 31) | fr
;
1379 /* Set root hub status */
1380 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
1384 old_state
= ohci
->rhstatus
;
1386 /* write 1 to clear OCIC */
1387 if (val
& OHCI_RHS_OCIC
)
1388 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
1390 if (val
& OHCI_RHS_LPS
) {
1393 for (i
= 0; i
< ohci
->num_ports
; i
++)
1394 ohci_port_power(ohci
, i
, 0);
1395 DPRINTF("usb-ohci: powered down all ports\n");
1398 if (val
& OHCI_RHS_LPSC
) {
1401 for (i
= 0; i
< ohci
->num_ports
; i
++)
1402 ohci_port_power(ohci
, i
, 1);
1403 DPRINTF("usb-ohci: powered up all ports\n");
1406 if (val
& OHCI_RHS_DRWE
)
1407 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
1409 if (val
& OHCI_RHS_CRWE
)
1410 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
1412 if (old_state
!= ohci
->rhstatus
)
1413 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1416 /* Set root hub port status */
1417 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
1422 port
= &ohci
->rhport
[portnum
];
1423 old_state
= port
->ctrl
;
1425 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1426 if (val
& OHCI_PORT_WTC
)
1427 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
1429 if (val
& OHCI_PORT_CCS
)
1430 port
->ctrl
&= ~OHCI_PORT_PES
;
1432 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
1434 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
)) {
1435 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum
);
1438 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
1439 DPRINTF("usb-ohci: port %d: RESET\n", portnum
);
1440 usb_device_reset(port
->port
.dev
);
1441 port
->ctrl
&= ~OHCI_PORT_PRS
;
1442 /* ??? Should this also set OHCI_PORT_PESC. */
1443 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
1446 /* Invert order here to ensure in ambiguous case, device is
1449 if (val
& OHCI_PORT_LSDA
)
1450 ohci_port_power(ohci
, portnum
, 0);
1451 if (val
& OHCI_PORT_PPS
)
1452 ohci_port_power(ohci
, portnum
, 1);
1454 if (old_state
!= port
->ctrl
)
1455 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1460 static uint64_t ohci_mem_read(void *opaque
,
1461 target_phys_addr_t addr
,
1464 OHCIState
*ohci
= opaque
;
1467 /* Only aligned reads are allowed on OHCI */
1469 fprintf(stderr
, "usb-ohci: Mis-aligned read\n");
1471 } else if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1472 /* HcRhPortStatus */
1473 retval
= ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
1475 switch (addr
>> 2) {
1476 case 0: /* HcRevision */
1480 case 1: /* HcControl */
1484 case 2: /* HcCommandStatus */
1485 retval
= ohci
->status
;
1488 case 3: /* HcInterruptStatus */
1489 retval
= ohci
->intr_status
;
1492 case 4: /* HcInterruptEnable */
1493 case 5: /* HcInterruptDisable */
1494 retval
= ohci
->intr
;
1497 case 6: /* HcHCCA */
1498 retval
= ohci
->hcca
;
1501 case 7: /* HcPeriodCurrentED */
1502 retval
= ohci
->per_cur
;
1505 case 8: /* HcControlHeadED */
1506 retval
= ohci
->ctrl_head
;
1509 case 9: /* HcControlCurrentED */
1510 retval
= ohci
->ctrl_cur
;
1513 case 10: /* HcBulkHeadED */
1514 retval
= ohci
->bulk_head
;
1517 case 11: /* HcBulkCurrentED */
1518 retval
= ohci
->bulk_cur
;
1521 case 12: /* HcDoneHead */
1522 retval
= ohci
->done
;
1525 case 13: /* HcFmInterretval */
1526 retval
= (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
1529 case 14: /* HcFmRemaining */
1530 retval
= ohci_get_frame_remaining(ohci
);
1533 case 15: /* HcFmNumber */
1534 retval
= ohci
->frame_number
;
1537 case 16: /* HcPeriodicStart */
1538 retval
= ohci
->pstart
;
1541 case 17: /* HcLSThreshold */
1545 case 18: /* HcRhDescriptorA */
1546 retval
= ohci
->rhdesc_a
;
1549 case 19: /* HcRhDescriptorB */
1550 retval
= ohci
->rhdesc_b
;
1553 case 20: /* HcRhStatus */
1554 retval
= ohci
->rhstatus
;
1557 /* PXA27x specific registers */
1558 case 24: /* HcStatus */
1559 retval
= ohci
->hstatus
& ohci
->hmask
;
1562 case 25: /* HcHReset */
1563 retval
= ohci
->hreset
;
1566 case 26: /* HcHInterruptEnable */
1567 retval
= ohci
->hmask
;
1570 case 27: /* HcHInterruptTest */
1571 retval
= ohci
->htest
;
1575 fprintf(stderr
, "ohci_read: Bad offset %x\n", (int)addr
);
1576 retval
= 0xffffffff;
1583 static void ohci_mem_write(void *opaque
,
1584 target_phys_addr_t addr
,
1588 OHCIState
*ohci
= opaque
;
1590 /* Only aligned reads are allowed on OHCI */
1592 fprintf(stderr
, "usb-ohci: Mis-aligned write\n");
1596 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1597 /* HcRhPortStatus */
1598 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1602 switch (addr
>> 2) {
1603 case 1: /* HcControl */
1604 ohci_set_ctl(ohci
, val
);
1607 case 2: /* HcCommandStatus */
1608 /* SOC is read-only */
1609 val
= (val
& ~OHCI_STATUS_SOC
);
1611 /* Bits written as '0' remain unchanged in the register */
1612 ohci
->status
|= val
;
1614 if (ohci
->status
& OHCI_STATUS_HCR
)
1618 case 3: /* HcInterruptStatus */
1619 ohci
->intr_status
&= ~val
;
1620 ohci_intr_update(ohci
);
1623 case 4: /* HcInterruptEnable */
1625 ohci_intr_update(ohci
);
1628 case 5: /* HcInterruptDisable */
1630 ohci_intr_update(ohci
);
1633 case 6: /* HcHCCA */
1634 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1637 case 7: /* HcPeriodCurrentED */
1638 /* Ignore writes to this read-only register, Linux does them */
1641 case 8: /* HcControlHeadED */
1642 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1645 case 9: /* HcControlCurrentED */
1646 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1649 case 10: /* HcBulkHeadED */
1650 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1653 case 11: /* HcBulkCurrentED */
1654 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1657 case 13: /* HcFmInterval */
1658 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1659 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1660 ohci_set_frame_interval(ohci
, val
);
1663 case 15: /* HcFmNumber */
1666 case 16: /* HcPeriodicStart */
1667 ohci
->pstart
= val
& 0xffff;
1670 case 17: /* HcLSThreshold */
1671 ohci
->lst
= val
& 0xffff;
1674 case 18: /* HcRhDescriptorA */
1675 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1676 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1679 case 19: /* HcRhDescriptorB */
1682 case 20: /* HcRhStatus */
1683 ohci_set_hub_status(ohci
, val
);
1686 /* PXA27x specific registers */
1687 case 24: /* HcStatus */
1688 ohci
->hstatus
&= ~(val
& ohci
->hmask
);
1690 case 25: /* HcHReset */
1691 ohci
->hreset
= val
& ~OHCI_HRESET_FSBIR
;
1692 if (val
& OHCI_HRESET_FSBIR
)
1696 case 26: /* HcHInterruptEnable */
1700 case 27: /* HcHInterruptTest */
1705 fprintf(stderr
, "ohci_write: Bad offset %x\n", (int)addr
);
1710 static void ohci_async_cancel_device(OHCIState
*ohci
, USBDevice
*dev
)
1712 if (ohci
->async_td
&&
1713 usb_packet_is_inflight(&ohci
->usb_packet
) &&
1714 ohci
->usb_packet
.ep
->dev
== dev
) {
1715 usb_cancel_packet(&ohci
->usb_packet
);
1720 static const MemoryRegionOps ohci_mem_ops
= {
1721 .read
= ohci_mem_read
,
1722 .write
= ohci_mem_write
,
1723 .endianness
= DEVICE_LITTLE_ENDIAN
,
1726 static USBPortOps ohci_port_ops
= {
1727 .attach
= ohci_attach
,
1728 .detach
= ohci_detach
,
1729 .child_detach
= ohci_child_detach
,
1730 .wakeup
= ohci_wakeup
,
1731 .complete
= ohci_async_complete_packet
,
1734 static USBBusOps ohci_bus_ops
= {
1737 static int usb_ohci_init(OHCIState
*ohci
, DeviceState
*dev
,
1738 int num_ports
, uint32_t localmem_base
,
1739 char *masterbus
, uint32_t firstport
)
1743 if (usb_frame_time
== 0) {
1744 #ifdef OHCI_TIME_WARP
1745 usb_frame_time
= get_ticks_per_sec();
1746 usb_bit_time
= muldiv64(1, get_ticks_per_sec(), USB_HZ
/1000);
1748 usb_frame_time
= muldiv64(1, get_ticks_per_sec(), 1000);
1749 if (get_ticks_per_sec() >= USB_HZ
) {
1750 usb_bit_time
= muldiv64(1, get_ticks_per_sec(), USB_HZ
);
1755 DPRINTF("usb-ohci: usb_bit_time=%" PRId64
" usb_frame_time=%" PRId64
"\n",
1756 usb_frame_time
, usb_bit_time
);
1759 ohci
->num_ports
= num_ports
;
1761 USBPort
*ports
[OHCI_MAX_PORTS
];
1762 for(i
= 0; i
< num_ports
; i
++) {
1763 ports
[i
] = &ohci
->rhport
[i
].port
;
1765 if (usb_register_companion(masterbus
, ports
, num_ports
,
1766 firstport
, ohci
, &ohci_port_ops
,
1767 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
) != 0) {
1771 usb_bus_new(&ohci
->bus
, &ohci_bus_ops
, dev
);
1772 for (i
= 0; i
< num_ports
; i
++) {
1773 usb_register_port(&ohci
->bus
, &ohci
->rhport
[i
].port
,
1774 ohci
, i
, &ohci_port_ops
,
1775 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1779 memory_region_init_io(&ohci
->mem
, &ohci_mem_ops
, ohci
, "ohci", 256);
1780 ohci
->localmem_base
= localmem_base
;
1782 ohci
->name
= object_get_typename(OBJECT(dev
));
1783 usb_packet_init(&ohci
->usb_packet
);
1786 qemu_register_reset(ohci_reset
, ohci
);
1799 static int usb_ohci_initfn_pci(struct PCIDevice
*dev
)
1801 OHCIPCIState
*ohci
= DO_UPCAST(OHCIPCIState
, pci_dev
, dev
);
1803 ohci
->pci_dev
.config
[PCI_CLASS_PROG
] = 0x10; /* OHCI */
1804 ohci
->pci_dev
.config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin A */
1806 if (usb_ohci_init(&ohci
->state
, &dev
->qdev
, ohci
->num_ports
, 0,
1807 ohci
->masterbus
, ohci
->firstport
) != 0) {
1810 ohci
->state
.irq
= ohci
->pci_dev
.irq
[0];
1812 /* TODO: avoid cast below by using dev */
1813 pci_register_bar(&ohci
->pci_dev
, 0, 0, &ohci
->state
.mem
);
1818 SysBusDevice busdev
;
1821 target_phys_addr_t dma_offset
;
1824 static int ohci_init_pxa(SysBusDevice
*dev
)
1826 OHCISysBusState
*s
= FROM_SYSBUS(OHCISysBusState
, dev
);
1828 /* Cannot fail as we pass NULL for masterbus */
1829 usb_ohci_init(&s
->ohci
, &dev
->qdev
, s
->num_ports
, s
->dma_offset
, NULL
, 0);
1830 sysbus_init_irq(dev
, &s
->ohci
.irq
);
1831 sysbus_init_mmio(dev
, &s
->ohci
.mem
);
1836 static Property ohci_pci_properties
[] = {
1837 DEFINE_PROP_STRING("masterbus", OHCIPCIState
, masterbus
),
1838 DEFINE_PROP_UINT32("num-ports", OHCIPCIState
, num_ports
, 3),
1839 DEFINE_PROP_UINT32("firstport", OHCIPCIState
, firstport
, 0),
1840 DEFINE_PROP_END_OF_LIST(),
1843 static void ohci_pci_class_init(ObjectClass
*klass
, void *data
)
1845 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1846 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1848 k
->init
= usb_ohci_initfn_pci
;
1849 k
->vendor_id
= PCI_VENDOR_ID_APPLE
;
1850 k
->device_id
= PCI_DEVICE_ID_APPLE_IPID_USB
;
1851 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1852 dc
->desc
= "Apple USB Controller";
1853 dc
->props
= ohci_pci_properties
;
1856 static TypeInfo ohci_pci_info
= {
1858 .parent
= TYPE_PCI_DEVICE
,
1859 .instance_size
= sizeof(OHCIPCIState
),
1860 .class_init
= ohci_pci_class_init
,
1863 static Property ohci_sysbus_properties
[] = {
1864 DEFINE_PROP_UINT32("num-ports", OHCISysBusState
, num_ports
, 3),
1865 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState
, dma_offset
, 3),
1866 DEFINE_PROP_END_OF_LIST(),
1869 static void ohci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1871 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1872 SysBusDeviceClass
*sbc
= SYS_BUS_DEVICE_CLASS(klass
);
1874 sbc
->init
= ohci_init_pxa
;
1875 dc
->desc
= "OHCI USB Controller";
1876 dc
->props
= ohci_sysbus_properties
;
1879 static TypeInfo ohci_sysbus_info
= {
1880 .name
= "sysbus-ohci",
1881 .parent
= TYPE_SYS_BUS_DEVICE
,
1882 .instance_size
= sizeof(OHCISysBusState
),
1883 .class_init
= ohci_sysbus_class_init
,
1886 static void ohci_register_types(void)
1888 type_register_static(&ohci_pci_info
);
1889 type_register_static(&ohci_sysbus_info
);
1892 type_init(ohci_register_types
)