hw/usb/hcd-uhci.c

   1 /*
   2  * USB UHCI controller emulation
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Copyright (c) 2008 Max Krasnyansky
   7  *     Magor rewrite of the UHCI data structures parser and frame processor
   8  *     Support for fully async operation and multiple outstanding transactions
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28 #include "hw/hw.h"
  29 #include "hw/usb.h"
  30 #include "hw/pci.h"
  31 #include "qemu-timer.h"
  32 #include "iov.h"
  33 #include "dma.h"
  34 #include "trace.h"
  35
  36 //#define DEBUG
  37 //#define DEBUG_DUMP_DATA
  38
  39 #define UHCI_CMD_FGR      (1 << 4)
  40 #define UHCI_CMD_EGSM     (1 << 3)
  41 #define UHCI_CMD_GRESET   (1 << 2)
  42 #define UHCI_CMD_HCRESET  (1 << 1)
  43 #define UHCI_CMD_RS       (1 << 0)
  44
  45 #define UHCI_STS_HCHALTED (1 << 5)
  46 #define UHCI_STS_HCPERR   (1 << 4)
  47 #define UHCI_STS_HSERR    (1 << 3)
  48 #define UHCI_STS_RD       (1 << 2)
  49 #define UHCI_STS_USBERR   (1 << 1)
  50 #define UHCI_STS_USBINT   (1 << 0)
  51
  52 #define TD_CTRL_SPD     (1 << 29)
  53 #define TD_CTRL_ERROR_SHIFT  27
  54 #define TD_CTRL_IOS     (1 << 25)
  55 #define TD_CTRL_IOC     (1 << 24)
  56 #define TD_CTRL_ACTIVE  (1 << 23)
  57 #define TD_CTRL_STALL   (1 << 22)
  58 #define TD_CTRL_BABBLE  (1 << 20)
  59 #define TD_CTRL_NAK     (1 << 19)
  60 #define TD_CTRL_TIMEOUT (1 << 18)
  61
  62 #define UHCI_PORT_SUSPEND (1 << 12)
  63 #define UHCI_PORT_RESET (1 << 9)
  64 #define UHCI_PORT_LSDA  (1 << 8)
  65 #define UHCI_PORT_RD    (1 << 6)
  66 #define UHCI_PORT_ENC   (1 << 3)
  67 #define UHCI_PORT_EN    (1 << 2)
  68 #define UHCI_PORT_CSC   (1 << 1)
  69 #define UHCI_PORT_CCS   (1 << 0)
  70
  71 #define UHCI_PORT_READ_ONLY    (0x1bb)
  72 #define UHCI_PORT_WRITE_CLEAR  (UHCI_PORT_CSC | UHCI_PORT_ENC)
  73
  74 #define FRAME_TIMER_FREQ 1000
  75
  76 #define FRAME_MAX_LOOPS  256
  77
  78 #define NB_PORTS 2
  79
  80 enum {
  81     TD_RESULT_STOP_FRAME = 10,
  82     TD_RESULT_COMPLETE,
  83     TD_RESULT_NEXT_QH,
  84     TD_RESULT_ASYNC_START,
  85     TD_RESULT_ASYNC_CONT,
  86 };
  87
  88 typedef struct UHCIState UHCIState;
  89 typedef struct UHCIAsync UHCIAsync;
  90 typedef struct UHCIQueue UHCIQueue;
  91
  92 /*
  93  * Pending async transaction.
  94  * 'packet' must be the first field because completion
  95  * handler does "(UHCIAsync *) pkt" cast.
  96  */
  97
  98 struct UHCIAsync {
  99     USBPacket packet;
 100     QEMUSGList sgl;
 101     UHCIQueue *queue;
 102     QTAILQ_ENTRY(UHCIAsync) next;
 103     uint32_t  td_addr;
 104     uint8_t   done;
 105 };
 106
 107 struct UHCIQueue {
 108     uint32_t  qh_addr;
 109     uint32_t  token;
 110     UHCIState *uhci;
 111     USBEndpoint *ep;
 112     QTAILQ_ENTRY(UHCIQueue) next;
 113     QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs;
 114     int8_t    valid;
 115 };
 116
 117 typedef struct UHCIPort {
 118     USBPort port;
 119     uint16_t ctrl;
 120 } UHCIPort;
 121
 122 struct UHCIState {
 123     PCIDevice dev;
 124     MemoryRegion io_bar;
 125     USBBus bus; /* Note unused when we're a companion controller */
 126     uint16_t cmd; /* cmd register */
 127     uint16_t status;
 128     uint16_t intr; /* interrupt enable register */
 129     uint16_t frnum; /* frame number */
 130     uint32_t fl_base_addr; /* frame list base address */
 131     uint8_t sof_timing;
 132     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
 133     int64_t expire_time;
 134     QEMUTimer *frame_timer;
 135     QEMUBH *bh;
 136     uint32_t frame_bytes;
 137     uint32_t frame_bandwidth;
 138     UHCIPort ports[NB_PORTS];
 139
 140     /* Interrupts that should be raised at the end of the current frame.  */
 141     uint32_t pending_int_mask;
 142     int irq_pin;
 143
 144     /* Active packets */
 145     QTAILQ_HEAD(, UHCIQueue) queues;
 146     uint8_t num_ports_vmstate;
 147
 148     /* Properties */
 149     char *masterbus;
 150     uint32_t firstport;
 151 };
 152
 153 typedef struct UHCI_TD {
 154     uint32_t link;
 155     uint32_t ctrl; /* see TD_CTRL_xxx */
 156     uint32_t token;
 157     uint32_t buffer;
 158 } UHCI_TD;
 159
 160 typedef struct UHCI_QH {
 161     uint32_t link;
 162     uint32_t el_link;
 163 } UHCI_QH;
 164
 165 static void uhci_async_cancel(UHCIAsync *async);
 166 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
 167
 168 static inline int32_t uhci_queue_token(UHCI_TD *td)
 169 {
 170     if ((td->token & (0xf << 15)) == 0) {
 171         /* ctrl ep, cover ep and dev, not pid! */
 172         return td->token & 0x7ff00;
 173     } else {
 174         /* covers ep, dev, pid -> identifies the endpoint */
 175         return td->token & 0x7ffff;
 176     }
 177 }
 178
 179 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
 180                                  USBEndpoint *ep)
 181 {
 182     UHCIQueue *queue;
 183
 184     queue = g_new0(UHCIQueue, 1);
 185     queue->uhci = s;
 186     queue->qh_addr = qh_addr;
 187     queue->token = uhci_queue_token(td);
 188     queue->ep = ep;
 189     QTAILQ_INIT(&queue->asyncs);
 190     QTAILQ_INSERT_HEAD(&s->queues, queue, next);
 191     /* valid needs to be large enough to handle 10 frame delay
 192      * for initial isochronous requests */
 193     queue->valid = 32;
 194     trace_usb_uhci_queue_add(queue->token);
 195     return queue;
 196 }
 197
 198 static void uhci_queue_free(UHCIQueue *queue, const char *reason)
 199 {
 200     UHCIState *s = queue->uhci;
 201     UHCIAsync *async;
 202
 203     while (!QTAILQ_EMPTY(&queue->asyncs)) {
 204         async = QTAILQ_FIRST(&queue->asyncs);
 205         uhci_async_cancel(async);
 206     }
 207
 208     trace_usb_uhci_queue_del(queue->token, reason);
 209     QTAILQ_REMOVE(&s->queues, queue, next);
 210     g_free(queue);
 211 }
 212
 213 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
 214 {
 215     uint32_t token = uhci_queue_token(td);
 216     UHCIQueue *queue;
 217
 218     QTAILQ_FOREACH(queue, &s->queues, next) {
 219         if (queue->token == token) {
 220             return queue;
 221         }
 222     }
 223     return NULL;
 224 }
 225
 226 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
 227                               uint32_t td_addr, bool queuing)
 228 {
 229     UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
 230
 231     return queue->qh_addr == qh_addr &&
 232            queue->token == uhci_queue_token(td) &&
 233            (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
 234             first->td_addr == td_addr);
 235 }
 236
 237 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
 238 {
 239     UHCIAsync *async = g_new0(UHCIAsync, 1);
 240
 241     async->queue = queue;
 242     async->td_addr = td_addr;
 243     usb_packet_init(&async->packet);
 244     pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
 245     trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
 246
 247     return async;
 248 }
 249
 250 static void uhci_async_free(UHCIAsync *async)
 251 {
 252     trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
 253     usb_packet_cleanup(&async->packet);
 254     qemu_sglist_destroy(&async->sgl);
 255     g_free(async);
 256 }
 257
 258 static void uhci_async_link(UHCIAsync *async)
 259 {
 260     UHCIQueue *queue = async->queue;
 261     QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
 262     trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
 263 }
 264
 265 static void uhci_async_unlink(UHCIAsync *async)
 266 {
 267     UHCIQueue *queue = async->queue;
 268     QTAILQ_REMOVE(&queue->asyncs, async, next);
 269     trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
 270 }
 271
 272 static void uhci_async_cancel(UHCIAsync *async)
 273 {
 274     uhci_async_unlink(async);
 275     trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
 276                                  async->done);
 277     if (!async->done)
 278         usb_cancel_packet(&async->packet);
 279     usb_packet_unmap(&async->packet, &async->sgl);
 280     uhci_async_free(async);
 281 }
 282
 283 /*
 284  * Mark all outstanding async packets as invalid.
 285  * This is used for canceling them when TDs are removed by the HCD.
 286  */
 287 static void uhci_async_validate_begin(UHCIState *s)
 288 {
 289     UHCIQueue *queue;
 290
 291     QTAILQ_FOREACH(queue, &s->queues, next) {
 292         queue->valid--;
 293     }
 294 }
 295
 296 /*
 297  * Cancel async packets that are no longer valid
 298  */
 299 static void uhci_async_validate_end(UHCIState *s)
 300 {
 301     UHCIQueue *queue, *n;
 302
 303     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
 304         if (!queue->valid) {
 305             uhci_queue_free(queue, "validate-end");
 306         }
 307     }
 308 }
 309
 310 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
 311 {
 312     UHCIQueue *queue, *n;
 313
 314     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
 315         if (queue->ep->dev == dev) {
 316             uhci_queue_free(queue, "cancel-device");
 317         }
 318     }
 319 }
 320
 321 static void uhci_async_cancel_all(UHCIState *s)
 322 {
 323     UHCIQueue *queue, *nq;
 324
 325     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
 326         uhci_queue_free(queue, "cancel-all");
 327     }
 328 }
 329
 330 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
 331 {
 332     UHCIQueue *queue;
 333     UHCIAsync *async;
 334
 335     QTAILQ_FOREACH(queue, &s->queues, next) {
 336         QTAILQ_FOREACH(async, &queue->asyncs, next) {
 337             if (async->td_addr == td_addr) {
 338                 return async;
 339             }
 340         }
 341     }
 342     return NULL;
 343 }
 344
 345 static void uhci_update_irq(UHCIState *s)
 346 {
 347     int level;
 348     if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
 349         ((s->status2 & 2) && (s->intr & (1 << 3))) ||
 350         ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
 351         ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
 352         (s->status & UHCI_STS_HSERR) ||
 353         (s->status & UHCI_STS_HCPERR)) {
 354         level = 1;
 355     } else {
 356         level = 0;
 357     }
 358     qemu_set_irq(s->dev.irq[s->irq_pin], level);
 359 }
 360
 361 static void uhci_reset(void *opaque)
 362 {
 363     UHCIState *s = opaque;
 364     uint8_t *pci_conf;
 365     int i;
 366     UHCIPort *port;
 367
 368     trace_usb_uhci_reset();
 369
 370     pci_conf = s->dev.config;
 371
 372     pci_conf[0x6a] = 0x01; /* usb clock */
 373     pci_conf[0x6b] = 0x00;
 374     s->cmd = 0;
 375     s->status = 0;
 376     s->status2 = 0;
 377     s->intr = 0;
 378     s->fl_base_addr = 0;
 379     s->sof_timing = 64;
 380
 381     for(i = 0; i < NB_PORTS; i++) {
 382         port = &s->ports[i];
 383         port->ctrl = 0x0080;
 384         if (port->port.dev && port->port.dev->attached) {
 385             usb_port_reset(&port->port);
 386         }
 387     }
 388
 389     uhci_async_cancel_all(s);
 390     qemu_bh_cancel(s->bh);
 391     uhci_update_irq(s);
 392 }
 393
 394 static const VMStateDescription vmstate_uhci_port = {
 395     .name = "uhci port",
 396     .version_id = 1,
 397     .minimum_version_id = 1,
 398     .minimum_version_id_old = 1,
 399     .fields      = (VMStateField []) {
 400         VMSTATE_UINT16(ctrl, UHCIPort),
 401         VMSTATE_END_OF_LIST()
 402     }
 403 };
 404
 405 static int uhci_post_load(void *opaque, int version_id)
 406 {
 407     UHCIState *s = opaque;
 408
 409     if (version_id < 2) {
 410         s->expire_time = qemu_get_clock_ns(vm_clock) +
 411             (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 412     }
 413     return 0;
 414 }
 415
 416 static const VMStateDescription vmstate_uhci = {
 417     .name = "uhci",
 418     .version_id = 2,
 419     .minimum_version_id = 1,
 420     .minimum_version_id_old = 1,
 421     .post_load = uhci_post_load,
 422     .fields      = (VMStateField []) {
 423         VMSTATE_PCI_DEVICE(dev, UHCIState),
 424         VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
 425         VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
 426                              vmstate_uhci_port, UHCIPort),
 427         VMSTATE_UINT16(cmd, UHCIState),
 428         VMSTATE_UINT16(status, UHCIState),
 429         VMSTATE_UINT16(intr, UHCIState),
 430         VMSTATE_UINT16(frnum, UHCIState),
 431         VMSTATE_UINT32(fl_base_addr, UHCIState),
 432         VMSTATE_UINT8(sof_timing, UHCIState),
 433         VMSTATE_UINT8(status2, UHCIState),
 434         VMSTATE_TIMER(frame_timer, UHCIState),
 435         VMSTATE_INT64_V(expire_time, UHCIState, 2),
 436         VMSTATE_END_OF_LIST()
 437     }
 438 };
 439
 440 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 441 {
 442     UHCIState *s = opaque;
 443
 444     addr &= 0x1f;
 445     switch(addr) {
 446     case 0x0c:
 447         s->sof_timing = val;
 448         break;
 449     }
 450 }
 451
 452 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
 453 {
 454     UHCIState *s = opaque;
 455     uint32_t val;
 456
 457     addr &= 0x1f;
 458     switch(addr) {
 459     case 0x0c:
 460         val = s->sof_timing;
 461         break;
 462     default:
 463         val = 0xff;
 464         break;
 465     }
 466     return val;
 467 }
 468
 469 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 470 {
 471     UHCIState *s = opaque;
 472
 473     addr &= 0x1f;
 474     trace_usb_uhci_mmio_writew(addr, val);
 475
 476     switch(addr) {
 477     case 0x00:
 478         if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
 479             /* start frame processing */
 480             trace_usb_uhci_schedule_start();
 481             s->expire_time = qemu_get_clock_ns(vm_clock) +
 482                 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 483             qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
 484             s->status &= ~UHCI_STS_HCHALTED;
 485         } else if (!(val & UHCI_CMD_RS)) {
 486             s->status |= UHCI_STS_HCHALTED;
 487         }
 488         if (val & UHCI_CMD_GRESET) {
 489             UHCIPort *port;
 490             int i;
 491
 492             /* send reset on the USB bus */
 493             for(i = 0; i < NB_PORTS; i++) {
 494                 port = &s->ports[i];
 495                 usb_device_reset(port->port.dev);
 496             }
 497             uhci_reset(s);
 498             return;
 499         }
 500         if (val & UHCI_CMD_HCRESET) {
 501             uhci_reset(s);
 502             return;
 503         }
 504         s->cmd = val;
 505         break;
 506     case 0x02:
 507         s->status &= ~val;
 508         /* XXX: the chip spec is not coherent, so we add a hidden
 509            register to distinguish between IOC and SPD */
 510         if (val & UHCI_STS_USBINT)
 511             s->status2 = 0;
 512         uhci_update_irq(s);
 513         break;
 514     case 0x04:
 515         s->intr = val;
 516         uhci_update_irq(s);
 517         break;
 518     case 0x06:
 519         if (s->status & UHCI_STS_HCHALTED)
 520             s->frnum = val & 0x7ff;
 521         break;
 522     case 0x10 ... 0x1f:
 523         {
 524             UHCIPort *port;
 525             USBDevice *dev;
 526             int n;
 527
 528             n = (addr >> 1) & 7;
 529             if (n >= NB_PORTS)
 530                 return;
 531             port = &s->ports[n];
 532             dev = port->port.dev;
 533             if (dev && dev->attached) {
 534                 /* port reset */
 535                 if ( (val & UHCI_PORT_RESET) &&
 536                      !(port->ctrl & UHCI_PORT_RESET) ) {
 537                     usb_device_reset(dev);
 538                 }
 539             }
 540             port->ctrl &= UHCI_PORT_READ_ONLY;
 541             port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
 542             /* some bits are reset when a '1' is written to them */
 543             port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
 544         }
 545         break;
 546     }
 547 }
 548
 549 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
 550 {
 551     UHCIState *s = opaque;
 552     uint32_t val;
 553
 554     addr &= 0x1f;
 555     switch(addr) {
 556     case 0x00:
 557         val = s->cmd;
 558         break;
 559     case 0x02:
 560         val = s->status;
 561         break;
 562     case 0x04:
 563         val = s->intr;
 564         break;
 565     case 0x06:
 566         val = s->frnum;
 567         break;
 568     case 0x10 ... 0x1f:
 569         {
 570             UHCIPort *port;
 571             int n;
 572             n = (addr >> 1) & 7;
 573             if (n >= NB_PORTS)
 574                 goto read_default;
 575             port = &s->ports[n];
 576             val = port->ctrl;
 577         }
 578         break;
 579     default:
 580     read_default:
 581         val = 0xff7f; /* disabled port */
 582         break;
 583     }
 584
 585     trace_usb_uhci_mmio_readw(addr, val);
 586
 587     return val;
 588 }
 589
 590 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 591 {
 592     UHCIState *s = opaque;
 593
 594     addr &= 0x1f;
 595     trace_usb_uhci_mmio_writel(addr, val);
 596
 597     switch(addr) {
 598     case 0x08:
 599         s->fl_base_addr = val & ~0xfff;
 600         break;
 601     }
 602 }
 603
 604 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
 605 {
 606     UHCIState *s = opaque;
 607     uint32_t val;
 608
 609     addr &= 0x1f;
 610     switch(addr) {
 611     case 0x08:
 612         val = s->fl_base_addr;
 613         break;
 614     default:
 615         val = 0xffffffff;
 616         break;
 617     }
 618     trace_usb_uhci_mmio_readl(addr, val);
 619     return val;
 620 }
 621
 622 /* signal resume if controller suspended */
 623 static void uhci_resume (void *opaque)
 624 {
 625     UHCIState *s = (UHCIState *)opaque;
 626
 627     if (!s)
 628         return;
 629
 630     if (s->cmd & UHCI_CMD_EGSM) {
 631         s->cmd |= UHCI_CMD_FGR;
 632         s->status |= UHCI_STS_RD;
 633         uhci_update_irq(s);
 634     }
 635 }
 636
 637 static void uhci_attach(USBPort *port1)
 638 {
 639     UHCIState *s = port1->opaque;
 640     UHCIPort *port = &s->ports[port1->index];
 641
 642     /* set connect status */
 643     port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
 644
 645     /* update speed */
 646     if (port->port.dev->speed == USB_SPEED_LOW) {
 647         port->ctrl |= UHCI_PORT_LSDA;
 648     } else {
 649         port->ctrl &= ~UHCI_PORT_LSDA;
 650     }
 651
 652     uhci_resume(s);
 653 }
 654
 655 static void uhci_detach(USBPort *port1)
 656 {
 657     UHCIState *s = port1->opaque;
 658     UHCIPort *port = &s->ports[port1->index];
 659
 660     uhci_async_cancel_device(s, port1->dev);
 661
 662     /* set connect status */
 663     if (port->ctrl & UHCI_PORT_CCS) {
 664         port->ctrl &= ~UHCI_PORT_CCS;
 665         port->ctrl |= UHCI_PORT_CSC;
 666     }
 667     /* disable port */
 668     if (port->ctrl & UHCI_PORT_EN) {
 669         port->ctrl &= ~UHCI_PORT_EN;
 670         port->ctrl |= UHCI_PORT_ENC;
 671     }
 672
 673     uhci_resume(s);
 674 }
 675
 676 static void uhci_child_detach(USBPort *port1, USBDevice *child)
 677 {
 678     UHCIState *s = port1->opaque;
 679
 680     uhci_async_cancel_device(s, child);
 681 }
 682
 683 static void uhci_wakeup(USBPort *port1)
 684 {
 685     UHCIState *s = port1->opaque;
 686     UHCIPort *port = &s->ports[port1->index];
 687
 688     if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
 689         port->ctrl |= UHCI_PORT_RD;
 690         uhci_resume(s);
 691     }
 692 }
 693
 694 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
 695 {
 696     USBDevice *dev;
 697     int i;
 698
 699     for (i = 0; i < NB_PORTS; i++) {
 700         UHCIPort *port = &s->ports[i];
 701         if (!(port->ctrl & UHCI_PORT_EN)) {
 702             continue;
 703         }
 704         dev = usb_find_device(&port->port, addr);
 705         if (dev != NULL) {
 706             return dev;
 707         }
 708     }
 709     return NULL;
 710 }
 711
 712 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
 713 {
 714     pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
 715     le32_to_cpus(&td->link);
 716     le32_to_cpus(&td->ctrl);
 717     le32_to_cpus(&td->token);
 718     le32_to_cpus(&td->buffer);
 719 }
 720
 721 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
 722 {
 723     int len = 0, max_len, err, ret;
 724     uint8_t pid;
 725
 726     max_len = ((td->token >> 21) + 1) & 0x7ff;
 727     pid = td->token & 0xff;
 728
 729     ret = async->packet.result;
 730
 731     if (td->ctrl & TD_CTRL_IOS)
 732         td->ctrl &= ~TD_CTRL_ACTIVE;
 733
 734     if (ret < 0)
 735         goto out;
 736
 737     len = async->packet.result;
 738     td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
 739
 740     /* The NAK bit may have been set by a previous frame, so clear it
 741        here.  The docs are somewhat unclear, but win2k relies on this
 742        behavior.  */
 743     td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
 744     if (td->ctrl & TD_CTRL_IOC)
 745         *int_mask |= 0x01;
 746
 747     if (pid == USB_TOKEN_IN) {
 748         if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
 749             *int_mask |= 0x02;
 750             /* short packet: do not update QH */
 751             trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
 752                                                      async->td_addr);
 753             return TD_RESULT_NEXT_QH;
 754         }
 755     }
 756
 757     /* success */
 758     trace_usb_uhci_packet_complete_success(async->queue->token,
 759                                            async->td_addr);
 760     return TD_RESULT_COMPLETE;
 761
 762 out:
 763     switch(ret) {
 764     case USB_RET_NAK:
 765         td->ctrl |= TD_CTRL_NAK;
 766         return TD_RESULT_NEXT_QH;
 767
 768     case USB_RET_STALL:
 769         td->ctrl |= TD_CTRL_STALL;
 770         trace_usb_uhci_packet_complete_stall(async->queue->token,
 771                                              async->td_addr);
 772         err = TD_RESULT_NEXT_QH;
 773         break;
 774
 775     case USB_RET_BABBLE:
 776         td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
 777         /* frame interrupted */
 778         trace_usb_uhci_packet_complete_babble(async->queue->token,
 779                                               async->td_addr);
 780         err = TD_RESULT_STOP_FRAME;
 781         break;
 782
 783     case USB_RET_IOERROR:
 784     case USB_RET_NODEV:
 785     default:
 786         td->ctrl |= TD_CTRL_TIMEOUT;
 787         td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
 788         trace_usb_uhci_packet_complete_error(async->queue->token,
 789                                              async->td_addr);
 790         err = TD_RESULT_NEXT_QH;
 791         break;
 792     }
 793
 794     td->ctrl &= ~TD_CTRL_ACTIVE;
 795     s->status |= UHCI_STS_USBERR;
 796     if (td->ctrl & TD_CTRL_IOC) {
 797         *int_mask |= 0x01;
 798     }
 799     uhci_update_irq(s);
 800     return err;
 801 }
 802
 803 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
 804                           UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
 805 {
 806     int len = 0, max_len;
 807     bool spd;
 808     bool queuing = (q != NULL);
 809     uint8_t pid = td->token & 0xff;
 810     UHCIAsync *async = uhci_async_find_td(s, td_addr);
 811
 812     if (async) {
 813         if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
 814             assert(q == NULL || q == async->queue);
 815             q = async->queue;
 816         } else {
 817             uhci_queue_free(async->queue, "guest re-used pending td");
 818             async = NULL;
 819         }
 820     }
 821
 822     if (q == NULL) {
 823         q = uhci_queue_find(s, td);
 824         if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
 825             uhci_queue_free(q, "guest re-used qh");
 826             q = NULL;
 827         }
 828     }
 829
 830     if (q) {
 831         q->valid = 32;
 832     }
 833
 834     /* Is active ? */
 835     if (!(td->ctrl & TD_CTRL_ACTIVE)) {
 836         if (async) {
 837             /* Guest marked a pending td non-active, cancel the queue */
 838             uhci_queue_free(async->queue, "pending td non-active");
 839         }
 840         /*
 841          * ehci11d spec page 22: "Even if the Active bit in the TD is already
 842          * cleared when the TD is fetched ... an IOC interrupt is generated"
 843          */
 844         if (td->ctrl & TD_CTRL_IOC) {
 845                 *int_mask |= 0x01;
 846         }
 847         return TD_RESULT_NEXT_QH;
 848     }
 849
 850     if (async) {
 851         if (queuing) {
 852             /* we are busy filling the queue, we are not prepared
 853                to consume completed packages then, just leave them
 854                in async state */
 855             return TD_RESULT_ASYNC_CONT;
 856         }
 857         if (!async->done) {
 858             UHCI_TD last_td;
 859             UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head);
 860             /*
 861              * While we are waiting for the current td to complete, the guest
 862              * may have added more tds to the queue. Note we re-read the td
 863              * rather then caching it, as we want to see guest made changes!
 864              */
 865             uhci_read_td(s, &last_td, last->td_addr);
 866             uhci_queue_fill(async->queue, &last_td);
 867
 868             return TD_RESULT_ASYNC_CONT;
 869         }
 870         uhci_async_unlink(async);
 871         goto done;
 872     }
 873
 874     /* Allocate new packet */
 875     if (q == NULL) {
 876         USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
 877         USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
 878         q = uhci_queue_new(s, qh_addr, td, ep);
 879     }
 880     async = uhci_async_alloc(q, td_addr);
 881
 882     max_len = ((td->token >> 21) + 1) & 0x7ff;
 883     spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
 884     usb_packet_setup(&async->packet, pid, q->ep, td_addr, spd,
 885                      (td->ctrl & TD_CTRL_IOC) != 0);
 886     qemu_sglist_add(&async->sgl, td->buffer, max_len);
 887     usb_packet_map(&async->packet, &async->sgl);
 888
 889     switch(pid) {
 890     case USB_TOKEN_OUT:
 891     case USB_TOKEN_SETUP:
 892         len = usb_handle_packet(q->ep->dev, &async->packet);
 893         if (len >= 0)
 894             len = max_len;
 895         break;
 896
 897     case USB_TOKEN_IN:
 898         len = usb_handle_packet(q->ep->dev, &async->packet);
 899         break;
 900
 901     default:
 902         /* invalid pid : frame interrupted */
 903         usb_packet_unmap(&async->packet, &async->sgl);
 904         uhci_async_free(async);
 905         s->status |= UHCI_STS_HCPERR;
 906         uhci_update_irq(s);
 907         return TD_RESULT_STOP_FRAME;
 908     }
 909
 910     if (len == USB_RET_ASYNC) {
 911         uhci_async_link(async);
 912         if (!queuing) {
 913             uhci_queue_fill(q, td);
 914         }
 915         return TD_RESULT_ASYNC_START;
 916     }
 917
 918     async->packet.result = len;
 919
 920 done:
 921     len = uhci_complete_td(s, td, async, int_mask);
 922     usb_packet_unmap(&async->packet, &async->sgl);
 923     uhci_async_free(async);
 924     return len;
 925 }
 926
 927 static void uhci_async_complete(USBPort *port, USBPacket *packet)
 928 {
 929     UHCIAsync *async = container_of(packet, UHCIAsync, packet);
 930     UHCIState *s = async->queue->uhci;
 931
 932     if (packet->result == USB_RET_REMOVE_FROM_QUEUE) {
 933         uhci_async_unlink(async);
 934         uhci_async_cancel(async);
 935         return;
 936     }
 937
 938     async->done = 1;
 939     if (s->frame_bytes < s->frame_bandwidth) {
 940         qemu_bh_schedule(s->bh);
 941     }
 942 }
 943
 944 static int is_valid(uint32_t link)
 945 {
 946     return (link & 1) == 0;
 947 }
 948
 949 static int is_qh(uint32_t link)
 950 {
 951     return (link & 2) != 0;
 952 }
 953
 954 static int depth_first(uint32_t link)
 955 {
 956     return (link & 4) != 0;
 957 }
 958
 959 /* QH DB used for detecting QH loops */
 960 #define UHCI_MAX_QUEUES 128
 961 typedef struct {
 962     uint32_t addr[UHCI_MAX_QUEUES];
 963     int      count;
 964 } QhDb;
 965
 966 static void qhdb_reset(QhDb *db)
 967 {
 968     db->count = 0;
 969 }
 970
 971 /* Add QH to DB. Returns 1 if already present or DB is full. */
 972 static int qhdb_insert(QhDb *db, uint32_t addr)
 973 {
 974     int i;
 975     for (i = 0; i < db->count; i++)
 976         if (db->addr[i] == addr)
 977             return 1;
 978
 979     if (db->count >= UHCI_MAX_QUEUES)
 980         return 1;
 981
 982     db->addr[db->count++] = addr;
 983     return 0;
 984 }
 985
 986 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
 987 {
 988     uint32_t int_mask = 0;
 989     uint32_t plink = td->link;
 990     UHCI_TD ptd;
 991     int ret;
 992
 993     while (is_valid(plink)) {
 994         uhci_read_td(q->uhci, &ptd, plink);
 995         if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
 996             break;
 997         }
 998         if (uhci_queue_token(&ptd) != q->token) {
 999             break;
1000         }
1001         trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
1002         ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
1003         if (ret == TD_RESULT_ASYNC_CONT) {
1004             break;
1005         }
1006         assert(ret == TD_RESULT_ASYNC_START);
1007         assert(int_mask == 0);
1008         plink = ptd.link;
1009     }
1010     usb_device_flush_ep_queue(q->ep->dev, q->ep);
1011 }
1012
1013 static void uhci_process_frame(UHCIState *s)
1014 {
1015     uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
1016     uint32_t curr_qh, td_count = 0;
1017     int cnt, ret;
1018     UHCI_TD td;
1019     UHCI_QH qh;
1020     QhDb qhdb;
1021
1022     frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
1023
1024     pci_dma_read(&s->dev, frame_addr, &link, 4);
1025     le32_to_cpus(&link);
1026
1027     int_mask = 0;
1028     curr_qh  = 0;
1029
1030     qhdb_reset(&qhdb);
1031
1032     for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1033         if (s->frame_bytes >= s->frame_bandwidth) {
1034             /* We've reached the usb 1.1 bandwidth, which is
1035                1280 bytes/frame, stop processing */
1036             trace_usb_uhci_frame_stop_bandwidth();
1037             break;
1038         }
1039         if (is_qh(link)) {
1040             /* QH */
1041             trace_usb_uhci_qh_load(link & ~0xf);
1042
1043             if (qhdb_insert(&qhdb, link)) {
1044                 /*
1045                  * We're going in circles. Which is not a bug because
1046                  * HCD is allowed to do that as part of the BW management.
1047                  *
1048                  * Stop processing here if no transaction has been done
1049                  * since we've been here last time.
1050                  */
1051                 if (td_count == 0) {
1052                     trace_usb_uhci_frame_loop_stop_idle();
1053                     break;
1054                 } else {
1055                     trace_usb_uhci_frame_loop_continue();
1056                     td_count = 0;
1057                     qhdb_reset(&qhdb);
1058                     qhdb_insert(&qhdb, link);
1059                 }
1060             }
1061
1062             pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1063             le32_to_cpus(&qh.link);
1064             le32_to_cpus(&qh.el_link);
1065
1066             if (!is_valid(qh.el_link)) {
1067                 /* QH w/o elements */
1068                 curr_qh = 0;
1069                 link = qh.link;
1070             } else {
1071                 /* QH with elements */
1072                 curr_qh = link;
1073                 link = qh.el_link;
1074             }
1075             continue;
1076         }
1077
1078         /* TD */
1079         uhci_read_td(s, &td, link);
1080         trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1081
1082         old_td_ctrl = td.ctrl;
1083         ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
1084         if (old_td_ctrl != td.ctrl) {
1085             /* update the status bits of the TD */
1086             val = cpu_to_le32(td.ctrl);
1087             pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1088         }
1089
1090         switch (ret) {
1091         case TD_RESULT_STOP_FRAME: /* interrupted frame */
1092             goto out;
1093
1094         case TD_RESULT_NEXT_QH:
1095         case TD_RESULT_ASYNC_CONT:
1096             trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1097             link = curr_qh ? qh.link : td.link;
1098             continue;
1099
1100         case TD_RESULT_ASYNC_START:
1101             trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1102             link = curr_qh ? qh.link : td.link;
1103             continue;
1104
1105         case TD_RESULT_COMPLETE:
1106             trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1107             link = td.link;
1108             td_count++;
1109             s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1110
1111             if (curr_qh) {
1112                 /* update QH element link */
1113                 qh.el_link = link;
1114                 val = cpu_to_le32(qh.el_link);
1115                 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1116
1117                 if (!depth_first(link)) {
1118                     /* done with this QH */
1119                     curr_qh = 0;
1120                     link    = qh.link;
1121                 }
1122             }
1123             break;
1124
1125         default:
1126             assert(!"unknown return code");
1127         }
1128
1129         /* go to the next entry */
1130     }
1131
1132 out:
1133     s->pending_int_mask |= int_mask;
1134 }
1135
1136 static void uhci_bh(void *opaque)
1137 {
1138     UHCIState *s = opaque;
1139     uhci_process_frame(s);
1140 }
1141
1142 static void uhci_frame_timer(void *opaque)
1143 {
1144     UHCIState *s = opaque;
1145
1146     /* prepare the timer for the next frame */
1147     s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1148     s->frame_bytes = 0;
1149     qemu_bh_cancel(s->bh);
1150
1151     if (!(s->cmd & UHCI_CMD_RS)) {
1152         /* Full stop */
1153         trace_usb_uhci_schedule_stop();
1154         qemu_del_timer(s->frame_timer);
1155         uhci_async_cancel_all(s);
1156         /* set hchalted bit in status - UHCI11D 2.1.2 */
1157         s->status |= UHCI_STS_HCHALTED;
1158         return;
1159     }
1160
1161     /* Complete the previous frame */
1162     if (s->pending_int_mask) {
1163         s->status2 |= s->pending_int_mask;
1164         s->status  |= UHCI_STS_USBINT;
1165         uhci_update_irq(s);
1166     }
1167     s->pending_int_mask = 0;
1168
1169     /* Start new frame */
1170     s->frnum = (s->frnum + 1) & 0x7ff;
1171
1172     trace_usb_uhci_frame_start(s->frnum);
1173
1174     uhci_async_validate_begin(s);
1175
1176     uhci_process_frame(s);
1177
1178     uhci_async_validate_end(s);
1179
1180     qemu_mod_timer(s->frame_timer, s->expire_time);
1181 }
1182
1183 static const MemoryRegionPortio uhci_portio[] = {
1184     { 0, 32, 2, .write = uhci_ioport_writew, },
1185     { 0, 32, 2, .read = uhci_ioport_readw, },
1186     { 0, 32, 4, .write = uhci_ioport_writel, },
1187     { 0, 32, 4, .read = uhci_ioport_readl, },
1188     { 0, 32, 1, .write = uhci_ioport_writeb, },
1189     { 0, 32, 1, .read = uhci_ioport_readb, },
1190     PORTIO_END_OF_LIST()
1191 };
1192
1193 static const MemoryRegionOps uhci_ioport_ops = {
1194     .old_portio = uhci_portio,
1195 };
1196
1197 static USBPortOps uhci_port_ops = {
1198     .attach = uhci_attach,
1199     .detach = uhci_detach,
1200     .child_detach = uhci_child_detach,
1201     .wakeup = uhci_wakeup,
1202     .complete = uhci_async_complete,
1203 };
1204
1205 static USBBusOps uhci_bus_ops = {
1206 };
1207
1208 static int usb_uhci_common_initfn(PCIDevice *dev)
1209 {
1210     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1211     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1212     uint8_t *pci_conf = s->dev.config;
1213     int i;
1214
1215     pci_conf[PCI_CLASS_PROG] = 0x00;
1216     /* TODO: reset value should be 0. */
1217     pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1218
1219     switch (pc->device_id) {
1220     case PCI_DEVICE_ID_INTEL_82801I_UHCI1:
1221         s->irq_pin = 0;  /* A */
1222         break;
1223     case PCI_DEVICE_ID_INTEL_82801I_UHCI2:
1224         s->irq_pin = 1;  /* B */
1225         break;
1226     case PCI_DEVICE_ID_INTEL_82801I_UHCI3:
1227         s->irq_pin = 2;  /* C */
1228         break;
1229     default:
1230         s->irq_pin = 3;  /* D */
1231         break;
1232     }
1233     pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1);
1234
1235     if (s->masterbus) {
1236         USBPort *ports[NB_PORTS];
1237         for(i = 0; i < NB_PORTS; i++) {
1238             ports[i] = &s->ports[i].port;
1239         }
1240         if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1241                 s->firstport, s, &uhci_port_ops,
1242                 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1243             return -1;
1244         }
1245     } else {
1246         usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1247         for (i = 0; i < NB_PORTS; i++) {
1248             usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1249                               USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1250         }
1251     }
1252     s->bh = qemu_bh_new(uhci_bh, s);
1253     s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1254     s->num_ports_vmstate = NB_PORTS;
1255     QTAILQ_INIT(&s->queues);
1256
1257     qemu_register_reset(uhci_reset, s);
1258
1259     memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1260     /* Use region 4 for consistency with real hardware.  BSD guests seem
1261        to rely on this.  */
1262     pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1263
1264     return 0;
1265 }
1266
1267 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1268 {
1269     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1270     uint8_t *pci_conf = s->dev.config;
1271
1272     /* USB misc control 1/2 */
1273     pci_set_long(pci_conf + 0x40,0x00001000);
1274     /* PM capability */
1275     pci_set_long(pci_conf + 0x80,0x00020001);
1276     /* USB legacy support  */
1277     pci_set_long(pci_conf + 0xc0,0x00002000);
1278
1279     return usb_uhci_common_initfn(dev);
1280 }
1281
1282 static void usb_uhci_exit(PCIDevice *dev)
1283 {
1284     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1285
1286     memory_region_destroy(&s->io_bar);
1287 }
1288
1289 static Property uhci_properties[] = {
1290     DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1291     DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1292     DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1293     DEFINE_PROP_END_OF_LIST(),
1294 };
1295
1296 static void piix3_uhci_class_init(ObjectClass *klass, void *data)
1297 {
1298     DeviceClass *dc = DEVICE_CLASS(klass);
1299     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1300
1301     k->init = usb_uhci_common_initfn;
1302     k->exit = usb_uhci_exit;
1303     k->vendor_id = PCI_VENDOR_ID_INTEL;
1304     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
1305     k->revision = 0x01;
1306     k->class_id = PCI_CLASS_SERIAL_USB;
1307     dc->vmsd = &vmstate_uhci;
1308     dc->props = uhci_properties;
1309 }
1310
1311 static TypeInfo piix3_uhci_info = {
1312     .name          = "piix3-usb-uhci",
1313     .parent        = TYPE_PCI_DEVICE,
1314     .instance_size = sizeof(UHCIState),
1315     .class_init    = piix3_uhci_class_init,
1316 };
1317
1318 static void piix4_uhci_class_init(ObjectClass *klass, void *data)
1319 {
1320     DeviceClass *dc = DEVICE_CLASS(klass);
1321     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1322
1323     k->init = usb_uhci_common_initfn;
1324     k->exit = usb_uhci_exit;
1325     k->vendor_id = PCI_VENDOR_ID_INTEL;
1326     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
1327     k->revision = 0x01;
1328     k->class_id = PCI_CLASS_SERIAL_USB;
1329     dc->vmsd = &vmstate_uhci;
1330     dc->props = uhci_properties;
1331 }
1332
1333 static TypeInfo piix4_uhci_info = {
1334     .name          = "piix4-usb-uhci",
1335     .parent        = TYPE_PCI_DEVICE,
1336     .instance_size = sizeof(UHCIState),
1337     .class_init    = piix4_uhci_class_init,
1338 };
1339
1340 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data)
1341 {
1342     DeviceClass *dc = DEVICE_CLASS(klass);
1343     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1344
1345     k->init = usb_uhci_vt82c686b_initfn;
1346     k->exit = usb_uhci_exit;
1347     k->vendor_id = PCI_VENDOR_ID_VIA;
1348     k->device_id = PCI_DEVICE_ID_VIA_UHCI;
1349     k->revision = 0x01;
1350     k->class_id = PCI_CLASS_SERIAL_USB;
1351     dc->vmsd = &vmstate_uhci;
1352     dc->props = uhci_properties;
1353 }
1354
1355 static TypeInfo vt82c686b_uhci_info = {
1356     .name          = "vt82c686b-usb-uhci",
1357     .parent        = TYPE_PCI_DEVICE,
1358     .instance_size = sizeof(UHCIState),
1359     .class_init    = vt82c686b_uhci_class_init,
1360 };
1361
1362 static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
1363 {
1364     DeviceClass *dc = DEVICE_CLASS(klass);
1365     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1366
1367     k->init = usb_uhci_common_initfn;
1368     k->vendor_id = PCI_VENDOR_ID_INTEL;
1369     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
1370     k->revision = 0x03;
1371     k->class_id = PCI_CLASS_SERIAL_USB;
1372     dc->vmsd = &vmstate_uhci;
1373     dc->props = uhci_properties;
1374 }
1375
1376 static TypeInfo ich9_uhci1_info = {
1377     .name          = "ich9-usb-uhci1",
1378     .parent        = TYPE_PCI_DEVICE,
1379     .instance_size = sizeof(UHCIState),
1380     .class_init    = ich9_uhci1_class_init,
1381 };
1382
1383 static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
1384 {
1385     DeviceClass *dc = DEVICE_CLASS(klass);
1386     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1387
1388     k->init = usb_uhci_common_initfn;
1389     k->vendor_id = PCI_VENDOR_ID_INTEL;
1390     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
1391     k->revision = 0x03;
1392     k->class_id = PCI_CLASS_SERIAL_USB;
1393     dc->vmsd = &vmstate_uhci;
1394     dc->props = uhci_properties;
1395 }
1396
1397 static TypeInfo ich9_uhci2_info = {
1398     .name          = "ich9-usb-uhci2",
1399     .parent        = TYPE_PCI_DEVICE,
1400     .instance_size = sizeof(UHCIState),
1401     .class_init    = ich9_uhci2_class_init,
1402 };
1403
1404 static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
1405 {
1406     DeviceClass *dc = DEVICE_CLASS(klass);
1407     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1408
1409     k->init = usb_uhci_common_initfn;
1410     k->vendor_id = PCI_VENDOR_ID_INTEL;
1411     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
1412     k->revision = 0x03;
1413     k->class_id = PCI_CLASS_SERIAL_USB;
1414     dc->vmsd = &vmstate_uhci;
1415     dc->props = uhci_properties;
1416 }
1417
1418 static TypeInfo ich9_uhci3_info = {
1419     .name          = "ich9-usb-uhci3",
1420     .parent        = TYPE_PCI_DEVICE,
1421     .instance_size = sizeof(UHCIState),
1422     .class_init    = ich9_uhci3_class_init,
1423 };
1424
1425 static void uhci_register_types(void)
1426 {
1427     type_register_static(&piix3_uhci_info);
1428     type_register_static(&piix4_uhci_info);
1429     type_register_static(&vt82c686b_uhci_info);
1430     type_register_static(&ich9_uhci1_info);
1431     type_register_static(&ich9_uhci2_info);
1432     type_register_static(&ich9_uhci3_info);
1433 }
1434
1435 type_init(uhci_register_types)