hw/usb/hcd-uhci.c

   1 /*
   2  * USB UHCI controller emulation
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Copyright (c) 2008 Max Krasnyansky
   7  *     Magor rewrite of the UHCI data structures parser and frame processor
   8  *     Support for fully async operation and multiple outstanding transactions
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28 #include "hw/hw.h"
  29 #include "hw/usb.h"
  30 #include "hw/pci.h"
  31 #include "qemu-timer.h"
  32 #include "iov.h"
  33 #include "dma.h"
  34 #include "trace.h"
  35
  36 //#define DEBUG
  37 //#define DEBUG_DUMP_DATA
  38
  39 #define UHCI_CMD_FGR      (1 << 4)
  40 #define UHCI_CMD_EGSM     (1 << 3)
  41 #define UHCI_CMD_GRESET   (1 << 2)
  42 #define UHCI_CMD_HCRESET  (1 << 1)
  43 #define UHCI_CMD_RS       (1 << 0)
  44
  45 #define UHCI_STS_HCHALTED (1 << 5)
  46 #define UHCI_STS_HCPERR   (1 << 4)
  47 #define UHCI_STS_HSERR    (1 << 3)
  48 #define UHCI_STS_RD       (1 << 2)
  49 #define UHCI_STS_USBERR   (1 << 1)
  50 #define UHCI_STS_USBINT   (1 << 0)
  51
  52 #define TD_CTRL_SPD     (1 << 29)
  53 #define TD_CTRL_ERROR_SHIFT  27
  54 #define TD_CTRL_IOS     (1 << 25)
  55 #define TD_CTRL_IOC     (1 << 24)
  56 #define TD_CTRL_ACTIVE  (1 << 23)
  57 #define TD_CTRL_STALL   (1 << 22)
  58 #define TD_CTRL_BABBLE  (1 << 20)
  59 #define TD_CTRL_NAK     (1 << 19)
  60 #define TD_CTRL_TIMEOUT (1 << 18)
  61
  62 #define UHCI_PORT_SUSPEND (1 << 12)
  63 #define UHCI_PORT_RESET (1 << 9)
  64 #define UHCI_PORT_LSDA  (1 << 8)
  65 #define UHCI_PORT_RD    (1 << 6)
  66 #define UHCI_PORT_ENC   (1 << 3)
  67 #define UHCI_PORT_EN    (1 << 2)
  68 #define UHCI_PORT_CSC   (1 << 1)
  69 #define UHCI_PORT_CCS   (1 << 0)
  70
  71 #define UHCI_PORT_READ_ONLY    (0x1bb)
  72 #define UHCI_PORT_WRITE_CLEAR  (UHCI_PORT_CSC | UHCI_PORT_ENC)
  73
  74 #define FRAME_TIMER_FREQ 1000
  75
  76 #define FRAME_MAX_LOOPS  256
  77
  78 #define NB_PORTS 2
  79
  80 enum {
  81     TD_RESULT_STOP_FRAME = 10,
  82     TD_RESULT_COMPLETE,
  83     TD_RESULT_NEXT_QH,
  84     TD_RESULT_ASYNC_START,
  85     TD_RESULT_ASYNC_CONT,
  86 };
  87
  88 typedef struct UHCIState UHCIState;
  89 typedef struct UHCIAsync UHCIAsync;
  90 typedef struct UHCIQueue UHCIQueue;
  91
  92 /*
  93  * Pending async transaction.
  94  * 'packet' must be the first field because completion
  95  * handler does "(UHCIAsync *) pkt" cast.
  96  */
  97
  98 struct UHCIAsync {
  99     USBPacket packet;
 100     QEMUSGList sgl;
 101     UHCIQueue *queue;
 102     QTAILQ_ENTRY(UHCIAsync) next;
 103     uint32_t  td;
 104     uint8_t   isoc;
 105     uint8_t   done;
 106 };
 107
 108 struct UHCIQueue {
 109     uint32_t  token;
 110     UHCIState *uhci;
 111     QTAILQ_ENTRY(UHCIQueue) next;
 112     QTAILQ_HEAD(, UHCIAsync) asyncs;
 113     int8_t    valid;
 114 };
 115
 116 typedef struct UHCIPort {
 117     USBPort port;
 118     uint16_t ctrl;
 119 } UHCIPort;
 120
 121 struct UHCIState {
 122     PCIDevice dev;
 123     MemoryRegion io_bar;
 124     USBBus bus; /* Note unused when we're a companion controller */
 125     uint16_t cmd; /* cmd register */
 126     uint16_t status;
 127     uint16_t intr; /* interrupt enable register */
 128     uint16_t frnum; /* frame number */
 129     uint32_t fl_base_addr; /* frame list base address */
 130     uint8_t sof_timing;
 131     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
 132     int64_t expire_time;
 133     QEMUTimer *frame_timer;
 134     QEMUBH *bh;
 135     uint32_t frame_bytes;
 136     uint32_t frame_bandwidth;
 137     UHCIPort ports[NB_PORTS];
 138
 139     /* Interrupts that should be raised at the end of the current frame.  */
 140     uint32_t pending_int_mask;
 141
 142     /* Active packets */
 143     QTAILQ_HEAD(, UHCIQueue) queues;
 144     uint8_t num_ports_vmstate;
 145
 146     /* Properties */
 147     char *masterbus;
 148     uint32_t firstport;
 149 };
 150
 151 typedef struct UHCI_TD {
 152     uint32_t link;
 153     uint32_t ctrl; /* see TD_CTRL_xxx */
 154     uint32_t token;
 155     uint32_t buffer;
 156 } UHCI_TD;
 157
 158 typedef struct UHCI_QH {
 159     uint32_t link;
 160     uint32_t el_link;
 161 } UHCI_QH;
 162
 163 static inline int32_t uhci_queue_token(UHCI_TD *td)
 164 {
 165     /* covers ep, dev, pid -> identifies the endpoint */
 166     return td->token & 0x7ffff;
 167 }
 168
 169 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td)
 170 {
 171     uint32_t token = uhci_queue_token(td);
 172     UHCIQueue *queue;
 173
 174     QTAILQ_FOREACH(queue, &s->queues, next) {
 175         if (queue->token == token) {
 176             return queue;
 177         }
 178     }
 179
 180     queue = g_new0(UHCIQueue, 1);
 181     queue->uhci = s;
 182     queue->token = token;
 183     QTAILQ_INIT(&queue->asyncs);
 184     QTAILQ_INSERT_HEAD(&s->queues, queue, next);
 185     trace_usb_uhci_queue_add(queue->token);
 186     return queue;
 187 }
 188
 189 static void uhci_queue_free(UHCIQueue *queue)
 190 {
 191     UHCIState *s = queue->uhci;
 192
 193     trace_usb_uhci_queue_del(queue->token);
 194     QTAILQ_REMOVE(&s->queues, queue, next);
 195     g_free(queue);
 196 }
 197
 198 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr)
 199 {
 200     UHCIAsync *async = g_new0(UHCIAsync, 1);
 201
 202     async->queue = queue;
 203     async->td = addr;
 204     usb_packet_init(&async->packet);
 205     pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
 206     trace_usb_uhci_packet_add(async->queue->token, async->td);
 207
 208     return async;
 209 }
 210
 211 static void uhci_async_free(UHCIAsync *async)
 212 {
 213     trace_usb_uhci_packet_del(async->queue->token, async->td);
 214     usb_packet_cleanup(&async->packet);
 215     qemu_sglist_destroy(&async->sgl);
 216     g_free(async);
 217 }
 218
 219 static void uhci_async_link(UHCIAsync *async)
 220 {
 221     UHCIQueue *queue = async->queue;
 222     QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
 223     trace_usb_uhci_packet_link_async(async->queue->token, async->td);
 224 }
 225
 226 static void uhci_async_unlink(UHCIAsync *async)
 227 {
 228     UHCIQueue *queue = async->queue;
 229     QTAILQ_REMOVE(&queue->asyncs, async, next);
 230     trace_usb_uhci_packet_unlink_async(async->queue->token, async->td);
 231 }
 232
 233 static void uhci_async_cancel(UHCIAsync *async)
 234 {
 235     trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done);
 236     if (!async->done)
 237         usb_cancel_packet(&async->packet);
 238     uhci_async_free(async);
 239 }
 240
 241 /*
 242  * Mark all outstanding async packets as invalid.
 243  * This is used for canceling them when TDs are removed by the HCD.
 244  */
 245 static void uhci_async_validate_begin(UHCIState *s)
 246 {
 247     UHCIQueue *queue;
 248
 249     QTAILQ_FOREACH(queue, &s->queues, next) {
 250         queue->valid--;
 251     }
 252 }
 253
 254 /*
 255  * Cancel async packets that are no longer valid
 256  */
 257 static void uhci_async_validate_end(UHCIState *s)
 258 {
 259     UHCIQueue *queue, *n;
 260     UHCIAsync *async;
 261
 262     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
 263         if (queue->valid > 0) {
 264             continue;
 265         }
 266         while (!QTAILQ_EMPTY(&queue->asyncs)) {
 267             async = QTAILQ_FIRST(&queue->asyncs);
 268             uhci_async_unlink(async);
 269             uhci_async_cancel(async);
 270         }
 271         uhci_queue_free(queue);
 272     }
 273 }
 274
 275 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
 276 {
 277     UHCIQueue *queue;
 278     UHCIAsync *curr, *n;
 279
 280     QTAILQ_FOREACH(queue, &s->queues, next) {
 281         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 282             if (!usb_packet_is_inflight(&curr->packet) ||
 283                 curr->packet.ep->dev != dev) {
 284                 continue;
 285             }
 286             uhci_async_unlink(curr);
 287             uhci_async_cancel(curr);
 288         }
 289     }
 290 }
 291
 292 static void uhci_async_cancel_all(UHCIState *s)
 293 {
 294     UHCIQueue *queue;
 295     UHCIAsync *curr, *n;
 296
 297     QTAILQ_FOREACH(queue, &s->queues, next) {
 298         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 299             uhci_async_unlink(curr);
 300             uhci_async_cancel(curr);
 301         }
 302         uhci_queue_free(queue);
 303     }
 304 }
 305
 306 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td)
 307 {
 308     uint32_t token = uhci_queue_token(td);
 309     UHCIQueue *queue;
 310     UHCIAsync *async;
 311
 312     QTAILQ_FOREACH(queue, &s->queues, next) {
 313         if (queue->token == token) {
 314             break;
 315         }
 316     }
 317     if (queue == NULL) {
 318         return NULL;
 319     }
 320
 321     QTAILQ_FOREACH(async, &queue->asyncs, next) {
 322         if (async->td == addr) {
 323             return async;
 324         }
 325     }
 326
 327     return NULL;
 328 }
 329
 330 static void uhci_update_irq(UHCIState *s)
 331 {
 332     int level;
 333     if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
 334         ((s->status2 & 2) && (s->intr & (1 << 3))) ||
 335         ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
 336         ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
 337         (s->status & UHCI_STS_HSERR) ||
 338         (s->status & UHCI_STS_HCPERR)) {
 339         level = 1;
 340     } else {
 341         level = 0;
 342     }
 343     qemu_set_irq(s->dev.irq[3], level);
 344 }
 345
 346 static void uhci_reset(void *opaque)
 347 {
 348     UHCIState *s = opaque;
 349     uint8_t *pci_conf;
 350     int i;
 351     UHCIPort *port;
 352
 353     trace_usb_uhci_reset();
 354
 355     pci_conf = s->dev.config;
 356
 357     pci_conf[0x6a] = 0x01; /* usb clock */
 358     pci_conf[0x6b] = 0x00;
 359     s->cmd = 0;
 360     s->status = 0;
 361     s->status2 = 0;
 362     s->intr = 0;
 363     s->fl_base_addr = 0;
 364     s->sof_timing = 64;
 365
 366     for(i = 0; i < NB_PORTS; i++) {
 367         port = &s->ports[i];
 368         port->ctrl = 0x0080;
 369         if (port->port.dev && port->port.dev->attached) {
 370             usb_port_reset(&port->port);
 371         }
 372     }
 373
 374     uhci_async_cancel_all(s);
 375     qemu_bh_cancel(s->bh);
 376     uhci_update_irq(s);
 377 }
 378
 379 static void uhci_pre_save(void *opaque)
 380 {
 381     UHCIState *s = opaque;
 382
 383     uhci_async_cancel_all(s);
 384 }
 385
 386 static const VMStateDescription vmstate_uhci_port = {
 387     .name = "uhci port",
 388     .version_id = 1,
 389     .minimum_version_id = 1,
 390     .minimum_version_id_old = 1,
 391     .fields      = (VMStateField []) {
 392         VMSTATE_UINT16(ctrl, UHCIPort),
 393         VMSTATE_END_OF_LIST()
 394     }
 395 };
 396
 397 static const VMStateDescription vmstate_uhci = {
 398     .name = "uhci",
 399     .version_id = 2,
 400     .minimum_version_id = 1,
 401     .minimum_version_id_old = 1,
 402     .pre_save = uhci_pre_save,
 403     .fields      = (VMStateField []) {
 404         VMSTATE_PCI_DEVICE(dev, UHCIState),
 405         VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
 406         VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
 407                              vmstate_uhci_port, UHCIPort),
 408         VMSTATE_UINT16(cmd, UHCIState),
 409         VMSTATE_UINT16(status, UHCIState),
 410         VMSTATE_UINT16(intr, UHCIState),
 411         VMSTATE_UINT16(frnum, UHCIState),
 412         VMSTATE_UINT32(fl_base_addr, UHCIState),
 413         VMSTATE_UINT8(sof_timing, UHCIState),
 414         VMSTATE_UINT8(status2, UHCIState),
 415         VMSTATE_TIMER(frame_timer, UHCIState),
 416         VMSTATE_INT64_V(expire_time, UHCIState, 2),
 417         VMSTATE_END_OF_LIST()
 418     }
 419 };
 420
 421 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 422 {
 423     UHCIState *s = opaque;
 424
 425     addr &= 0x1f;
 426     switch(addr) {
 427     case 0x0c:
 428         s->sof_timing = val;
 429         break;
 430     }
 431 }
 432
 433 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
 434 {
 435     UHCIState *s = opaque;
 436     uint32_t val;
 437
 438     addr &= 0x1f;
 439     switch(addr) {
 440     case 0x0c:
 441         val = s->sof_timing;
 442         break;
 443     default:
 444         val = 0xff;
 445         break;
 446     }
 447     return val;
 448 }
 449
 450 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 451 {
 452     UHCIState *s = opaque;
 453
 454     addr &= 0x1f;
 455     trace_usb_uhci_mmio_writew(addr, val);
 456
 457     switch(addr) {
 458     case 0x00:
 459         if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
 460             /* start frame processing */
 461             trace_usb_uhci_schedule_start();
 462             s->expire_time = qemu_get_clock_ns(vm_clock) +
 463                 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 464             qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
 465             s->status &= ~UHCI_STS_HCHALTED;
 466         } else if (!(val & UHCI_CMD_RS)) {
 467             s->status |= UHCI_STS_HCHALTED;
 468         }
 469         if (val & UHCI_CMD_GRESET) {
 470             UHCIPort *port;
 471             int i;
 472
 473             /* send reset on the USB bus */
 474             for(i = 0; i < NB_PORTS; i++) {
 475                 port = &s->ports[i];
 476                 usb_device_reset(port->port.dev);
 477             }
 478             uhci_reset(s);
 479             return;
 480         }
 481         if (val & UHCI_CMD_HCRESET) {
 482             uhci_reset(s);
 483             return;
 484         }
 485         s->cmd = val;
 486         break;
 487     case 0x02:
 488         s->status &= ~val;
 489         /* XXX: the chip spec is not coherent, so we add a hidden
 490            register to distinguish between IOC and SPD */
 491         if (val & UHCI_STS_USBINT)
 492             s->status2 = 0;
 493         uhci_update_irq(s);
 494         break;
 495     case 0x04:
 496         s->intr = val;
 497         uhci_update_irq(s);
 498         break;
 499     case 0x06:
 500         if (s->status & UHCI_STS_HCHALTED)
 501             s->frnum = val & 0x7ff;
 502         break;
 503     case 0x10 ... 0x1f:
 504         {
 505             UHCIPort *port;
 506             USBDevice *dev;
 507             int n;
 508
 509             n = (addr >> 1) & 7;
 510             if (n >= NB_PORTS)
 511                 return;
 512             port = &s->ports[n];
 513             dev = port->port.dev;
 514             if (dev && dev->attached) {
 515                 /* port reset */
 516                 if ( (val & UHCI_PORT_RESET) &&
 517                      !(port->ctrl & UHCI_PORT_RESET) ) {
 518                     usb_device_reset(dev);
 519                 }
 520             }
 521             port->ctrl &= UHCI_PORT_READ_ONLY;
 522             port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
 523             /* some bits are reset when a '1' is written to them */
 524             port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
 525         }
 526         break;
 527     }
 528 }
 529
 530 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
 531 {
 532     UHCIState *s = opaque;
 533     uint32_t val;
 534
 535     addr &= 0x1f;
 536     switch(addr) {
 537     case 0x00:
 538         val = s->cmd;
 539         break;
 540     case 0x02:
 541         val = s->status;
 542         break;
 543     case 0x04:
 544         val = s->intr;
 545         break;
 546     case 0x06:
 547         val = s->frnum;
 548         break;
 549     case 0x10 ... 0x1f:
 550         {
 551             UHCIPort *port;
 552             int n;
 553             n = (addr >> 1) & 7;
 554             if (n >= NB_PORTS)
 555                 goto read_default;
 556             port = &s->ports[n];
 557             val = port->ctrl;
 558         }
 559         break;
 560     default:
 561     read_default:
 562         val = 0xff7f; /* disabled port */
 563         break;
 564     }
 565
 566     trace_usb_uhci_mmio_readw(addr, val);
 567
 568     return val;
 569 }
 570
 571 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 572 {
 573     UHCIState *s = opaque;
 574
 575     addr &= 0x1f;
 576     trace_usb_uhci_mmio_writel(addr, val);
 577
 578     switch(addr) {
 579     case 0x08:
 580         s->fl_base_addr = val & ~0xfff;
 581         break;
 582     }
 583 }
 584
 585 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
 586 {
 587     UHCIState *s = opaque;
 588     uint32_t val;
 589
 590     addr &= 0x1f;
 591     switch(addr) {
 592     case 0x08:
 593         val = s->fl_base_addr;
 594         break;
 595     default:
 596         val = 0xffffffff;
 597         break;
 598     }
 599     trace_usb_uhci_mmio_readl(addr, val);
 600     return val;
 601 }
 602
 603 /* signal resume if controller suspended */
 604 static void uhci_resume (void *opaque)
 605 {
 606     UHCIState *s = (UHCIState *)opaque;
 607
 608     if (!s)
 609         return;
 610
 611     if (s->cmd & UHCI_CMD_EGSM) {
 612         s->cmd |= UHCI_CMD_FGR;
 613         s->status |= UHCI_STS_RD;
 614         uhci_update_irq(s);
 615     }
 616 }
 617
 618 static void uhci_attach(USBPort *port1)
 619 {
 620     UHCIState *s = port1->opaque;
 621     UHCIPort *port = &s->ports[port1->index];
 622
 623     /* set connect status */
 624     port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
 625
 626     /* update speed */
 627     if (port->port.dev->speed == USB_SPEED_LOW) {
 628         port->ctrl |= UHCI_PORT_LSDA;
 629     } else {
 630         port->ctrl &= ~UHCI_PORT_LSDA;
 631     }
 632
 633     uhci_resume(s);
 634 }
 635
 636 static void uhci_detach(USBPort *port1)
 637 {
 638     UHCIState *s = port1->opaque;
 639     UHCIPort *port = &s->ports[port1->index];
 640
 641     uhci_async_cancel_device(s, port1->dev);
 642
 643     /* set connect status */
 644     if (port->ctrl & UHCI_PORT_CCS) {
 645         port->ctrl &= ~UHCI_PORT_CCS;
 646         port->ctrl |= UHCI_PORT_CSC;
 647     }
 648     /* disable port */
 649     if (port->ctrl & UHCI_PORT_EN) {
 650         port->ctrl &= ~UHCI_PORT_EN;
 651         port->ctrl |= UHCI_PORT_ENC;
 652     }
 653
 654     uhci_resume(s);
 655 }
 656
 657 static void uhci_child_detach(USBPort *port1, USBDevice *child)
 658 {
 659     UHCIState *s = port1->opaque;
 660
 661     uhci_async_cancel_device(s, child);
 662 }
 663
 664 static void uhci_wakeup(USBPort *port1)
 665 {
 666     UHCIState *s = port1->opaque;
 667     UHCIPort *port = &s->ports[port1->index];
 668
 669     if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
 670         port->ctrl |= UHCI_PORT_RD;
 671         uhci_resume(s);
 672     }
 673 }
 674
 675 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
 676 {
 677     USBDevice *dev;
 678     int i;
 679
 680     for (i = 0; i < NB_PORTS; i++) {
 681         UHCIPort *port = &s->ports[i];
 682         if (!(port->ctrl & UHCI_PORT_EN)) {
 683             continue;
 684         }
 685         dev = usb_find_device(&port->port, addr);
 686         if (dev != NULL) {
 687             return dev;
 688         }
 689     }
 690     return NULL;
 691 }
 692
 693 static void uhci_async_complete(USBPort *port, USBPacket *packet);
 694 static void uhci_process_frame(UHCIState *s);
 695
 696 /* return -1 if fatal error (frame must be stopped)
 697           0 if TD successful
 698           1 if TD unsuccessful or inactive
 699 */
 700 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
 701 {
 702     int len = 0, max_len, err, ret;
 703     uint8_t pid;
 704
 705     max_len = ((td->token >> 21) + 1) & 0x7ff;
 706     pid = td->token & 0xff;
 707
 708     ret = async->packet.result;
 709
 710     if (td->ctrl & TD_CTRL_IOS)
 711         td->ctrl &= ~TD_CTRL_ACTIVE;
 712
 713     if (ret < 0)
 714         goto out;
 715
 716     len = async->packet.result;
 717     td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
 718
 719     /* The NAK bit may have been set by a previous frame, so clear it
 720        here.  The docs are somewhat unclear, but win2k relies on this
 721        behavior.  */
 722     td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
 723     if (td->ctrl & TD_CTRL_IOC)
 724         *int_mask |= 0x01;
 725
 726     if (pid == USB_TOKEN_IN) {
 727         if (len > max_len) {
 728             ret = USB_RET_BABBLE;
 729             goto out;
 730         }
 731
 732         if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
 733             *int_mask |= 0x02;
 734             /* short packet: do not update QH */
 735             trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
 736                                                     async->td);
 737             return TD_RESULT_NEXT_QH;
 738         }
 739     }
 740
 741     /* success */
 742     trace_usb_uhci_packet_complete_success(async->queue->token, async->td);
 743     return TD_RESULT_COMPLETE;
 744
 745 out:
 746     switch(ret) {
 747     case USB_RET_STALL:
 748         td->ctrl |= TD_CTRL_STALL;
 749         td->ctrl &= ~TD_CTRL_ACTIVE;
 750         s->status |= UHCI_STS_USBERR;
 751         if (td->ctrl & TD_CTRL_IOC) {
 752             *int_mask |= 0x01;
 753         }
 754         uhci_update_irq(s);
 755         trace_usb_uhci_packet_complete_stall(async->queue->token, async->td);
 756         return TD_RESULT_NEXT_QH;
 757
 758     case USB_RET_BABBLE:
 759         td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
 760         td->ctrl &= ~TD_CTRL_ACTIVE;
 761         s->status |= UHCI_STS_USBERR;
 762         if (td->ctrl & TD_CTRL_IOC) {
 763             *int_mask |= 0x01;
 764         }
 765         uhci_update_irq(s);
 766         /* frame interrupted */
 767         trace_usb_uhci_packet_complete_babble(async->queue->token, async->td);
 768         return TD_RESULT_STOP_FRAME;
 769
 770     case USB_RET_NAK:
 771         td->ctrl |= TD_CTRL_NAK;
 772         if (pid == USB_TOKEN_SETUP)
 773             break;
 774         return TD_RESULT_NEXT_QH;
 775
 776     case USB_RET_IOERROR:
 777     case USB_RET_NODEV:
 778     default:
 779         break;
 780     }
 781
 782     /* Retry the TD if error count is not zero */
 783
 784     td->ctrl |= TD_CTRL_TIMEOUT;
 785     err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
 786     if (err != 0) {
 787         err--;
 788         if (err == 0) {
 789             td->ctrl &= ~TD_CTRL_ACTIVE;
 790             s->status |= UHCI_STS_USBERR;
 791             if (td->ctrl & TD_CTRL_IOC)
 792                 *int_mask |= 0x01;
 793             uhci_update_irq(s);
 794             trace_usb_uhci_packet_complete_error(async->queue->token,
 795                                                  async->td);
 796         }
 797     }
 798     td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
 799         (err << TD_CTRL_ERROR_SHIFT);
 800     return TD_RESULT_NEXT_QH;
 801 }
 802
 803 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td,
 804                           uint32_t *int_mask, bool queuing)
 805 {
 806     UHCIAsync *async;
 807     int len = 0, max_len;
 808     uint8_t pid;
 809     USBDevice *dev;
 810     USBEndpoint *ep;
 811
 812     /* Is active ? */
 813     if (!(td->ctrl & TD_CTRL_ACTIVE))
 814         return TD_RESULT_NEXT_QH;
 815
 816     async = uhci_async_find_td(s, addr, td);
 817     if (async) {
 818         /* Already submitted */
 819         async->queue->valid = 32;
 820
 821         if (!async->done)
 822             return TD_RESULT_ASYNC_CONT;
 823         if (queuing) {
 824             /* we are busy filling the queue, we are not prepared
 825                to consume completed packages then, just leave them
 826                in async state */
 827             return TD_RESULT_ASYNC_CONT;
 828         }
 829
 830         uhci_async_unlink(async);
 831         goto done;
 832     }
 833
 834     /* Allocate new packet */
 835     async = uhci_async_alloc(uhci_queue_get(s, td), addr);
 836
 837     /* valid needs to be large enough to handle 10 frame delay
 838      * for initial isochronous requests
 839      */
 840     async->queue->valid = 32;
 841     async->isoc  = td->ctrl & TD_CTRL_IOS;
 842
 843     max_len = ((td->token >> 21) + 1) & 0x7ff;
 844     pid = td->token & 0xff;
 845
 846     dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
 847     ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
 848     usb_packet_setup(&async->packet, pid, ep);
 849     qemu_sglist_add(&async->sgl, td->buffer, max_len);
 850     usb_packet_map(&async->packet, &async->sgl);
 851
 852     switch(pid) {
 853     case USB_TOKEN_OUT:
 854     case USB_TOKEN_SETUP:
 855         len = usb_handle_packet(dev, &async->packet);
 856         if (len >= 0)
 857             len = max_len;
 858         break;
 859
 860     case USB_TOKEN_IN:
 861         len = usb_handle_packet(dev, &async->packet);
 862         break;
 863
 864     default:
 865         /* invalid pid : frame interrupted */
 866         uhci_async_free(async);
 867         s->status |= UHCI_STS_HCPERR;
 868         uhci_update_irq(s);
 869         return TD_RESULT_STOP_FRAME;
 870     }
 871
 872     if (len == USB_RET_ASYNC) {
 873         uhci_async_link(async);
 874         return TD_RESULT_ASYNC_START;
 875     }
 876
 877     async->packet.result = len;
 878
 879 done:
 880     len = uhci_complete_td(s, td, async, int_mask);
 881     usb_packet_unmap(&async->packet);
 882     uhci_async_free(async);
 883     return len;
 884 }
 885
 886 static void uhci_async_complete(USBPort *port, USBPacket *packet)
 887 {
 888     UHCIAsync *async = container_of(packet, UHCIAsync, packet);
 889     UHCIState *s = async->queue->uhci;
 890
 891     if (async->isoc) {
 892         UHCI_TD td;
 893         uint32_t link = async->td;
 894         uint32_t int_mask = 0, val;
 895
 896         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
 897         le32_to_cpus(&td.link);
 898         le32_to_cpus(&td.ctrl);
 899         le32_to_cpus(&td.token);
 900         le32_to_cpus(&td.buffer);
 901
 902         uhci_async_unlink(async);
 903         uhci_complete_td(s, &td, async, &int_mask);
 904         s->pending_int_mask |= int_mask;
 905
 906         /* update the status bits of the TD */
 907         val = cpu_to_le32(td.ctrl);
 908         pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
 909         uhci_async_free(async);
 910     } else {
 911         async->done = 1;
 912         if (s->frame_bytes < s->frame_bandwidth) {
 913             qemu_bh_schedule(s->bh);
 914         }
 915     }
 916 }
 917
 918 static int is_valid(uint32_t link)
 919 {
 920     return (link & 1) == 0;
 921 }
 922
 923 static int is_qh(uint32_t link)
 924 {
 925     return (link & 2) != 0;
 926 }
 927
 928 static int depth_first(uint32_t link)
 929 {
 930     return (link & 4) != 0;
 931 }
 932
 933 /* QH DB used for detecting QH loops */
 934 #define UHCI_MAX_QUEUES 128
 935 typedef struct {
 936     uint32_t addr[UHCI_MAX_QUEUES];
 937     int      count;
 938 } QhDb;
 939
 940 static void qhdb_reset(QhDb *db)
 941 {
 942     db->count = 0;
 943 }
 944
 945 /* Add QH to DB. Returns 1 if already present or DB is full. */
 946 static int qhdb_insert(QhDb *db, uint32_t addr)
 947 {
 948     int i;
 949     for (i = 0; i < db->count; i++)
 950         if (db->addr[i] == addr)
 951             return 1;
 952
 953     if (db->count >= UHCI_MAX_QUEUES)
 954         return 1;
 955
 956     db->addr[db->count++] = addr;
 957     return 0;
 958 }
 959
 960 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td)
 961 {
 962     uint32_t int_mask = 0;
 963     uint32_t plink = td->link;
 964     uint32_t token = uhci_queue_token(td);
 965     UHCI_TD ptd;
 966     int ret;
 967
 968     while (is_valid(plink)) {
 969         pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd));
 970         le32_to_cpus(&ptd.link);
 971         le32_to_cpus(&ptd.ctrl);
 972         le32_to_cpus(&ptd.token);
 973         le32_to_cpus(&ptd.buffer);
 974         if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
 975             break;
 976         }
 977         if (uhci_queue_token(&ptd) != token) {
 978             break;
 979         }
 980         trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
 981         ret = uhci_handle_td(s, plink, &ptd, &int_mask, true);
 982         if (ret == TD_RESULT_ASYNC_CONT) {
 983             break;
 984         }
 985         assert(ret == TD_RESULT_ASYNC_START);
 986         assert(int_mask == 0);
 987         plink = ptd.link;
 988     }
 989 }
 990
 991 static void uhci_process_frame(UHCIState *s)
 992 {
 993     uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
 994     uint32_t curr_qh, td_count = 0;
 995     int cnt, ret;
 996     UHCI_TD td;
 997     UHCI_QH qh;
 998     QhDb qhdb;
 999
1000     frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
1001
1002     pci_dma_read(&s->dev, frame_addr, &link, 4);
1003     le32_to_cpus(&link);
1004
1005     int_mask = 0;
1006     curr_qh  = 0;
1007
1008     qhdb_reset(&qhdb);
1009
1010     for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1011         if (s->frame_bytes >= s->frame_bandwidth) {
1012             /* We've reached the usb 1.1 bandwidth, which is
1013                1280 bytes/frame, stop processing */
1014             trace_usb_uhci_frame_stop_bandwidth();
1015             break;
1016         }
1017         if (is_qh(link)) {
1018             /* QH */
1019             trace_usb_uhci_qh_load(link & ~0xf);
1020
1021             if (qhdb_insert(&qhdb, link)) {
1022                 /*
1023                  * We're going in circles. Which is not a bug because
1024                  * HCD is allowed to do that as part of the BW management.
1025                  *
1026                  * Stop processing here if no transaction has been done
1027                  * since we've been here last time.
1028                  */
1029                 if (td_count == 0) {
1030                     trace_usb_uhci_frame_loop_stop_idle();
1031                     break;
1032                 } else {
1033                     trace_usb_uhci_frame_loop_continue();
1034                     td_count = 0;
1035                     qhdb_reset(&qhdb);
1036                     qhdb_insert(&qhdb, link);
1037                 }
1038             }
1039
1040             pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1041             le32_to_cpus(&qh.link);
1042             le32_to_cpus(&qh.el_link);
1043
1044             if (!is_valid(qh.el_link)) {
1045                 /* QH w/o elements */
1046                 curr_qh = 0;
1047                 link = qh.link;
1048             } else {
1049                 /* QH with elements */
1050                 curr_qh = link;
1051                 link = qh.el_link;
1052             }
1053             continue;
1054         }
1055
1056         /* TD */
1057         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
1058         le32_to_cpus(&td.link);
1059         le32_to_cpus(&td.ctrl);
1060         le32_to_cpus(&td.token);
1061         le32_to_cpus(&td.buffer);
1062         trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1063
1064         old_td_ctrl = td.ctrl;
1065         ret = uhci_handle_td(s, link, &td, &int_mask, false);
1066         if (old_td_ctrl != td.ctrl) {
1067             /* update the status bits of the TD */
1068             val = cpu_to_le32(td.ctrl);
1069             pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1070         }
1071
1072         switch (ret) {
1073         case TD_RESULT_STOP_FRAME: /* interrupted frame */
1074             goto out;
1075
1076         case TD_RESULT_NEXT_QH:
1077         case TD_RESULT_ASYNC_CONT:
1078             trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1079             link = curr_qh ? qh.link : td.link;
1080             continue;
1081
1082         case TD_RESULT_ASYNC_START:
1083             trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1084             if (is_valid(td.link)) {
1085                 uhci_fill_queue(s, &td);
1086             }
1087             link = curr_qh ? qh.link : td.link;
1088             continue;
1089
1090         case TD_RESULT_COMPLETE:
1091             trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1092             link = td.link;
1093             td_count++;
1094             s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1095
1096             if (curr_qh) {
1097                 /* update QH element link */
1098                 qh.el_link = link;
1099                 val = cpu_to_le32(qh.el_link);
1100                 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1101
1102                 if (!depth_first(link)) {
1103                     /* done with this QH */
1104                     curr_qh = 0;
1105                     link    = qh.link;
1106                 }
1107             }
1108             break;
1109
1110         default:
1111             assert(!"unknown return code");
1112         }
1113
1114         /* go to the next entry */
1115     }
1116
1117 out:
1118     s->pending_int_mask |= int_mask;
1119 }
1120
1121 static void uhci_bh(void *opaque)
1122 {
1123     UHCIState *s = opaque;
1124     uhci_process_frame(s);
1125 }
1126
1127 static void uhci_frame_timer(void *opaque)
1128 {
1129     UHCIState *s = opaque;
1130
1131     /* prepare the timer for the next frame */
1132     s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1133     s->frame_bytes = 0;
1134     qemu_bh_cancel(s->bh);
1135
1136     if (!(s->cmd & UHCI_CMD_RS)) {
1137         /* Full stop */
1138         trace_usb_uhci_schedule_stop();
1139         qemu_del_timer(s->frame_timer);
1140         uhci_async_cancel_all(s);
1141         /* set hchalted bit in status - UHCI11D 2.1.2 */
1142         s->status |= UHCI_STS_HCHALTED;
1143         return;
1144     }
1145
1146     /* Complete the previous frame */
1147     if (s->pending_int_mask) {
1148         s->status2 |= s->pending_int_mask;
1149         s->status  |= UHCI_STS_USBINT;
1150         uhci_update_irq(s);
1151     }
1152     s->pending_int_mask = 0;
1153
1154     /* Start new frame */
1155     s->frnum = (s->frnum + 1) & 0x7ff;
1156
1157     trace_usb_uhci_frame_start(s->frnum);
1158
1159     uhci_async_validate_begin(s);
1160
1161     uhci_process_frame(s);
1162
1163     uhci_async_validate_end(s);
1164
1165     qemu_mod_timer(s->frame_timer, s->expire_time);
1166 }
1167
1168 static const MemoryRegionPortio uhci_portio[] = {
1169     { 0, 32, 2, .write = uhci_ioport_writew, },
1170     { 0, 32, 2, .read = uhci_ioport_readw, },
1171     { 0, 32, 4, .write = uhci_ioport_writel, },
1172     { 0, 32, 4, .read = uhci_ioport_readl, },
1173     { 0, 32, 1, .write = uhci_ioport_writeb, },
1174     { 0, 32, 1, .read = uhci_ioport_readb, },
1175     PORTIO_END_OF_LIST()
1176 };
1177
1178 static const MemoryRegionOps uhci_ioport_ops = {
1179     .old_portio = uhci_portio,
1180 };
1181
1182 static USBPortOps uhci_port_ops = {
1183     .attach = uhci_attach,
1184     .detach = uhci_detach,
1185     .child_detach = uhci_child_detach,
1186     .wakeup = uhci_wakeup,
1187     .complete = uhci_async_complete,
1188 };
1189
1190 static USBBusOps uhci_bus_ops = {
1191 };
1192
1193 static int usb_uhci_common_initfn(PCIDevice *dev)
1194 {
1195     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1196     uint8_t *pci_conf = s->dev.config;
1197     int i;
1198
1199     pci_conf[PCI_CLASS_PROG] = 0x00;
1200     /* TODO: reset value should be 0. */
1201     pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */
1202     pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1203
1204     if (s->masterbus) {
1205         USBPort *ports[NB_PORTS];
1206         for(i = 0; i < NB_PORTS; i++) {
1207             ports[i] = &s->ports[i].port;
1208         }
1209         if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1210                 s->firstport, s, &uhci_port_ops,
1211                 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1212             return -1;
1213         }
1214     } else {
1215         usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1216         for (i = 0; i < NB_PORTS; i++) {
1217             usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1218                               USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1219         }
1220     }
1221     s->bh = qemu_bh_new(uhci_bh, s);
1222     s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1223     s->num_ports_vmstate = NB_PORTS;
1224     QTAILQ_INIT(&s->queues);
1225
1226     qemu_register_reset(uhci_reset, s);
1227
1228     memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1229     /* Use region 4 for consistency with real hardware.  BSD guests seem
1230        to rely on this.  */
1231     pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1232
1233     return 0;
1234 }
1235
1236 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1237 {
1238     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1239     uint8_t *pci_conf = s->dev.config;
1240
1241     /* USB misc control 1/2 */
1242     pci_set_long(pci_conf + 0x40,0x00001000);
1243     /* PM capability */
1244     pci_set_long(pci_conf + 0x80,0x00020001);
1245     /* USB legacy support  */
1246     pci_set_long(pci_conf + 0xc0,0x00002000);
1247
1248     return usb_uhci_common_initfn(dev);
1249 }
1250
1251 static int usb_uhci_exit(PCIDevice *dev)
1252 {
1253     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1254
1255     memory_region_destroy(&s->io_bar);
1256     return 0;
1257 }
1258
1259 static Property uhci_properties[] = {
1260     DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1261     DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1262     DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1263     DEFINE_PROP_END_OF_LIST(),
1264 };
1265
1266 static void piix3_uhci_class_init(ObjectClass *klass, void *data)
1267 {
1268     DeviceClass *dc = DEVICE_CLASS(klass);
1269     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1270
1271     k->init = usb_uhci_common_initfn;
1272     k->exit = usb_uhci_exit;
1273     k->vendor_id = PCI_VENDOR_ID_INTEL;
1274     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
1275     k->revision = 0x01;
1276     k->class_id = PCI_CLASS_SERIAL_USB;
1277     dc->vmsd = &vmstate_uhci;
1278     dc->props = uhci_properties;
1279 }
1280
1281 static TypeInfo piix3_uhci_info = {
1282     .name          = "piix3-usb-uhci",
1283     .parent        = TYPE_PCI_DEVICE,
1284     .instance_size = sizeof(UHCIState),
1285     .class_init    = piix3_uhci_class_init,
1286 };
1287
1288 static void piix4_uhci_class_init(ObjectClass *klass, void *data)
1289 {
1290     DeviceClass *dc = DEVICE_CLASS(klass);
1291     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1292
1293     k->init = usb_uhci_common_initfn;
1294     k->exit = usb_uhci_exit;
1295     k->vendor_id = PCI_VENDOR_ID_INTEL;
1296     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
1297     k->revision = 0x01;
1298     k->class_id = PCI_CLASS_SERIAL_USB;
1299     dc->vmsd = &vmstate_uhci;
1300     dc->props = uhci_properties;
1301 }
1302
1303 static TypeInfo piix4_uhci_info = {
1304     .name          = "piix4-usb-uhci",
1305     .parent        = TYPE_PCI_DEVICE,
1306     .instance_size = sizeof(UHCIState),
1307     .class_init    = piix4_uhci_class_init,
1308 };
1309
1310 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data)
1311 {
1312     DeviceClass *dc = DEVICE_CLASS(klass);
1313     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1314
1315     k->init = usb_uhci_vt82c686b_initfn;
1316     k->exit = usb_uhci_exit;
1317     k->vendor_id = PCI_VENDOR_ID_VIA;
1318     k->device_id = PCI_DEVICE_ID_VIA_UHCI;
1319     k->revision = 0x01;
1320     k->class_id = PCI_CLASS_SERIAL_USB;
1321     dc->vmsd = &vmstate_uhci;
1322     dc->props = uhci_properties;
1323 }
1324
1325 static TypeInfo vt82c686b_uhci_info = {
1326     .name          = "vt82c686b-usb-uhci",
1327     .parent        = TYPE_PCI_DEVICE,
1328     .instance_size = sizeof(UHCIState),
1329     .class_init    = vt82c686b_uhci_class_init,
1330 };
1331
1332 static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
1333 {
1334     DeviceClass *dc = DEVICE_CLASS(klass);
1335     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1336
1337     k->init = usb_uhci_common_initfn;
1338     k->vendor_id = PCI_VENDOR_ID_INTEL;
1339     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
1340     k->revision = 0x03;
1341     k->class_id = PCI_CLASS_SERIAL_USB;
1342     dc->vmsd = &vmstate_uhci;
1343     dc->props = uhci_properties;
1344 }
1345
1346 static TypeInfo ich9_uhci1_info = {
1347     .name          = "ich9-usb-uhci1",
1348     .parent        = TYPE_PCI_DEVICE,
1349     .instance_size = sizeof(UHCIState),
1350     .class_init    = ich9_uhci1_class_init,
1351 };
1352
1353 static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
1354 {
1355     DeviceClass *dc = DEVICE_CLASS(klass);
1356     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1357
1358     k->init = usb_uhci_common_initfn;
1359     k->vendor_id = PCI_VENDOR_ID_INTEL;
1360     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
1361     k->revision = 0x03;
1362     k->class_id = PCI_CLASS_SERIAL_USB;
1363     dc->vmsd = &vmstate_uhci;
1364     dc->props = uhci_properties;
1365 }
1366
1367 static TypeInfo ich9_uhci2_info = {
1368     .name          = "ich9-usb-uhci2",
1369     .parent        = TYPE_PCI_DEVICE,
1370     .instance_size = sizeof(UHCIState),
1371     .class_init    = ich9_uhci2_class_init,
1372 };
1373
1374 static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
1375 {
1376     DeviceClass *dc = DEVICE_CLASS(klass);
1377     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1378
1379     k->init = usb_uhci_common_initfn;
1380     k->vendor_id = PCI_VENDOR_ID_INTEL;
1381     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
1382     k->revision = 0x03;
1383     k->class_id = PCI_CLASS_SERIAL_USB;
1384     dc->vmsd = &vmstate_uhci;
1385     dc->props = uhci_properties;
1386 }
1387
1388 static TypeInfo ich9_uhci3_info = {
1389     .name          = "ich9-usb-uhci3",
1390     .parent        = TYPE_PCI_DEVICE,
1391     .instance_size = sizeof(UHCIState),
1392     .class_init    = ich9_uhci3_class_init,
1393 };
1394
1395 static void uhci_register_types(void)
1396 {
1397     type_register_static(&piix3_uhci_info);
1398     type_register_static(&piix4_uhci_info);
1399     type_register_static(&vt82c686b_uhci_info);
1400     type_register_static(&ich9_uhci1_info);
1401     type_register_static(&ich9_uhci2_info);
1402     type_register_static(&ich9_uhci3_info);
1403 }
1404
1405 type_init(uhci_register_types)