hw/usb/hcd-uhci.c

   1 /*
   2  * USB UHCI controller emulation
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Copyright (c) 2008 Max Krasnyansky
   7  *     Magor rewrite of the UHCI data structures parser and frame processor
   8  *     Support for fully async operation and multiple outstanding transactions
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a copy
  11  * of this software and associated documentation files (the "Software"), to deal
  12  * in the Software without restriction, including without limitation the rights
  13  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14  * copies of the Software, and to permit persons to whom the Software is
  15  * furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  26  * THE SOFTWARE.
  27  */
  28 #include "hw/hw.h"
  29 #include "hw/usb.h"
  30 #include "hw/pci.h"
  31 #include "qemu-timer.h"
  32 #include "iov.h"
  33 #include "dma.h"
  34
  35 //#define DEBUG
  36 //#define DEBUG_DUMP_DATA
  37
  38 #define UHCI_CMD_FGR      (1 << 4)
  39 #define UHCI_CMD_EGSM     (1 << 3)
  40 #define UHCI_CMD_GRESET   (1 << 2)
  41 #define UHCI_CMD_HCRESET  (1 << 1)
  42 #define UHCI_CMD_RS       (1 << 0)
  43
  44 #define UHCI_STS_HCHALTED (1 << 5)
  45 #define UHCI_STS_HCPERR   (1 << 4)
  46 #define UHCI_STS_HSERR    (1 << 3)
  47 #define UHCI_STS_RD       (1 << 2)
  48 #define UHCI_STS_USBERR   (1 << 1)
  49 #define UHCI_STS_USBINT   (1 << 0)
  50
  51 #define TD_CTRL_SPD     (1 << 29)
  52 #define TD_CTRL_ERROR_SHIFT  27
  53 #define TD_CTRL_IOS     (1 << 25)
  54 #define TD_CTRL_IOC     (1 << 24)
  55 #define TD_CTRL_ACTIVE  (1 << 23)
  56 #define TD_CTRL_STALL   (1 << 22)
  57 #define TD_CTRL_BABBLE  (1 << 20)
  58 #define TD_CTRL_NAK     (1 << 19)
  59 #define TD_CTRL_TIMEOUT (1 << 18)
  60
  61 #define UHCI_PORT_SUSPEND (1 << 12)
  62 #define UHCI_PORT_RESET (1 << 9)
  63 #define UHCI_PORT_LSDA  (1 << 8)
  64 #define UHCI_PORT_RD    (1 << 6)
  65 #define UHCI_PORT_ENC   (1 << 3)
  66 #define UHCI_PORT_EN    (1 << 2)
  67 #define UHCI_PORT_CSC   (1 << 1)
  68 #define UHCI_PORT_CCS   (1 << 0)
  69
  70 #define UHCI_PORT_READ_ONLY    (0x1bb)
  71 #define UHCI_PORT_WRITE_CLEAR  (UHCI_PORT_CSC | UHCI_PORT_ENC)
  72
  73 #define FRAME_TIMER_FREQ 1000
  74
  75 #define FRAME_MAX_LOOPS  256
  76
  77 #define NB_PORTS 2
  78
  79 #ifdef DEBUG
  80 #define DPRINTF printf
  81
  82 static const char *pid2str(int pid)
  83 {
  84     switch (pid) {
  85     case USB_TOKEN_SETUP: return "SETUP";
  86     case USB_TOKEN_IN:    return "IN";
  87     case USB_TOKEN_OUT:   return "OUT";
  88     }
  89     return "?";
  90 }
  91
  92 #else
  93 #define DPRINTF(...)
  94 #endif
  95
  96 typedef struct UHCIState UHCIState;
  97 typedef struct UHCIAsync UHCIAsync;
  98 typedef struct UHCIQueue UHCIQueue;
  99
 100 /*
 101  * Pending async transaction.
 102  * 'packet' must be the first field because completion
 103  * handler does "(UHCIAsync *) pkt" cast.
 104  */
 105
 106 struct UHCIAsync {
 107     USBPacket packet;
 108     QEMUSGList sgl;
 109     UHCIQueue *queue;
 110     QTAILQ_ENTRY(UHCIAsync) next;
 111     uint32_t  td;
 112     uint8_t   isoc;
 113     uint8_t   done;
 114 };
 115
 116 struct UHCIQueue {
 117     uint32_t  token;
 118     UHCIState *uhci;
 119     QTAILQ_ENTRY(UHCIQueue) next;
 120     QTAILQ_HEAD(, UHCIAsync) asyncs;
 121     int8_t    valid;
 122 };
 123
 124 typedef struct UHCIPort {
 125     USBPort port;
 126     uint16_t ctrl;
 127 } UHCIPort;
 128
 129 struct UHCIState {
 130     PCIDevice dev;
 131     MemoryRegion io_bar;
 132     USBBus bus; /* Note unused when we're a companion controller */
 133     uint16_t cmd; /* cmd register */
 134     uint16_t status;
 135     uint16_t intr; /* interrupt enable register */
 136     uint16_t frnum; /* frame number */
 137     uint32_t fl_base_addr; /* frame list base address */
 138     uint8_t sof_timing;
 139     uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
 140     int64_t expire_time;
 141     QEMUTimer *frame_timer;
 142     UHCIPort ports[NB_PORTS];
 143
 144     /* Interrupts that should be raised at the end of the current frame.  */
 145     uint32_t pending_int_mask;
 146
 147     /* Active packets */
 148     QTAILQ_HEAD(, UHCIQueue) queues;
 149     uint8_t num_ports_vmstate;
 150
 151     /* Properties */
 152     char *masterbus;
 153     uint32_t firstport;
 154 };
 155
 156 typedef struct UHCI_TD {
 157     uint32_t link;
 158     uint32_t ctrl; /* see TD_CTRL_xxx */
 159     uint32_t token;
 160     uint32_t buffer;
 161 } UHCI_TD;
 162
 163 typedef struct UHCI_QH {
 164     uint32_t link;
 165     uint32_t el_link;
 166 } UHCI_QH;
 167
 168 static inline int32_t uhci_queue_token(UHCI_TD *td)
 169 {
 170     /* covers ep, dev, pid -> identifies the endpoint */
 171     return td->token & 0x7ffff;
 172 }
 173
 174 static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td)
 175 {
 176     uint32_t token = uhci_queue_token(td);
 177     UHCIQueue *queue;
 178
 179     QTAILQ_FOREACH(queue, &s->queues, next) {
 180         if (queue->token == token) {
 181             return queue;
 182         }
 183     }
 184
 185     queue = g_new0(UHCIQueue, 1);
 186     queue->uhci = s;
 187     queue->token = token;
 188     QTAILQ_INIT(&queue->asyncs);
 189     QTAILQ_INSERT_HEAD(&s->queues, queue, next);
 190     return queue;
 191 }
 192
 193 static void uhci_queue_free(UHCIQueue *queue)
 194 {
 195     UHCIState *s = queue->uhci;
 196
 197     QTAILQ_REMOVE(&s->queues, queue, next);
 198     g_free(queue);
 199 }
 200
 201 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr)
 202 {
 203     UHCIAsync *async = g_new0(UHCIAsync, 1);
 204
 205     async->queue = queue;
 206     async->td = addr;
 207     usb_packet_init(&async->packet);
 208     pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
 209
 210     return async;
 211 }
 212
 213 static void uhci_async_free(UHCIAsync *async)
 214 {
 215     usb_packet_cleanup(&async->packet);
 216     qemu_sglist_destroy(&async->sgl);
 217     g_free(async);
 218 }
 219
 220 static void uhci_async_link(UHCIAsync *async)
 221 {
 222     UHCIQueue *queue = async->queue;
 223     QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
 224 }
 225
 226 static void uhci_async_unlink(UHCIAsync *async)
 227 {
 228     UHCIQueue *queue = async->queue;
 229     QTAILQ_REMOVE(&queue->asyncs, async, next);
 230 }
 231
 232 static void uhci_async_cancel(UHCIAsync *async)
 233 {
 234     DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n",
 235            async->td, async->token, async->done);
 236
 237     if (!async->done)
 238         usb_cancel_packet(&async->packet);
 239     uhci_async_free(async);
 240 }
 241
 242 /*
 243  * Mark all outstanding async packets as invalid.
 244  * This is used for canceling them when TDs are removed by the HCD.
 245  */
 246 static void uhci_async_validate_begin(UHCIState *s)
 247 {
 248     UHCIQueue *queue;
 249
 250     QTAILQ_FOREACH(queue, &s->queues, next) {
 251         queue->valid--;
 252     }
 253 }
 254
 255 /*
 256  * Cancel async packets that are no longer valid
 257  */
 258 static void uhci_async_validate_end(UHCIState *s)
 259 {
 260     UHCIQueue *queue, *n;
 261     UHCIAsync *async;
 262
 263     QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
 264         if (queue->valid > 0) {
 265             continue;
 266         }
 267         while (!QTAILQ_EMPTY(&queue->asyncs)) {
 268             async = QTAILQ_FIRST(&queue->asyncs);
 269             uhci_async_unlink(async);
 270             uhci_async_cancel(async);
 271         }
 272         uhci_queue_free(queue);
 273     }
 274 }
 275
 276 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
 277 {
 278     UHCIQueue *queue;
 279     UHCIAsync *curr, *n;
 280
 281     QTAILQ_FOREACH(queue, &s->queues, next) {
 282         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 283             if (!usb_packet_is_inflight(&curr->packet) ||
 284                 curr->packet.ep->dev != dev) {
 285                 continue;
 286             }
 287             uhci_async_unlink(curr);
 288             uhci_async_cancel(curr);
 289         }
 290     }
 291 }
 292
 293 static void uhci_async_cancel_all(UHCIState *s)
 294 {
 295     UHCIQueue *queue;
 296     UHCIAsync *curr, *n;
 297
 298     QTAILQ_FOREACH(queue, &s->queues, next) {
 299         QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) {
 300             uhci_async_unlink(curr);
 301             uhci_async_cancel(curr);
 302         }
 303         uhci_queue_free(queue);
 304     }
 305 }
 306
 307 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td)
 308 {
 309     uint32_t token = uhci_queue_token(td);
 310     UHCIQueue *queue;
 311     UHCIAsync *async;
 312
 313     QTAILQ_FOREACH(queue, &s->queues, next) {
 314         if (queue->token == token) {
 315             break;
 316         }
 317     }
 318     if (queue == NULL) {
 319         return NULL;
 320     }
 321
 322     QTAILQ_FOREACH(async, &queue->asyncs, next) {
 323         if (async->td == addr) {
 324             return async;
 325         }
 326     }
 327
 328     return NULL;
 329 }
 330
 331 static void uhci_update_irq(UHCIState *s)
 332 {
 333     int level;
 334     if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
 335         ((s->status2 & 2) && (s->intr & (1 << 3))) ||
 336         ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
 337         ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
 338         (s->status & UHCI_STS_HSERR) ||
 339         (s->status & UHCI_STS_HCPERR)) {
 340         level = 1;
 341     } else {
 342         level = 0;
 343     }
 344     qemu_set_irq(s->dev.irq[3], level);
 345 }
 346
 347 static void uhci_reset(void *opaque)
 348 {
 349     UHCIState *s = opaque;
 350     uint8_t *pci_conf;
 351     int i;
 352     UHCIPort *port;
 353
 354     DPRINTF("uhci: full reset\n");
 355
 356     pci_conf = s->dev.config;
 357
 358     pci_conf[0x6a] = 0x01; /* usb clock */
 359     pci_conf[0x6b] = 0x00;
 360     s->cmd = 0;
 361     s->status = 0;
 362     s->status2 = 0;
 363     s->intr = 0;
 364     s->fl_base_addr = 0;
 365     s->sof_timing = 64;
 366
 367     for(i = 0; i < NB_PORTS; i++) {
 368         port = &s->ports[i];
 369         port->ctrl = 0x0080;
 370         if (port->port.dev && port->port.dev->attached) {
 371             usb_port_reset(&port->port);
 372         }
 373     }
 374
 375     uhci_async_cancel_all(s);
 376 }
 377
 378 static void uhci_pre_save(void *opaque)
 379 {
 380     UHCIState *s = opaque;
 381
 382     uhci_async_cancel_all(s);
 383 }
 384
 385 static const VMStateDescription vmstate_uhci_port = {
 386     .name = "uhci port",
 387     .version_id = 1,
 388     .minimum_version_id = 1,
 389     .minimum_version_id_old = 1,
 390     .fields      = (VMStateField []) {
 391         VMSTATE_UINT16(ctrl, UHCIPort),
 392         VMSTATE_END_OF_LIST()
 393     }
 394 };
 395
 396 static const VMStateDescription vmstate_uhci = {
 397     .name = "uhci",
 398     .version_id = 2,
 399     .minimum_version_id = 1,
 400     .minimum_version_id_old = 1,
 401     .pre_save = uhci_pre_save,
 402     .fields      = (VMStateField []) {
 403         VMSTATE_PCI_DEVICE(dev, UHCIState),
 404         VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
 405         VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
 406                              vmstate_uhci_port, UHCIPort),
 407         VMSTATE_UINT16(cmd, UHCIState),
 408         VMSTATE_UINT16(status, UHCIState),
 409         VMSTATE_UINT16(intr, UHCIState),
 410         VMSTATE_UINT16(frnum, UHCIState),
 411         VMSTATE_UINT32(fl_base_addr, UHCIState),
 412         VMSTATE_UINT8(sof_timing, UHCIState),
 413         VMSTATE_UINT8(status2, UHCIState),
 414         VMSTATE_TIMER(frame_timer, UHCIState),
 415         VMSTATE_INT64_V(expire_time, UHCIState, 2),
 416         VMSTATE_END_OF_LIST()
 417     }
 418 };
 419
 420 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 421 {
 422     UHCIState *s = opaque;
 423
 424     addr &= 0x1f;
 425     switch(addr) {
 426     case 0x0c:
 427         s->sof_timing = val;
 428         break;
 429     }
 430 }
 431
 432 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
 433 {
 434     UHCIState *s = opaque;
 435     uint32_t val;
 436
 437     addr &= 0x1f;
 438     switch(addr) {
 439     case 0x0c:
 440         val = s->sof_timing;
 441         break;
 442     default:
 443         val = 0xff;
 444         break;
 445     }
 446     return val;
 447 }
 448
 449 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 450 {
 451     UHCIState *s = opaque;
 452
 453     addr &= 0x1f;
 454     DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val);
 455
 456     switch(addr) {
 457     case 0x00:
 458         if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
 459             /* start frame processing */
 460             s->expire_time = qemu_get_clock_ns(vm_clock) +
 461                 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
 462             qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
 463             s->status &= ~UHCI_STS_HCHALTED;
 464         } else if (!(val & UHCI_CMD_RS)) {
 465             s->status |= UHCI_STS_HCHALTED;
 466         }
 467         if (val & UHCI_CMD_GRESET) {
 468             UHCIPort *port;
 469             int i;
 470
 471             /* send reset on the USB bus */
 472             for(i = 0; i < NB_PORTS; i++) {
 473                 port = &s->ports[i];
 474                 usb_device_reset(port->port.dev);
 475             }
 476             uhci_reset(s);
 477             return;
 478         }
 479         if (val & UHCI_CMD_HCRESET) {
 480             uhci_reset(s);
 481             return;
 482         }
 483         s->cmd = val;
 484         break;
 485     case 0x02:
 486         s->status &= ~val;
 487         /* XXX: the chip spec is not coherent, so we add a hidden
 488            register to distinguish between IOC and SPD */
 489         if (val & UHCI_STS_USBINT)
 490             s->status2 = 0;
 491         uhci_update_irq(s);
 492         break;
 493     case 0x04:
 494         s->intr = val;
 495         uhci_update_irq(s);
 496         break;
 497     case 0x06:
 498         if (s->status & UHCI_STS_HCHALTED)
 499             s->frnum = val & 0x7ff;
 500         break;
 501     case 0x10 ... 0x1f:
 502         {
 503             UHCIPort *port;
 504             USBDevice *dev;
 505             int n;
 506
 507             n = (addr >> 1) & 7;
 508             if (n >= NB_PORTS)
 509                 return;
 510             port = &s->ports[n];
 511             dev = port->port.dev;
 512             if (dev && dev->attached) {
 513                 /* port reset */
 514                 if ( (val & UHCI_PORT_RESET) &&
 515                      !(port->ctrl & UHCI_PORT_RESET) ) {
 516                     usb_device_reset(dev);
 517                 }
 518             }
 519             port->ctrl &= UHCI_PORT_READ_ONLY;
 520             port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
 521             /* some bits are reset when a '1' is written to them */
 522             port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
 523         }
 524         break;
 525     }
 526 }
 527
 528 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
 529 {
 530     UHCIState *s = opaque;
 531     uint32_t val;
 532
 533     addr &= 0x1f;
 534     switch(addr) {
 535     case 0x00:
 536         val = s->cmd;
 537         break;
 538     case 0x02:
 539         val = s->status;
 540         break;
 541     case 0x04:
 542         val = s->intr;
 543         break;
 544     case 0x06:
 545         val = s->frnum;
 546         break;
 547     case 0x10 ... 0x1f:
 548         {
 549             UHCIPort *port;
 550             int n;
 551             n = (addr >> 1) & 7;
 552             if (n >= NB_PORTS)
 553                 goto read_default;
 554             port = &s->ports[n];
 555             val = port->ctrl;
 556         }
 557         break;
 558     default:
 559     read_default:
 560         val = 0xff7f; /* disabled port */
 561         break;
 562     }
 563
 564     DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val);
 565
 566     return val;
 567 }
 568
 569 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 570 {
 571     UHCIState *s = opaque;
 572
 573     addr &= 0x1f;
 574     DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val);
 575
 576     switch(addr) {
 577     case 0x08:
 578         s->fl_base_addr = val & ~0xfff;
 579         break;
 580     }
 581 }
 582
 583 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
 584 {
 585     UHCIState *s = opaque;
 586     uint32_t val;
 587
 588     addr &= 0x1f;
 589     switch(addr) {
 590     case 0x08:
 591         val = s->fl_base_addr;
 592         break;
 593     default:
 594         val = 0xffffffff;
 595         break;
 596     }
 597     return val;
 598 }
 599
 600 /* signal resume if controller suspended */
 601 static void uhci_resume (void *opaque)
 602 {
 603     UHCIState *s = (UHCIState *)opaque;
 604
 605     if (!s)
 606         return;
 607
 608     if (s->cmd & UHCI_CMD_EGSM) {
 609         s->cmd |= UHCI_CMD_FGR;
 610         s->status |= UHCI_STS_RD;
 611         uhci_update_irq(s);
 612     }
 613 }
 614
 615 static void uhci_attach(USBPort *port1)
 616 {
 617     UHCIState *s = port1->opaque;
 618     UHCIPort *port = &s->ports[port1->index];
 619
 620     /* set connect status */
 621     port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
 622
 623     /* update speed */
 624     if (port->port.dev->speed == USB_SPEED_LOW) {
 625         port->ctrl |= UHCI_PORT_LSDA;
 626     } else {
 627         port->ctrl &= ~UHCI_PORT_LSDA;
 628     }
 629
 630     uhci_resume(s);
 631 }
 632
 633 static void uhci_detach(USBPort *port1)
 634 {
 635     UHCIState *s = port1->opaque;
 636     UHCIPort *port = &s->ports[port1->index];
 637
 638     uhci_async_cancel_device(s, port1->dev);
 639
 640     /* set connect status */
 641     if (port->ctrl & UHCI_PORT_CCS) {
 642         port->ctrl &= ~UHCI_PORT_CCS;
 643         port->ctrl |= UHCI_PORT_CSC;
 644     }
 645     /* disable port */
 646     if (port->ctrl & UHCI_PORT_EN) {
 647         port->ctrl &= ~UHCI_PORT_EN;
 648         port->ctrl |= UHCI_PORT_ENC;
 649     }
 650
 651     uhci_resume(s);
 652 }
 653
 654 static void uhci_child_detach(USBPort *port1, USBDevice *child)
 655 {
 656     UHCIState *s = port1->opaque;
 657
 658     uhci_async_cancel_device(s, child);
 659 }
 660
 661 static void uhci_wakeup(USBPort *port1)
 662 {
 663     UHCIState *s = port1->opaque;
 664     UHCIPort *port = &s->ports[port1->index];
 665
 666     if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
 667         port->ctrl |= UHCI_PORT_RD;
 668         uhci_resume(s);
 669     }
 670 }
 671
 672 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
 673 {
 674     USBDevice *dev;
 675     int i;
 676
 677     for (i = 0; i < NB_PORTS; i++) {
 678         UHCIPort *port = &s->ports[i];
 679         if (!(port->ctrl & UHCI_PORT_EN)) {
 680             continue;
 681         }
 682         dev = usb_find_device(&port->port, addr);
 683         if (dev != NULL) {
 684             return dev;
 685         }
 686     }
 687     return NULL;
 688 }
 689
 690 static void uhci_async_complete(USBPort *port, USBPacket *packet);
 691 static void uhci_process_frame(UHCIState *s);
 692
 693 /* return -1 if fatal error (frame must be stopped)
 694           0 if TD successful
 695           1 if TD unsuccessful or inactive
 696 */
 697 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
 698 {
 699     int len = 0, max_len, err, ret;
 700     uint8_t pid;
 701
 702     max_len = ((td->token >> 21) + 1) & 0x7ff;
 703     pid = td->token & 0xff;
 704
 705     ret = async->packet.result;
 706
 707     if (td->ctrl & TD_CTRL_IOS)
 708         td->ctrl &= ~TD_CTRL_ACTIVE;
 709
 710     if (ret < 0)
 711         goto out;
 712
 713     len = async->packet.result;
 714     td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
 715
 716     /* The NAK bit may have been set by a previous frame, so clear it
 717        here.  The docs are somewhat unclear, but win2k relies on this
 718        behavior.  */
 719     td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
 720     if (td->ctrl & TD_CTRL_IOC)
 721         *int_mask |= 0x01;
 722
 723     if (pid == USB_TOKEN_IN) {
 724         if (len > max_len) {
 725             ret = USB_RET_BABBLE;
 726             goto out;
 727         }
 728
 729         if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
 730             *int_mask |= 0x02;
 731             /* short packet: do not update QH */
 732             DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token);
 733             return 1;
 734         }
 735     }
 736
 737     /* success */
 738     return 0;
 739
 740 out:
 741     switch(ret) {
 742     case USB_RET_STALL:
 743         td->ctrl |= TD_CTRL_STALL;
 744         td->ctrl &= ~TD_CTRL_ACTIVE;
 745         s->status |= UHCI_STS_USBERR;
 746         if (td->ctrl & TD_CTRL_IOC) {
 747             *int_mask |= 0x01;
 748         }
 749         uhci_update_irq(s);
 750         return 1;
 751
 752     case USB_RET_BABBLE:
 753         td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
 754         td->ctrl &= ~TD_CTRL_ACTIVE;
 755         s->status |= UHCI_STS_USBERR;
 756         if (td->ctrl & TD_CTRL_IOC) {
 757             *int_mask |= 0x01;
 758         }
 759         uhci_update_irq(s);
 760         /* frame interrupted */
 761         return -1;
 762
 763     case USB_RET_NAK:
 764         td->ctrl |= TD_CTRL_NAK;
 765         if (pid == USB_TOKEN_SETUP)
 766             break;
 767         return 1;
 768
 769     case USB_RET_IOERROR:
 770     case USB_RET_NODEV:
 771     default:
 772         break;
 773     }
 774
 775     /* Retry the TD if error count is not zero */
 776
 777     td->ctrl |= TD_CTRL_TIMEOUT;
 778     err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
 779     if (err != 0) {
 780         err--;
 781         if (err == 0) {
 782             td->ctrl &= ~TD_CTRL_ACTIVE;
 783             s->status |= UHCI_STS_USBERR;
 784             if (td->ctrl & TD_CTRL_IOC)
 785                 *int_mask |= 0x01;
 786             uhci_update_irq(s);
 787         }
 788     }
 789     td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
 790         (err << TD_CTRL_ERROR_SHIFT);
 791     return 1;
 792 }
 793
 794 static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask)
 795 {
 796     UHCIAsync *async;
 797     int len = 0, max_len;
 798     uint8_t pid;
 799     USBDevice *dev;
 800     USBEndpoint *ep;
 801
 802     /* Is active ? */
 803     if (!(td->ctrl & TD_CTRL_ACTIVE))
 804         return 1;
 805
 806     async = uhci_async_find_td(s, addr, td);
 807     if (async) {
 808         /* Already submitted */
 809         async->queue->valid = 32;
 810
 811         if (!async->done)
 812             return 1;
 813
 814         uhci_async_unlink(async);
 815         goto done;
 816     }
 817
 818     /* Allocate new packet */
 819     async = uhci_async_alloc(uhci_queue_get(s, td), addr);
 820     if (!async)
 821         return 1;
 822
 823     /* valid needs to be large enough to handle 10 frame delay
 824      * for initial isochronous requests
 825      */
 826     async->queue->valid = 32;
 827     async->isoc  = td->ctrl & TD_CTRL_IOS;
 828
 829     max_len = ((td->token >> 21) + 1) & 0x7ff;
 830     pid = td->token & 0xff;
 831
 832     dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
 833     ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
 834     usb_packet_setup(&async->packet, pid, ep);
 835     qemu_sglist_add(&async->sgl, td->buffer, max_len);
 836     usb_packet_map(&async->packet, &async->sgl);
 837
 838     switch(pid) {
 839     case USB_TOKEN_OUT:
 840     case USB_TOKEN_SETUP:
 841         len = usb_handle_packet(dev, &async->packet);
 842         if (len >= 0)
 843             len = max_len;
 844         break;
 845
 846     case USB_TOKEN_IN:
 847         len = usb_handle_packet(dev, &async->packet);
 848         break;
 849
 850     default:
 851         /* invalid pid : frame interrupted */
 852         uhci_async_free(async);
 853         s->status |= UHCI_STS_HCPERR;
 854         uhci_update_irq(s);
 855         return -1;
 856     }
 857
 858     if (len == USB_RET_ASYNC) {
 859         uhci_async_link(async);
 860         return 2;
 861     }
 862
 863     async->packet.result = len;
 864
 865 done:
 866     len = uhci_complete_td(s, td, async, int_mask);
 867     usb_packet_unmap(&async->packet);
 868     uhci_async_free(async);
 869     return len;
 870 }
 871
 872 static void uhci_async_complete(USBPort *port, USBPacket *packet)
 873 {
 874     UHCIAsync *async = container_of(packet, UHCIAsync, packet);
 875     UHCIState *s = async->queue->uhci;
 876
 877     DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token);
 878
 879     if (async->isoc) {
 880         UHCI_TD td;
 881         uint32_t link = async->td;
 882         uint32_t int_mask = 0, val;
 883
 884         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
 885         le32_to_cpus(&td.link);
 886         le32_to_cpus(&td.ctrl);
 887         le32_to_cpus(&td.token);
 888         le32_to_cpus(&td.buffer);
 889
 890         uhci_async_unlink(async);
 891         uhci_complete_td(s, &td, async, &int_mask);
 892         s->pending_int_mask |= int_mask;
 893
 894         /* update the status bits of the TD */
 895         val = cpu_to_le32(td.ctrl);
 896         pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
 897         uhci_async_free(async);
 898     } else {
 899         async->done = 1;
 900         uhci_process_frame(s);
 901     }
 902 }
 903
 904 static int is_valid(uint32_t link)
 905 {
 906     return (link & 1) == 0;
 907 }
 908
 909 static int is_qh(uint32_t link)
 910 {
 911     return (link & 2) != 0;
 912 }
 913
 914 static int depth_first(uint32_t link)
 915 {
 916     return (link & 4) != 0;
 917 }
 918
 919 /* QH DB used for detecting QH loops */
 920 #define UHCI_MAX_QUEUES 128
 921 typedef struct {
 922     uint32_t addr[UHCI_MAX_QUEUES];
 923     int      count;
 924 } QhDb;
 925
 926 static void qhdb_reset(QhDb *db)
 927 {
 928     db->count = 0;
 929 }
 930
 931 /* Add QH to DB. Returns 1 if already present or DB is full. */
 932 static int qhdb_insert(QhDb *db, uint32_t addr)
 933 {
 934     int i;
 935     for (i = 0; i < db->count; i++)
 936         if (db->addr[i] == addr)
 937             return 1;
 938
 939     if (db->count >= UHCI_MAX_QUEUES)
 940         return 1;
 941
 942     db->addr[db->count++] = addr;
 943     return 0;
 944 }
 945
 946 static void uhci_fill_queue(UHCIState *s, UHCI_TD *td)
 947 {
 948     uint32_t int_mask = 0;
 949     uint32_t plink = td->link;
 950     uint32_t token = uhci_queue_token(td);
 951     UHCI_TD ptd;
 952     int ret;
 953
 954     while (is_valid(plink)) {
 955         pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd));
 956         le32_to_cpus(&ptd.link);
 957         le32_to_cpus(&ptd.ctrl);
 958         le32_to_cpus(&ptd.token);
 959         le32_to_cpus(&ptd.buffer);
 960         if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
 961             break;
 962         }
 963         if (uhci_queue_token(&ptd) != token) {
 964             break;
 965         }
 966         ret = uhci_handle_td(s, plink, &ptd, &int_mask);
 967         assert(ret == 2); /* got USB_RET_ASYNC */
 968         assert(int_mask == 0);
 969         plink = ptd.link;
 970     }
 971 }
 972
 973 static void uhci_process_frame(UHCIState *s)
 974 {
 975     uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
 976     uint32_t curr_qh, td_count = 0, bytes_count = 0;
 977     int cnt, ret;
 978     UHCI_TD td;
 979     UHCI_QH qh;
 980     QhDb qhdb;
 981
 982     frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
 983
 984     DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr);
 985
 986     pci_dma_read(&s->dev, frame_addr, &link, 4);
 987     le32_to_cpus(&link);
 988
 989     int_mask = 0;
 990     curr_qh  = 0;
 991
 992     qhdb_reset(&qhdb);
 993
 994     for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
 995         if (is_qh(link)) {
 996             /* QH */
 997
 998             if (qhdb_insert(&qhdb, link)) {
 999                 /*
1000                  * We're going in circles. Which is not a bug because
1001                  * HCD is allowed to do that as part of the BW management.
1002                  *
1003                  * Stop processing here if
1004                  *  (a) no transaction has been done since we've been
1005                  *      here last time, or
1006                  *  (b) we've reached the usb 1.1 bandwidth, which is
1007                  *      1280 bytes/frame.
1008                  */
1009                 DPRINTF("uhci: detected loop. qh 0x%x\n", link);
1010                 if (td_count == 0) {
1011                     DPRINTF("uhci: no transaction last round, stop\n");
1012                     break;
1013                 } else if (bytes_count >= 1280) {
1014                     DPRINTF("uhci: bandwidth limit reached, stop\n");
1015                     break;
1016                 } else {
1017                     td_count = 0;
1018                     qhdb_reset(&qhdb);
1019                     qhdb_insert(&qhdb, link);
1020                 }
1021             }
1022
1023             pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1024             le32_to_cpus(&qh.link);
1025             le32_to_cpus(&qh.el_link);
1026
1027             DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n",
1028                     link, qh.link, qh.el_link);
1029
1030             if (!is_valid(qh.el_link)) {
1031                 /* QH w/o elements */
1032                 curr_qh = 0;
1033                 link = qh.link;
1034             } else {
1035                 /* QH with elements */
1036                 curr_qh = link;
1037                 link = qh.el_link;
1038             }
1039             continue;
1040         }
1041
1042         /* TD */
1043         pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td));
1044         le32_to_cpus(&td.link);
1045         le32_to_cpus(&td.ctrl);
1046         le32_to_cpus(&td.token);
1047         le32_to_cpus(&td.buffer);
1048
1049         DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1050                 link, td.link, td.ctrl, td.token, curr_qh);
1051
1052         old_td_ctrl = td.ctrl;
1053         ret = uhci_handle_td(s, link, &td, &int_mask);
1054         if (old_td_ctrl != td.ctrl) {
1055             /* update the status bits of the TD */
1056             val = cpu_to_le32(td.ctrl);
1057             pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1058         }
1059
1060         switch (ret) {
1061         case -1: /* interrupted frame */
1062             goto out;
1063
1064         case 1: /* goto next queue */
1065             DPRINTF("uhci: TD 0x%x skip. "
1066                     "link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1067                     link, td.link, td.ctrl, td.token, curr_qh);
1068             link = curr_qh ? qh.link : td.link;
1069             continue;
1070
1071         case 2: /* got USB_RET_ASYNC */
1072             DPRINTF("uhci: TD 0x%x async. "
1073                     "link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1074                     link, td.link, td.ctrl, td.token, curr_qh);
1075             if (is_valid(td.link)) {
1076                 uhci_fill_queue(s, &td);
1077             }
1078             link = curr_qh ? qh.link : td.link;
1079             continue;
1080
1081         case 0: /* completed TD */
1082             DPRINTF("uhci: TD 0x%x done. "
1083                     "link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n",
1084                     link, td.link, td.ctrl, td.token, curr_qh);
1085
1086             link = td.link;
1087             td_count++;
1088             bytes_count += (td.ctrl & 0x7ff) + 1;
1089
1090             if (curr_qh) {
1091                 /* update QH element link */
1092                 qh.el_link = link;
1093                 val = cpu_to_le32(qh.el_link);
1094                 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1095
1096                 if (!depth_first(link)) {
1097                     /* done with this QH */
1098
1099                     DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n",
1100                             curr_qh, qh.link, qh.el_link);
1101
1102                     curr_qh = 0;
1103                     link    = qh.link;
1104                 }
1105             }
1106             break;
1107
1108         default:
1109             assert(!"unknown return code");
1110         }
1111
1112         /* go to the next entry */
1113     }
1114
1115 out:
1116     s->pending_int_mask |= int_mask;
1117 }
1118
1119 static void uhci_frame_timer(void *opaque)
1120 {
1121     UHCIState *s = opaque;
1122
1123     /* prepare the timer for the next frame */
1124     s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1125
1126     if (!(s->cmd & UHCI_CMD_RS)) {
1127         /* Full stop */
1128         qemu_del_timer(s->frame_timer);
1129         uhci_async_cancel_all(s);
1130         /* set hchalted bit in status - UHCI11D 2.1.2 */
1131         s->status |= UHCI_STS_HCHALTED;
1132
1133         DPRINTF("uhci: halted\n");
1134         return;
1135     }
1136
1137     /* Complete the previous frame */
1138     if (s->pending_int_mask) {
1139         s->status2 |= s->pending_int_mask;
1140         s->status  |= UHCI_STS_USBINT;
1141         uhci_update_irq(s);
1142     }
1143     s->pending_int_mask = 0;
1144
1145     /* Start new frame */
1146     s->frnum = (s->frnum + 1) & 0x7ff;
1147
1148     DPRINTF("uhci: new frame #%u\n" , s->frnum);
1149
1150     uhci_async_validate_begin(s);
1151
1152     uhci_process_frame(s);
1153
1154     uhci_async_validate_end(s);
1155
1156     qemu_mod_timer(s->frame_timer, s->expire_time);
1157 }
1158
1159 static const MemoryRegionPortio uhci_portio[] = {
1160     { 0, 32, 2, .write = uhci_ioport_writew, },
1161     { 0, 32, 2, .read = uhci_ioport_readw, },
1162     { 0, 32, 4, .write = uhci_ioport_writel, },
1163     { 0, 32, 4, .read = uhci_ioport_readl, },
1164     { 0, 32, 1, .write = uhci_ioport_writeb, },
1165     { 0, 32, 1, .read = uhci_ioport_readb, },
1166     PORTIO_END_OF_LIST()
1167 };
1168
1169 static const MemoryRegionOps uhci_ioport_ops = {
1170     .old_portio = uhci_portio,
1171 };
1172
1173 static USBPortOps uhci_port_ops = {
1174     .attach = uhci_attach,
1175     .detach = uhci_detach,
1176     .child_detach = uhci_child_detach,
1177     .wakeup = uhci_wakeup,
1178     .complete = uhci_async_complete,
1179 };
1180
1181 static USBBusOps uhci_bus_ops = {
1182 };
1183
1184 static int usb_uhci_common_initfn(PCIDevice *dev)
1185 {
1186     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1187     uint8_t *pci_conf = s->dev.config;
1188     int i;
1189
1190     pci_conf[PCI_CLASS_PROG] = 0x00;
1191     /* TODO: reset value should be 0. */
1192     pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */
1193     pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1194
1195     if (s->masterbus) {
1196         USBPort *ports[NB_PORTS];
1197         for(i = 0; i < NB_PORTS; i++) {
1198             ports[i] = &s->ports[i].port;
1199         }
1200         if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1201                 s->firstport, s, &uhci_port_ops,
1202                 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1203             return -1;
1204         }
1205     } else {
1206         usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1207         for (i = 0; i < NB_PORTS; i++) {
1208             usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1209                               USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1210         }
1211     }
1212     s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1213     s->num_ports_vmstate = NB_PORTS;
1214     QTAILQ_INIT(&s->queues);
1215
1216     qemu_register_reset(uhci_reset, s);
1217
1218     memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1219     /* Use region 4 for consistency with real hardware.  BSD guests seem
1220        to rely on this.  */
1221     pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1222
1223     return 0;
1224 }
1225
1226 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1227 {
1228     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1229     uint8_t *pci_conf = s->dev.config;
1230
1231     /* USB misc control 1/2 */
1232     pci_set_long(pci_conf + 0x40,0x00001000);
1233     /* PM capability */
1234     pci_set_long(pci_conf + 0x80,0x00020001);
1235     /* USB legacy support  */
1236     pci_set_long(pci_conf + 0xc0,0x00002000);
1237
1238     return usb_uhci_common_initfn(dev);
1239 }
1240
1241 static int usb_uhci_exit(PCIDevice *dev)
1242 {
1243     UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1244
1245     memory_region_destroy(&s->io_bar);
1246     return 0;
1247 }
1248
1249 static Property uhci_properties[] = {
1250     DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1251     DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1252     DEFINE_PROP_END_OF_LIST(),
1253 };
1254
1255 static void piix3_uhci_class_init(ObjectClass *klass, void *data)
1256 {
1257     DeviceClass *dc = DEVICE_CLASS(klass);
1258     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1259
1260     k->init = usb_uhci_common_initfn;
1261     k->exit = usb_uhci_exit;
1262     k->vendor_id = PCI_VENDOR_ID_INTEL;
1263     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2;
1264     k->revision = 0x01;
1265     k->class_id = PCI_CLASS_SERIAL_USB;
1266     dc->vmsd = &vmstate_uhci;
1267     dc->props = uhci_properties;
1268 }
1269
1270 static TypeInfo piix3_uhci_info = {
1271     .name          = "piix3-usb-uhci",
1272     .parent        = TYPE_PCI_DEVICE,
1273     .instance_size = sizeof(UHCIState),
1274     .class_init    = piix3_uhci_class_init,
1275 };
1276
1277 static void piix4_uhci_class_init(ObjectClass *klass, void *data)
1278 {
1279     DeviceClass *dc = DEVICE_CLASS(klass);
1280     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1281
1282     k->init = usb_uhci_common_initfn;
1283     k->exit = usb_uhci_exit;
1284     k->vendor_id = PCI_VENDOR_ID_INTEL;
1285     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2;
1286     k->revision = 0x01;
1287     k->class_id = PCI_CLASS_SERIAL_USB;
1288     dc->vmsd = &vmstate_uhci;
1289     dc->props = uhci_properties;
1290 }
1291
1292 static TypeInfo piix4_uhci_info = {
1293     .name          = "piix4-usb-uhci",
1294     .parent        = TYPE_PCI_DEVICE,
1295     .instance_size = sizeof(UHCIState),
1296     .class_init    = piix4_uhci_class_init,
1297 };
1298
1299 static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data)
1300 {
1301     DeviceClass *dc = DEVICE_CLASS(klass);
1302     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1303
1304     k->init = usb_uhci_vt82c686b_initfn;
1305     k->exit = usb_uhci_exit;
1306     k->vendor_id = PCI_VENDOR_ID_VIA;
1307     k->device_id = PCI_DEVICE_ID_VIA_UHCI;
1308     k->revision = 0x01;
1309     k->class_id = PCI_CLASS_SERIAL_USB;
1310     dc->vmsd = &vmstate_uhci;
1311     dc->props = uhci_properties;
1312 }
1313
1314 static TypeInfo vt82c686b_uhci_info = {
1315     .name          = "vt82c686b-usb-uhci",
1316     .parent        = TYPE_PCI_DEVICE,
1317     .instance_size = sizeof(UHCIState),
1318     .class_init    = vt82c686b_uhci_class_init,
1319 };
1320
1321 static void ich9_uhci1_class_init(ObjectClass *klass, void *data)
1322 {
1323     DeviceClass *dc = DEVICE_CLASS(klass);
1324     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1325
1326     k->init = usb_uhci_common_initfn;
1327     k->vendor_id = PCI_VENDOR_ID_INTEL;
1328     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1;
1329     k->revision = 0x03;
1330     k->class_id = PCI_CLASS_SERIAL_USB;
1331     dc->vmsd = &vmstate_uhci;
1332     dc->props = uhci_properties;
1333 }
1334
1335 static TypeInfo ich9_uhci1_info = {
1336     .name          = "ich9-usb-uhci1",
1337     .parent        = TYPE_PCI_DEVICE,
1338     .instance_size = sizeof(UHCIState),
1339     .class_init    = ich9_uhci1_class_init,
1340 };
1341
1342 static void ich9_uhci2_class_init(ObjectClass *klass, void *data)
1343 {
1344     DeviceClass *dc = DEVICE_CLASS(klass);
1345     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1346
1347     k->init = usb_uhci_common_initfn;
1348     k->vendor_id = PCI_VENDOR_ID_INTEL;
1349     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2;
1350     k->revision = 0x03;
1351     k->class_id = PCI_CLASS_SERIAL_USB;
1352     dc->vmsd = &vmstate_uhci;
1353     dc->props = uhci_properties;
1354 }
1355
1356 static TypeInfo ich9_uhci2_info = {
1357     .name          = "ich9-usb-uhci2",
1358     .parent        = TYPE_PCI_DEVICE,
1359     .instance_size = sizeof(UHCIState),
1360     .class_init    = ich9_uhci2_class_init,
1361 };
1362
1363 static void ich9_uhci3_class_init(ObjectClass *klass, void *data)
1364 {
1365     DeviceClass *dc = DEVICE_CLASS(klass);
1366     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1367
1368     k->init = usb_uhci_common_initfn;
1369     k->vendor_id = PCI_VENDOR_ID_INTEL;
1370     k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3;
1371     k->revision = 0x03;
1372     k->class_id = PCI_CLASS_SERIAL_USB;
1373     dc->vmsd = &vmstate_uhci;
1374     dc->props = uhci_properties;
1375 }
1376
1377 static TypeInfo ich9_uhci3_info = {
1378     .name          = "ich9-usb-uhci3",
1379     .parent        = TYPE_PCI_DEVICE,
1380     .instance_size = sizeof(UHCIState),
1381     .class_init    = ich9_uhci3_class_init,
1382 };
1383
1384 static void uhci_register_types(void)
1385 {
1386     type_register_static(&piix3_uhci_info);
1387     type_register_static(&piix4_uhci_info);
1388     type_register_static(&vt82c686b_uhci_info);
1389     type_register_static(&ich9_uhci1_info);
1390     type_register_static(&ich9_uhci2_info);
1391     type_register_static(&ich9_uhci3_info);
1392 }
1393
1394 type_init(uhci_register_types)