2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "hw/pci/pci.h"
31 #include "qemu/timer.h"
33 #include "sysemu/dma.h"
37 //#define DEBUG_DUMP_DATA
39 #define UHCI_CMD_FGR (1 << 4)
40 #define UHCI_CMD_EGSM (1 << 3)
41 #define UHCI_CMD_GRESET (1 << 2)
42 #define UHCI_CMD_HCRESET (1 << 1)
43 #define UHCI_CMD_RS (1 << 0)
45 #define UHCI_STS_HCHALTED (1 << 5)
46 #define UHCI_STS_HCPERR (1 << 4)
47 #define UHCI_STS_HSERR (1 << 3)
48 #define UHCI_STS_RD (1 << 2)
49 #define UHCI_STS_USBERR (1 << 1)
50 #define UHCI_STS_USBINT (1 << 0)
52 #define TD_CTRL_SPD (1 << 29)
53 #define TD_CTRL_ERROR_SHIFT 27
54 #define TD_CTRL_IOS (1 << 25)
55 #define TD_CTRL_IOC (1 << 24)
56 #define TD_CTRL_ACTIVE (1 << 23)
57 #define TD_CTRL_STALL (1 << 22)
58 #define TD_CTRL_BABBLE (1 << 20)
59 #define TD_CTRL_NAK (1 << 19)
60 #define TD_CTRL_TIMEOUT (1 << 18)
62 #define UHCI_PORT_SUSPEND (1 << 12)
63 #define UHCI_PORT_RESET (1 << 9)
64 #define UHCI_PORT_LSDA (1 << 8)
65 #define UHCI_PORT_RD (1 << 6)
66 #define UHCI_PORT_ENC (1 << 3)
67 #define UHCI_PORT_EN (1 << 2)
68 #define UHCI_PORT_CSC (1 << 1)
69 #define UHCI_PORT_CCS (1 << 0)
71 #define UHCI_PORT_READ_ONLY (0x1bb)
72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
74 #define FRAME_TIMER_FREQ 1000
76 #define FRAME_MAX_LOOPS 256
78 /* Must be large enough to handle 10 frame delay for initial isoc requests */
81 #define MAX_FRAMES_PER_TICK (QH_VALID / 2)
86 TD_RESULT_STOP_FRAME
= 10,
89 TD_RESULT_ASYNC_START
,
93 typedef struct UHCIState UHCIState
;
94 typedef struct UHCIAsync UHCIAsync
;
95 typedef struct UHCIQueue UHCIQueue
;
96 typedef struct UHCIInfo UHCIInfo
;
97 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass
;
105 int (*initfn
)(PCIDevice
*dev
);
109 struct UHCIPCIDeviceClass
{
110 PCIDeviceClass parent_class
;
115 * Pending async transaction.
116 * 'packet' must be the first field because completion
117 * handler does "(UHCIAsync *) pkt" cast.
124 QTAILQ_ENTRY(UHCIAsync
) next
;
134 QTAILQ_ENTRY(UHCIQueue
) next
;
135 QTAILQ_HEAD(asyncs_head
, UHCIAsync
) asyncs
;
139 typedef struct UHCIPort
{
147 USBBus bus
; /* Note unused when we're a companion controller */
148 uint16_t cmd
; /* cmd register */
150 uint16_t intr
; /* interrupt enable register */
151 uint16_t frnum
; /* frame number */
152 uint32_t fl_base_addr
; /* frame list base address */
154 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
156 QEMUTimer
*frame_timer
;
158 uint32_t frame_bytes
;
159 uint32_t frame_bandwidth
;
160 bool completions_only
;
161 UHCIPort ports
[NB_PORTS
];
163 /* Interrupts that should be raised at the end of the current frame. */
164 uint32_t pending_int_mask
;
168 QTAILQ_HEAD(, UHCIQueue
) queues
;
169 uint8_t num_ports_vmstate
;
177 typedef struct UHCI_TD
{
179 uint32_t ctrl
; /* see TD_CTRL_xxx */
184 typedef struct UHCI_QH
{
189 static void uhci_async_cancel(UHCIAsync
*async
);
190 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
);
192 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
194 if ((td
->token
& (0xf << 15)) == 0) {
195 /* ctrl ep, cover ep and dev, not pid! */
196 return td
->token
& 0x7ff00;
198 /* covers ep, dev, pid -> identifies the endpoint */
199 return td
->token
& 0x7ffff;
203 static UHCIQueue
*uhci_queue_new(UHCIState
*s
, uint32_t qh_addr
, UHCI_TD
*td
,
208 queue
= g_new0(UHCIQueue
, 1);
210 queue
->qh_addr
= qh_addr
;
211 queue
->token
= uhci_queue_token(td
);
213 QTAILQ_INIT(&queue
->asyncs
);
214 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
215 queue
->valid
= QH_VALID
;
216 trace_usb_uhci_queue_add(queue
->token
);
220 static void uhci_queue_free(UHCIQueue
*queue
, const char *reason
)
222 UHCIState
*s
= queue
->uhci
;
225 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
226 async
= QTAILQ_FIRST(&queue
->asyncs
);
227 uhci_async_cancel(async
);
229 usb_device_ep_stopped(queue
->ep
->dev
, queue
->ep
);
231 trace_usb_uhci_queue_del(queue
->token
, reason
);
232 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
236 static UHCIQueue
*uhci_queue_find(UHCIState
*s
, UHCI_TD
*td
)
238 uint32_t token
= uhci_queue_token(td
);
241 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
242 if (queue
->token
== token
) {
249 static bool uhci_queue_verify(UHCIQueue
*queue
, uint32_t qh_addr
, UHCI_TD
*td
,
250 uint32_t td_addr
, bool queuing
)
252 UHCIAsync
*first
= QTAILQ_FIRST(&queue
->asyncs
);
254 return queue
->qh_addr
== qh_addr
&&
255 queue
->token
== uhci_queue_token(td
) &&
256 (queuing
|| !(td
->ctrl
& TD_CTRL_ACTIVE
) || first
== NULL
||
257 first
->td_addr
== td_addr
);
260 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
, uint32_t td_addr
)
262 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
264 async
->queue
= queue
;
265 async
->td_addr
= td_addr
;
266 usb_packet_init(&async
->packet
);
267 pci_dma_sglist_init(&async
->sgl
, &queue
->uhci
->dev
, 1);
268 trace_usb_uhci_packet_add(async
->queue
->token
, async
->td_addr
);
273 static void uhci_async_free(UHCIAsync
*async
)
275 trace_usb_uhci_packet_del(async
->queue
->token
, async
->td_addr
);
276 usb_packet_cleanup(&async
->packet
);
277 qemu_sglist_destroy(&async
->sgl
);
281 static void uhci_async_link(UHCIAsync
*async
)
283 UHCIQueue
*queue
= async
->queue
;
284 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
285 trace_usb_uhci_packet_link_async(async
->queue
->token
, async
->td_addr
);
288 static void uhci_async_unlink(UHCIAsync
*async
)
290 UHCIQueue
*queue
= async
->queue
;
291 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
292 trace_usb_uhci_packet_unlink_async(async
->queue
->token
, async
->td_addr
);
295 static void uhci_async_cancel(UHCIAsync
*async
)
297 uhci_async_unlink(async
);
298 trace_usb_uhci_packet_cancel(async
->queue
->token
, async
->td_addr
,
301 usb_cancel_packet(&async
->packet
);
302 usb_packet_unmap(&async
->packet
, &async
->sgl
);
303 uhci_async_free(async
);
307 * Mark all outstanding async packets as invalid.
308 * This is used for canceling them when TDs are removed by the HCD.
310 static void uhci_async_validate_begin(UHCIState
*s
)
314 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
320 * Cancel async packets that are no longer valid
322 static void uhci_async_validate_end(UHCIState
*s
)
324 UHCIQueue
*queue
, *n
;
326 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
328 uhci_queue_free(queue
, "validate-end");
333 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
335 UHCIQueue
*queue
, *n
;
337 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
338 if (queue
->ep
->dev
== dev
) {
339 uhci_queue_free(queue
, "cancel-device");
344 static void uhci_async_cancel_all(UHCIState
*s
)
346 UHCIQueue
*queue
, *nq
;
348 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, nq
) {
349 uhci_queue_free(queue
, "cancel-all");
353 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t td_addr
)
358 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
359 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
360 if (async
->td_addr
== td_addr
) {
368 static void uhci_update_irq(UHCIState
*s
)
371 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
372 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
373 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
374 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
375 (s
->status
& UHCI_STS_HSERR
) ||
376 (s
->status
& UHCI_STS_HCPERR
)) {
381 qemu_set_irq(s
->dev
.irq
[s
->irq_pin
], level
);
384 static void uhci_reset(void *opaque
)
386 UHCIState
*s
= opaque
;
391 trace_usb_uhci_reset();
393 pci_conf
= s
->dev
.config
;
395 pci_conf
[0x6a] = 0x01; /* usb clock */
396 pci_conf
[0x6b] = 0x00;
404 for(i
= 0; i
< NB_PORTS
; i
++) {
407 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
408 usb_port_reset(&port
->port
);
412 uhci_async_cancel_all(s
);
413 qemu_bh_cancel(s
->bh
);
417 static const VMStateDescription vmstate_uhci_port
= {
420 .minimum_version_id
= 1,
421 .minimum_version_id_old
= 1,
422 .fields
= (VMStateField
[]) {
423 VMSTATE_UINT16(ctrl
, UHCIPort
),
424 VMSTATE_END_OF_LIST()
428 static int uhci_post_load(void *opaque
, int version_id
)
430 UHCIState
*s
= opaque
;
432 if (version_id
< 2) {
433 s
->expire_time
= qemu_get_clock_ns(vm_clock
) +
434 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
439 static const VMStateDescription vmstate_uhci
= {
442 .minimum_version_id
= 1,
443 .minimum_version_id_old
= 1,
444 .post_load
= uhci_post_load
,
445 .fields
= (VMStateField
[]) {
446 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
447 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
),
448 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
449 vmstate_uhci_port
, UHCIPort
),
450 VMSTATE_UINT16(cmd
, UHCIState
),
451 VMSTATE_UINT16(status
, UHCIState
),
452 VMSTATE_UINT16(intr
, UHCIState
),
453 VMSTATE_UINT16(frnum
, UHCIState
),
454 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
455 VMSTATE_UINT8(sof_timing
, UHCIState
),
456 VMSTATE_UINT8(status2
, UHCIState
),
457 VMSTATE_TIMER(frame_timer
, UHCIState
),
458 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
459 VMSTATE_UINT32_V(pending_int_mask
, UHCIState
, 3),
460 VMSTATE_END_OF_LIST()
464 static void uhci_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
466 UHCIState
*s
= opaque
;
476 static uint32_t uhci_ioport_readb(void *opaque
, uint32_t addr
)
478 UHCIState
*s
= opaque
;
493 static void uhci_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
495 UHCIState
*s
= opaque
;
498 trace_usb_uhci_mmio_writew(addr
, val
);
502 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
503 /* start frame processing */
504 trace_usb_uhci_schedule_start();
505 s
->expire_time
= qemu_get_clock_ns(vm_clock
) +
506 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
507 qemu_mod_timer(s
->frame_timer
, s
->expire_time
);
508 s
->status
&= ~UHCI_STS_HCHALTED
;
509 } else if (!(val
& UHCI_CMD_RS
)) {
510 s
->status
|= UHCI_STS_HCHALTED
;
512 if (val
& UHCI_CMD_GRESET
) {
516 /* send reset on the USB bus */
517 for(i
= 0; i
< NB_PORTS
; i
++) {
519 usb_device_reset(port
->port
.dev
);
524 if (val
& UHCI_CMD_HCRESET
) {
532 /* XXX: the chip spec is not coherent, so we add a hidden
533 register to distinguish between IOC and SPD */
534 if (val
& UHCI_STS_USBINT
)
543 if (s
->status
& UHCI_STS_HCHALTED
)
544 s
->frnum
= val
& 0x7ff;
556 dev
= port
->port
.dev
;
557 if (dev
&& dev
->attached
) {
559 if ( (val
& UHCI_PORT_RESET
) &&
560 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
561 usb_device_reset(dev
);
564 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
565 /* enabled may only be set if a device is connected */
566 if (!(port
->ctrl
& UHCI_PORT_CCS
)) {
567 val
&= ~UHCI_PORT_EN
;
569 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
570 /* some bits are reset when a '1' is written to them */
571 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
577 static uint32_t uhci_ioport_readw(void *opaque
, uint32_t addr
)
579 UHCIState
*s
= opaque
;
609 val
= 0xff7f; /* disabled port */
613 trace_usb_uhci_mmio_readw(addr
, val
);
618 static void uhci_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
620 UHCIState
*s
= opaque
;
623 trace_usb_uhci_mmio_writel(addr
, val
);
627 s
->fl_base_addr
= val
& ~0xfff;
632 static uint32_t uhci_ioport_readl(void *opaque
, uint32_t addr
)
634 UHCIState
*s
= opaque
;
640 val
= s
->fl_base_addr
;
646 trace_usb_uhci_mmio_readl(addr
, val
);
650 /* signal resume if controller suspended */
651 static void uhci_resume (void *opaque
)
653 UHCIState
*s
= (UHCIState
*)opaque
;
658 if (s
->cmd
& UHCI_CMD_EGSM
) {
659 s
->cmd
|= UHCI_CMD_FGR
;
660 s
->status
|= UHCI_STS_RD
;
665 static void uhci_attach(USBPort
*port1
)
667 UHCIState
*s
= port1
->opaque
;
668 UHCIPort
*port
= &s
->ports
[port1
->index
];
670 /* set connect status */
671 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
674 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
675 port
->ctrl
|= UHCI_PORT_LSDA
;
677 port
->ctrl
&= ~UHCI_PORT_LSDA
;
683 static void uhci_detach(USBPort
*port1
)
685 UHCIState
*s
= port1
->opaque
;
686 UHCIPort
*port
= &s
->ports
[port1
->index
];
688 uhci_async_cancel_device(s
, port1
->dev
);
690 /* set connect status */
691 if (port
->ctrl
& UHCI_PORT_CCS
) {
692 port
->ctrl
&= ~UHCI_PORT_CCS
;
693 port
->ctrl
|= UHCI_PORT_CSC
;
696 if (port
->ctrl
& UHCI_PORT_EN
) {
697 port
->ctrl
&= ~UHCI_PORT_EN
;
698 port
->ctrl
|= UHCI_PORT_ENC
;
704 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
706 UHCIState
*s
= port1
->opaque
;
708 uhci_async_cancel_device(s
, child
);
711 static void uhci_wakeup(USBPort
*port1
)
713 UHCIState
*s
= port1
->opaque
;
714 UHCIPort
*port
= &s
->ports
[port1
->index
];
716 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
717 port
->ctrl
|= UHCI_PORT_RD
;
722 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
727 for (i
= 0; i
< NB_PORTS
; i
++) {
728 UHCIPort
*port
= &s
->ports
[i
];
729 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
732 dev
= usb_find_device(&port
->port
, addr
);
740 static void uhci_read_td(UHCIState
*s
, UHCI_TD
*td
, uint32_t link
)
742 pci_dma_read(&s
->dev
, link
& ~0xf, td
, sizeof(*td
));
743 le32_to_cpus(&td
->link
);
744 le32_to_cpus(&td
->ctrl
);
745 le32_to_cpus(&td
->token
);
746 le32_to_cpus(&td
->buffer
);
749 static int uhci_handle_td_error(UHCIState
*s
, UHCI_TD
*td
, uint32_t td_addr
,
750 int status
, uint32_t *int_mask
)
752 uint32_t queue_token
= uhci_queue_token(td
);
757 td
->ctrl
|= TD_CTRL_NAK
;
758 return TD_RESULT_NEXT_QH
;
761 td
->ctrl
|= TD_CTRL_STALL
;
762 trace_usb_uhci_packet_complete_stall(queue_token
, td_addr
);
763 ret
= TD_RESULT_NEXT_QH
;
767 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
768 /* frame interrupted */
769 trace_usb_uhci_packet_complete_babble(queue_token
, td_addr
);
770 ret
= TD_RESULT_STOP_FRAME
;
773 case USB_RET_IOERROR
:
776 td
->ctrl
|= TD_CTRL_TIMEOUT
;
777 td
->ctrl
&= ~(3 << TD_CTRL_ERROR_SHIFT
);
778 trace_usb_uhci_packet_complete_error(queue_token
, td_addr
);
779 ret
= TD_RESULT_NEXT_QH
;
783 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
784 s
->status
|= UHCI_STS_USBERR
;
785 if (td
->ctrl
& TD_CTRL_IOC
) {
792 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
794 int len
= 0, max_len
;
797 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
798 pid
= td
->token
& 0xff;
800 if (td
->ctrl
& TD_CTRL_IOS
)
801 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
803 if (async
->packet
.status
!= USB_RET_SUCCESS
) {
804 return uhci_handle_td_error(s
, td
, async
->td_addr
,
805 async
->packet
.status
, int_mask
);
808 len
= async
->packet
.actual_length
;
809 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
811 /* The NAK bit may have been set by a previous frame, so clear it
812 here. The docs are somewhat unclear, but win2k relies on this
814 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
815 if (td
->ctrl
& TD_CTRL_IOC
)
818 if (pid
== USB_TOKEN_IN
) {
819 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
821 /* short packet: do not update QH */
822 trace_usb_uhci_packet_complete_shortxfer(async
->queue
->token
,
824 return TD_RESULT_NEXT_QH
;
829 trace_usb_uhci_packet_complete_success(async
->queue
->token
,
831 return TD_RESULT_COMPLETE
;
834 static int uhci_handle_td(UHCIState
*s
, UHCIQueue
*q
, uint32_t qh_addr
,
835 UHCI_TD
*td
, uint32_t td_addr
, uint32_t *int_mask
)
839 bool queuing
= (q
!= NULL
);
840 uint8_t pid
= td
->token
& 0xff;
841 UHCIAsync
*async
= uhci_async_find_td(s
, td_addr
);
844 if (uhci_queue_verify(async
->queue
, qh_addr
, td
, td_addr
, queuing
)) {
845 assert(q
== NULL
|| q
== async
->queue
);
848 uhci_queue_free(async
->queue
, "guest re-used pending td");
854 q
= uhci_queue_find(s
, td
);
855 if (q
&& !uhci_queue_verify(q
, qh_addr
, td
, td_addr
, queuing
)) {
856 uhci_queue_free(q
, "guest re-used qh");
866 if (!(td
->ctrl
& TD_CTRL_ACTIVE
)) {
868 /* Guest marked a pending td non-active, cancel the queue */
869 uhci_queue_free(async
->queue
, "pending td non-active");
872 * ehci11d spec page 22: "Even if the Active bit in the TD is already
873 * cleared when the TD is fetched ... an IOC interrupt is generated"
875 if (td
->ctrl
& TD_CTRL_IOC
) {
878 return TD_RESULT_NEXT_QH
;
883 /* we are busy filling the queue, we are not prepared
884 to consume completed packages then, just leave them
886 return TD_RESULT_ASYNC_CONT
;
890 UHCIAsync
*last
= QTAILQ_LAST(&async
->queue
->asyncs
, asyncs_head
);
892 * While we are waiting for the current td to complete, the guest
893 * may have added more tds to the queue. Note we re-read the td
894 * rather then caching it, as we want to see guest made changes!
896 uhci_read_td(s
, &last_td
, last
->td_addr
);
897 uhci_queue_fill(async
->queue
, &last_td
);
899 return TD_RESULT_ASYNC_CONT
;
901 uhci_async_unlink(async
);
905 if (s
->completions_only
) {
906 return TD_RESULT_ASYNC_CONT
;
909 /* Allocate new packet */
911 USBDevice
*dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
912 USBEndpoint
*ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
915 return uhci_handle_td_error(s
, td
, td_addr
, USB_RET_NODEV
,
918 q
= uhci_queue_new(s
, qh_addr
, td
, ep
);
920 async
= uhci_async_alloc(q
, td_addr
);
922 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
923 spd
= (pid
== USB_TOKEN_IN
&& (td
->ctrl
& TD_CTRL_SPD
) != 0);
924 usb_packet_setup(&async
->packet
, pid
, q
->ep
, td_addr
, spd
,
925 (td
->ctrl
& TD_CTRL_IOC
) != 0);
926 qemu_sglist_add(&async
->sgl
, td
->buffer
, max_len
);
927 usb_packet_map(&async
->packet
, &async
->sgl
);
931 case USB_TOKEN_SETUP
:
932 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
933 if (async
->packet
.status
== USB_RET_SUCCESS
) {
934 async
->packet
.actual_length
= max_len
;
939 usb_handle_packet(q
->ep
->dev
, &async
->packet
);
943 /* invalid pid : frame interrupted */
944 usb_packet_unmap(&async
->packet
, &async
->sgl
);
945 uhci_async_free(async
);
946 s
->status
|= UHCI_STS_HCPERR
;
948 return TD_RESULT_STOP_FRAME
;
951 if (async
->packet
.status
== USB_RET_ASYNC
) {
952 uhci_async_link(async
);
954 uhci_queue_fill(q
, td
);
956 return TD_RESULT_ASYNC_START
;
960 ret
= uhci_complete_td(s
, td
, async
, int_mask
);
961 usb_packet_unmap(&async
->packet
, &async
->sgl
);
962 uhci_async_free(async
);
966 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
968 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
969 UHCIState
*s
= async
->queue
->uhci
;
971 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
972 uhci_async_cancel(async
);
977 /* Force processing of this packet *now*, needed for migration */
978 s
->completions_only
= true;
979 qemu_bh_schedule(s
->bh
);
982 static int is_valid(uint32_t link
)
984 return (link
& 1) == 0;
987 static int is_qh(uint32_t link
)
989 return (link
& 2) != 0;
992 static int depth_first(uint32_t link
)
994 return (link
& 4) != 0;
997 /* QH DB used for detecting QH loops */
998 #define UHCI_MAX_QUEUES 128
1000 uint32_t addr
[UHCI_MAX_QUEUES
];
1004 static void qhdb_reset(QhDb
*db
)
1009 /* Add QH to DB. Returns 1 if already present or DB is full. */
1010 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
1013 for (i
= 0; i
< db
->count
; i
++)
1014 if (db
->addr
[i
] == addr
)
1017 if (db
->count
>= UHCI_MAX_QUEUES
)
1020 db
->addr
[db
->count
++] = addr
;
1024 static void uhci_queue_fill(UHCIQueue
*q
, UHCI_TD
*td
)
1026 uint32_t int_mask
= 0;
1027 uint32_t plink
= td
->link
;
1031 while (is_valid(plink
)) {
1032 uhci_read_td(q
->uhci
, &ptd
, plink
);
1033 if (!(ptd
.ctrl
& TD_CTRL_ACTIVE
)) {
1036 if (uhci_queue_token(&ptd
) != q
->token
) {
1039 trace_usb_uhci_td_queue(plink
& ~0xf, ptd
.ctrl
, ptd
.token
);
1040 ret
= uhci_handle_td(q
->uhci
, q
, q
->qh_addr
, &ptd
, plink
, &int_mask
);
1041 if (ret
== TD_RESULT_ASYNC_CONT
) {
1044 assert(ret
== TD_RESULT_ASYNC_START
);
1045 assert(int_mask
== 0);
1048 usb_device_flush_ep_queue(q
->ep
->dev
, q
->ep
);
1051 static void uhci_process_frame(UHCIState
*s
)
1053 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
1054 uint32_t curr_qh
, td_count
= 0;
1060 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
1062 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
1063 le32_to_cpus(&link
);
1070 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
1071 if (!s
->completions_only
&& s
->frame_bytes
>= s
->frame_bandwidth
) {
1072 /* We've reached the usb 1.1 bandwidth, which is
1073 1280 bytes/frame, stop processing */
1074 trace_usb_uhci_frame_stop_bandwidth();
1079 trace_usb_uhci_qh_load(link
& ~0xf);
1081 if (qhdb_insert(&qhdb
, link
)) {
1083 * We're going in circles. Which is not a bug because
1084 * HCD is allowed to do that as part of the BW management.
1086 * Stop processing here if no transaction has been done
1087 * since we've been here last time.
1089 if (td_count
== 0) {
1090 trace_usb_uhci_frame_loop_stop_idle();
1093 trace_usb_uhci_frame_loop_continue();
1096 qhdb_insert(&qhdb
, link
);
1100 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
1101 le32_to_cpus(&qh
.link
);
1102 le32_to_cpus(&qh
.el_link
);
1104 if (!is_valid(qh
.el_link
)) {
1105 /* QH w/o elements */
1109 /* QH with elements */
1117 uhci_read_td(s
, &td
, link
);
1118 trace_usb_uhci_td_load(curr_qh
& ~0xf, link
& ~0xf, td
.ctrl
, td
.token
);
1120 old_td_ctrl
= td
.ctrl
;
1121 ret
= uhci_handle_td(s
, NULL
, curr_qh
, &td
, link
, &int_mask
);
1122 if (old_td_ctrl
!= td
.ctrl
) {
1123 /* update the status bits of the TD */
1124 val
= cpu_to_le32(td
.ctrl
);
1125 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1129 case TD_RESULT_STOP_FRAME
: /* interrupted frame */
1132 case TD_RESULT_NEXT_QH
:
1133 case TD_RESULT_ASYNC_CONT
:
1134 trace_usb_uhci_td_nextqh(curr_qh
& ~0xf, link
& ~0xf);
1135 link
= curr_qh
? qh
.link
: td
.link
;
1138 case TD_RESULT_ASYNC_START
:
1139 trace_usb_uhci_td_async(curr_qh
& ~0xf, link
& ~0xf);
1140 link
= curr_qh
? qh
.link
: td
.link
;
1143 case TD_RESULT_COMPLETE
:
1144 trace_usb_uhci_td_complete(curr_qh
& ~0xf, link
& ~0xf);
1147 s
->frame_bytes
+= (td
.ctrl
& 0x7ff) + 1;
1150 /* update QH element link */
1152 val
= cpu_to_le32(qh
.el_link
);
1153 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1155 if (!depth_first(link
)) {
1156 /* done with this QH */
1164 assert(!"unknown return code");
1167 /* go to the next entry */
1171 s
->pending_int_mask
|= int_mask
;
1174 static void uhci_bh(void *opaque
)
1176 UHCIState
*s
= opaque
;
1177 uhci_process_frame(s
);
1180 static void uhci_frame_timer(void *opaque
)
1182 UHCIState
*s
= opaque
;
1183 uint64_t t_now
, t_last_run
;
1185 const uint64_t frame_t
= get_ticks_per_sec() / FRAME_TIMER_FREQ
;
1187 s
->completions_only
= false;
1188 qemu_bh_cancel(s
->bh
);
1190 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1192 trace_usb_uhci_schedule_stop();
1193 qemu_del_timer(s
->frame_timer
);
1194 uhci_async_cancel_all(s
);
1195 /* set hchalted bit in status - UHCI11D 2.1.2 */
1196 s
->status
|= UHCI_STS_HCHALTED
;
1200 /* We still store expire_time in our state, for migration */
1201 t_last_run
= s
->expire_time
- frame_t
;
1202 t_now
= qemu_get_clock_ns(vm_clock
);
1204 /* Process up to MAX_FRAMES_PER_TICK frames */
1205 frames
= (t_now
- t_last_run
) / frame_t
;
1206 if (frames
> s
->maxframes
) {
1207 int skipped
= frames
- s
->maxframes
;
1208 s
->expire_time
+= skipped
* frame_t
;
1209 s
->frnum
= (s
->frnum
+ skipped
) & 0x7ff;
1212 if (frames
> MAX_FRAMES_PER_TICK
) {
1213 frames
= MAX_FRAMES_PER_TICK
;
1216 for (i
= 0; i
< frames
; i
++) {
1218 trace_usb_uhci_frame_start(s
->frnum
);
1219 uhci_async_validate_begin(s
);
1220 uhci_process_frame(s
);
1221 uhci_async_validate_end(s
);
1222 /* The spec says frnum is the frame currently being processed, and
1223 * the guest must look at frnum - 1 on interrupt, so inc frnum now */
1224 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1225 s
->expire_time
+= frame_t
;
1228 /* Complete the previous frame(s) */
1229 if (s
->pending_int_mask
) {
1230 s
->status2
|= s
->pending_int_mask
;
1231 s
->status
|= UHCI_STS_USBINT
;
1234 s
->pending_int_mask
= 0;
1236 qemu_mod_timer(s
->frame_timer
, t_now
+ frame_t
);
1239 static const MemoryRegionPortio uhci_portio
[] = {
1240 { 0, 32, 2, .write
= uhci_ioport_writew
, },
1241 { 0, 32, 2, .read
= uhci_ioport_readw
, },
1242 { 0, 32, 4, .write
= uhci_ioport_writel
, },
1243 { 0, 32, 4, .read
= uhci_ioport_readl
, },
1244 { 0, 32, 1, .write
= uhci_ioport_writeb
, },
1245 { 0, 32, 1, .read
= uhci_ioport_readb
, },
1246 PORTIO_END_OF_LIST()
1249 static const MemoryRegionOps uhci_ioport_ops
= {
1250 .old_portio
= uhci_portio
,
1253 static USBPortOps uhci_port_ops
= {
1254 .attach
= uhci_attach
,
1255 .detach
= uhci_detach
,
1256 .child_detach
= uhci_child_detach
,
1257 .wakeup
= uhci_wakeup
,
1258 .complete
= uhci_async_complete
,
1261 static USBBusOps uhci_bus_ops
= {
1264 static int usb_uhci_common_initfn(PCIDevice
*dev
)
1266 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1267 UHCIPCIDeviceClass
*u
= container_of(pc
, UHCIPCIDeviceClass
, parent_class
);
1268 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1269 uint8_t *pci_conf
= s
->dev
.config
;
1272 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1273 /* TODO: reset value should be 0. */
1274 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; // release number
1276 s
->irq_pin
= u
->info
.irq_pin
;
1277 pci_config_set_interrupt_pin(pci_conf
, s
->irq_pin
+ 1);
1280 USBPort
*ports
[NB_PORTS
];
1281 for(i
= 0; i
< NB_PORTS
; i
++) {
1282 ports
[i
] = &s
->ports
[i
].port
;
1284 if (usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1285 s
->firstport
, s
, &uhci_port_ops
,
1286 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
) != 0) {
1290 usb_bus_new(&s
->bus
, &uhci_bus_ops
, &s
->dev
.qdev
);
1291 for (i
= 0; i
< NB_PORTS
; i
++) {
1292 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1293 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1296 s
->bh
= qemu_bh_new(uhci_bh
, s
);
1297 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, uhci_frame_timer
, s
);
1298 s
->num_ports_vmstate
= NB_PORTS
;
1299 QTAILQ_INIT(&s
->queues
);
1301 qemu_register_reset(uhci_reset
, s
);
1303 memory_region_init_io(&s
->io_bar
, &uhci_ioport_ops
, s
, "uhci", 0x20);
1304 /* Use region 4 for consistency with real hardware. BSD guests seem
1306 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1311 static int usb_uhci_vt82c686b_initfn(PCIDevice
*dev
)
1313 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1314 uint8_t *pci_conf
= s
->dev
.config
;
1316 /* USB misc control 1/2 */
1317 pci_set_long(pci_conf
+ 0x40,0x00001000);
1319 pci_set_long(pci_conf
+ 0x80,0x00020001);
1320 /* USB legacy support */
1321 pci_set_long(pci_conf
+ 0xc0,0x00002000);
1323 return usb_uhci_common_initfn(dev
);
1326 static void usb_uhci_exit(PCIDevice
*dev
)
1328 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1330 memory_region_destroy(&s
->io_bar
);
1333 static Property uhci_properties
[] = {
1334 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1335 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1336 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1337 DEFINE_PROP_UINT32("maxframes", UHCIState
, maxframes
, 128),
1338 DEFINE_PROP_END_OF_LIST(),
1341 static void uhci_class_init(ObjectClass
*klass
, void *data
)
1343 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1344 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1345 UHCIPCIDeviceClass
*u
= container_of(k
, UHCIPCIDeviceClass
, parent_class
);
1346 UHCIInfo
*info
= data
;
1348 k
->init
= info
->initfn
? info
->initfn
: usb_uhci_common_initfn
;
1349 k
->exit
= info
->unplug
? usb_uhci_exit
: NULL
;
1350 k
->vendor_id
= info
->vendor_id
;
1351 k
->device_id
= info
->device_id
;
1352 k
->revision
= info
->revision
;
1353 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1355 dc
->vmsd
= &vmstate_uhci
;
1356 dc
->props
= uhci_properties
;
1360 static UHCIInfo uhci_info
[] = {
1362 .name
= "piix3-usb-uhci",
1363 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1364 .device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
,
1369 .name
= "piix4-usb-uhci",
1370 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1371 .device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
,
1376 .name
= "vt82c686b-usb-uhci",
1377 .vendor_id
= PCI_VENDOR_ID_VIA
,
1378 .device_id
= PCI_DEVICE_ID_VIA_UHCI
,
1381 .initfn
= usb_uhci_vt82c686b_initfn
,
1384 .name
= "ich9-usb-uhci1", /* 00:1d.0 */
1385 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1386 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
,
1391 .name
= "ich9-usb-uhci2", /* 00:1d.1 */
1392 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1393 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
,
1398 .name
= "ich9-usb-uhci3", /* 00:1d.2 */
1399 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1400 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
,
1405 .name
= "ich9-usb-uhci4", /* 00:1a.0 */
1406 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1407 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI4
,
1412 .name
= "ich9-usb-uhci5", /* 00:1a.1 */
1413 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1414 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI5
,
1419 .name
= "ich9-usb-uhci6", /* 00:1a.2 */
1420 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1421 .device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI6
,
1428 static void uhci_register_types(void)
1430 TypeInfo uhci_type_info
= {
1431 .parent
= TYPE_PCI_DEVICE
,
1432 .instance_size
= sizeof(UHCIState
),
1433 .class_size
= sizeof(UHCIPCIDeviceClass
),
1434 .class_init
= uhci_class_init
,
1438 for (i
= 0; i
< ARRAY_SIZE(uhci_info
); i
++) {
1439 uhci_type_info
.name
= uhci_info
[i
].name
;
1440 uhci_type_info
.class_data
= uhci_info
+ i
;
1441 type_register(&uhci_type_info
);
1445 type_init(uhci_register_types
)