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uhci: Add a uhci_handle_td_error() helper function
[qemu.git] / hw / usb / hcd-uhci.c
1 /*
2 * USB UHCI controller emulation
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * THE SOFTWARE.
27 */
28 #include "hw/hw.h"
29 #include "hw/usb.h"
30 #include "hw/pci.h"
31 #include "qemu-timer.h"
32 #include "iov.h"
33 #include "dma.h"
34 #include "trace.h"
35
36 //#define DEBUG
37 //#define DEBUG_DUMP_DATA
38
39 #define UHCI_CMD_FGR (1 << 4)
40 #define UHCI_CMD_EGSM (1 << 3)
41 #define UHCI_CMD_GRESET (1 << 2)
42 #define UHCI_CMD_HCRESET (1 << 1)
43 #define UHCI_CMD_RS (1 << 0)
44
45 #define UHCI_STS_HCHALTED (1 << 5)
46 #define UHCI_STS_HCPERR (1 << 4)
47 #define UHCI_STS_HSERR (1 << 3)
48 #define UHCI_STS_RD (1 << 2)
49 #define UHCI_STS_USBERR (1 << 1)
50 #define UHCI_STS_USBINT (1 << 0)
51
52 #define TD_CTRL_SPD (1 << 29)
53 #define TD_CTRL_ERROR_SHIFT 27
54 #define TD_CTRL_IOS (1 << 25)
55 #define TD_CTRL_IOC (1 << 24)
56 #define TD_CTRL_ACTIVE (1 << 23)
57 #define TD_CTRL_STALL (1 << 22)
58 #define TD_CTRL_BABBLE (1 << 20)
59 #define TD_CTRL_NAK (1 << 19)
60 #define TD_CTRL_TIMEOUT (1 << 18)
61
62 #define UHCI_PORT_SUSPEND (1 << 12)
63 #define UHCI_PORT_RESET (1 << 9)
64 #define UHCI_PORT_LSDA (1 << 8)
65 #define UHCI_PORT_RD (1 << 6)
66 #define UHCI_PORT_ENC (1 << 3)
67 #define UHCI_PORT_EN (1 << 2)
68 #define UHCI_PORT_CSC (1 << 1)
69 #define UHCI_PORT_CCS (1 << 0)
70
71 #define UHCI_PORT_READ_ONLY (0x1bb)
72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
73
74 #define FRAME_TIMER_FREQ 1000
75
76 #define FRAME_MAX_LOOPS 256
77
78 #define NB_PORTS 2
79
80 enum {
81 TD_RESULT_STOP_FRAME = 10,
82 TD_RESULT_COMPLETE,
83 TD_RESULT_NEXT_QH,
84 TD_RESULT_ASYNC_START,
85 TD_RESULT_ASYNC_CONT,
86 };
87
88 typedef struct UHCIState UHCIState;
89 typedef struct UHCIAsync UHCIAsync;
90 typedef struct UHCIQueue UHCIQueue;
91 typedef struct UHCIInfo UHCIInfo;
92 typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass;
93
94 struct UHCIInfo {
95 const char *name;
96 uint16_t vendor_id;
97 uint16_t device_id;
98 uint8_t revision;
99 uint8_t irq_pin;
100 int (*initfn)(PCIDevice *dev);
101 bool unplug;
102 };
103
104 struct UHCIPCIDeviceClass {
105 PCIDeviceClass parent_class;
106 UHCIInfo info;
107 };
108
109 /*
110 * Pending async transaction.
111 * 'packet' must be the first field because completion
112 * handler does "(UHCIAsync *) pkt" cast.
113 */
114
115 struct UHCIAsync {
116 USBPacket packet;
117 QEMUSGList sgl;
118 UHCIQueue *queue;
119 QTAILQ_ENTRY(UHCIAsync) next;
120 uint32_t td_addr;
121 uint8_t done;
122 };
123
124 struct UHCIQueue {
125 uint32_t qh_addr;
126 uint32_t token;
127 UHCIState *uhci;
128 USBEndpoint *ep;
129 QTAILQ_ENTRY(UHCIQueue) next;
130 QTAILQ_HEAD(asyncs_head, UHCIAsync) asyncs;
131 int8_t valid;
132 };
133
134 typedef struct UHCIPort {
135 USBPort port;
136 uint16_t ctrl;
137 } UHCIPort;
138
139 struct UHCIState {
140 PCIDevice dev;
141 MemoryRegion io_bar;
142 USBBus bus; /* Note unused when we're a companion controller */
143 uint16_t cmd; /* cmd register */
144 uint16_t status;
145 uint16_t intr; /* interrupt enable register */
146 uint16_t frnum; /* frame number */
147 uint32_t fl_base_addr; /* frame list base address */
148 uint8_t sof_timing;
149 uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
150 int64_t expire_time;
151 QEMUTimer *frame_timer;
152 QEMUBH *bh;
153 uint32_t frame_bytes;
154 uint32_t frame_bandwidth;
155 UHCIPort ports[NB_PORTS];
156
157 /* Interrupts that should be raised at the end of the current frame. */
158 uint32_t pending_int_mask;
159 int irq_pin;
160
161 /* Active packets */
162 QTAILQ_HEAD(, UHCIQueue) queues;
163 uint8_t num_ports_vmstate;
164
165 /* Properties */
166 char *masterbus;
167 uint32_t firstport;
168 };
169
170 typedef struct UHCI_TD {
171 uint32_t link;
172 uint32_t ctrl; /* see TD_CTRL_xxx */
173 uint32_t token;
174 uint32_t buffer;
175 } UHCI_TD;
176
177 typedef struct UHCI_QH {
178 uint32_t link;
179 uint32_t el_link;
180 } UHCI_QH;
181
182 static void uhci_async_cancel(UHCIAsync *async);
183 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td);
184
185 static inline int32_t uhci_queue_token(UHCI_TD *td)
186 {
187 if ((td->token & (0xf << 15)) == 0) {
188 /* ctrl ep, cover ep and dev, not pid! */
189 return td->token & 0x7ff00;
190 } else {
191 /* covers ep, dev, pid -> identifies the endpoint */
192 return td->token & 0x7ffff;
193 }
194 }
195
196 static UHCIQueue *uhci_queue_new(UHCIState *s, uint32_t qh_addr, UHCI_TD *td,
197 USBEndpoint *ep)
198 {
199 UHCIQueue *queue;
200
201 queue = g_new0(UHCIQueue, 1);
202 queue->uhci = s;
203 queue->qh_addr = qh_addr;
204 queue->token = uhci_queue_token(td);
205 queue->ep = ep;
206 QTAILQ_INIT(&queue->asyncs);
207 QTAILQ_INSERT_HEAD(&s->queues, queue, next);
208 /* valid needs to be large enough to handle 10 frame delay
209 * for initial isochronous requests */
210 queue->valid = 32;
211 trace_usb_uhci_queue_add(queue->token);
212 return queue;
213 }
214
215 static void uhci_queue_free(UHCIQueue *queue, const char *reason)
216 {
217 UHCIState *s = queue->uhci;
218 UHCIAsync *async;
219
220 while (!QTAILQ_EMPTY(&queue->asyncs)) {
221 async = QTAILQ_FIRST(&queue->asyncs);
222 uhci_async_cancel(async);
223 }
224
225 trace_usb_uhci_queue_del(queue->token, reason);
226 QTAILQ_REMOVE(&s->queues, queue, next);
227 g_free(queue);
228 }
229
230 static UHCIQueue *uhci_queue_find(UHCIState *s, UHCI_TD *td)
231 {
232 uint32_t token = uhci_queue_token(td);
233 UHCIQueue *queue;
234
235 QTAILQ_FOREACH(queue, &s->queues, next) {
236 if (queue->token == token) {
237 return queue;
238 }
239 }
240 return NULL;
241 }
242
243 static bool uhci_queue_verify(UHCIQueue *queue, uint32_t qh_addr, UHCI_TD *td,
244 uint32_t td_addr, bool queuing)
245 {
246 UHCIAsync *first = QTAILQ_FIRST(&queue->asyncs);
247
248 return queue->qh_addr == qh_addr &&
249 queue->token == uhci_queue_token(td) &&
250 (queuing || !(td->ctrl & TD_CTRL_ACTIVE) || first == NULL ||
251 first->td_addr == td_addr);
252 }
253
254 static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t td_addr)
255 {
256 UHCIAsync *async = g_new0(UHCIAsync, 1);
257
258 async->queue = queue;
259 async->td_addr = td_addr;
260 usb_packet_init(&async->packet);
261 pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1);
262 trace_usb_uhci_packet_add(async->queue->token, async->td_addr);
263
264 return async;
265 }
266
267 static void uhci_async_free(UHCIAsync *async)
268 {
269 trace_usb_uhci_packet_del(async->queue->token, async->td_addr);
270 usb_packet_cleanup(&async->packet);
271 qemu_sglist_destroy(&async->sgl);
272 g_free(async);
273 }
274
275 static void uhci_async_link(UHCIAsync *async)
276 {
277 UHCIQueue *queue = async->queue;
278 QTAILQ_INSERT_TAIL(&queue->asyncs, async, next);
279 trace_usb_uhci_packet_link_async(async->queue->token, async->td_addr);
280 }
281
282 static void uhci_async_unlink(UHCIAsync *async)
283 {
284 UHCIQueue *queue = async->queue;
285 QTAILQ_REMOVE(&queue->asyncs, async, next);
286 trace_usb_uhci_packet_unlink_async(async->queue->token, async->td_addr);
287 }
288
289 static void uhci_async_cancel(UHCIAsync *async)
290 {
291 uhci_async_unlink(async);
292 trace_usb_uhci_packet_cancel(async->queue->token, async->td_addr,
293 async->done);
294 if (!async->done)
295 usb_cancel_packet(&async->packet);
296 usb_packet_unmap(&async->packet, &async->sgl);
297 uhci_async_free(async);
298 }
299
300 /*
301 * Mark all outstanding async packets as invalid.
302 * This is used for canceling them when TDs are removed by the HCD.
303 */
304 static void uhci_async_validate_begin(UHCIState *s)
305 {
306 UHCIQueue *queue;
307
308 QTAILQ_FOREACH(queue, &s->queues, next) {
309 queue->valid--;
310 }
311 }
312
313 /*
314 * Cancel async packets that are no longer valid
315 */
316 static void uhci_async_validate_end(UHCIState *s)
317 {
318 UHCIQueue *queue, *n;
319
320 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
321 if (!queue->valid) {
322 uhci_queue_free(queue, "validate-end");
323 }
324 }
325 }
326
327 static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev)
328 {
329 UHCIQueue *queue, *n;
330
331 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) {
332 if (queue->ep->dev == dev) {
333 uhci_queue_free(queue, "cancel-device");
334 }
335 }
336 }
337
338 static void uhci_async_cancel_all(UHCIState *s)
339 {
340 UHCIQueue *queue, *nq;
341
342 QTAILQ_FOREACH_SAFE(queue, &s->queues, next, nq) {
343 uhci_queue_free(queue, "cancel-all");
344 }
345 }
346
347 static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t td_addr)
348 {
349 UHCIQueue *queue;
350 UHCIAsync *async;
351
352 QTAILQ_FOREACH(queue, &s->queues, next) {
353 QTAILQ_FOREACH(async, &queue->asyncs, next) {
354 if (async->td_addr == td_addr) {
355 return async;
356 }
357 }
358 }
359 return NULL;
360 }
361
362 static void uhci_update_irq(UHCIState *s)
363 {
364 int level;
365 if (((s->status2 & 1) && (s->intr & (1 << 2))) ||
366 ((s->status2 & 2) && (s->intr & (1 << 3))) ||
367 ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) ||
368 ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) ||
369 (s->status & UHCI_STS_HSERR) ||
370 (s->status & UHCI_STS_HCPERR)) {
371 level = 1;
372 } else {
373 level = 0;
374 }
375 qemu_set_irq(s->dev.irq[s->irq_pin], level);
376 }
377
378 static void uhci_reset(void *opaque)
379 {
380 UHCIState *s = opaque;
381 uint8_t *pci_conf;
382 int i;
383 UHCIPort *port;
384
385 trace_usb_uhci_reset();
386
387 pci_conf = s->dev.config;
388
389 pci_conf[0x6a] = 0x01; /* usb clock */
390 pci_conf[0x6b] = 0x00;
391 s->cmd = 0;
392 s->status = 0;
393 s->status2 = 0;
394 s->intr = 0;
395 s->fl_base_addr = 0;
396 s->sof_timing = 64;
397
398 for(i = 0; i < NB_PORTS; i++) {
399 port = &s->ports[i];
400 port->ctrl = 0x0080;
401 if (port->port.dev && port->port.dev->attached) {
402 usb_port_reset(&port->port);
403 }
404 }
405
406 uhci_async_cancel_all(s);
407 qemu_bh_cancel(s->bh);
408 uhci_update_irq(s);
409 }
410
411 static const VMStateDescription vmstate_uhci_port = {
412 .name = "uhci port",
413 .version_id = 1,
414 .minimum_version_id = 1,
415 .minimum_version_id_old = 1,
416 .fields = (VMStateField []) {
417 VMSTATE_UINT16(ctrl, UHCIPort),
418 VMSTATE_END_OF_LIST()
419 }
420 };
421
422 static int uhci_post_load(void *opaque, int version_id)
423 {
424 UHCIState *s = opaque;
425
426 if (version_id < 2) {
427 s->expire_time = qemu_get_clock_ns(vm_clock) +
428 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
429 }
430 return 0;
431 }
432
433 static const VMStateDescription vmstate_uhci = {
434 .name = "uhci",
435 .version_id = 2,
436 .minimum_version_id = 1,
437 .minimum_version_id_old = 1,
438 .post_load = uhci_post_load,
439 .fields = (VMStateField []) {
440 VMSTATE_PCI_DEVICE(dev, UHCIState),
441 VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState),
442 VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1,
443 vmstate_uhci_port, UHCIPort),
444 VMSTATE_UINT16(cmd, UHCIState),
445 VMSTATE_UINT16(status, UHCIState),
446 VMSTATE_UINT16(intr, UHCIState),
447 VMSTATE_UINT16(frnum, UHCIState),
448 VMSTATE_UINT32(fl_base_addr, UHCIState),
449 VMSTATE_UINT8(sof_timing, UHCIState),
450 VMSTATE_UINT8(status2, UHCIState),
451 VMSTATE_TIMER(frame_timer, UHCIState),
452 VMSTATE_INT64_V(expire_time, UHCIState, 2),
453 VMSTATE_END_OF_LIST()
454 }
455 };
456
457 static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
458 {
459 UHCIState *s = opaque;
460
461 addr &= 0x1f;
462 switch(addr) {
463 case 0x0c:
464 s->sof_timing = val;
465 break;
466 }
467 }
468
469 static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr)
470 {
471 UHCIState *s = opaque;
472 uint32_t val;
473
474 addr &= 0x1f;
475 switch(addr) {
476 case 0x0c:
477 val = s->sof_timing;
478 break;
479 default:
480 val = 0xff;
481 break;
482 }
483 return val;
484 }
485
486 static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
487 {
488 UHCIState *s = opaque;
489
490 addr &= 0x1f;
491 trace_usb_uhci_mmio_writew(addr, val);
492
493 switch(addr) {
494 case 0x00:
495 if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
496 /* start frame processing */
497 trace_usb_uhci_schedule_start();
498 s->expire_time = qemu_get_clock_ns(vm_clock) +
499 (get_ticks_per_sec() / FRAME_TIMER_FREQ);
500 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
501 s->status &= ~UHCI_STS_HCHALTED;
502 } else if (!(val & UHCI_CMD_RS)) {
503 s->status |= UHCI_STS_HCHALTED;
504 }
505 if (val & UHCI_CMD_GRESET) {
506 UHCIPort *port;
507 int i;
508
509 /* send reset on the USB bus */
510 for(i = 0; i < NB_PORTS; i++) {
511 port = &s->ports[i];
512 usb_device_reset(port->port.dev);
513 }
514 uhci_reset(s);
515 return;
516 }
517 if (val & UHCI_CMD_HCRESET) {
518 uhci_reset(s);
519 return;
520 }
521 s->cmd = val;
522 break;
523 case 0x02:
524 s->status &= ~val;
525 /* XXX: the chip spec is not coherent, so we add a hidden
526 register to distinguish between IOC and SPD */
527 if (val & UHCI_STS_USBINT)
528 s->status2 = 0;
529 uhci_update_irq(s);
530 break;
531 case 0x04:
532 s->intr = val;
533 uhci_update_irq(s);
534 break;
535 case 0x06:
536 if (s->status & UHCI_STS_HCHALTED)
537 s->frnum = val & 0x7ff;
538 break;
539 case 0x10 ... 0x1f:
540 {
541 UHCIPort *port;
542 USBDevice *dev;
543 int n;
544
545 n = (addr >> 1) & 7;
546 if (n >= NB_PORTS)
547 return;
548 port = &s->ports[n];
549 dev = port->port.dev;
550 if (dev && dev->attached) {
551 /* port reset */
552 if ( (val & UHCI_PORT_RESET) &&
553 !(port->ctrl & UHCI_PORT_RESET) ) {
554 usb_device_reset(dev);
555 }
556 }
557 port->ctrl &= UHCI_PORT_READ_ONLY;
558 port->ctrl |= (val & ~UHCI_PORT_READ_ONLY);
559 /* some bits are reset when a '1' is written to them */
560 port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR);
561 }
562 break;
563 }
564 }
565
566 static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr)
567 {
568 UHCIState *s = opaque;
569 uint32_t val;
570
571 addr &= 0x1f;
572 switch(addr) {
573 case 0x00:
574 val = s->cmd;
575 break;
576 case 0x02:
577 val = s->status;
578 break;
579 case 0x04:
580 val = s->intr;
581 break;
582 case 0x06:
583 val = s->frnum;
584 break;
585 case 0x10 ... 0x1f:
586 {
587 UHCIPort *port;
588 int n;
589 n = (addr >> 1) & 7;
590 if (n >= NB_PORTS)
591 goto read_default;
592 port = &s->ports[n];
593 val = port->ctrl;
594 }
595 break;
596 default:
597 read_default:
598 val = 0xff7f; /* disabled port */
599 break;
600 }
601
602 trace_usb_uhci_mmio_readw(addr, val);
603
604 return val;
605 }
606
607 static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
608 {
609 UHCIState *s = opaque;
610
611 addr &= 0x1f;
612 trace_usb_uhci_mmio_writel(addr, val);
613
614 switch(addr) {
615 case 0x08:
616 s->fl_base_addr = val & ~0xfff;
617 break;
618 }
619 }
620
621 static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr)
622 {
623 UHCIState *s = opaque;
624 uint32_t val;
625
626 addr &= 0x1f;
627 switch(addr) {
628 case 0x08:
629 val = s->fl_base_addr;
630 break;
631 default:
632 val = 0xffffffff;
633 break;
634 }
635 trace_usb_uhci_mmio_readl(addr, val);
636 return val;
637 }
638
639 /* signal resume if controller suspended */
640 static void uhci_resume (void *opaque)
641 {
642 UHCIState *s = (UHCIState *)opaque;
643
644 if (!s)
645 return;
646
647 if (s->cmd & UHCI_CMD_EGSM) {
648 s->cmd |= UHCI_CMD_FGR;
649 s->status |= UHCI_STS_RD;
650 uhci_update_irq(s);
651 }
652 }
653
654 static void uhci_attach(USBPort *port1)
655 {
656 UHCIState *s = port1->opaque;
657 UHCIPort *port = &s->ports[port1->index];
658
659 /* set connect status */
660 port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC;
661
662 /* update speed */
663 if (port->port.dev->speed == USB_SPEED_LOW) {
664 port->ctrl |= UHCI_PORT_LSDA;
665 } else {
666 port->ctrl &= ~UHCI_PORT_LSDA;
667 }
668
669 uhci_resume(s);
670 }
671
672 static void uhci_detach(USBPort *port1)
673 {
674 UHCIState *s = port1->opaque;
675 UHCIPort *port = &s->ports[port1->index];
676
677 uhci_async_cancel_device(s, port1->dev);
678
679 /* set connect status */
680 if (port->ctrl & UHCI_PORT_CCS) {
681 port->ctrl &= ~UHCI_PORT_CCS;
682 port->ctrl |= UHCI_PORT_CSC;
683 }
684 /* disable port */
685 if (port->ctrl & UHCI_PORT_EN) {
686 port->ctrl &= ~UHCI_PORT_EN;
687 port->ctrl |= UHCI_PORT_ENC;
688 }
689
690 uhci_resume(s);
691 }
692
693 static void uhci_child_detach(USBPort *port1, USBDevice *child)
694 {
695 UHCIState *s = port1->opaque;
696
697 uhci_async_cancel_device(s, child);
698 }
699
700 static void uhci_wakeup(USBPort *port1)
701 {
702 UHCIState *s = port1->opaque;
703 UHCIPort *port = &s->ports[port1->index];
704
705 if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) {
706 port->ctrl |= UHCI_PORT_RD;
707 uhci_resume(s);
708 }
709 }
710
711 static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr)
712 {
713 USBDevice *dev;
714 int i;
715
716 for (i = 0; i < NB_PORTS; i++) {
717 UHCIPort *port = &s->ports[i];
718 if (!(port->ctrl & UHCI_PORT_EN)) {
719 continue;
720 }
721 dev = usb_find_device(&port->port, addr);
722 if (dev != NULL) {
723 return dev;
724 }
725 }
726 return NULL;
727 }
728
729 static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link)
730 {
731 pci_dma_read(&s->dev, link & ~0xf, td, sizeof(*td));
732 le32_to_cpus(&td->link);
733 le32_to_cpus(&td->ctrl);
734 le32_to_cpus(&td->token);
735 le32_to_cpus(&td->buffer);
736 }
737
738 static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr,
739 int status, uint32_t *int_mask)
740 {
741 uint32_t queue_token = uhci_queue_token(td);
742 int ret;
743
744 switch (status) {
745 case USB_RET_NAK:
746 td->ctrl |= TD_CTRL_NAK;
747 return TD_RESULT_NEXT_QH;
748
749 case USB_RET_STALL:
750 td->ctrl |= TD_CTRL_STALL;
751 trace_usb_uhci_packet_complete_stall(queue_token, td_addr);
752 ret = TD_RESULT_NEXT_QH;
753 break;
754
755 case USB_RET_BABBLE:
756 td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL;
757 /* frame interrupted */
758 trace_usb_uhci_packet_complete_babble(queue_token, td_addr);
759 ret = TD_RESULT_STOP_FRAME;
760 break;
761
762 case USB_RET_IOERROR:
763 case USB_RET_NODEV:
764 default:
765 td->ctrl |= TD_CTRL_TIMEOUT;
766 td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT);
767 trace_usb_uhci_packet_complete_error(queue_token, td_addr);
768 ret = TD_RESULT_NEXT_QH;
769 break;
770 }
771
772 td->ctrl &= ~TD_CTRL_ACTIVE;
773 s->status |= UHCI_STS_USBERR;
774 if (td->ctrl & TD_CTRL_IOC) {
775 *int_mask |= 0x01;
776 }
777 uhci_update_irq(s);
778 return ret;
779 }
780
781 static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask)
782 {
783 int len = 0, max_len, ret;
784 uint8_t pid;
785
786 max_len = ((td->token >> 21) + 1) & 0x7ff;
787 pid = td->token & 0xff;
788
789 ret = async->packet.result;
790
791 if (td->ctrl & TD_CTRL_IOS)
792 td->ctrl &= ~TD_CTRL_ACTIVE;
793
794 if (ret < 0) {
795 return uhci_handle_td_error(s, td, async->td_addr, ret, int_mask);
796 }
797
798 len = async->packet.result;
799 td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff);
800
801 /* The NAK bit may have been set by a previous frame, so clear it
802 here. The docs are somewhat unclear, but win2k relies on this
803 behavior. */
804 td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK);
805 if (td->ctrl & TD_CTRL_IOC)
806 *int_mask |= 0x01;
807
808 if (pid == USB_TOKEN_IN) {
809 if ((td->ctrl & TD_CTRL_SPD) && len < max_len) {
810 *int_mask |= 0x02;
811 /* short packet: do not update QH */
812 trace_usb_uhci_packet_complete_shortxfer(async->queue->token,
813 async->td_addr);
814 return TD_RESULT_NEXT_QH;
815 }
816 }
817
818 /* success */
819 trace_usb_uhci_packet_complete_success(async->queue->token,
820 async->td_addr);
821 return TD_RESULT_COMPLETE;
822 }
823
824 static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr,
825 UHCI_TD *td, uint32_t td_addr, uint32_t *int_mask)
826 {
827 int len = 0, max_len;
828 bool spd;
829 bool queuing = (q != NULL);
830 uint8_t pid = td->token & 0xff;
831 UHCIAsync *async = uhci_async_find_td(s, td_addr);
832
833 if (async) {
834 if (uhci_queue_verify(async->queue, qh_addr, td, td_addr, queuing)) {
835 assert(q == NULL || q == async->queue);
836 q = async->queue;
837 } else {
838 uhci_queue_free(async->queue, "guest re-used pending td");
839 async = NULL;
840 }
841 }
842
843 if (q == NULL) {
844 q = uhci_queue_find(s, td);
845 if (q && !uhci_queue_verify(q, qh_addr, td, td_addr, queuing)) {
846 uhci_queue_free(q, "guest re-used qh");
847 q = NULL;
848 }
849 }
850
851 if (q) {
852 q->valid = 32;
853 }
854
855 /* Is active ? */
856 if (!(td->ctrl & TD_CTRL_ACTIVE)) {
857 if (async) {
858 /* Guest marked a pending td non-active, cancel the queue */
859 uhci_queue_free(async->queue, "pending td non-active");
860 }
861 /*
862 * ehci11d spec page 22: "Even if the Active bit in the TD is already
863 * cleared when the TD is fetched ... an IOC interrupt is generated"
864 */
865 if (td->ctrl & TD_CTRL_IOC) {
866 *int_mask |= 0x01;
867 }
868 return TD_RESULT_NEXT_QH;
869 }
870
871 if (async) {
872 if (queuing) {
873 /* we are busy filling the queue, we are not prepared
874 to consume completed packages then, just leave them
875 in async state */
876 return TD_RESULT_ASYNC_CONT;
877 }
878 if (!async->done) {
879 UHCI_TD last_td;
880 UHCIAsync *last = QTAILQ_LAST(&async->queue->asyncs, asyncs_head);
881 /*
882 * While we are waiting for the current td to complete, the guest
883 * may have added more tds to the queue. Note we re-read the td
884 * rather then caching it, as we want to see guest made changes!
885 */
886 uhci_read_td(s, &last_td, last->td_addr);
887 uhci_queue_fill(async->queue, &last_td);
888
889 return TD_RESULT_ASYNC_CONT;
890 }
891 uhci_async_unlink(async);
892 goto done;
893 }
894
895 /* Allocate new packet */
896 if (q == NULL) {
897 USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f);
898 USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf);
899 q = uhci_queue_new(s, qh_addr, td, ep);
900 }
901 async = uhci_async_alloc(q, td_addr);
902
903 max_len = ((td->token >> 21) + 1) & 0x7ff;
904 spd = (pid == USB_TOKEN_IN && (td->ctrl & TD_CTRL_SPD) != 0);
905 usb_packet_setup(&async->packet, pid, q->ep, td_addr, spd,
906 (td->ctrl & TD_CTRL_IOC) != 0);
907 qemu_sglist_add(&async->sgl, td->buffer, max_len);
908 usb_packet_map(&async->packet, &async->sgl);
909
910 switch(pid) {
911 case USB_TOKEN_OUT:
912 case USB_TOKEN_SETUP:
913 len = usb_handle_packet(q->ep->dev, &async->packet);
914 if (len >= 0)
915 len = max_len;
916 break;
917
918 case USB_TOKEN_IN:
919 len = usb_handle_packet(q->ep->dev, &async->packet);
920 break;
921
922 default:
923 /* invalid pid : frame interrupted */
924 usb_packet_unmap(&async->packet, &async->sgl);
925 uhci_async_free(async);
926 s->status |= UHCI_STS_HCPERR;
927 uhci_update_irq(s);
928 return TD_RESULT_STOP_FRAME;
929 }
930
931 if (len == USB_RET_ASYNC) {
932 uhci_async_link(async);
933 if (!queuing) {
934 uhci_queue_fill(q, td);
935 }
936 return TD_RESULT_ASYNC_START;
937 }
938
939 async->packet.result = len;
940
941 done:
942 len = uhci_complete_td(s, td, async, int_mask);
943 usb_packet_unmap(&async->packet, &async->sgl);
944 uhci_async_free(async);
945 return len;
946 }
947
948 static void uhci_async_complete(USBPort *port, USBPacket *packet)
949 {
950 UHCIAsync *async = container_of(packet, UHCIAsync, packet);
951 UHCIState *s = async->queue->uhci;
952
953 if (packet->result == USB_RET_REMOVE_FROM_QUEUE) {
954 uhci_async_unlink(async);
955 uhci_async_cancel(async);
956 return;
957 }
958
959 async->done = 1;
960 if (s->frame_bytes < s->frame_bandwidth) {
961 qemu_bh_schedule(s->bh);
962 }
963 }
964
965 static int is_valid(uint32_t link)
966 {
967 return (link & 1) == 0;
968 }
969
970 static int is_qh(uint32_t link)
971 {
972 return (link & 2) != 0;
973 }
974
975 static int depth_first(uint32_t link)
976 {
977 return (link & 4) != 0;
978 }
979
980 /* QH DB used for detecting QH loops */
981 #define UHCI_MAX_QUEUES 128
982 typedef struct {
983 uint32_t addr[UHCI_MAX_QUEUES];
984 int count;
985 } QhDb;
986
987 static void qhdb_reset(QhDb *db)
988 {
989 db->count = 0;
990 }
991
992 /* Add QH to DB. Returns 1 if already present or DB is full. */
993 static int qhdb_insert(QhDb *db, uint32_t addr)
994 {
995 int i;
996 for (i = 0; i < db->count; i++)
997 if (db->addr[i] == addr)
998 return 1;
999
1000 if (db->count >= UHCI_MAX_QUEUES)
1001 return 1;
1002
1003 db->addr[db->count++] = addr;
1004 return 0;
1005 }
1006
1007 static void uhci_queue_fill(UHCIQueue *q, UHCI_TD *td)
1008 {
1009 uint32_t int_mask = 0;
1010 uint32_t plink = td->link;
1011 UHCI_TD ptd;
1012 int ret;
1013
1014 while (is_valid(plink)) {
1015 uhci_read_td(q->uhci, &ptd, plink);
1016 if (!(ptd.ctrl & TD_CTRL_ACTIVE)) {
1017 break;
1018 }
1019 if (uhci_queue_token(&ptd) != q->token) {
1020 break;
1021 }
1022 trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token);
1023 ret = uhci_handle_td(q->uhci, q, q->qh_addr, &ptd, plink, &int_mask);
1024 if (ret == TD_RESULT_ASYNC_CONT) {
1025 break;
1026 }
1027 assert(ret == TD_RESULT_ASYNC_START);
1028 assert(int_mask == 0);
1029 plink = ptd.link;
1030 }
1031 usb_device_flush_ep_queue(q->ep->dev, q->ep);
1032 }
1033
1034 static void uhci_process_frame(UHCIState *s)
1035 {
1036 uint32_t frame_addr, link, old_td_ctrl, val, int_mask;
1037 uint32_t curr_qh, td_count = 0;
1038 int cnt, ret;
1039 UHCI_TD td;
1040 UHCI_QH qh;
1041 QhDb qhdb;
1042
1043 frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2);
1044
1045 pci_dma_read(&s->dev, frame_addr, &link, 4);
1046 le32_to_cpus(&link);
1047
1048 int_mask = 0;
1049 curr_qh = 0;
1050
1051 qhdb_reset(&qhdb);
1052
1053 for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) {
1054 if (s->frame_bytes >= s->frame_bandwidth) {
1055 /* We've reached the usb 1.1 bandwidth, which is
1056 1280 bytes/frame, stop processing */
1057 trace_usb_uhci_frame_stop_bandwidth();
1058 break;
1059 }
1060 if (is_qh(link)) {
1061 /* QH */
1062 trace_usb_uhci_qh_load(link & ~0xf);
1063
1064 if (qhdb_insert(&qhdb, link)) {
1065 /*
1066 * We're going in circles. Which is not a bug because
1067 * HCD is allowed to do that as part of the BW management.
1068 *
1069 * Stop processing here if no transaction has been done
1070 * since we've been here last time.
1071 */
1072 if (td_count == 0) {
1073 trace_usb_uhci_frame_loop_stop_idle();
1074 break;
1075 } else {
1076 trace_usb_uhci_frame_loop_continue();
1077 td_count = 0;
1078 qhdb_reset(&qhdb);
1079 qhdb_insert(&qhdb, link);
1080 }
1081 }
1082
1083 pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh));
1084 le32_to_cpus(&qh.link);
1085 le32_to_cpus(&qh.el_link);
1086
1087 if (!is_valid(qh.el_link)) {
1088 /* QH w/o elements */
1089 curr_qh = 0;
1090 link = qh.link;
1091 } else {
1092 /* QH with elements */
1093 curr_qh = link;
1094 link = qh.el_link;
1095 }
1096 continue;
1097 }
1098
1099 /* TD */
1100 uhci_read_td(s, &td, link);
1101 trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token);
1102
1103 old_td_ctrl = td.ctrl;
1104 ret = uhci_handle_td(s, NULL, curr_qh, &td, link, &int_mask);
1105 if (old_td_ctrl != td.ctrl) {
1106 /* update the status bits of the TD */
1107 val = cpu_to_le32(td.ctrl);
1108 pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val));
1109 }
1110
1111 switch (ret) {
1112 case TD_RESULT_STOP_FRAME: /* interrupted frame */
1113 goto out;
1114
1115 case TD_RESULT_NEXT_QH:
1116 case TD_RESULT_ASYNC_CONT:
1117 trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf);
1118 link = curr_qh ? qh.link : td.link;
1119 continue;
1120
1121 case TD_RESULT_ASYNC_START:
1122 trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf);
1123 link = curr_qh ? qh.link : td.link;
1124 continue;
1125
1126 case TD_RESULT_COMPLETE:
1127 trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf);
1128 link = td.link;
1129 td_count++;
1130 s->frame_bytes += (td.ctrl & 0x7ff) + 1;
1131
1132 if (curr_qh) {
1133 /* update QH element link */
1134 qh.el_link = link;
1135 val = cpu_to_le32(qh.el_link);
1136 pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val));
1137
1138 if (!depth_first(link)) {
1139 /* done with this QH */
1140 curr_qh = 0;
1141 link = qh.link;
1142 }
1143 }
1144 break;
1145
1146 default:
1147 assert(!"unknown return code");
1148 }
1149
1150 /* go to the next entry */
1151 }
1152
1153 out:
1154 s->pending_int_mask |= int_mask;
1155 }
1156
1157 static void uhci_bh(void *opaque)
1158 {
1159 UHCIState *s = opaque;
1160 uhci_process_frame(s);
1161 }
1162
1163 static void uhci_frame_timer(void *opaque)
1164 {
1165 UHCIState *s = opaque;
1166
1167 /* prepare the timer for the next frame */
1168 s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1169 s->frame_bytes = 0;
1170 qemu_bh_cancel(s->bh);
1171
1172 if (!(s->cmd & UHCI_CMD_RS)) {
1173 /* Full stop */
1174 trace_usb_uhci_schedule_stop();
1175 qemu_del_timer(s->frame_timer);
1176 uhci_async_cancel_all(s);
1177 /* set hchalted bit in status - UHCI11D 2.1.2 */
1178 s->status |= UHCI_STS_HCHALTED;
1179 return;
1180 }
1181
1182 /* Complete the previous frame */
1183 if (s->pending_int_mask) {
1184 s->status2 |= s->pending_int_mask;
1185 s->status |= UHCI_STS_USBINT;
1186 uhci_update_irq(s);
1187 }
1188 s->pending_int_mask = 0;
1189
1190 /* Start new frame */
1191 s->frnum = (s->frnum + 1) & 0x7ff;
1192
1193 trace_usb_uhci_frame_start(s->frnum);
1194
1195 uhci_async_validate_begin(s);
1196
1197 uhci_process_frame(s);
1198
1199 uhci_async_validate_end(s);
1200
1201 qemu_mod_timer(s->frame_timer, s->expire_time);
1202 }
1203
1204 static const MemoryRegionPortio uhci_portio[] = {
1205 { 0, 32, 2, .write = uhci_ioport_writew, },
1206 { 0, 32, 2, .read = uhci_ioport_readw, },
1207 { 0, 32, 4, .write = uhci_ioport_writel, },
1208 { 0, 32, 4, .read = uhci_ioport_readl, },
1209 { 0, 32, 1, .write = uhci_ioport_writeb, },
1210 { 0, 32, 1, .read = uhci_ioport_readb, },
1211 PORTIO_END_OF_LIST()
1212 };
1213
1214 static const MemoryRegionOps uhci_ioport_ops = {
1215 .old_portio = uhci_portio,
1216 };
1217
1218 static USBPortOps uhci_port_ops = {
1219 .attach = uhci_attach,
1220 .detach = uhci_detach,
1221 .child_detach = uhci_child_detach,
1222 .wakeup = uhci_wakeup,
1223 .complete = uhci_async_complete,
1224 };
1225
1226 static USBBusOps uhci_bus_ops = {
1227 };
1228
1229 static int usb_uhci_common_initfn(PCIDevice *dev)
1230 {
1231 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1232 UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class);
1233 UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1234 uint8_t *pci_conf = s->dev.config;
1235 int i;
1236
1237 pci_conf[PCI_CLASS_PROG] = 0x00;
1238 /* TODO: reset value should be 0. */
1239 pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
1240
1241 s->irq_pin = u->info.irq_pin;
1242 pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1);
1243
1244 if (s->masterbus) {
1245 USBPort *ports[NB_PORTS];
1246 for(i = 0; i < NB_PORTS; i++) {
1247 ports[i] = &s->ports[i].port;
1248 }
1249 if (usb_register_companion(s->masterbus, ports, NB_PORTS,
1250 s->firstport, s, &uhci_port_ops,
1251 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) {
1252 return -1;
1253 }
1254 } else {
1255 usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev);
1256 for (i = 0; i < NB_PORTS; i++) {
1257 usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops,
1258 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1259 }
1260 }
1261 s->bh = qemu_bh_new(uhci_bh, s);
1262 s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s);
1263 s->num_ports_vmstate = NB_PORTS;
1264 QTAILQ_INIT(&s->queues);
1265
1266 qemu_register_reset(uhci_reset, s);
1267
1268 memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20);
1269 /* Use region 4 for consistency with real hardware. BSD guests seem
1270 to rely on this. */
1271 pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1272
1273 return 0;
1274 }
1275
1276 static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)
1277 {
1278 UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1279 uint8_t *pci_conf = s->dev.config;
1280
1281 /* USB misc control 1/2 */
1282 pci_set_long(pci_conf + 0x40,0x00001000);
1283 /* PM capability */
1284 pci_set_long(pci_conf + 0x80,0x00020001);
1285 /* USB legacy support */
1286 pci_set_long(pci_conf + 0xc0,0x00002000);
1287
1288 return usb_uhci_common_initfn(dev);
1289 }
1290
1291 static void usb_uhci_exit(PCIDevice *dev)
1292 {
1293 UHCIState *s = DO_UPCAST(UHCIState, dev, dev);
1294
1295 memory_region_destroy(&s->io_bar);
1296 }
1297
1298 static Property uhci_properties[] = {
1299 DEFINE_PROP_STRING("masterbus", UHCIState, masterbus),
1300 DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0),
1301 DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280),
1302 DEFINE_PROP_END_OF_LIST(),
1303 };
1304
1305 static void uhci_class_init(ObjectClass *klass, void *data)
1306 {
1307 DeviceClass *dc = DEVICE_CLASS(klass);
1308 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1309 UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class);
1310 UHCIInfo *info = data;
1311
1312 k->init = info->initfn ? info->initfn : usb_uhci_common_initfn;
1313 k->exit = info->unplug ? usb_uhci_exit : NULL;
1314 k->vendor_id = info->vendor_id;
1315 k->device_id = info->device_id;
1316 k->revision = info->revision;
1317 k->class_id = PCI_CLASS_SERIAL_USB;
1318 dc->vmsd = &vmstate_uhci;
1319 dc->props = uhci_properties;
1320 u->info = *info;
1321 }
1322
1323 static UHCIInfo uhci_info[] = {
1324 {
1325 .name = "piix3-usb-uhci",
1326 .vendor_id = PCI_VENDOR_ID_INTEL,
1327 .device_id = PCI_DEVICE_ID_INTEL_82371SB_2,
1328 .revision = 0x01,
1329 .irq_pin = 3,
1330 .unplug = true,
1331 },{
1332 .name = "piix4-usb-uhci",
1333 .vendor_id = PCI_VENDOR_ID_INTEL,
1334 .device_id = PCI_DEVICE_ID_INTEL_82371AB_2,
1335 .revision = 0x01,
1336 .irq_pin = 3,
1337 .unplug = true,
1338 },{
1339 .name = "vt82c686b-usb-uhci",
1340 .vendor_id = PCI_VENDOR_ID_VIA,
1341 .device_id = PCI_DEVICE_ID_VIA_UHCI,
1342 .revision = 0x01,
1343 .irq_pin = 3,
1344 .initfn = usb_uhci_vt82c686b_initfn,
1345 .unplug = true,
1346 },{
1347 .name = "ich9-usb-uhci1", /* 00:1d.0 */
1348 .vendor_id = PCI_VENDOR_ID_INTEL,
1349 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1,
1350 .revision = 0x03,
1351 .irq_pin = 0,
1352 .unplug = false,
1353 },{
1354 .name = "ich9-usb-uhci2", /* 00:1d.1 */
1355 .vendor_id = PCI_VENDOR_ID_INTEL,
1356 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2,
1357 .revision = 0x03,
1358 .irq_pin = 1,
1359 .unplug = false,
1360 },{
1361 .name = "ich9-usb-uhci3", /* 00:1d.2 */
1362 .vendor_id = PCI_VENDOR_ID_INTEL,
1363 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3,
1364 .revision = 0x03,
1365 .irq_pin = 2,
1366 .unplug = false,
1367 },{
1368 .name = "ich9-usb-uhci4", /* 00:1a.0 */
1369 .vendor_id = PCI_VENDOR_ID_INTEL,
1370 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4,
1371 .revision = 0x03,
1372 .irq_pin = 0,
1373 .unplug = false,
1374 },{
1375 .name = "ich9-usb-uhci5", /* 00:1a.1 */
1376 .vendor_id = PCI_VENDOR_ID_INTEL,
1377 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5,
1378 .revision = 0x03,
1379 .irq_pin = 1,
1380 .unplug = false,
1381 },{
1382 .name = "ich9-usb-uhci6", /* 00:1a.2 */
1383 .vendor_id = PCI_VENDOR_ID_INTEL,
1384 .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6,
1385 .revision = 0x03,
1386 .irq_pin = 2,
1387 .unplug = false,
1388 }
1389 };
1390
1391 static void uhci_register_types(void)
1392 {
1393 TypeInfo uhci_type_info = {
1394 .parent = TYPE_PCI_DEVICE,
1395 .instance_size = sizeof(UHCIState),
1396 .class_size = sizeof(UHCIPCIDeviceClass),
1397 .class_init = uhci_class_init,
1398 };
1399 int i;
1400
1401 for (i = 0; i < ARRAY_SIZE(uhci_info); i++) {
1402 uhci_type_info.name = uhci_info[i].name;
1403 uhci_type_info.class_data = uhci_info + i;
1404 type_register(&uhci_type_info);
1405 }
1406 }
1407
1408 type_init(uhci_register_types)
Qemu copy for testing