2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/timer.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
35 #define DPRINTF(...) do {} while (0)
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
138 #define ERDP_EHB (1<<3)
141 typedef struct XHCITRB
{
160 PLS_COMPILANCE_MODE
= 10,
165 typedef enum TRBType
{
178 CR_CONFIGURE_ENDPOINT
,
186 CR_SET_LATENCY_TOLERANCE
,
187 CR_GET_PORT_BANDWIDTH
,
192 ER_PORT_STATUS_CHANGE
,
193 ER_BANDWIDTH_REQUEST
,
196 ER_DEVICE_NOTIFICATION
,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
204 #define CR_LINK TR_LINK
206 typedef enum TRBCCode
{
209 CC_DATA_BUFFER_ERROR
,
211 CC_USB_TRANSACTION_ERROR
,
217 CC_INVALID_STREAM_TYPE_ERROR
,
218 CC_SLOT_NOT_ENABLED_ERROR
,
219 CC_EP_NOT_ENABLED_ERROR
,
225 CC_BANDWIDTH_OVERRUN
,
226 CC_CONTEXT_STATE_ERROR
,
227 CC_NO_PING_RESPONSE_ERROR
,
228 CC_EVENT_RING_FULL_ERROR
,
229 CC_INCOMPATIBLE_DEVICE_ERROR
,
230 CC_MISSED_SERVICE_ERROR
,
231 CC_COMMAND_RING_STOPPED
,
234 CC_STOPPED_LENGTH_INVALID
,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
236 CC_ISOCH_BUFFER_OVERRUN
= 31,
239 CC_INVALID_STREAM_ID_ERROR
,
240 CC_SECONDARY_BANDWIDTH_ERROR
,
241 CC_SPLIT_TRANSACTION_ERROR
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
249 #define TRB_EV_ED (1<<2)
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
266 #define TRB_TR_DIR (1<<16)
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
276 #define TRB_LK_TC (1<<1)
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
303 typedef struct XHCIState XHCIState
;
304 typedef struct XHCIStreamContext XHCIStreamContext
;
305 typedef struct XHCIEPContext XHCIEPContext
;
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
317 typedef enum EPType
{
328 typedef struct XHCIRing
{
333 typedef struct XHCIPort
{
343 typedef struct XHCITransfer
{
351 unsigned int iso_pkts
;
354 unsigned int streamid
;
359 unsigned int trb_count
;
360 unsigned int trb_alloced
;
366 unsigned int pktsize
;
367 unsigned int cur_pkt
;
369 uint64_t mfindex_kick
;
372 struct XHCIStreamContext
{
378 struct XHCIEPContext
{
384 unsigned int next_xfer
;
385 unsigned int comp_xfer
;
386 XHCITransfer transfers
[TD_QUEUE
];
390 unsigned int max_psize
;
394 unsigned int max_pstreams
;
396 unsigned int nr_pstreams
;
397 XHCIStreamContext
*pstreams
;
399 /* iso xfer scheduling */
400 unsigned int interval
;
401 int64_t mfindex_last
;
402 QEMUTimer
*kick_timer
;
405 typedef struct XHCISlot
{
410 XHCIEPContext
* eps
[31];
413 typedef struct XHCIEvent
{
423 typedef struct XHCIInterrupter
{
428 uint32_t erstba_high
;
432 bool msix_used
, er_pcs
, er_full
;
436 unsigned int er_ep_idx
;
438 XHCIEvent ev_buffer
[EV_QUEUE
];
439 unsigned int ev_buffer_put
;
440 unsigned int ev_buffer_get
;
446 PCIDevice parent_obj
;
451 MemoryRegion mem_cap
;
452 MemoryRegion mem_oper
;
453 MemoryRegion mem_runtime
;
454 MemoryRegion mem_doorbell
;
463 /* Operational Registers */
470 uint32_t dcbaap_high
;
473 USBPort uports
[MAX(MAXPORTS_2
, MAXPORTS_3
)];
474 XHCIPort ports
[MAXPORTS
];
475 XHCISlot slots
[MAXSLOTS
];
478 /* Runtime Registers */
479 int64_t mfindex_start
;
480 QEMUTimer
*mfwrap_timer
;
481 XHCIInterrupter intr
[MAXINTRS
];
486 #define TYPE_XHCI "nec-usb-xhci"
489 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
491 typedef struct XHCIEvRingSeg
{
499 XHCI_FLAG_USE_MSI
= 1,
503 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
504 unsigned int epid
, unsigned int streamid
);
505 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
507 static void xhci_xfer_report(XHCITransfer
*xfer
);
508 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
509 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
510 static USBEndpoint
*xhci_epid_to_usbep(XHCIState
*xhci
,
511 unsigned int slotid
, unsigned int epid
);
513 static const char *TRBType_names
[] = {
514 [TRB_RESERVED
] = "TRB_RESERVED",
515 [TR_NORMAL
] = "TR_NORMAL",
516 [TR_SETUP
] = "TR_SETUP",
517 [TR_DATA
] = "TR_DATA",
518 [TR_STATUS
] = "TR_STATUS",
519 [TR_ISOCH
] = "TR_ISOCH",
520 [TR_LINK
] = "TR_LINK",
521 [TR_EVDATA
] = "TR_EVDATA",
522 [TR_NOOP
] = "TR_NOOP",
523 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
524 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
525 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
526 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
527 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
528 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
529 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
530 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
531 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
532 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
533 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
534 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
535 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
536 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
537 [CR_NOOP
] = "CR_NOOP",
538 [ER_TRANSFER
] = "ER_TRANSFER",
539 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
540 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
541 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
542 [ER_DOORBELL
] = "ER_DOORBELL",
543 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
544 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
545 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
546 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
547 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
548 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
551 static const char *TRBCCode_names
[] = {
552 [CC_INVALID
] = "CC_INVALID",
553 [CC_SUCCESS
] = "CC_SUCCESS",
554 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
555 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
556 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
557 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
558 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
559 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
560 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
561 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
562 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
563 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
564 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
565 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
566 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
567 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
568 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
569 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
570 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
571 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
572 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
573 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
574 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
575 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
576 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
577 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
578 [CC_STOPPED
] = "CC_STOPPED",
579 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
580 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
581 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
582 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
583 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
584 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
585 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
586 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
587 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
590 static const char *ep_state_names
[] = {
591 [EP_DISABLED
] = "disabled",
592 [EP_RUNNING
] = "running",
593 [EP_HALTED
] = "halted",
594 [EP_STOPPED
] = "stopped",
595 [EP_ERROR
] = "error",
598 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
600 if (index
>= llen
|| list
[index
] == NULL
) {
606 static const char *trb_name(XHCITRB
*trb
)
608 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
609 ARRAY_SIZE(TRBType_names
));
612 static const char *event_name(XHCIEvent
*event
)
614 return lookup_name(event
->ccode
, TRBCCode_names
,
615 ARRAY_SIZE(TRBCCode_names
));
618 static const char *ep_state_name(uint32_t state
)
620 return lookup_name(state
, ep_state_names
,
621 ARRAY_SIZE(ep_state_names
));
624 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
626 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
627 return (now
- xhci
->mfindex_start
) / 125000;
630 static void xhci_mfwrap_update(XHCIState
*xhci
)
632 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
633 uint32_t mfindex
, left
;
636 if ((xhci
->usbcmd
& bits
) == bits
) {
637 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
638 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
639 left
= 0x4000 - mfindex
;
640 timer_mod(xhci
->mfwrap_timer
, now
+ left
* 125000);
642 timer_del(xhci
->mfwrap_timer
);
646 static void xhci_mfwrap_timer(void *opaque
)
648 XHCIState
*xhci
= opaque
;
649 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
651 xhci_event(xhci
, &wrap
, 0);
652 xhci_mfwrap_update(xhci
);
655 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
657 if (sizeof(dma_addr_t
) == 4) {
660 return low
| (((dma_addr_t
)high
<< 16) << 16);
664 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
666 if (sizeof(dma_addr_t
) == 4) {
667 return addr
& 0xffffffff;
673 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
674 uint32_t *buf
, size_t len
)
678 assert((len
% sizeof(uint32_t)) == 0);
680 pci_dma_read(PCI_DEVICE(xhci
), addr
, buf
, len
);
682 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
683 buf
[i
] = le32_to_cpu(buf
[i
]);
687 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
688 uint32_t *buf
, size_t len
)
691 uint32_t tmp
[len
/ sizeof(uint32_t)];
693 assert((len
% sizeof(uint32_t)) == 0);
695 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
696 tmp
[i
] = cpu_to_le32(buf
[i
]);
698 pci_dma_write(PCI_DEVICE(xhci
), addr
, tmp
, len
);
701 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
708 switch (uport
->dev
->speed
) {
712 index
= uport
->index
;
714 case USB_SPEED_SUPER
:
715 index
= uport
->index
+ xhci
->numports_2
;
720 return &xhci
->ports
[index
];
723 static void xhci_intx_update(XHCIState
*xhci
)
725 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
728 if (msix_enabled(pci_dev
) ||
729 msi_enabled(pci_dev
)) {
733 if (xhci
->intr
[0].iman
& IMAN_IP
&&
734 xhci
->intr
[0].iman
& IMAN_IE
&&
735 xhci
->usbcmd
& USBCMD_INTE
) {
739 trace_usb_xhci_irq_intx(level
);
740 pci_set_irq(pci_dev
, level
);
743 static void xhci_msix_update(XHCIState
*xhci
, int v
)
745 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
748 if (!msix_enabled(pci_dev
)) {
752 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
753 if (enabled
== xhci
->intr
[v
].msix_used
) {
758 trace_usb_xhci_irq_msix_use(v
);
759 msix_vector_use(pci_dev
, v
);
760 xhci
->intr
[v
].msix_used
= true;
762 trace_usb_xhci_irq_msix_unuse(v
);
763 msix_vector_unuse(pci_dev
, v
);
764 xhci
->intr
[v
].msix_used
= false;
768 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
770 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
772 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
773 xhci
->intr
[v
].iman
|= IMAN_IP
;
774 xhci
->usbsts
|= USBSTS_EINT
;
776 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
780 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
784 if (msix_enabled(pci_dev
)) {
785 trace_usb_xhci_irq_msix(v
);
786 msix_notify(pci_dev
, v
);
790 if (msi_enabled(pci_dev
)) {
791 trace_usb_xhci_irq_msi(v
);
792 msi_notify(pci_dev
, v
);
797 trace_usb_xhci_irq_intx(1);
798 pci_irq_assert(pci_dev
);
802 static inline int xhci_running(XHCIState
*xhci
)
804 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->intr
[0].er_full
;
807 static void xhci_die(XHCIState
*xhci
)
809 xhci
->usbsts
|= USBSTS_HCE
;
810 fprintf(stderr
, "xhci: asserted controller error\n");
813 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
815 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
816 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
820 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
821 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
822 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
823 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
825 ev_trb
.control
|= TRB_C
;
827 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
829 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
830 event_name(event
), ev_trb
.parameter
,
831 ev_trb
.status
, ev_trb
.control
);
833 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
834 pci_dma_write(pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
837 if (intr
->er_ep_idx
>= intr
->er_size
) {
839 intr
->er_pcs
= !intr
->er_pcs
;
843 static void xhci_events_update(XHCIState
*xhci
, int v
)
845 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
850 if (xhci
->usbsts
& USBSTS_HCH
) {
854 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
855 if (erdp
< intr
->er_start
||
856 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
857 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
858 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
859 v
, intr
->er_start
, intr
->er_size
);
863 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
864 assert(dp_idx
< intr
->er_size
);
866 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
867 * deadlocks when the ER is full. Hack it by holding off events until
868 * the driver decides to free at least half of the ring */
870 int er_free
= dp_idx
- intr
->er_ep_idx
;
872 er_free
+= intr
->er_size
;
874 if (er_free
< (intr
->er_size
/2)) {
875 DPRINTF("xhci_events_update(): event ring still "
876 "more than half full (hack)\n");
881 while (intr
->ev_buffer_put
!= intr
->ev_buffer_get
) {
882 assert(intr
->er_full
);
883 if (((intr
->er_ep_idx
+1) % intr
->er_size
) == dp_idx
) {
884 DPRINTF("xhci_events_update(): event ring full again\n");
886 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
887 xhci_write_event(xhci
, &full
, v
);
892 XHCIEvent
*event
= &intr
->ev_buffer
[intr
->ev_buffer_get
];
893 xhci_write_event(xhci
, event
, v
);
894 intr
->ev_buffer_get
++;
896 if (intr
->ev_buffer_get
== EV_QUEUE
) {
897 intr
->ev_buffer_get
= 0;
902 xhci_intr_raise(xhci
, v
);
905 if (intr
->er_full
&& intr
->ev_buffer_put
== intr
->ev_buffer_get
) {
906 DPRINTF("xhci_events_update(): event ring no longer full\n");
911 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
913 XHCIInterrupter
*intr
;
917 if (v
>= xhci
->numintrs
) {
918 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
921 intr
= &xhci
->intr
[v
];
924 DPRINTF("xhci_event(): ER full, queueing\n");
925 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
926 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
929 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
930 if (intr
->ev_buffer_put
== EV_QUEUE
) {
931 intr
->ev_buffer_put
= 0;
936 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
937 if (erdp
< intr
->er_start
||
938 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
939 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
940 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
941 v
, intr
->er_start
, intr
->er_size
);
946 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
947 assert(dp_idx
< intr
->er_size
);
949 if ((intr
->er_ep_idx
+1) % intr
->er_size
== dp_idx
) {
950 DPRINTF("xhci_event(): ER full, queueing\n");
952 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
953 xhci_write_event(xhci
, &full
);
956 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
957 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
960 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
961 if (intr
->ev_buffer_put
== EV_QUEUE
) {
962 intr
->ev_buffer_put
= 0;
965 xhci_write_event(xhci
, event
, v
);
968 xhci_intr_raise(xhci
, v
);
971 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
974 ring
->dequeue
= base
;
978 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
981 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
985 pci_dma_read(pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
986 trb
->addr
= ring
->dequeue
;
987 trb
->ccs
= ring
->ccs
;
988 le64_to_cpus(&trb
->parameter
);
989 le32_to_cpus(&trb
->status
);
990 le32_to_cpus(&trb
->control
);
992 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
993 trb
->parameter
, trb
->status
, trb
->control
);
995 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
999 type
= TRB_TYPE(*trb
);
1001 if (type
!= TR_LINK
) {
1003 *addr
= ring
->dequeue
;
1005 ring
->dequeue
+= TRB_SIZE
;
1008 ring
->dequeue
= xhci_mask64(trb
->parameter
);
1009 if (trb
->control
& TRB_LK_TC
) {
1010 ring
->ccs
= !ring
->ccs
;
1016 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
1018 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
1021 dma_addr_t dequeue
= ring
->dequeue
;
1022 bool ccs
= ring
->ccs
;
1023 /* hack to bundle together the two/three TDs that make a setup transfer */
1024 bool control_td_set
= 0;
1028 pci_dma_read(pci_dev
, dequeue
, &trb
, TRB_SIZE
);
1029 le64_to_cpus(&trb
.parameter
);
1030 le32_to_cpus(&trb
.status
);
1031 le32_to_cpus(&trb
.control
);
1033 if ((trb
.control
& TRB_C
) != ccs
) {
1037 type
= TRB_TYPE(trb
);
1039 if (type
== TR_LINK
) {
1040 dequeue
= xhci_mask64(trb
.parameter
);
1041 if (trb
.control
& TRB_LK_TC
) {
1048 dequeue
+= TRB_SIZE
;
1050 if (type
== TR_SETUP
) {
1052 } else if (type
== TR_STATUS
) {
1056 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
1062 static void xhci_er_reset(XHCIState
*xhci
, int v
)
1064 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
1067 if (intr
->erstsz
== 0) {
1073 /* cache the (sole) event ring segment location */
1074 if (intr
->erstsz
!= 1) {
1075 fprintf(stderr
, "xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
1079 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
1080 pci_dma_read(PCI_DEVICE(xhci
), erstba
, &seg
, sizeof(seg
));
1081 le32_to_cpus(&seg
.addr_low
);
1082 le32_to_cpus(&seg
.addr_high
);
1083 le32_to_cpus(&seg
.size
);
1084 if (seg
.size
< 16 || seg
.size
> 4096) {
1085 fprintf(stderr
, "xhci: invalid value for segment size: %d\n", seg
.size
);
1089 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
1090 intr
->er_size
= seg
.size
;
1092 intr
->er_ep_idx
= 0;
1096 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
1097 v
, intr
->er_start
, intr
->er_size
);
1100 static void xhci_run(XHCIState
*xhci
)
1102 trace_usb_xhci_run();
1103 xhci
->usbsts
&= ~USBSTS_HCH
;
1104 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1107 static void xhci_stop(XHCIState
*xhci
)
1109 trace_usb_xhci_stop();
1110 xhci
->usbsts
|= USBSTS_HCH
;
1111 xhci
->crcr_low
&= ~CRCR_CRR
;
1114 static XHCIStreamContext
*xhci_alloc_stream_contexts(unsigned count
,
1117 XHCIStreamContext
*stctx
;
1120 stctx
= g_new0(XHCIStreamContext
, count
);
1121 for (i
= 0; i
< count
; i
++) {
1122 stctx
[i
].pctx
= base
+ i
* 16;
1128 static void xhci_reset_streams(XHCIEPContext
*epctx
)
1132 for (i
= 0; i
< epctx
->nr_pstreams
; i
++) {
1133 epctx
->pstreams
[i
].sct
= -1;
1137 static void xhci_alloc_streams(XHCIEPContext
*epctx
, dma_addr_t base
)
1139 assert(epctx
->pstreams
== NULL
);
1140 epctx
->nr_pstreams
= 2 << (epctx
->max_pstreams
+ 1);
1141 epctx
->pstreams
= xhci_alloc_stream_contexts(epctx
->nr_pstreams
, base
);
1144 static void xhci_free_streams(XHCIEPContext
*epctx
)
1146 assert(epctx
->pstreams
!= NULL
);
1148 g_free(epctx
->pstreams
);
1149 epctx
->pstreams
= NULL
;
1150 epctx
->nr_pstreams
= 0;
1153 static XHCIStreamContext
*xhci_find_stream(XHCIEPContext
*epctx
,
1154 unsigned int streamid
,
1157 XHCIStreamContext
*sctx
;
1159 uint32_t ctx
[2], sct
;
1161 assert(streamid
!= 0);
1163 if (streamid
>= epctx
->nr_pstreams
) {
1164 *cc_error
= CC_INVALID_STREAM_ID_ERROR
;
1167 sctx
= epctx
->pstreams
+ streamid
;
1169 FIXME("secondary streams not implemented yet");
1172 if (sctx
->sct
== -1) {
1173 xhci_dma_read_u32s(epctx
->xhci
, sctx
->pctx
, ctx
, sizeof(ctx
));
1174 sct
= (ctx
[0] >> 1) & 0x07;
1175 if (epctx
->lsa
&& sct
!= 1) {
1176 *cc_error
= CC_INVALID_STREAM_TYPE_ERROR
;
1180 base
= xhci_addr64(ctx
[0] & ~0xf, ctx
[1]);
1181 xhci_ring_init(epctx
->xhci
, &sctx
->ring
, base
);
1186 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1187 XHCIStreamContext
*sctx
, uint32_t state
)
1189 XHCIRing
*ring
= NULL
;
1193 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1194 ctx
[0] &= ~EP_STATE_MASK
;
1197 /* update ring dequeue ptr */
1198 if (epctx
->nr_pstreams
) {
1201 xhci_dma_read_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1203 ctx2
[0] |= sctx
->ring
.dequeue
| sctx
->ring
.ccs
;
1204 ctx2
[1] = (sctx
->ring
.dequeue
>> 16) >> 16;
1205 xhci_dma_write_u32s(xhci
, sctx
->pctx
, ctx2
, sizeof(ctx2
));
1208 ring
= &epctx
->ring
;
1211 ctx
[2] = ring
->dequeue
| ring
->ccs
;
1212 ctx
[3] = (ring
->dequeue
>> 16) >> 16;
1214 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1215 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1218 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1219 if (epctx
->state
!= state
) {
1220 trace_usb_xhci_ep_state(epctx
->slotid
, epctx
->epid
,
1221 ep_state_name(epctx
->state
),
1222 ep_state_name(state
));
1224 epctx
->state
= state
;
1227 static void xhci_ep_kick_timer(void *opaque
)
1229 XHCIEPContext
*epctx
= opaque
;
1230 xhci_kick_ep(epctx
->xhci
, epctx
->slotid
, epctx
->epid
, 0);
1233 static XHCIEPContext
*xhci_alloc_epctx(XHCIState
*xhci
,
1234 unsigned int slotid
,
1237 XHCIEPContext
*epctx
;
1240 epctx
= g_new0(XHCIEPContext
, 1);
1242 epctx
->slotid
= slotid
;
1245 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
1246 epctx
->transfers
[i
].xhci
= xhci
;
1247 epctx
->transfers
[i
].slotid
= slotid
;
1248 epctx
->transfers
[i
].epid
= epid
;
1249 usb_packet_init(&epctx
->transfers
[i
].packet
);
1251 epctx
->kick_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_ep_kick_timer
, epctx
);
1256 static void xhci_init_epctx(XHCIEPContext
*epctx
,
1257 dma_addr_t pctx
, uint32_t *ctx
)
1261 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1263 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1264 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid
/2, epid
%2, epctx
->type
);
1266 epctx
->max_psize
= ctx
[1]>>16;
1267 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1268 epctx
->max_pstreams
= (ctx
[0] >> 10) & 0xf;
1269 epctx
->lsa
= (ctx
[0] >> 15) & 1;
1270 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1271 epid
/2, epid
%2, epctx
->max_psize
);
1272 if (epctx
->max_pstreams
) {
1273 xhci_alloc_streams(epctx
, dequeue
);
1275 xhci_ring_init(epctx
->xhci
, &epctx
->ring
, dequeue
);
1276 epctx
->ring
.ccs
= ctx
[2] & 1;
1279 epctx
->interval
= 1 << ((ctx
[0] >> 16) & 0xff);
1282 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1283 unsigned int epid
, dma_addr_t pctx
,
1287 XHCIEPContext
*epctx
;
1289 trace_usb_xhci_ep_enable(slotid
, epid
);
1290 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1291 assert(epid
>= 1 && epid
<= 31);
1293 slot
= &xhci
->slots
[slotid
-1];
1294 if (slot
->eps
[epid
-1]) {
1295 xhci_disable_ep(xhci
, slotid
, epid
);
1298 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
1299 slot
->eps
[epid
-1] = epctx
;
1300 xhci_init_epctx(epctx
, pctx
, ctx
);
1302 epctx
->mfindex_last
= 0;
1304 epctx
->state
= EP_RUNNING
;
1305 ctx
[0] &= ~EP_STATE_MASK
;
1306 ctx
[0] |= EP_RUNNING
;
1311 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
, TRBCCode report
)
1315 if (report
&& (t
->running_async
|| t
->running_retry
)) {
1317 xhci_xfer_report(t
);
1320 if (t
->running_async
) {
1321 usb_cancel_packet(&t
->packet
);
1322 t
->running_async
= 0;
1325 if (t
->running_retry
) {
1326 XHCIEPContext
*epctx
= t
->xhci
->slots
[t
->slotid
-1].eps
[t
->epid
-1];
1328 epctx
->retry
= NULL
;
1329 timer_del(epctx
->kick_timer
);
1331 t
->running_retry
= 0;
1339 t
->trb_count
= t
->trb_alloced
= 0;
1344 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1345 unsigned int epid
, TRBCCode report
)
1348 XHCIEPContext
*epctx
;
1349 int i
, xferi
, killed
= 0;
1350 USBEndpoint
*ep
= NULL
;
1351 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1352 assert(epid
>= 1 && epid
<= 31);
1354 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1356 slot
= &xhci
->slots
[slotid
-1];
1358 if (!slot
->eps
[epid
-1]) {
1362 epctx
= slot
->eps
[epid
-1];
1364 xferi
= epctx
->next_xfer
;
1365 for (i
= 0; i
< TD_QUEUE
; i
++) {
1366 killed
+= xhci_ep_nuke_one_xfer(&epctx
->transfers
[xferi
], report
);
1368 report
= 0; /* Only report once */
1370 epctx
->transfers
[xferi
].packet
.ep
= NULL
;
1371 xferi
= (xferi
+ 1) % TD_QUEUE
;
1374 ep
= xhci_epid_to_usbep(xhci
, slotid
, epid
);
1376 usb_device_ep_stopped(ep
->dev
, ep
);
1381 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1385 XHCIEPContext
*epctx
;
1388 trace_usb_xhci_ep_disable(slotid
, epid
);
1389 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1390 assert(epid
>= 1 && epid
<= 31);
1392 slot
= &xhci
->slots
[slotid
-1];
1394 if (!slot
->eps
[epid
-1]) {
1395 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1399 xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0);
1401 epctx
= slot
->eps
[epid
-1];
1403 if (epctx
->nr_pstreams
) {
1404 xhci_free_streams(epctx
);
1407 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
1408 usb_packet_cleanup(&epctx
->transfers
[i
].packet
);
1411 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_DISABLED
);
1413 timer_free(epctx
->kick_timer
);
1415 slot
->eps
[epid
-1] = NULL
;
1420 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1424 XHCIEPContext
*epctx
;
1426 trace_usb_xhci_ep_stop(slotid
, epid
);
1427 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1429 if (epid
< 1 || epid
> 31) {
1430 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1431 return CC_TRB_ERROR
;
1434 slot
= &xhci
->slots
[slotid
-1];
1436 if (!slot
->eps
[epid
-1]) {
1437 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1438 return CC_EP_NOT_ENABLED_ERROR
;
1441 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, CC_STOPPED
) > 0) {
1442 fprintf(stderr
, "xhci: FIXME: endpoint stopped w/ xfers running, "
1443 "data might be lost\n");
1446 epctx
= slot
->eps
[epid
-1];
1448 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1450 if (epctx
->nr_pstreams
) {
1451 xhci_reset_streams(epctx
);
1457 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1461 XHCIEPContext
*epctx
;
1463 trace_usb_xhci_ep_reset(slotid
, epid
);
1464 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1466 if (epid
< 1 || epid
> 31) {
1467 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1468 return CC_TRB_ERROR
;
1471 slot
= &xhci
->slots
[slotid
-1];
1473 if (!slot
->eps
[epid
-1]) {
1474 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1475 return CC_EP_NOT_ENABLED_ERROR
;
1478 epctx
= slot
->eps
[epid
-1];
1480 if (epctx
->state
!= EP_HALTED
) {
1481 fprintf(stderr
, "xhci: reset EP while EP %d not halted (%d)\n",
1482 epid
, epctx
->state
);
1483 return CC_CONTEXT_STATE_ERROR
;
1486 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
, 0) > 0) {
1487 fprintf(stderr
, "xhci: FIXME: endpoint reset w/ xfers running, "
1488 "data might be lost\n");
1491 uint8_t ep
= epid
>>1;
1497 if (!xhci
->slots
[slotid
-1].uport
||
1498 !xhci
->slots
[slotid
-1].uport
->dev
) {
1499 return CC_USB_TRANSACTION_ERROR
;
1502 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_STOPPED
);
1504 if (epctx
->nr_pstreams
) {
1505 xhci_reset_streams(epctx
);
1511 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1512 unsigned int epid
, unsigned int streamid
,
1516 XHCIEPContext
*epctx
;
1517 XHCIStreamContext
*sctx
;
1520 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1522 if (epid
< 1 || epid
> 31) {
1523 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1524 return CC_TRB_ERROR
;
1527 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, streamid
, pdequeue
);
1528 dequeue
= xhci_mask64(pdequeue
);
1530 slot
= &xhci
->slots
[slotid
-1];
1532 if (!slot
->eps
[epid
-1]) {
1533 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1534 return CC_EP_NOT_ENABLED_ERROR
;
1537 epctx
= slot
->eps
[epid
-1];
1539 if (epctx
->state
!= EP_STOPPED
) {
1540 fprintf(stderr
, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1541 return CC_CONTEXT_STATE_ERROR
;
1544 if (epctx
->nr_pstreams
) {
1546 sctx
= xhci_find_stream(epctx
, streamid
, &err
);
1550 xhci_ring_init(xhci
, &sctx
->ring
, dequeue
& ~0xf);
1551 sctx
->ring
.ccs
= dequeue
& 1;
1554 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1555 epctx
->ring
.ccs
= dequeue
& 1;
1558 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_STOPPED
);
1563 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1565 XHCIState
*xhci
= xfer
->xhci
;
1568 xfer
->int_req
= false;
1569 pci_dma_sglist_init(&xfer
->sgl
, PCI_DEVICE(xhci
), xfer
->trb_count
);
1570 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1571 XHCITRB
*trb
= &xfer
->trbs
[i
];
1573 unsigned int chunk
= 0;
1575 if (trb
->control
& TRB_TR_IOC
) {
1576 xfer
->int_req
= true;
1579 switch (TRB_TYPE(*trb
)) {
1581 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1582 fprintf(stderr
, "xhci: data direction mismatch for TR_DATA\n");
1588 addr
= xhci_mask64(trb
->parameter
);
1589 chunk
= trb
->status
& 0x1ffff;
1590 if (trb
->control
& TRB_TR_IDT
) {
1591 if (chunk
> 8 || in_xfer
) {
1592 fprintf(stderr
, "xhci: invalid immediate data TRB\n");
1595 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1597 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1606 qemu_sglist_destroy(&xfer
->sgl
);
1611 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1613 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1614 qemu_sglist_destroy(&xfer
->sgl
);
1617 static void xhci_xfer_report(XHCITransfer
*xfer
)
1623 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1624 XHCIState
*xhci
= xfer
->xhci
;
1627 left
= xfer
->packet
.actual_length
;
1629 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1630 XHCITRB
*trb
= &xfer
->trbs
[i
];
1631 unsigned int chunk
= 0;
1633 switch (TRB_TYPE(*trb
)) {
1637 chunk
= trb
->status
& 0x1ffff;
1640 if (xfer
->status
== CC_SUCCESS
) {
1653 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1654 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1655 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1656 event
.slotid
= xfer
->slotid
;
1657 event
.epid
= xfer
->epid
;
1658 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1660 event
.ptr
= trb
->addr
;
1661 if (xfer
->status
== CC_SUCCESS
) {
1662 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1664 event
.ccode
= xfer
->status
;
1666 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1667 event
.ptr
= trb
->parameter
;
1668 event
.flags
|= TRB_EV_ED
;
1669 event
.length
= edtla
& 0xffffff;
1670 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1673 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1675 if (xfer
->status
!= CC_SUCCESS
) {
1682 static void xhci_stall_ep(XHCITransfer
*xfer
)
1684 XHCIState
*xhci
= xfer
->xhci
;
1685 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1686 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1688 XHCIStreamContext
*sctx
;
1690 if (epctx
->nr_pstreams
) {
1691 sctx
= xhci_find_stream(epctx
, xfer
->streamid
, &err
);
1695 sctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1696 sctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1697 xhci_set_ep_state(xhci
, epctx
, sctx
, EP_HALTED
);
1699 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1700 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1701 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_HALTED
);
1705 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1706 XHCIEPContext
*epctx
);
1708 static int xhci_setup_packet(XHCITransfer
*xfer
)
1710 XHCIState
*xhci
= xfer
->xhci
;
1714 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1716 if (xfer
->packet
.ep
) {
1717 ep
= xfer
->packet
.ep
;
1719 ep
= xhci_epid_to_usbep(xhci
, xfer
->slotid
, xfer
->epid
);
1721 fprintf(stderr
, "xhci: slot %d has no device\n",
1727 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1728 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->streamid
,
1729 xfer
->trbs
[0].addr
, false, xfer
->int_req
);
1730 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1731 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1732 xfer
->packet
.pid
, ep
->dev
->addr
, ep
->nr
);
1736 static int xhci_complete_packet(XHCITransfer
*xfer
)
1738 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1739 trace_usb_xhci_xfer_async(xfer
);
1740 xfer
->running_async
= 1;
1741 xfer
->running_retry
= 0;
1744 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1745 trace_usb_xhci_xfer_nak(xfer
);
1746 xfer
->running_async
= 0;
1747 xfer
->running_retry
= 1;
1751 xfer
->running_async
= 0;
1752 xfer
->running_retry
= 0;
1754 xhci_xfer_unmap(xfer
);
1757 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1758 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1759 xfer
->status
= CC_SUCCESS
;
1760 xhci_xfer_report(xfer
);
1765 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1766 switch (xfer
->packet
.status
) {
1768 case USB_RET_IOERROR
:
1769 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1770 xhci_xfer_report(xfer
);
1771 xhci_stall_ep(xfer
);
1774 xfer
->status
= CC_STALL_ERROR
;
1775 xhci_xfer_report(xfer
);
1776 xhci_stall_ep(xfer
);
1778 case USB_RET_BABBLE
:
1779 xfer
->status
= CC_BABBLE_DETECTED
;
1780 xhci_xfer_report(xfer
);
1781 xhci_stall_ep(xfer
);
1784 fprintf(stderr
, "%s: FIXME: status = %d\n", __func__
,
1785 xfer
->packet
.status
);
1786 FIXME("unhandled USB_RET_*");
1791 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1793 XHCITRB
*trb_setup
, *trb_status
;
1794 uint8_t bmRequestType
;
1796 trb_setup
= &xfer
->trbs
[0];
1797 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1799 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
1801 /* at most one Event Data TRB allowed after STATUS */
1802 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1806 /* do some sanity checks */
1807 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1808 fprintf(stderr
, "xhci: ep0 first TD not SETUP: %d\n",
1809 TRB_TYPE(*trb_setup
));
1812 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1813 fprintf(stderr
, "xhci: ep0 last TD not STATUS: %d\n",
1814 TRB_TYPE(*trb_status
));
1817 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1818 fprintf(stderr
, "xhci: Setup TRB doesn't have IDT set\n");
1821 if ((trb_setup
->status
& 0x1ffff) != 8) {
1822 fprintf(stderr
, "xhci: Setup TRB has bad length (%d)\n",
1823 (trb_setup
->status
& 0x1ffff));
1827 bmRequestType
= trb_setup
->parameter
;
1829 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1830 xfer
->iso_xfer
= false;
1831 xfer
->timed_xfer
= false;
1833 if (xhci_setup_packet(xfer
) < 0) {
1836 xfer
->packet
.parameter
= trb_setup
->parameter
;
1838 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1840 xhci_complete_packet(xfer
);
1841 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1842 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
, 0);
1847 static void xhci_calc_intr_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1848 XHCIEPContext
*epctx
, uint64_t mfindex
)
1850 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1851 ~(epctx
->interval
-1));
1852 uint64_t kick
= epctx
->mfindex_last
+ epctx
->interval
;
1854 assert(epctx
->interval
!= 0);
1855 xfer
->mfindex_kick
= MAX(asap
, kick
);
1858 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1859 XHCIEPContext
*epctx
, uint64_t mfindex
)
1861 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1862 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1863 ~(epctx
->interval
-1));
1864 if (asap
>= epctx
->mfindex_last
&&
1865 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1866 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1868 xfer
->mfindex_kick
= asap
;
1871 xfer
->mfindex_kick
= (xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1872 & TRB_TR_FRAMEID_MASK
;
1873 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1874 if (xfer
->mfindex_kick
< mfindex
) {
1875 xfer
->mfindex_kick
+= 0x4000;
1880 static void xhci_check_intr_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1881 XHCIEPContext
*epctx
, uint64_t mfindex
)
1883 if (xfer
->mfindex_kick
> mfindex
) {
1884 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
1885 (xfer
->mfindex_kick
- mfindex
) * 125000);
1886 xfer
->running_retry
= 1;
1888 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1889 timer_del(epctx
->kick_timer
);
1890 xfer
->running_retry
= 0;
1895 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1899 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1901 xfer
->in_xfer
= epctx
->type
>>2;
1903 switch(epctx
->type
) {
1907 xfer
->iso_xfer
= false;
1908 xfer
->timed_xfer
= true;
1909 mfindex
= xhci_mfindex_get(xhci
);
1910 xhci_calc_intr_kick(xhci
, xfer
, epctx
, mfindex
);
1911 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1912 if (xfer
->running_retry
) {
1919 xfer
->iso_xfer
= false;
1920 xfer
->timed_xfer
= false;
1925 xfer
->iso_xfer
= true;
1926 xfer
->timed_xfer
= true;
1927 mfindex
= xhci_mfindex_get(xhci
);
1928 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1929 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1930 if (xfer
->running_retry
) {
1935 fprintf(stderr
, "xhci: unknown or unhandled EP "
1936 "(type %d, in %d, ep %02x)\n",
1937 epctx
->type
, xfer
->in_xfer
, xfer
->epid
);
1941 if (xhci_setup_packet(xfer
) < 0) {
1944 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1946 xhci_complete_packet(xfer
);
1947 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1948 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
1953 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1955 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
1956 return xhci_submit(xhci
, xfer
, epctx
);
1959 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
1960 unsigned int epid
, unsigned int streamid
)
1962 XHCIStreamContext
*stctx
;
1963 XHCIEPContext
*epctx
;
1965 USBEndpoint
*ep
= NULL
;
1970 trace_usb_xhci_ep_kick(slotid
, epid
, streamid
);
1971 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1972 assert(epid
>= 1 && epid
<= 31);
1974 if (!xhci
->slots
[slotid
-1].enabled
) {
1975 fprintf(stderr
, "xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1978 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1980 fprintf(stderr
, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1986 XHCITransfer
*xfer
= epctx
->retry
;
1988 trace_usb_xhci_xfer_retry(xfer
);
1989 assert(xfer
->running_retry
);
1990 if (xfer
->timed_xfer
) {
1991 /* time to kick the transfer? */
1992 mfindex
= xhci_mfindex_get(xhci
);
1993 xhci_check_intr_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1994 if (xfer
->running_retry
) {
1997 xfer
->timed_xfer
= 0;
1998 xfer
->running_retry
= 1;
2000 if (xfer
->iso_xfer
) {
2001 /* retry iso transfer */
2002 if (xhci_setup_packet(xfer
) < 0) {
2005 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2006 assert(xfer
->packet
.status
!= USB_RET_NAK
);
2007 xhci_complete_packet(xfer
);
2009 /* retry nak'ed transfer */
2010 if (xhci_setup_packet(xfer
) < 0) {
2013 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
2014 if (xfer
->packet
.status
== USB_RET_NAK
) {
2017 xhci_complete_packet(xfer
);
2019 assert(!xfer
->running_retry
);
2020 epctx
->retry
= NULL
;
2023 if (epctx
->state
== EP_HALTED
) {
2024 DPRINTF("xhci: ep halted, not running schedule\n");
2029 if (epctx
->nr_pstreams
) {
2031 stctx
= xhci_find_stream(epctx
, streamid
, &err
);
2032 if (stctx
== NULL
) {
2035 ring
= &stctx
->ring
;
2036 xhci_set_ep_state(xhci
, epctx
, stctx
, EP_RUNNING
);
2038 ring
= &epctx
->ring
;
2040 xhci_set_ep_state(xhci
, epctx
, NULL
, EP_RUNNING
);
2042 assert(ring
->dequeue
!= 0);
2045 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
2046 if (xfer
->running_async
|| xfer
->running_retry
) {
2049 length
= xhci_ring_chain_length(xhci
, ring
);
2052 } else if (length
== 0) {
2055 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
2056 xfer
->trb_count
= 0;
2057 xfer
->trb_alloced
= 0;
2062 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
2063 xfer
->trb_alloced
= length
;
2065 xfer
->trb_count
= length
;
2067 for (i
= 0; i
< length
; i
++) {
2068 assert(xhci_ring_fetch(xhci
, ring
, &xfer
->trbs
[i
], NULL
));
2070 xfer
->streamid
= streamid
;
2073 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
2074 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
2075 ep
= xfer
->packet
.ep
;
2077 fprintf(stderr
, "xhci: error firing CTL transfer\n");
2080 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
2081 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
2083 if (!xfer
->timed_xfer
) {
2084 fprintf(stderr
, "xhci: error firing data transfer\n");
2089 if (epctx
->state
== EP_HALTED
) {
2092 if (xfer
->running_retry
) {
2093 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2094 epctx
->retry
= xfer
;
2099 ep
= xhci_epid_to_usbep(xhci
, slotid
, epid
);
2101 usb_device_flush_ep_queue(ep
->dev
, ep
);
2105 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
2107 trace_usb_xhci_slot_enable(slotid
);
2108 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2109 xhci
->slots
[slotid
-1].enabled
= 1;
2110 xhci
->slots
[slotid
-1].uport
= NULL
;
2111 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
2116 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
2120 trace_usb_xhci_slot_disable(slotid
);
2121 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2123 for (i
= 1; i
<= 31; i
++) {
2124 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2125 xhci_disable_ep(xhci
, slotid
, i
);
2129 xhci
->slots
[slotid
-1].enabled
= 0;
2130 xhci
->slots
[slotid
-1].addressed
= 0;
2131 xhci
->slots
[slotid
-1].uport
= NULL
;
2135 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
2141 port
= (slot_ctx
[1]>>16) & 0xFF;
2142 port
= xhci
->ports
[port
-1].uport
->index
+1;
2143 pos
= snprintf(path
, sizeof(path
), "%d", port
);
2144 for (i
= 0; i
< 5; i
++) {
2145 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
2149 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
2152 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
2153 if (strcmp(uport
->path
, path
) == 0) {
2160 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
2161 uint64_t pictx
, bool bsr
)
2166 dma_addr_t ictx
, octx
, dcbaap
;
2168 uint32_t ictl_ctx
[2];
2169 uint32_t slot_ctx
[4];
2170 uint32_t ep0_ctx
[5];
2174 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2176 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
2177 poctx
= ldq_le_pci_dma(PCI_DEVICE(xhci
), dcbaap
+ 8 * slotid
);
2178 ictx
= xhci_mask64(pictx
);
2179 octx
= xhci_mask64(poctx
);
2181 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2182 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2184 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2186 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
2187 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2188 ictl_ctx
[0], ictl_ctx
[1]);
2189 return CC_TRB_ERROR
;
2192 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
2193 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
2195 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2196 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2198 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2199 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2201 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
2202 if (uport
== NULL
) {
2203 fprintf(stderr
, "xhci: port not found\n");
2204 return CC_TRB_ERROR
;
2206 trace_usb_xhci_slot_address(slotid
, uport
->path
);
2210 fprintf(stderr
, "xhci: port %s not connected\n", uport
->path
);
2211 return CC_USB_TRANSACTION_ERROR
;
2214 for (i
= 0; i
< xhci
->numslots
; i
++) {
2215 if (i
== slotid
-1) {
2218 if (xhci
->slots
[i
].uport
== uport
) {
2219 fprintf(stderr
, "xhci: port %s already assigned to slot %d\n",
2221 return CC_TRB_ERROR
;
2225 slot
= &xhci
->slots
[slotid
-1];
2226 slot
->uport
= uport
;
2230 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2235 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slotid
;
2236 usb_device_reset(dev
);
2237 memset(&p
, 0, sizeof(p
));
2238 usb_packet_addbuf(&p
, buf
, sizeof(buf
));
2239 usb_packet_setup(&p
, USB_TOKEN_OUT
,
2240 usb_ep_get(dev
, USB_TOKEN_OUT
, 0), 0,
2242 usb_device_handle_control(dev
, &p
,
2243 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
2244 slotid
, 0, 0, NULL
);
2245 assert(p
.status
!= USB_RET_ASYNC
);
2248 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
2250 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2251 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2252 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2253 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2255 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2256 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2258 xhci
->slots
[slotid
-1].addressed
= 1;
2263 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2264 uint64_t pictx
, bool dc
)
2266 dma_addr_t ictx
, octx
;
2267 uint32_t ictl_ctx
[2];
2268 uint32_t slot_ctx
[4];
2269 uint32_t islot_ctx
[4];
2274 trace_usb_xhci_slot_configure(slotid
);
2275 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2277 ictx
= xhci_mask64(pictx
);
2278 octx
= xhci
->slots
[slotid
-1].ctx
;
2280 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2281 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2284 for (i
= 2; i
<= 31; i
++) {
2285 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2286 xhci_disable_ep(xhci
, slotid
, i
);
2290 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2291 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2292 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2293 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2294 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2295 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2300 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2302 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2303 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2304 ictl_ctx
[0], ictl_ctx
[1]);
2305 return CC_TRB_ERROR
;
2308 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2309 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2311 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2312 fprintf(stderr
, "xhci: invalid slot state %08x\n", slot_ctx
[3]);
2313 return CC_CONTEXT_STATE_ERROR
;
2316 for (i
= 2; i
<= 31; i
++) {
2317 if (ictl_ctx
[0] & (1<<i
)) {
2318 xhci_disable_ep(xhci
, slotid
, i
);
2320 if (ictl_ctx
[1] & (1<<i
)) {
2321 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2322 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2323 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2324 ep_ctx
[3], ep_ctx
[4]);
2325 xhci_disable_ep(xhci
, slotid
, i
);
2326 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2327 if (res
!= CC_SUCCESS
) {
2330 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2331 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2332 ep_ctx
[3], ep_ctx
[4]);
2333 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2337 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2338 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2339 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2340 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2341 SLOT_CONTEXT_ENTRIES_SHIFT
);
2342 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2343 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2345 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2351 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2354 dma_addr_t ictx
, octx
;
2355 uint32_t ictl_ctx
[2];
2356 uint32_t iep0_ctx
[5];
2357 uint32_t ep0_ctx
[5];
2358 uint32_t islot_ctx
[4];
2359 uint32_t slot_ctx
[4];
2361 trace_usb_xhci_slot_evaluate(slotid
);
2362 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2364 ictx
= xhci_mask64(pictx
);
2365 octx
= xhci
->slots
[slotid
-1].ctx
;
2367 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2368 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2370 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2372 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2373 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2374 ictl_ctx
[0], ictl_ctx
[1]);
2375 return CC_TRB_ERROR
;
2378 if (ictl_ctx
[1] & 0x1) {
2379 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2381 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2382 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2384 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2386 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2387 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2388 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2389 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2391 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2392 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2394 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2397 if (ictl_ctx
[1] & 0x2) {
2398 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2400 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2401 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2402 iep0_ctx
[3], iep0_ctx
[4]);
2404 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2406 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2407 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2409 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2410 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2412 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2418 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2420 uint32_t slot_ctx
[4];
2424 trace_usb_xhci_slot_reset(slotid
);
2425 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2427 octx
= xhci
->slots
[slotid
-1].ctx
;
2429 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2431 for (i
= 2; i
<= 31; i
++) {
2432 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2433 xhci_disable_ep(xhci
, slotid
, i
);
2437 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2438 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2439 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2440 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2441 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2442 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2447 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2449 unsigned int slotid
;
2450 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2451 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2452 fprintf(stderr
, "xhci: bad slot id %d\n", slotid
);
2453 event
->ccode
= CC_TRB_ERROR
;
2455 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2456 fprintf(stderr
, "xhci: slot id %d not enabled\n", slotid
);
2457 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2463 /* cleanup slot state on usb device detach */
2464 static void xhci_detach_slot(XHCIState
*xhci
, USBPort
*uport
)
2468 for (slot
= 0; slot
< xhci
->numslots
; slot
++) {
2469 if (xhci
->slots
[slot
].uport
== uport
) {
2473 if (slot
== xhci
->numslots
) {
2477 for (ep
= 0; ep
< 31; ep
++) {
2478 if (xhci
->slots
[slot
].eps
[ep
]) {
2479 xhci_ep_nuke_xfers(xhci
, slot
+ 1, ep
+ 1, 0);
2482 xhci
->slots
[slot
].uport
= NULL
;
2485 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2488 uint8_t bw_ctx
[xhci
->numports
+1];
2490 DPRINTF("xhci_get_port_bandwidth()\n");
2492 ctx
= xhci_mask64(pctx
);
2494 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2496 /* TODO: actually implement real values here */
2498 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2499 pci_dma_write(PCI_DEVICE(xhci
), ctx
, bw_ctx
, sizeof(bw_ctx
));
2504 static uint32_t rotl(uint32_t v
, unsigned count
)
2507 return (v
<< count
) | (v
>> (32 - count
));
2511 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2514 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2515 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2516 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2520 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2522 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
2525 dma_addr_t paddr
= xhci_mask64(addr
);
2527 pci_dma_read(pci_dev
, paddr
, &buf
, 32);
2529 memcpy(obuf
, buf
, sizeof(obuf
));
2531 if ((buf
[0] & 0xff) == 2) {
2532 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2533 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2534 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2535 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2536 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2537 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2538 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2539 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2540 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2543 pci_dma_write(pci_dev
, paddr
, &obuf
, 32);
2546 static void xhci_process_commands(XHCIState
*xhci
)
2550 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2552 unsigned int i
, slotid
= 0;
2554 DPRINTF("xhci_process_commands()\n");
2555 if (!xhci_running(xhci
)) {
2556 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2560 xhci
->crcr_low
|= CRCR_CRR
;
2562 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2565 case CR_ENABLE_SLOT
:
2566 for (i
= 0; i
< xhci
->numslots
; i
++) {
2567 if (!xhci
->slots
[i
].enabled
) {
2571 if (i
>= xhci
->numslots
) {
2572 fprintf(stderr
, "xhci: no device slots available\n");
2573 event
.ccode
= CC_NO_SLOTS_ERROR
;
2576 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2579 case CR_DISABLE_SLOT
:
2580 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2582 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2585 case CR_ADDRESS_DEVICE
:
2586 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2588 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2589 trb
.control
& TRB_CR_BSR
);
2592 case CR_CONFIGURE_ENDPOINT
:
2593 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2595 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2596 trb
.control
& TRB_CR_DC
);
2599 case CR_EVALUATE_CONTEXT
:
2600 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2602 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2605 case CR_STOP_ENDPOINT
:
2606 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2608 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2610 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2613 case CR_RESET_ENDPOINT
:
2614 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2616 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2618 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2621 case CR_SET_TR_DEQUEUE
:
2622 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2624 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2626 unsigned int streamid
= (trb
.status
>> 16) & 0xffff;
2627 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
,
2632 case CR_RESET_DEVICE
:
2633 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2635 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2638 case CR_GET_PORT_BANDWIDTH
:
2639 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2641 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2642 xhci_via_challenge(xhci
, trb
.parameter
);
2644 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2645 event
.type
= 48; /* NEC reply */
2646 event
.length
= 0x3025;
2648 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2650 uint32_t chi
= trb
.parameter
>> 32;
2651 uint32_t clo
= trb
.parameter
;
2652 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2653 event
.length
= val
& 0xFFFF;
2654 event
.epid
= val
>> 16;
2656 event
.type
= 48; /* NEC reply */
2660 trace_usb_xhci_unimplemented("command", type
);
2661 event
.ccode
= CC_TRB_ERROR
;
2664 event
.slotid
= slotid
;
2665 xhci_event(xhci
, &event
, 0);
2669 static bool xhci_port_have_device(XHCIPort
*port
)
2671 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2672 return false; /* no device present */
2674 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2675 return false; /* speed mismatch */
2680 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2682 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2683 port
->portnr
<< 24 };
2685 if ((port
->portsc
& bits
) == bits
) {
2688 trace_usb_xhci_port_notify(port
->portnr
, bits
);
2689 port
->portsc
|= bits
;
2690 if (!xhci_running(port
->xhci
)) {
2693 xhci_event(port
->xhci
, &ev
, 0);
2696 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2698 uint32_t pls
= PLS_RX_DETECT
;
2700 port
->portsc
= PORTSC_PP
;
2701 if (!is_detach
&& xhci_port_have_device(port
)) {
2702 port
->portsc
|= PORTSC_CCS
;
2703 switch (port
->uport
->dev
->speed
) {
2705 port
->portsc
|= PORTSC_SPEED_LOW
;
2708 case USB_SPEED_FULL
:
2709 port
->portsc
|= PORTSC_SPEED_FULL
;
2712 case USB_SPEED_HIGH
:
2713 port
->portsc
|= PORTSC_SPEED_HIGH
;
2716 case USB_SPEED_SUPER
:
2717 port
->portsc
|= PORTSC_SPEED_SUPER
;
2718 port
->portsc
|= PORTSC_PED
;
2723 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2724 trace_usb_xhci_port_link(port
->portnr
, pls
);
2725 xhci_port_notify(port
, PORTSC_CSC
);
2728 static void xhci_port_reset(XHCIPort
*port
, bool warm_reset
)
2730 trace_usb_xhci_port_reset(port
->portnr
);
2732 if (!xhci_port_have_device(port
)) {
2736 usb_device_reset(port
->uport
->dev
);
2738 switch (port
->uport
->dev
->speed
) {
2739 case USB_SPEED_SUPER
:
2741 port
->portsc
|= PORTSC_WRC
;
2745 case USB_SPEED_FULL
:
2746 case USB_SPEED_HIGH
:
2747 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2748 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2749 port
->portsc
|= PORTSC_PED
;
2753 port
->portsc
&= ~PORTSC_PR
;
2754 xhci_port_notify(port
, PORTSC_PRC
);
2757 static void xhci_reset(DeviceState
*dev
)
2759 XHCIState
*xhci
= XHCI(dev
);
2762 trace_usb_xhci_reset();
2763 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2764 fprintf(stderr
, "xhci: reset while running!\n");
2768 xhci
->usbsts
= USBSTS_HCH
;
2771 xhci
->crcr_high
= 0;
2772 xhci
->dcbaap_low
= 0;
2773 xhci
->dcbaap_high
= 0;
2776 for (i
= 0; i
< xhci
->numslots
; i
++) {
2777 xhci_disable_slot(xhci
, i
+1);
2780 for (i
= 0; i
< xhci
->numports
; i
++) {
2781 xhci_port_update(xhci
->ports
+ i
, 0);
2784 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2785 xhci
->intr
[i
].iman
= 0;
2786 xhci
->intr
[i
].imod
= 0;
2787 xhci
->intr
[i
].erstsz
= 0;
2788 xhci
->intr
[i
].erstba_low
= 0;
2789 xhci
->intr
[i
].erstba_high
= 0;
2790 xhci
->intr
[i
].erdp_low
= 0;
2791 xhci
->intr
[i
].erdp_high
= 0;
2792 xhci
->intr
[i
].msix_used
= 0;
2794 xhci
->intr
[i
].er_ep_idx
= 0;
2795 xhci
->intr
[i
].er_pcs
= 1;
2796 xhci
->intr
[i
].er_full
= 0;
2797 xhci
->intr
[i
].ev_buffer_put
= 0;
2798 xhci
->intr
[i
].ev_buffer_get
= 0;
2801 xhci
->mfindex_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
2802 xhci_mfwrap_update(xhci
);
2805 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2807 XHCIState
*xhci
= ptr
;
2811 case 0x00: /* HCIVERSION, CAPLENGTH */
2812 ret
= 0x01000000 | LEN_CAP
;
2814 case 0x04: /* HCSPARAMS 1 */
2815 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2816 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2818 case 0x08: /* HCSPARAMS 2 */
2821 case 0x0c: /* HCSPARAMS 3 */
2824 case 0x10: /* HCCPARAMS */
2825 if (sizeof(dma_addr_t
) == 4) {
2831 case 0x14: /* DBOFF */
2834 case 0x18: /* RTSOFF */
2838 /* extended capabilities */
2839 case 0x20: /* Supported Protocol:00 */
2840 ret
= 0x02000402; /* USB 2.0 */
2842 case 0x24: /* Supported Protocol:04 */
2843 ret
= 0x20425355; /* "USB " */
2845 case 0x28: /* Supported Protocol:08 */
2846 ret
= 0x00000001 | (xhci
->numports_2
<<8);
2848 case 0x2c: /* Supported Protocol:0c */
2849 ret
= 0x00000000; /* reserved */
2851 case 0x30: /* Supported Protocol:00 */
2852 ret
= 0x03000002; /* USB 3.0 */
2854 case 0x34: /* Supported Protocol:04 */
2855 ret
= 0x20425355; /* "USB " */
2857 case 0x38: /* Supported Protocol:08 */
2858 ret
= 0x00000000 | (xhci
->numports_2
+1) | (xhci
->numports_3
<<8);
2860 case 0x3c: /* Supported Protocol:0c */
2861 ret
= 0x00000000; /* reserved */
2864 trace_usb_xhci_unimplemented("cap read", reg
);
2868 trace_usb_xhci_cap_read(reg
, ret
);
2872 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2874 XHCIPort
*port
= ptr
;
2878 case 0x00: /* PORTSC */
2881 case 0x04: /* PORTPMSC */
2882 case 0x08: /* PORTLI */
2885 case 0x0c: /* reserved */
2887 trace_usb_xhci_unimplemented("port read", reg
);
2891 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2895 static void xhci_port_write(void *ptr
, hwaddr reg
,
2896 uint64_t val
, unsigned size
)
2898 XHCIPort
*port
= ptr
;
2899 uint32_t portsc
, notify
;
2901 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2904 case 0x00: /* PORTSC */
2905 /* write-1-to-start bits */
2906 if (val
& PORTSC_WPR
) {
2907 xhci_port_reset(port
, true);
2910 if (val
& PORTSC_PR
) {
2911 xhci_port_reset(port
, false);
2915 portsc
= port
->portsc
;
2917 /* write-1-to-clear bits*/
2918 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2919 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2920 if (val
& PORTSC_LWS
) {
2921 /* overwrite PLS only when LWS=1 */
2922 uint32_t old_pls
= get_field(port
->portsc
, PORTSC_PLS
);
2923 uint32_t new_pls
= get_field(val
, PORTSC_PLS
);
2926 if (old_pls
!= PLS_U0
) {
2927 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2928 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2929 notify
= PORTSC_PLC
;
2933 if (old_pls
< PLS_U3
) {
2934 set_field(&portsc
, new_pls
, PORTSC_PLS
);
2935 trace_usb_xhci_port_link(port
->portnr
, new_pls
);
2939 /* windows does this for some reason, don't spam stderr */
2942 fprintf(stderr
, "%s: ignore pls write (old %d, new %d)\n",
2943 __func__
, old_pls
, new_pls
);
2947 /* read/write bits */
2948 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2949 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2950 port
->portsc
= portsc
;
2952 xhci_port_notify(port
, notify
);
2955 case 0x04: /* PORTPMSC */
2956 case 0x08: /* PORTLI */
2958 trace_usb_xhci_unimplemented("port write", reg
);
2962 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2964 XHCIState
*xhci
= ptr
;
2968 case 0x00: /* USBCMD */
2971 case 0x04: /* USBSTS */
2974 case 0x08: /* PAGESIZE */
2977 case 0x14: /* DNCTRL */
2980 case 0x18: /* CRCR low */
2981 ret
= xhci
->crcr_low
& ~0xe;
2983 case 0x1c: /* CRCR high */
2984 ret
= xhci
->crcr_high
;
2986 case 0x30: /* DCBAAP low */
2987 ret
= xhci
->dcbaap_low
;
2989 case 0x34: /* DCBAAP high */
2990 ret
= xhci
->dcbaap_high
;
2992 case 0x38: /* CONFIG */
2996 trace_usb_xhci_unimplemented("oper read", reg
);
3000 trace_usb_xhci_oper_read(reg
, ret
);
3004 static void xhci_oper_write(void *ptr
, hwaddr reg
,
3005 uint64_t val
, unsigned size
)
3007 XHCIState
*xhci
= ptr
;
3008 DeviceState
*d
= DEVICE(ptr
);
3010 trace_usb_xhci_oper_write(reg
, val
);
3013 case 0x00: /* USBCMD */
3014 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
3016 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
3019 xhci
->usbcmd
= val
& 0xc0f;
3020 xhci_mfwrap_update(xhci
);
3021 if (val
& USBCMD_HCRST
) {
3024 xhci_intx_update(xhci
);
3027 case 0x04: /* USBSTS */
3028 /* these bits are write-1-to-clear */
3029 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
3030 xhci_intx_update(xhci
);
3033 case 0x14: /* DNCTRL */
3034 xhci
->dnctrl
= val
& 0xffff;
3036 case 0x18: /* CRCR low */
3037 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
3039 case 0x1c: /* CRCR high */
3040 xhci
->crcr_high
= val
;
3041 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
3042 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
3043 xhci
->crcr_low
&= ~CRCR_CRR
;
3044 xhci_event(xhci
, &event
, 0);
3045 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
3047 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
3048 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
3050 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
3052 case 0x30: /* DCBAAP low */
3053 xhci
->dcbaap_low
= val
& 0xffffffc0;
3055 case 0x34: /* DCBAAP high */
3056 xhci
->dcbaap_high
= val
;
3058 case 0x38: /* CONFIG */
3059 xhci
->config
= val
& 0xff;
3062 trace_usb_xhci_unimplemented("oper write", reg
);
3066 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
3069 XHCIState
*xhci
= ptr
;
3074 case 0x00: /* MFINDEX */
3075 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
3078 trace_usb_xhci_unimplemented("runtime read", reg
);
3082 int v
= (reg
- 0x20) / 0x20;
3083 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3084 switch (reg
& 0x1f) {
3085 case 0x00: /* IMAN */
3088 case 0x04: /* IMOD */
3091 case 0x08: /* ERSTSZ */
3094 case 0x10: /* ERSTBA low */
3095 ret
= intr
->erstba_low
;
3097 case 0x14: /* ERSTBA high */
3098 ret
= intr
->erstba_high
;
3100 case 0x18: /* ERDP low */
3101 ret
= intr
->erdp_low
;
3103 case 0x1c: /* ERDP high */
3104 ret
= intr
->erdp_high
;
3109 trace_usb_xhci_runtime_read(reg
, ret
);
3113 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
3114 uint64_t val
, unsigned size
)
3116 XHCIState
*xhci
= ptr
;
3117 int v
= (reg
- 0x20) / 0x20;
3118 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
3119 trace_usb_xhci_runtime_write(reg
, val
);
3122 trace_usb_xhci_unimplemented("runtime write", reg
);
3126 switch (reg
& 0x1f) {
3127 case 0x00: /* IMAN */
3128 if (val
& IMAN_IP
) {
3129 intr
->iman
&= ~IMAN_IP
;
3131 intr
->iman
&= ~IMAN_IE
;
3132 intr
->iman
|= val
& IMAN_IE
;
3134 xhci_intx_update(xhci
);
3136 xhci_msix_update(xhci
, v
);
3138 case 0x04: /* IMOD */
3141 case 0x08: /* ERSTSZ */
3142 intr
->erstsz
= val
& 0xffff;
3144 case 0x10: /* ERSTBA low */
3145 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3146 intr->erstba_low = val & 0xffffffc0; */
3147 intr
->erstba_low
= val
& 0xfffffff0;
3149 case 0x14: /* ERSTBA high */
3150 intr
->erstba_high
= val
;
3151 xhci_er_reset(xhci
, v
);
3153 case 0x18: /* ERDP low */
3154 if (val
& ERDP_EHB
) {
3155 intr
->erdp_low
&= ~ERDP_EHB
;
3157 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
3159 case 0x1c: /* ERDP high */
3160 intr
->erdp_high
= val
;
3161 xhci_events_update(xhci
, v
);
3164 trace_usb_xhci_unimplemented("oper write", reg
);
3168 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
3171 /* doorbells always read as 0 */
3172 trace_usb_xhci_doorbell_read(reg
, 0);
3176 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
3177 uint64_t val
, unsigned size
)
3179 XHCIState
*xhci
= ptr
;
3180 unsigned int epid
, streamid
;
3182 trace_usb_xhci_doorbell_write(reg
, val
);
3184 if (!xhci_running(xhci
)) {
3185 fprintf(stderr
, "xhci: wrote doorbell while xHC stopped or paused\n");
3193 xhci_process_commands(xhci
);
3195 fprintf(stderr
, "xhci: bad doorbell 0 write: 0x%x\n",
3200 streamid
= (val
>> 16) & 0xffff;
3201 if (reg
> xhci
->numslots
) {
3202 fprintf(stderr
, "xhci: bad doorbell %d\n", (int)reg
);
3203 } else if (epid
> 31) {
3204 fprintf(stderr
, "xhci: bad doorbell %d write: 0x%x\n",
3205 (int)reg
, (uint32_t)val
);
3207 xhci_kick_ep(xhci
, reg
, epid
, streamid
);
3212 static void xhci_cap_write(void *opaque
, hwaddr addr
, uint64_t val
,
3218 static const MemoryRegionOps xhci_cap_ops
= {
3219 .read
= xhci_cap_read
,
3220 .write
= xhci_cap_write
,
3221 .valid
.min_access_size
= 1,
3222 .valid
.max_access_size
= 4,
3223 .impl
.min_access_size
= 4,
3224 .impl
.max_access_size
= 4,
3225 .endianness
= DEVICE_LITTLE_ENDIAN
,
3228 static const MemoryRegionOps xhci_oper_ops
= {
3229 .read
= xhci_oper_read
,
3230 .write
= xhci_oper_write
,
3231 .valid
.min_access_size
= 4,
3232 .valid
.max_access_size
= 4,
3233 .endianness
= DEVICE_LITTLE_ENDIAN
,
3236 static const MemoryRegionOps xhci_port_ops
= {
3237 .read
= xhci_port_read
,
3238 .write
= xhci_port_write
,
3239 .valid
.min_access_size
= 4,
3240 .valid
.max_access_size
= 4,
3241 .endianness
= DEVICE_LITTLE_ENDIAN
,
3244 static const MemoryRegionOps xhci_runtime_ops
= {
3245 .read
= xhci_runtime_read
,
3246 .write
= xhci_runtime_write
,
3247 .valid
.min_access_size
= 4,
3248 .valid
.max_access_size
= 4,
3249 .endianness
= DEVICE_LITTLE_ENDIAN
,
3252 static const MemoryRegionOps xhci_doorbell_ops
= {
3253 .read
= xhci_doorbell_read
,
3254 .write
= xhci_doorbell_write
,
3255 .valid
.min_access_size
= 4,
3256 .valid
.max_access_size
= 4,
3257 .endianness
= DEVICE_LITTLE_ENDIAN
,
3260 static void xhci_attach(USBPort
*usbport
)
3262 XHCIState
*xhci
= usbport
->opaque
;
3263 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3265 xhci_port_update(port
, 0);
3268 static void xhci_detach(USBPort
*usbport
)
3270 XHCIState
*xhci
= usbport
->opaque
;
3271 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3273 xhci_detach_slot(xhci
, usbport
);
3274 xhci_port_update(port
, 1);
3277 static void xhci_wakeup(USBPort
*usbport
)
3279 XHCIState
*xhci
= usbport
->opaque
;
3280 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
3282 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
3285 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
3286 xhci_port_notify(port
, PORTSC_PLC
);
3289 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
3291 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
3293 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
3294 xhci_ep_nuke_one_xfer(xfer
, 0);
3297 xhci_complete_packet(xfer
);
3298 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
, xfer
->streamid
);
3301 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
3303 USBBus
*bus
= usb_bus_from_device(child
);
3304 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3306 xhci_detach_slot(xhci
, uport
);
3309 static USBPortOps xhci_uport_ops
= {
3310 .attach
= xhci_attach
,
3311 .detach
= xhci_detach
,
3312 .wakeup
= xhci_wakeup
,
3313 .complete
= xhci_complete
,
3314 .child_detach
= xhci_child_detach
,
3317 static int xhci_find_epid(USBEndpoint
*ep
)
3322 if (ep
->pid
== USB_TOKEN_IN
) {
3323 return ep
->nr
* 2 + 1;
3329 static USBEndpoint
*xhci_epid_to_usbep(XHCIState
*xhci
,
3330 unsigned int slotid
, unsigned int epid
)
3332 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
3334 if (!xhci
->slots
[slotid
- 1].uport
) {
3338 return usb_ep_get(xhci
->slots
[slotid
- 1].uport
->dev
,
3339 (epid
& 1) ? USB_TOKEN_IN
: USB_TOKEN_OUT
, epid
>> 1);
3342 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
,
3343 unsigned int stream
)
3345 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3348 DPRINTF("%s\n", __func__
);
3349 slotid
= ep
->dev
->addr
;
3350 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3351 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3354 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
), stream
);
3357 static USBBusOps xhci_bus_ops
= {
3358 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3361 static void usb_xhci_init(XHCIState
*xhci
)
3363 DeviceState
*dev
= DEVICE(xhci
);
3365 int i
, usbports
, speedmask
;
3367 xhci
->usbsts
= USBSTS_HCH
;
3369 if (xhci
->numports_2
> MAXPORTS_2
) {
3370 xhci
->numports_2
= MAXPORTS_2
;
3372 if (xhci
->numports_3
> MAXPORTS_3
) {
3373 xhci
->numports_3
= MAXPORTS_3
;
3375 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3376 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3378 usb_bus_new(&xhci
->bus
, sizeof(xhci
->bus
), &xhci_bus_ops
, dev
);
3380 for (i
= 0; i
< usbports
; i
++) {
3382 if (i
< xhci
->numports_2
) {
3383 port
= &xhci
->ports
[i
];
3384 port
->portnr
= i
+ 1;
3385 port
->uport
= &xhci
->uports
[i
];
3387 USB_SPEED_MASK_LOW
|
3388 USB_SPEED_MASK_FULL
|
3389 USB_SPEED_MASK_HIGH
;
3390 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3391 speedmask
|= port
->speedmask
;
3393 if (i
< xhci
->numports_3
) {
3394 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3395 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3396 port
->uport
= &xhci
->uports
[i
];
3397 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3398 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3399 speedmask
|= port
->speedmask
;
3401 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3402 &xhci_uport_ops
, speedmask
);
3406 static int usb_xhci_initfn(struct PCIDevice
*dev
)
3410 XHCIState
*xhci
= XHCI(dev
);
3412 dev
->config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3413 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3414 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3415 dev
->config
[0x60] = 0x30; /* release number */
3417 usb_xhci_init(xhci
);
3419 if (xhci
->numintrs
> MAXINTRS
) {
3420 xhci
->numintrs
= MAXINTRS
;
3422 while (xhci
->numintrs
& (xhci
->numintrs
- 1)) { /* ! power of 2 */
3425 if (xhci
->numintrs
< 1) {
3428 if (xhci
->numslots
> MAXSLOTS
) {
3429 xhci
->numslots
= MAXSLOTS
;
3431 if (xhci
->numslots
< 1) {
3435 xhci
->mfwrap_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, xhci_mfwrap_timer
, xhci
);
3437 memory_region_init(&xhci
->mem
, OBJECT(xhci
), "xhci", LEN_REGS
);
3438 memory_region_init_io(&xhci
->mem_cap
, OBJECT(xhci
), &xhci_cap_ops
, xhci
,
3439 "capabilities", LEN_CAP
);
3440 memory_region_init_io(&xhci
->mem_oper
, OBJECT(xhci
), &xhci_oper_ops
, xhci
,
3441 "operational", 0x400);
3442 memory_region_init_io(&xhci
->mem_runtime
, OBJECT(xhci
), &xhci_runtime_ops
, xhci
,
3443 "runtime", LEN_RUNTIME
);
3444 memory_region_init_io(&xhci
->mem_doorbell
, OBJECT(xhci
), &xhci_doorbell_ops
, xhci
,
3445 "doorbell", LEN_DOORBELL
);
3447 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3448 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3449 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3450 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3452 for (i
= 0; i
< xhci
->numports
; i
++) {
3453 XHCIPort
*port
= &xhci
->ports
[i
];
3454 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3456 memory_region_init_io(&port
->mem
, OBJECT(xhci
), &xhci_port_ops
, port
,
3458 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3461 pci_register_bar(dev
, 0,
3462 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3465 ret
= pcie_endpoint_cap_init(dev
, 0xa0);
3468 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI
)) {
3469 msi_init(dev
, 0x70, xhci
->numintrs
, true, false);
3471 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI_X
)) {
3472 msix_init(dev
, xhci
->numintrs
,
3473 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3474 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3481 static int usb_xhci_post_load(void *opaque
, int version_id
)
3483 XHCIState
*xhci
= opaque
;
3484 PCIDevice
*pci_dev
= PCI_DEVICE(xhci
);
3486 XHCIEPContext
*epctx
;
3487 dma_addr_t dcbaap
, pctx
;
3488 uint32_t slot_ctx
[4];
3490 int slotid
, epid
, state
, intr
;
3492 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
3494 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
3495 slot
= &xhci
->slots
[slotid
-1];
3496 if (!slot
->addressed
) {
3500 xhci_mask64(ldq_le_pci_dma(pci_dev
, dcbaap
+ 8 * slotid
));
3501 xhci_dma_read_u32s(xhci
, slot
->ctx
, slot_ctx
, sizeof(slot_ctx
));
3502 slot
->uport
= xhci_lookup_uport(xhci
, slot_ctx
);
3503 assert(slot
->uport
&& slot
->uport
->dev
);
3505 for (epid
= 1; epid
<= 32; epid
++) {
3506 pctx
= slot
->ctx
+ 32 * epid
;
3507 xhci_dma_read_u32s(xhci
, pctx
, ep_ctx
, sizeof(ep_ctx
));
3508 state
= ep_ctx
[0] & EP_STATE_MASK
;
3509 if (state
== EP_DISABLED
) {
3512 epctx
= xhci_alloc_epctx(xhci
, slotid
, epid
);
3513 slot
->eps
[epid
-1] = epctx
;
3514 xhci_init_epctx(epctx
, pctx
, ep_ctx
);
3515 epctx
->state
= state
;
3516 if (state
== EP_RUNNING
) {
3517 /* kick endpoint after vmload is finished */
3518 timer_mod(epctx
->kick_timer
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
3523 for (intr
= 0; intr
< xhci
->numintrs
; intr
++) {
3524 if (xhci
->intr
[intr
].msix_used
) {
3525 msix_vector_use(pci_dev
, intr
);
3527 msix_vector_unuse(pci_dev
, intr
);
3534 static const VMStateDescription vmstate_xhci_ring
= {
3535 .name
= "xhci-ring",
3537 .fields
= (VMStateField
[]) {
3538 VMSTATE_UINT64(dequeue
, XHCIRing
),
3539 VMSTATE_BOOL(ccs
, XHCIRing
),
3540 VMSTATE_END_OF_LIST()
3544 static const VMStateDescription vmstate_xhci_port
= {
3545 .name
= "xhci-port",
3547 .fields
= (VMStateField
[]) {
3548 VMSTATE_UINT32(portsc
, XHCIPort
),
3549 VMSTATE_END_OF_LIST()
3553 static const VMStateDescription vmstate_xhci_slot
= {
3554 .name
= "xhci-slot",
3556 .fields
= (VMStateField
[]) {
3557 VMSTATE_BOOL(enabled
, XHCISlot
),
3558 VMSTATE_BOOL(addressed
, XHCISlot
),
3559 VMSTATE_END_OF_LIST()
3563 static const VMStateDescription vmstate_xhci_event
= {
3564 .name
= "xhci-event",
3566 .fields
= (VMStateField
[]) {
3567 VMSTATE_UINT32(type
, XHCIEvent
),
3568 VMSTATE_UINT32(ccode
, XHCIEvent
),
3569 VMSTATE_UINT64(ptr
, XHCIEvent
),
3570 VMSTATE_UINT32(length
, XHCIEvent
),
3571 VMSTATE_UINT32(flags
, XHCIEvent
),
3572 VMSTATE_UINT8(slotid
, XHCIEvent
),
3573 VMSTATE_UINT8(epid
, XHCIEvent
),
3577 static bool xhci_er_full(void *opaque
, int version_id
)
3579 struct XHCIInterrupter
*intr
= opaque
;
3580 return intr
->er_full
;
3583 static const VMStateDescription vmstate_xhci_intr
= {
3584 .name
= "xhci-intr",
3586 .fields
= (VMStateField
[]) {
3588 VMSTATE_UINT32(iman
, XHCIInterrupter
),
3589 VMSTATE_UINT32(imod
, XHCIInterrupter
),
3590 VMSTATE_UINT32(erstsz
, XHCIInterrupter
),
3591 VMSTATE_UINT32(erstba_low
, XHCIInterrupter
),
3592 VMSTATE_UINT32(erstba_high
, XHCIInterrupter
),
3593 VMSTATE_UINT32(erdp_low
, XHCIInterrupter
),
3594 VMSTATE_UINT32(erdp_high
, XHCIInterrupter
),
3597 VMSTATE_BOOL(msix_used
, XHCIInterrupter
),
3598 VMSTATE_BOOL(er_pcs
, XHCIInterrupter
),
3599 VMSTATE_UINT64(er_start
, XHCIInterrupter
),
3600 VMSTATE_UINT32(er_size
, XHCIInterrupter
),
3601 VMSTATE_UINT32(er_ep_idx
, XHCIInterrupter
),
3603 /* event queue (used if ring is full) */
3604 VMSTATE_BOOL(er_full
, XHCIInterrupter
),
3605 VMSTATE_UINT32_TEST(ev_buffer_put
, XHCIInterrupter
, xhci_er_full
),
3606 VMSTATE_UINT32_TEST(ev_buffer_get
, XHCIInterrupter
, xhci_er_full
),
3607 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer
, XHCIInterrupter
, EV_QUEUE
,
3609 vmstate_xhci_event
, XHCIEvent
),
3611 VMSTATE_END_OF_LIST()
3615 static const VMStateDescription vmstate_xhci
= {
3618 .post_load
= usb_xhci_post_load
,
3619 .fields
= (VMStateField
[]) {
3620 VMSTATE_PCIE_DEVICE(parent_obj
, XHCIState
),
3621 VMSTATE_MSIX(parent_obj
, XHCIState
),
3623 VMSTATE_STRUCT_VARRAY_UINT32(ports
, XHCIState
, numports
, 1,
3624 vmstate_xhci_port
, XHCIPort
),
3625 VMSTATE_STRUCT_VARRAY_UINT32(slots
, XHCIState
, numslots
, 1,
3626 vmstate_xhci_slot
, XHCISlot
),
3627 VMSTATE_STRUCT_VARRAY_UINT32(intr
, XHCIState
, numintrs
, 1,
3628 vmstate_xhci_intr
, XHCIInterrupter
),
3630 /* Operational Registers */
3631 VMSTATE_UINT32(usbcmd
, XHCIState
),
3632 VMSTATE_UINT32(usbsts
, XHCIState
),
3633 VMSTATE_UINT32(dnctrl
, XHCIState
),
3634 VMSTATE_UINT32(crcr_low
, XHCIState
),
3635 VMSTATE_UINT32(crcr_high
, XHCIState
),
3636 VMSTATE_UINT32(dcbaap_low
, XHCIState
),
3637 VMSTATE_UINT32(dcbaap_high
, XHCIState
),
3638 VMSTATE_UINT32(config
, XHCIState
),
3640 /* Runtime Registers & state */
3641 VMSTATE_INT64(mfindex_start
, XHCIState
),
3642 VMSTATE_TIMER(mfwrap_timer
, XHCIState
),
3643 VMSTATE_STRUCT(cmd_ring
, XHCIState
, 1, vmstate_xhci_ring
, XHCIRing
),
3645 VMSTATE_END_OF_LIST()
3649 static Property xhci_properties
[] = {
3650 DEFINE_PROP_BIT("msi", XHCIState
, flags
, XHCI_FLAG_USE_MSI
, true),
3651 DEFINE_PROP_BIT("msix", XHCIState
, flags
, XHCI_FLAG_USE_MSI_X
, true),
3652 DEFINE_PROP_UINT32("intrs", XHCIState
, numintrs
, MAXINTRS
),
3653 DEFINE_PROP_UINT32("slots", XHCIState
, numslots
, MAXSLOTS
),
3654 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3655 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3656 DEFINE_PROP_END_OF_LIST(),
3659 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3661 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3662 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3664 dc
->vmsd
= &vmstate_xhci
;
3665 dc
->props
= xhci_properties
;
3666 dc
->reset
= xhci_reset
;
3667 set_bit(DEVICE_CATEGORY_USB
, dc
->categories
);
3668 k
->init
= usb_xhci_initfn
;
3669 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
3670 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
3671 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3677 static const TypeInfo xhci_info
= {
3679 .parent
= TYPE_PCI_DEVICE
,
3680 .instance_size
= sizeof(XHCIState
),
3681 .class_init
= xhci_class_init
,
3684 static void xhci_register_types(void)
3686 type_register_static(&xhci_info
);
3689 type_init(xhci_register_types
)