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xhci: implement mfindex
[qemu.git] / hw / usb / hcd-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu-timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci.h"
25 #include "hw/msi.h"
26 #include "trace.h"
27
28 //#define DEBUG_XHCI
29 //#define DEBUG_DATA
30
31 #ifdef DEBUG_XHCI
32 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
33 #else
34 #define DPRINTF(...) do {} while (0)
35 #endif
36 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
38
39 #define MAXSLOTS 8
40 #define MAXINTRS 1
41
42 #define USB2_PORTS 4
43 #define USB3_PORTS 4
44
45 #define MAXPORTS (USB2_PORTS+USB3_PORTS)
46
47 #define TD_QUEUE 24
48
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53 #define ER_FULL_HACK
54
55 #define LEN_CAP 0x40
56 #define OFF_OPER LEN_CAP
57 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
58 #define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
59 #define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
60 #define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
61 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
62
63 /* must be power of 2 */
64 #define LEN_REGS 0x2000
65
66 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
67 # error Increase LEN_REGS
68 #endif
69
70 #if MAXINTRS > 1
71 # error TODO: only one interrupter supported
72 #endif
73
74 /* bit definitions */
75 #define USBCMD_RS (1<<0)
76 #define USBCMD_HCRST (1<<1)
77 #define USBCMD_INTE (1<<2)
78 #define USBCMD_HSEE (1<<3)
79 #define USBCMD_LHCRST (1<<7)
80 #define USBCMD_CSS (1<<8)
81 #define USBCMD_CRS (1<<9)
82 #define USBCMD_EWE (1<<10)
83 #define USBCMD_EU3S (1<<11)
84
85 #define USBSTS_HCH (1<<0)
86 #define USBSTS_HSE (1<<2)
87 #define USBSTS_EINT (1<<3)
88 #define USBSTS_PCD (1<<4)
89 #define USBSTS_SSS (1<<8)
90 #define USBSTS_RSS (1<<9)
91 #define USBSTS_SRE (1<<10)
92 #define USBSTS_CNR (1<<11)
93 #define USBSTS_HCE (1<<12)
94
95
96 #define PORTSC_CCS (1<<0)
97 #define PORTSC_PED (1<<1)
98 #define PORTSC_OCA (1<<3)
99 #define PORTSC_PR (1<<4)
100 #define PORTSC_PLS_SHIFT 5
101 #define PORTSC_PLS_MASK 0xf
102 #define PORTSC_PP (1<<9)
103 #define PORTSC_SPEED_SHIFT 10
104 #define PORTSC_SPEED_MASK 0xf
105 #define PORTSC_SPEED_FULL (1<<10)
106 #define PORTSC_SPEED_LOW (2<<10)
107 #define PORTSC_SPEED_HIGH (3<<10)
108 #define PORTSC_SPEED_SUPER (4<<10)
109 #define PORTSC_PIC_SHIFT 14
110 #define PORTSC_PIC_MASK 0x3
111 #define PORTSC_LWS (1<<16)
112 #define PORTSC_CSC (1<<17)
113 #define PORTSC_PEC (1<<18)
114 #define PORTSC_WRC (1<<19)
115 #define PORTSC_OCC (1<<20)
116 #define PORTSC_PRC (1<<21)
117 #define PORTSC_PLC (1<<22)
118 #define PORTSC_CEC (1<<23)
119 #define PORTSC_CAS (1<<24)
120 #define PORTSC_WCE (1<<25)
121 #define PORTSC_WDE (1<<26)
122 #define PORTSC_WOE (1<<27)
123 #define PORTSC_DR (1<<30)
124 #define PORTSC_WPR (1<<31)
125
126 #define CRCR_RCS (1<<0)
127 #define CRCR_CS (1<<1)
128 #define CRCR_CA (1<<2)
129 #define CRCR_CRR (1<<3)
130
131 #define IMAN_IP (1<<0)
132 #define IMAN_IE (1<<1)
133
134 #define ERDP_EHB (1<<3)
135
136 #define TRB_SIZE 16
137 typedef struct XHCITRB {
138 uint64_t parameter;
139 uint32_t status;
140 uint32_t control;
141 dma_addr_t addr;
142 bool ccs;
143 } XHCITRB;
144
145
146 typedef enum TRBType {
147 TRB_RESERVED = 0,
148 TR_NORMAL,
149 TR_SETUP,
150 TR_DATA,
151 TR_STATUS,
152 TR_ISOCH,
153 TR_LINK,
154 TR_EVDATA,
155 TR_NOOP,
156 CR_ENABLE_SLOT,
157 CR_DISABLE_SLOT,
158 CR_ADDRESS_DEVICE,
159 CR_CONFIGURE_ENDPOINT,
160 CR_EVALUATE_CONTEXT,
161 CR_RESET_ENDPOINT,
162 CR_STOP_ENDPOINT,
163 CR_SET_TR_DEQUEUE,
164 CR_RESET_DEVICE,
165 CR_FORCE_EVENT,
166 CR_NEGOTIATE_BW,
167 CR_SET_LATENCY_TOLERANCE,
168 CR_GET_PORT_BANDWIDTH,
169 CR_FORCE_HEADER,
170 CR_NOOP,
171 ER_TRANSFER = 32,
172 ER_COMMAND_COMPLETE,
173 ER_PORT_STATUS_CHANGE,
174 ER_BANDWIDTH_REQUEST,
175 ER_DOORBELL,
176 ER_HOST_CONTROLLER,
177 ER_DEVICE_NOTIFICATION,
178 ER_MFINDEX_WRAP,
179 /* vendor specific bits */
180 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
181 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
182 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
183 } TRBType;
184
185 #define CR_LINK TR_LINK
186
187 typedef enum TRBCCode {
188 CC_INVALID = 0,
189 CC_SUCCESS,
190 CC_DATA_BUFFER_ERROR,
191 CC_BABBLE_DETECTED,
192 CC_USB_TRANSACTION_ERROR,
193 CC_TRB_ERROR,
194 CC_STALL_ERROR,
195 CC_RESOURCE_ERROR,
196 CC_BANDWIDTH_ERROR,
197 CC_NO_SLOTS_ERROR,
198 CC_INVALID_STREAM_TYPE_ERROR,
199 CC_SLOT_NOT_ENABLED_ERROR,
200 CC_EP_NOT_ENABLED_ERROR,
201 CC_SHORT_PACKET,
202 CC_RING_UNDERRUN,
203 CC_RING_OVERRUN,
204 CC_VF_ER_FULL,
205 CC_PARAMETER_ERROR,
206 CC_BANDWIDTH_OVERRUN,
207 CC_CONTEXT_STATE_ERROR,
208 CC_NO_PING_RESPONSE_ERROR,
209 CC_EVENT_RING_FULL_ERROR,
210 CC_INCOMPATIBLE_DEVICE_ERROR,
211 CC_MISSED_SERVICE_ERROR,
212 CC_COMMAND_RING_STOPPED,
213 CC_COMMAND_ABORTED,
214 CC_STOPPED,
215 CC_STOPPED_LENGTH_INVALID,
216 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
217 CC_ISOCH_BUFFER_OVERRUN = 31,
218 CC_EVENT_LOST_ERROR,
219 CC_UNDEFINED_ERROR,
220 CC_INVALID_STREAM_ID_ERROR,
221 CC_SECONDARY_BANDWIDTH_ERROR,
222 CC_SPLIT_TRANSACTION_ERROR
223 } TRBCCode;
224
225 #define TRB_C (1<<0)
226 #define TRB_TYPE_SHIFT 10
227 #define TRB_TYPE_MASK 0x3f
228 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
229
230 #define TRB_EV_ED (1<<2)
231
232 #define TRB_TR_ENT (1<<1)
233 #define TRB_TR_ISP (1<<2)
234 #define TRB_TR_NS (1<<3)
235 #define TRB_TR_CH (1<<4)
236 #define TRB_TR_IOC (1<<5)
237 #define TRB_TR_IDT (1<<6)
238 #define TRB_TR_TBC_SHIFT 7
239 #define TRB_TR_TBC_MASK 0x3
240 #define TRB_TR_BEI (1<<9)
241 #define TRB_TR_TLBPC_SHIFT 16
242 #define TRB_TR_TLBPC_MASK 0xf
243 #define TRB_TR_FRAMEID_SHIFT 20
244 #define TRB_TR_FRAMEID_MASK 0x7ff
245 #define TRB_TR_SIA (1<<31)
246
247 #define TRB_TR_DIR (1<<16)
248
249 #define TRB_CR_SLOTID_SHIFT 24
250 #define TRB_CR_SLOTID_MASK 0xff
251 #define TRB_CR_EPID_SHIFT 16
252 #define TRB_CR_EPID_MASK 0x1f
253
254 #define TRB_CR_BSR (1<<9)
255 #define TRB_CR_DC (1<<9)
256
257 #define TRB_LK_TC (1<<1)
258
259 #define EP_TYPE_MASK 0x7
260 #define EP_TYPE_SHIFT 3
261
262 #define EP_STATE_MASK 0x7
263 #define EP_DISABLED (0<<0)
264 #define EP_RUNNING (1<<0)
265 #define EP_HALTED (2<<0)
266 #define EP_STOPPED (3<<0)
267 #define EP_ERROR (4<<0)
268
269 #define SLOT_STATE_MASK 0x1f
270 #define SLOT_STATE_SHIFT 27
271 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
272 #define SLOT_ENABLED 0
273 #define SLOT_DEFAULT 1
274 #define SLOT_ADDRESSED 2
275 #define SLOT_CONFIGURED 3
276
277 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
278 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
279
280 typedef enum EPType {
281 ET_INVALID = 0,
282 ET_ISO_OUT,
283 ET_BULK_OUT,
284 ET_INTR_OUT,
285 ET_CONTROL,
286 ET_ISO_IN,
287 ET_BULK_IN,
288 ET_INTR_IN,
289 } EPType;
290
291 typedef struct XHCIRing {
292 dma_addr_t base;
293 dma_addr_t dequeue;
294 bool ccs;
295 } XHCIRing;
296
297 typedef struct XHCIPort {
298 USBPort port;
299 uint32_t portsc;
300 } XHCIPort;
301
302 struct XHCIState;
303 typedef struct XHCIState XHCIState;
304
305 typedef struct XHCITransfer {
306 XHCIState *xhci;
307 USBPacket packet;
308 QEMUSGList sgl;
309 bool running_async;
310 bool running_retry;
311 bool cancelled;
312 bool complete;
313 unsigned int iso_pkts;
314 unsigned int slotid;
315 unsigned int epid;
316 bool in_xfer;
317 bool iso_xfer;
318
319 unsigned int trb_count;
320 unsigned int trb_alloced;
321 XHCITRB *trbs;
322
323 TRBCCode status;
324
325 unsigned int pkts;
326 unsigned int pktsize;
327 unsigned int cur_pkt;
328 } XHCITransfer;
329
330 typedef struct XHCIEPContext {
331 XHCIRing ring;
332 unsigned int next_xfer;
333 unsigned int comp_xfer;
334 XHCITransfer transfers[TD_QUEUE];
335 XHCITransfer *retry;
336 EPType type;
337 dma_addr_t pctx;
338 unsigned int max_psize;
339 uint32_t state;
340 } XHCIEPContext;
341
342 typedef struct XHCISlot {
343 bool enabled;
344 dma_addr_t ctx;
345 unsigned int port;
346 unsigned int devaddr;
347 XHCIEPContext * eps[31];
348 } XHCISlot;
349
350 typedef struct XHCIEvent {
351 TRBType type;
352 TRBCCode ccode;
353 uint64_t ptr;
354 uint32_t length;
355 uint32_t flags;
356 uint8_t slotid;
357 uint8_t epid;
358 } XHCIEvent;
359
360 struct XHCIState {
361 PCIDevice pci_dev;
362 USBBus bus;
363 qemu_irq irq;
364 MemoryRegion mem;
365 const char *name;
366 uint32_t msi;
367 unsigned int devaddr;
368
369 /* Operational Registers */
370 uint32_t usbcmd;
371 uint32_t usbsts;
372 uint32_t dnctrl;
373 uint32_t crcr_low;
374 uint32_t crcr_high;
375 uint32_t dcbaap_low;
376 uint32_t dcbaap_high;
377 uint32_t config;
378
379 XHCIPort ports[MAXPORTS];
380 XHCISlot slots[MAXSLOTS];
381
382 /* Runtime Registers */
383 uint32_t iman;
384 uint32_t imod;
385 uint32_t erstsz;
386 uint32_t erstba_low;
387 uint32_t erstba_high;
388 uint32_t erdp_low;
389 uint32_t erdp_high;
390
391 int64_t mfindex_start;
392 QEMUTimer *mfwrap_timer;
393
394 dma_addr_t er_start;
395 uint32_t er_size;
396 bool er_pcs;
397 unsigned int er_ep_idx;
398 bool er_full;
399
400 XHCIEvent ev_buffer[EV_QUEUE];
401 unsigned int ev_buffer_put;
402 unsigned int ev_buffer_get;
403
404 XHCIRing cmd_ring;
405 };
406
407 typedef struct XHCIEvRingSeg {
408 uint32_t addr_low;
409 uint32_t addr_high;
410 uint32_t size;
411 uint32_t rsvd;
412 } XHCIEvRingSeg;
413
414 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
415 unsigned int epid);
416 static void xhci_event(XHCIState *xhci, XHCIEvent *event);
417 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event);
418
419 static const char *TRBType_names[] = {
420 [TRB_RESERVED] = "TRB_RESERVED",
421 [TR_NORMAL] = "TR_NORMAL",
422 [TR_SETUP] = "TR_SETUP",
423 [TR_DATA] = "TR_DATA",
424 [TR_STATUS] = "TR_STATUS",
425 [TR_ISOCH] = "TR_ISOCH",
426 [TR_LINK] = "TR_LINK",
427 [TR_EVDATA] = "TR_EVDATA",
428 [TR_NOOP] = "TR_NOOP",
429 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
430 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
431 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
432 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
433 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
434 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
435 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
436 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
437 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
438 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
439 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
440 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
441 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
442 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
443 [CR_NOOP] = "CR_NOOP",
444 [ER_TRANSFER] = "ER_TRANSFER",
445 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
446 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
447 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
448 [ER_DOORBELL] = "ER_DOORBELL",
449 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
450 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
451 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
452 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
453 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
454 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
455 };
456
457 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
458 {
459 if (index >= llen || list[index] == NULL) {
460 return "???";
461 }
462 return list[index];
463 }
464
465 static const char *trb_name(XHCITRB *trb)
466 {
467 return lookup_name(TRB_TYPE(*trb), TRBType_names,
468 ARRAY_SIZE(TRBType_names));
469 }
470
471 static uint64_t xhci_mfindex_get(XHCIState *xhci)
472 {
473 int64_t now = qemu_get_clock_ns(vm_clock);
474 return (now - xhci->mfindex_start) / 125000;
475 }
476
477 static void xhci_mfwrap_update(XHCIState *xhci)
478 {
479 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
480 uint32_t mfindex, left;
481 int64_t now;
482
483 if ((xhci->usbcmd & bits) == bits) {
484 now = qemu_get_clock_ns(vm_clock);
485 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
486 left = 0x4000 - mfindex;
487 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
488 } else {
489 qemu_del_timer(xhci->mfwrap_timer);
490 }
491 }
492
493 static void xhci_mfwrap_timer(void *opaque)
494 {
495 XHCIState *xhci = opaque;
496 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
497
498 xhci_event(xhci, &wrap);
499 xhci_mfwrap_update(xhci);
500 }
501
502 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
503 {
504 if (sizeof(dma_addr_t) == 4) {
505 return low;
506 } else {
507 return low | (((dma_addr_t)high << 16) << 16);
508 }
509 }
510
511 static inline dma_addr_t xhci_mask64(uint64_t addr)
512 {
513 if (sizeof(dma_addr_t) == 4) {
514 return addr & 0xffffffff;
515 } else {
516 return addr;
517 }
518 }
519
520 static void xhci_irq_update(XHCIState *xhci)
521 {
522 int level = 0;
523
524 if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
525 xhci->usbcmd & USBCMD_INTE) {
526 level = 1;
527 }
528
529 if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
530 if (level) {
531 trace_usb_xhci_irq_msi(0);
532 msi_notify(&xhci->pci_dev, 0);
533 }
534 } else {
535 trace_usb_xhci_irq_intx(level);
536 qemu_set_irq(xhci->irq, level);
537 }
538 }
539
540 static inline int xhci_running(XHCIState *xhci)
541 {
542 return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
543 }
544
545 static void xhci_die(XHCIState *xhci)
546 {
547 xhci->usbsts |= USBSTS_HCE;
548 fprintf(stderr, "xhci: asserted controller error\n");
549 }
550
551 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event)
552 {
553 XHCITRB ev_trb;
554 dma_addr_t addr;
555
556 ev_trb.parameter = cpu_to_le64(event->ptr);
557 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
558 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
559 event->flags | (event->type << TRB_TYPE_SHIFT);
560 if (xhci->er_pcs) {
561 ev_trb.control |= TRB_C;
562 }
563 ev_trb.control = cpu_to_le32(ev_trb.control);
564
565 trace_usb_xhci_queue_event(xhci->er_ep_idx, trb_name(&ev_trb),
566 ev_trb.parameter, ev_trb.status, ev_trb.control);
567
568 addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx;
569 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
570
571 xhci->er_ep_idx++;
572 if (xhci->er_ep_idx >= xhci->er_size) {
573 xhci->er_ep_idx = 0;
574 xhci->er_pcs = !xhci->er_pcs;
575 }
576 }
577
578 static void xhci_events_update(XHCIState *xhci)
579 {
580 dma_addr_t erdp;
581 unsigned int dp_idx;
582 bool do_irq = 0;
583
584 if (xhci->usbsts & USBSTS_HCH) {
585 return;
586 }
587
588 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
589 if (erdp < xhci->er_start ||
590 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
591 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
592 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
593 xhci->er_start, xhci->er_size);
594 xhci_die(xhci);
595 return;
596 }
597 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
598 assert(dp_idx < xhci->er_size);
599
600 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
601 * deadlocks when the ER is full. Hack it by holding off events until
602 * the driver decides to free at least half of the ring */
603 if (xhci->er_full) {
604 int er_free = dp_idx - xhci->er_ep_idx;
605 if (er_free <= 0) {
606 er_free += xhci->er_size;
607 }
608 if (er_free < (xhci->er_size/2)) {
609 DPRINTF("xhci_events_update(): event ring still "
610 "more than half full (hack)\n");
611 return;
612 }
613 }
614
615 while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
616 assert(xhci->er_full);
617 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) {
618 DPRINTF("xhci_events_update(): event ring full again\n");
619 #ifndef ER_FULL_HACK
620 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
621 xhci_write_event(xhci, &full);
622 #endif
623 do_irq = 1;
624 break;
625 }
626 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get];
627 xhci_write_event(xhci, event);
628 xhci->ev_buffer_get++;
629 do_irq = 1;
630 if (xhci->ev_buffer_get == EV_QUEUE) {
631 xhci->ev_buffer_get = 0;
632 }
633 }
634
635 if (do_irq) {
636 xhci->erdp_low |= ERDP_EHB;
637 xhci->iman |= IMAN_IP;
638 xhci->usbsts |= USBSTS_EINT;
639 xhci_irq_update(xhci);
640 }
641
642 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
643 DPRINTF("xhci_events_update(): event ring no longer full\n");
644 xhci->er_full = 0;
645 }
646 return;
647 }
648
649 static void xhci_event(XHCIState *xhci, XHCIEvent *event)
650 {
651 dma_addr_t erdp;
652 unsigned int dp_idx;
653
654 if (xhci->er_full) {
655 DPRINTF("xhci_event(): ER full, queueing\n");
656 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
657 fprintf(stderr, "xhci: event queue full, dropping event!\n");
658 return;
659 }
660 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
661 if (xhci->ev_buffer_put == EV_QUEUE) {
662 xhci->ev_buffer_put = 0;
663 }
664 return;
665 }
666
667 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
668 if (erdp < xhci->er_start ||
669 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
670 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
671 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
672 xhci->er_start, xhci->er_size);
673 xhci_die(xhci);
674 return;
675 }
676
677 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
678 assert(dp_idx < xhci->er_size);
679
680 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) {
681 DPRINTF("xhci_event(): ER full, queueing\n");
682 #ifndef ER_FULL_HACK
683 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
684 xhci_write_event(xhci, &full);
685 #endif
686 xhci->er_full = 1;
687 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
688 fprintf(stderr, "xhci: event queue full, dropping event!\n");
689 return;
690 }
691 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
692 if (xhci->ev_buffer_put == EV_QUEUE) {
693 xhci->ev_buffer_put = 0;
694 }
695 } else {
696 xhci_write_event(xhci, event);
697 }
698
699 xhci->erdp_low |= ERDP_EHB;
700 xhci->iman |= IMAN_IP;
701 xhci->usbsts |= USBSTS_EINT;
702
703 xhci_irq_update(xhci);
704 }
705
706 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
707 dma_addr_t base)
708 {
709 ring->base = base;
710 ring->dequeue = base;
711 ring->ccs = 1;
712 }
713
714 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
715 dma_addr_t *addr)
716 {
717 while (1) {
718 TRBType type;
719 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
720 trb->addr = ring->dequeue;
721 trb->ccs = ring->ccs;
722 le64_to_cpus(&trb->parameter);
723 le32_to_cpus(&trb->status);
724 le32_to_cpus(&trb->control);
725
726 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
727 trb->parameter, trb->status, trb->control);
728
729 if ((trb->control & TRB_C) != ring->ccs) {
730 return 0;
731 }
732
733 type = TRB_TYPE(*trb);
734
735 if (type != TR_LINK) {
736 if (addr) {
737 *addr = ring->dequeue;
738 }
739 ring->dequeue += TRB_SIZE;
740 return type;
741 } else {
742 ring->dequeue = xhci_mask64(trb->parameter);
743 if (trb->control & TRB_LK_TC) {
744 ring->ccs = !ring->ccs;
745 }
746 }
747 }
748 }
749
750 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
751 {
752 XHCITRB trb;
753 int length = 0;
754 dma_addr_t dequeue = ring->dequeue;
755 bool ccs = ring->ccs;
756 /* hack to bundle together the two/three TDs that make a setup transfer */
757 bool control_td_set = 0;
758
759 while (1) {
760 TRBType type;
761 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
762 le64_to_cpus(&trb.parameter);
763 le32_to_cpus(&trb.status);
764 le32_to_cpus(&trb.control);
765
766 if ((trb.control & TRB_C) != ccs) {
767 return -length;
768 }
769
770 type = TRB_TYPE(trb);
771
772 if (type == TR_LINK) {
773 dequeue = xhci_mask64(trb.parameter);
774 if (trb.control & TRB_LK_TC) {
775 ccs = !ccs;
776 }
777 continue;
778 }
779
780 length += 1;
781 dequeue += TRB_SIZE;
782
783 if (type == TR_SETUP) {
784 control_td_set = 1;
785 } else if (type == TR_STATUS) {
786 control_td_set = 0;
787 }
788
789 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
790 return length;
791 }
792 }
793 }
794
795 static void xhci_er_reset(XHCIState *xhci)
796 {
797 XHCIEvRingSeg seg;
798
799 /* cache the (sole) event ring segment location */
800 if (xhci->erstsz != 1) {
801 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
802 xhci_die(xhci);
803 return;
804 }
805 dma_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high);
806 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
807 le32_to_cpus(&seg.addr_low);
808 le32_to_cpus(&seg.addr_high);
809 le32_to_cpus(&seg.size);
810 if (seg.size < 16 || seg.size > 4096) {
811 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
812 xhci_die(xhci);
813 return;
814 }
815 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
816 xhci->er_size = seg.size;
817
818 xhci->er_ep_idx = 0;
819 xhci->er_pcs = 1;
820 xhci->er_full = 0;
821
822 DPRINTF("xhci: event ring:" DMA_ADDR_FMT " [%d]\n",
823 xhci->er_start, xhci->er_size);
824 }
825
826 static void xhci_run(XHCIState *xhci)
827 {
828 trace_usb_xhci_run();
829 xhci->usbsts &= ~USBSTS_HCH;
830 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
831 }
832
833 static void xhci_stop(XHCIState *xhci)
834 {
835 trace_usb_xhci_stop();
836 xhci->usbsts |= USBSTS_HCH;
837 xhci->crcr_low &= ~CRCR_CRR;
838 }
839
840 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
841 uint32_t state)
842 {
843 uint32_t ctx[5];
844 if (epctx->state == state) {
845 return;
846 }
847
848 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
849 ctx[0] &= ~EP_STATE_MASK;
850 ctx[0] |= state;
851 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
852 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
853 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
854 epctx->pctx, state, ctx[3], ctx[2]);
855 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
856 epctx->state = state;
857 }
858
859 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
860 unsigned int epid, dma_addr_t pctx,
861 uint32_t *ctx)
862 {
863 XHCISlot *slot;
864 XHCIEPContext *epctx;
865 dma_addr_t dequeue;
866 int i;
867
868 trace_usb_xhci_ep_enable(slotid, epid);
869 assert(slotid >= 1 && slotid <= MAXSLOTS);
870 assert(epid >= 1 && epid <= 31);
871
872 slot = &xhci->slots[slotid-1];
873 if (slot->eps[epid-1]) {
874 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
875 return CC_TRB_ERROR;
876 }
877
878 epctx = g_malloc(sizeof(XHCIEPContext));
879 memset(epctx, 0, sizeof(XHCIEPContext));
880
881 slot->eps[epid-1] = epctx;
882
883 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
884 xhci_ring_init(xhci, &epctx->ring, dequeue);
885 epctx->ring.ccs = ctx[2] & 1;
886
887 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
888 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
889 epctx->pctx = pctx;
890 epctx->max_psize = ctx[1]>>16;
891 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
892 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
893 epid/2, epid%2, epctx->max_psize);
894 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
895 usb_packet_init(&epctx->transfers[i].packet);
896 }
897
898 epctx->state = EP_RUNNING;
899 ctx[0] &= ~EP_STATE_MASK;
900 ctx[0] |= EP_RUNNING;
901
902 return CC_SUCCESS;
903 }
904
905 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
906 unsigned int epid)
907 {
908 XHCISlot *slot;
909 XHCIEPContext *epctx;
910 int i, xferi, killed = 0;
911 assert(slotid >= 1 && slotid <= MAXSLOTS);
912 assert(epid >= 1 && epid <= 31);
913
914 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
915
916 slot = &xhci->slots[slotid-1];
917
918 if (!slot->eps[epid-1]) {
919 return 0;
920 }
921
922 epctx = slot->eps[epid-1];
923
924 xferi = epctx->next_xfer;
925 for (i = 0; i < TD_QUEUE; i++) {
926 XHCITransfer *t = &epctx->transfers[xferi];
927 if (t->running_async) {
928 usb_cancel_packet(&t->packet);
929 t->running_async = 0;
930 t->cancelled = 1;
931 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
932 killed++;
933 }
934 if (t->running_retry) {
935 t->running_retry = 0;
936 epctx->retry = NULL;
937 }
938 if (t->trbs) {
939 g_free(t->trbs);
940 }
941
942 t->trbs = NULL;
943 t->trb_count = t->trb_alloced = 0;
944 xferi = (xferi + 1) % TD_QUEUE;
945 }
946 return killed;
947 }
948
949 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
950 unsigned int epid)
951 {
952 XHCISlot *slot;
953 XHCIEPContext *epctx;
954
955 trace_usb_xhci_ep_disable(slotid, epid);
956 assert(slotid >= 1 && slotid <= MAXSLOTS);
957 assert(epid >= 1 && epid <= 31);
958
959 slot = &xhci->slots[slotid-1];
960
961 if (!slot->eps[epid-1]) {
962 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
963 return CC_SUCCESS;
964 }
965
966 xhci_ep_nuke_xfers(xhci, slotid, epid);
967
968 epctx = slot->eps[epid-1];
969
970 xhci_set_ep_state(xhci, epctx, EP_DISABLED);
971
972 g_free(epctx);
973 slot->eps[epid-1] = NULL;
974
975 return CC_SUCCESS;
976 }
977
978 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
979 unsigned int epid)
980 {
981 XHCISlot *slot;
982 XHCIEPContext *epctx;
983
984 trace_usb_xhci_ep_stop(slotid, epid);
985 assert(slotid >= 1 && slotid <= MAXSLOTS);
986
987 if (epid < 1 || epid > 31) {
988 fprintf(stderr, "xhci: bad ep %d\n", epid);
989 return CC_TRB_ERROR;
990 }
991
992 slot = &xhci->slots[slotid-1];
993
994 if (!slot->eps[epid-1]) {
995 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
996 return CC_EP_NOT_ENABLED_ERROR;
997 }
998
999 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1000 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1001 "data might be lost\n");
1002 }
1003
1004 epctx = slot->eps[epid-1];
1005
1006 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1007
1008 return CC_SUCCESS;
1009 }
1010
1011 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1012 unsigned int epid)
1013 {
1014 XHCISlot *slot;
1015 XHCIEPContext *epctx;
1016 USBDevice *dev;
1017
1018 trace_usb_xhci_ep_reset(slotid, epid);
1019 assert(slotid >= 1 && slotid <= MAXSLOTS);
1020
1021 if (epid < 1 || epid > 31) {
1022 fprintf(stderr, "xhci: bad ep %d\n", epid);
1023 return CC_TRB_ERROR;
1024 }
1025
1026 slot = &xhci->slots[slotid-1];
1027
1028 if (!slot->eps[epid-1]) {
1029 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1030 return CC_EP_NOT_ENABLED_ERROR;
1031 }
1032
1033 epctx = slot->eps[epid-1];
1034
1035 if (epctx->state != EP_HALTED) {
1036 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1037 epid, epctx->state);
1038 return CC_CONTEXT_STATE_ERROR;
1039 }
1040
1041 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1042 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1043 "data might be lost\n");
1044 }
1045
1046 uint8_t ep = epid>>1;
1047
1048 if (epid & 1) {
1049 ep |= 0x80;
1050 }
1051
1052 dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev;
1053 if (!dev) {
1054 return CC_USB_TRANSACTION_ERROR;
1055 }
1056
1057 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1058
1059 return CC_SUCCESS;
1060 }
1061
1062 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1063 unsigned int epid, uint64_t pdequeue)
1064 {
1065 XHCISlot *slot;
1066 XHCIEPContext *epctx;
1067 dma_addr_t dequeue;
1068
1069 assert(slotid >= 1 && slotid <= MAXSLOTS);
1070
1071 if (epid < 1 || epid > 31) {
1072 fprintf(stderr, "xhci: bad ep %d\n", epid);
1073 return CC_TRB_ERROR;
1074 }
1075
1076 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64")\n", slotid, epid, pdequeue);
1077 dequeue = xhci_mask64(pdequeue);
1078
1079 slot = &xhci->slots[slotid-1];
1080
1081 if (!slot->eps[epid-1]) {
1082 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1083 return CC_EP_NOT_ENABLED_ERROR;
1084 }
1085
1086 epctx = slot->eps[epid-1];
1087
1088
1089 if (epctx->state != EP_STOPPED) {
1090 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1091 return CC_CONTEXT_STATE_ERROR;
1092 }
1093
1094 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1095 epctx->ring.ccs = dequeue & 1;
1096
1097 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1098
1099 return CC_SUCCESS;
1100 }
1101
1102 static int xhci_xfer_map(XHCITransfer *xfer)
1103 {
1104 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN);
1105 XHCIState *xhci = xfer->xhci;
1106 int i;
1107
1108 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
1109 for (i = 0; i < xfer->trb_count; i++) {
1110 XHCITRB *trb = &xfer->trbs[i];
1111 dma_addr_t addr;
1112 unsigned int chunk = 0;
1113
1114 switch (TRB_TYPE(*trb)) {
1115 case TR_DATA:
1116 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1117 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
1118 goto err;
1119 }
1120 /* fallthrough */
1121 case TR_NORMAL:
1122 case TR_ISOCH:
1123 addr = xhci_mask64(trb->parameter);
1124 chunk = trb->status & 0x1ffff;
1125 if (trb->control & TRB_TR_IDT) {
1126 if (chunk > 8 || in_xfer) {
1127 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1128 goto err;
1129 }
1130 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1131 } else {
1132 qemu_sglist_add(&xfer->sgl, addr, chunk);
1133 }
1134 break;
1135 }
1136 }
1137
1138 usb_packet_map(&xfer->packet, &xfer->sgl);
1139 return 0;
1140
1141 err:
1142 qemu_sglist_destroy(&xfer->sgl);
1143 xhci_die(xhci);
1144 return -1;
1145 }
1146
1147 static void xhci_xfer_unmap(XHCITransfer *xfer)
1148 {
1149 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1150 qemu_sglist_destroy(&xfer->sgl);
1151 }
1152
1153 static void xhci_xfer_report(XHCITransfer *xfer)
1154 {
1155 uint32_t edtla = 0;
1156 unsigned int left;
1157 bool reported = 0;
1158 bool shortpkt = 0;
1159 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1160 XHCIState *xhci = xfer->xhci;
1161 int i;
1162
1163 left = xfer->packet.result < 0 ? 0 : xfer->packet.result;
1164
1165 for (i = 0; i < xfer->trb_count; i++) {
1166 XHCITRB *trb = &xfer->trbs[i];
1167 unsigned int chunk = 0;
1168
1169 switch (TRB_TYPE(*trb)) {
1170 case TR_DATA:
1171 case TR_NORMAL:
1172 case TR_ISOCH:
1173 chunk = trb->status & 0x1ffff;
1174 if (chunk > left) {
1175 chunk = left;
1176 if (xfer->status == CC_SUCCESS) {
1177 shortpkt = 1;
1178 }
1179 }
1180 left -= chunk;
1181 edtla += chunk;
1182 break;
1183 case TR_STATUS:
1184 reported = 0;
1185 shortpkt = 0;
1186 break;
1187 }
1188
1189 if (!reported && ((trb->control & TRB_TR_IOC) ||
1190 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1191 (xfer->status != CC_SUCCESS))) {
1192 event.slotid = xfer->slotid;
1193 event.epid = xfer->epid;
1194 event.length = (trb->status & 0x1ffff) - chunk;
1195 event.flags = 0;
1196 event.ptr = trb->addr;
1197 if (xfer->status == CC_SUCCESS) {
1198 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1199 } else {
1200 event.ccode = xfer->status;
1201 }
1202 if (TRB_TYPE(*trb) == TR_EVDATA) {
1203 event.ptr = trb->parameter;
1204 event.flags |= TRB_EV_ED;
1205 event.length = edtla & 0xffffff;
1206 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1207 edtla = 0;
1208 }
1209 xhci_event(xhci, &event);
1210 reported = 1;
1211 if (xfer->status != CC_SUCCESS) {
1212 return;
1213 }
1214 }
1215 }
1216 }
1217
1218 static void xhci_stall_ep(XHCITransfer *xfer)
1219 {
1220 XHCIState *xhci = xfer->xhci;
1221 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1222 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1223
1224 epctx->ring.dequeue = xfer->trbs[0].addr;
1225 epctx->ring.ccs = xfer->trbs[0].ccs;
1226 xhci_set_ep_state(xhci, epctx, EP_HALTED);
1227 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
1228 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue);
1229 }
1230
1231 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1232 XHCIEPContext *epctx);
1233
1234 static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
1235 {
1236 if (!(port->portsc & PORTSC_PED)) {
1237 return NULL;
1238 }
1239 return usb_find_device(&port->port, addr);
1240 }
1241
1242 static int xhci_setup_packet(XHCITransfer *xfer)
1243 {
1244 XHCIState *xhci = xfer->xhci;
1245 XHCIPort *port;
1246 USBDevice *dev;
1247 USBEndpoint *ep;
1248 int dir;
1249
1250 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1251
1252 if (xfer->packet.ep) {
1253 ep = xfer->packet.ep;
1254 dev = ep->dev;
1255 } else {
1256 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1257 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1258 if (!dev) {
1259 fprintf(stderr, "xhci: slot %d port %d has no device\n",
1260 xfer->slotid, xhci->slots[xfer->slotid-1].port);
1261 return -1;
1262 }
1263 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1264 }
1265
1266 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr);
1267 xhci_xfer_map(xfer);
1268 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1269 xfer->packet.pid, dev->addr, ep->nr);
1270 return 0;
1271 }
1272
1273 static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1274 {
1275 if (ret == USB_RET_ASYNC) {
1276 trace_usb_xhci_xfer_async(xfer);
1277 xfer->running_async = 1;
1278 xfer->running_retry = 0;
1279 xfer->complete = 0;
1280 xfer->cancelled = 0;
1281 return 0;
1282 } else if (ret == USB_RET_NAK) {
1283 trace_usb_xhci_xfer_nak(xfer);
1284 xfer->running_async = 0;
1285 xfer->running_retry = 1;
1286 xfer->complete = 0;
1287 xfer->cancelled = 0;
1288 return 0;
1289 } else {
1290 xfer->running_async = 0;
1291 xfer->running_retry = 0;
1292 xfer->complete = 1;
1293 xhci_xfer_unmap(xfer);
1294 }
1295
1296 if (ret >= 0) {
1297 trace_usb_xhci_xfer_success(xfer, ret);
1298 xfer->status = CC_SUCCESS;
1299 xhci_xfer_report(xfer);
1300 return 0;
1301 }
1302
1303 /* error */
1304 trace_usb_xhci_xfer_error(xfer, ret);
1305 switch (ret) {
1306 case USB_RET_NODEV:
1307 xfer->status = CC_USB_TRANSACTION_ERROR;
1308 xhci_xfer_report(xfer);
1309 xhci_stall_ep(xfer);
1310 break;
1311 case USB_RET_STALL:
1312 xfer->status = CC_STALL_ERROR;
1313 xhci_xfer_report(xfer);
1314 xhci_stall_ep(xfer);
1315 break;
1316 default:
1317 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1318 FIXME();
1319 }
1320 return 0;
1321 }
1322
1323 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1324 {
1325 XHCITRB *trb_setup, *trb_status;
1326 uint8_t bmRequestType;
1327 int ret;
1328
1329 trb_setup = &xfer->trbs[0];
1330 trb_status = &xfer->trbs[xfer->trb_count-1];
1331
1332 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
1333
1334 /* at most one Event Data TRB allowed after STATUS */
1335 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1336 trb_status--;
1337 }
1338
1339 /* do some sanity checks */
1340 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1341 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1342 TRB_TYPE(*trb_setup));
1343 return -1;
1344 }
1345 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1346 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1347 TRB_TYPE(*trb_status));
1348 return -1;
1349 }
1350 if (!(trb_setup->control & TRB_TR_IDT)) {
1351 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1352 return -1;
1353 }
1354 if ((trb_setup->status & 0x1ffff) != 8) {
1355 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1356 (trb_setup->status & 0x1ffff));
1357 return -1;
1358 }
1359
1360 bmRequestType = trb_setup->parameter;
1361
1362 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1363 xfer->iso_xfer = false;
1364
1365 if (xhci_setup_packet(xfer) < 0) {
1366 return -1;
1367 }
1368 xfer->packet.parameter = trb_setup->parameter;
1369
1370 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1371
1372 xhci_complete_packet(xfer, ret);
1373 if (!xfer->running_async && !xfer->running_retry) {
1374 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1375 }
1376 return 0;
1377 }
1378
1379 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1380 {
1381 int ret;
1382
1383 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1384
1385 xfer->in_xfer = epctx->type>>2;
1386
1387 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1388 xfer->pkts = 1;
1389 } else {
1390 xfer->pkts = 0;
1391 }
1392
1393 switch(epctx->type) {
1394 case ET_INTR_OUT:
1395 case ET_INTR_IN:
1396 case ET_BULK_OUT:
1397 case ET_BULK_IN:
1398 break;
1399 case ET_ISO_OUT:
1400 case ET_ISO_IN:
1401 FIXME();
1402 break;
1403 default:
1404 fprintf(stderr, "xhci: unknown or unhandled EP "
1405 "(type %d, in %d, ep %02x)\n",
1406 epctx->type, xfer->in_xfer, xfer->epid);
1407 return -1;
1408 }
1409
1410 if (xhci_setup_packet(xfer) < 0) {
1411 return -1;
1412 }
1413 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1414
1415 xhci_complete_packet(xfer, ret);
1416 if (!xfer->running_async && !xfer->running_retry) {
1417 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1418 }
1419 return 0;
1420 }
1421
1422 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1423 {
1424 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
1425 return xhci_submit(xhci, xfer, epctx);
1426 }
1427
1428 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1429 {
1430 XHCIEPContext *epctx;
1431 int length;
1432 int i;
1433
1434 trace_usb_xhci_ep_kick(slotid, epid);
1435 assert(slotid >= 1 && slotid <= MAXSLOTS);
1436 assert(epid >= 1 && epid <= 31);
1437
1438 if (!xhci->slots[slotid-1].enabled) {
1439 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1440 return;
1441 }
1442 epctx = xhci->slots[slotid-1].eps[epid-1];
1443 if (!epctx) {
1444 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1445 epid, slotid);
1446 return;
1447 }
1448
1449 if (epctx->retry) {
1450 /* retry nak'ed transfer */
1451 XHCITransfer *xfer = epctx->retry;
1452 int result;
1453
1454 trace_usb_xhci_xfer_retry(xfer);
1455 assert(xfer->running_retry);
1456 if (xhci_setup_packet(xfer) < 0) {
1457 return;
1458 }
1459 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1460 if (result == USB_RET_NAK) {
1461 return;
1462 }
1463 xhci_complete_packet(xfer, result);
1464 assert(!xfer->running_retry);
1465 epctx->retry = NULL;
1466 }
1467
1468 if (epctx->state == EP_HALTED) {
1469 DPRINTF("xhci: ep halted, not running schedule\n");
1470 return;
1471 }
1472
1473 xhci_set_ep_state(xhci, epctx, EP_RUNNING);
1474
1475 while (1) {
1476 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
1477 if (xfer->running_async || xfer->running_retry) {
1478 break;
1479 }
1480 length = xhci_ring_chain_length(xhci, &epctx->ring);
1481 if (length < 0) {
1482 break;
1483 } else if (length == 0) {
1484 break;
1485 }
1486 if (xfer->trbs && xfer->trb_alloced < length) {
1487 xfer->trb_count = 0;
1488 xfer->trb_alloced = 0;
1489 g_free(xfer->trbs);
1490 xfer->trbs = NULL;
1491 }
1492 if (!xfer->trbs) {
1493 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1494 xfer->trb_alloced = length;
1495 }
1496 xfer->trb_count = length;
1497
1498 for (i = 0; i < length; i++) {
1499 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
1500 }
1501 xfer->xhci = xhci;
1502 xfer->epid = epid;
1503 xfer->slotid = slotid;
1504
1505 if (epid == 1) {
1506 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1507 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1508 } else {
1509 fprintf(stderr, "xhci: error firing CTL transfer\n");
1510 }
1511 } else {
1512 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1513 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1514 } else {
1515 fprintf(stderr, "xhci: error firing data transfer\n");
1516 }
1517 }
1518
1519 if (epctx->state == EP_HALTED) {
1520 break;
1521 }
1522 if (xfer->running_retry) {
1523 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1524 epctx->retry = xfer;
1525 break;
1526 }
1527 }
1528 }
1529
1530 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1531 {
1532 trace_usb_xhci_slot_enable(slotid);
1533 assert(slotid >= 1 && slotid <= MAXSLOTS);
1534 xhci->slots[slotid-1].enabled = 1;
1535 xhci->slots[slotid-1].port = 0;
1536 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1537
1538 return CC_SUCCESS;
1539 }
1540
1541 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1542 {
1543 int i;
1544
1545 trace_usb_xhci_slot_disable(slotid);
1546 assert(slotid >= 1 && slotid <= MAXSLOTS);
1547
1548 for (i = 1; i <= 31; i++) {
1549 if (xhci->slots[slotid-1].eps[i-1]) {
1550 xhci_disable_ep(xhci, slotid, i);
1551 }
1552 }
1553
1554 xhci->slots[slotid-1].enabled = 0;
1555 return CC_SUCCESS;
1556 }
1557
1558 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1559 uint64_t pictx, bool bsr)
1560 {
1561 XHCISlot *slot;
1562 USBDevice *dev;
1563 dma_addr_t ictx, octx, dcbaap;
1564 uint64_t poctx;
1565 uint32_t ictl_ctx[2];
1566 uint32_t slot_ctx[4];
1567 uint32_t ep0_ctx[5];
1568 unsigned int port;
1569 int i;
1570 TRBCCode res;
1571
1572 trace_usb_xhci_slot_address(slotid);
1573 assert(slotid >= 1 && slotid <= MAXSLOTS);
1574
1575 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
1576 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx));
1577 ictx = xhci_mask64(pictx);
1578 octx = xhci_mask64(le64_to_cpu(poctx));
1579
1580 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1581 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1582
1583 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1584
1585 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1586 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1587 ictl_ctx[0], ictl_ctx[1]);
1588 return CC_TRB_ERROR;
1589 }
1590
1591 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx));
1592 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx));
1593
1594 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1595 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1596
1597 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1598 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1599
1600 port = (slot_ctx[1]>>16) & 0xFF;
1601 dev = xhci->ports[port-1].port.dev;
1602
1603 if (port < 1 || port > MAXPORTS) {
1604 fprintf(stderr, "xhci: bad port %d\n", port);
1605 return CC_TRB_ERROR;
1606 } else if (!dev) {
1607 fprintf(stderr, "xhci: port %d not connected\n", port);
1608 return CC_USB_TRANSACTION_ERROR;
1609 }
1610
1611 for (i = 0; i < MAXSLOTS; i++) {
1612 if (xhci->slots[i].port == port) {
1613 fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
1614 port, i+1);
1615 return CC_TRB_ERROR;
1616 }
1617 }
1618
1619 slot = &xhci->slots[slotid-1];
1620 slot->port = port;
1621 slot->ctx = octx;
1622
1623 if (bsr) {
1624 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
1625 } else {
1626 slot->devaddr = xhci->devaddr++;
1627 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
1628 DPRINTF("xhci: device address is %d\n", slot->devaddr);
1629 usb_device_handle_control(dev, NULL,
1630 DeviceOutRequest | USB_REQ_SET_ADDRESS,
1631 slot->devaddr, 0, 0, NULL);
1632 }
1633
1634 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1635
1636 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1637 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1638 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1639 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1640
1641 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1642 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1643
1644 return res;
1645 }
1646
1647
1648 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1649 uint64_t pictx, bool dc)
1650 {
1651 dma_addr_t ictx, octx;
1652 uint32_t ictl_ctx[2];
1653 uint32_t slot_ctx[4];
1654 uint32_t islot_ctx[4];
1655 uint32_t ep_ctx[5];
1656 int i;
1657 TRBCCode res;
1658
1659 trace_usb_xhci_slot_configure(slotid);
1660 assert(slotid >= 1 && slotid <= MAXSLOTS);
1661
1662 ictx = xhci_mask64(pictx);
1663 octx = xhci->slots[slotid-1].ctx;
1664
1665 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1666 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1667
1668 if (dc) {
1669 for (i = 2; i <= 31; i++) {
1670 if (xhci->slots[slotid-1].eps[i-1]) {
1671 xhci_disable_ep(xhci, slotid, i);
1672 }
1673 }
1674
1675 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1676 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1677 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
1678 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1679 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1680 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1681
1682 return CC_SUCCESS;
1683 }
1684
1685 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1686
1687 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1688 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1689 ictl_ctx[0], ictl_ctx[1]);
1690 return CC_TRB_ERROR;
1691 }
1692
1693 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1694 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1695
1696 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
1697 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1698 return CC_CONTEXT_STATE_ERROR;
1699 }
1700
1701 for (i = 2; i <= 31; i++) {
1702 if (ictl_ctx[0] & (1<<i)) {
1703 xhci_disable_ep(xhci, slotid, i);
1704 }
1705 if (ictl_ctx[1] & (1<<i)) {
1706 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx,
1707 sizeof(ep_ctx));
1708 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1709 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1710 ep_ctx[3], ep_ctx[4]);
1711 xhci_disable_ep(xhci, slotid, i);
1712 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1713 if (res != CC_SUCCESS) {
1714 return res;
1715 }
1716 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1717 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1718 ep_ctx[3], ep_ctx[4]);
1719 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx));
1720 }
1721 }
1722
1723 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1724 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
1725 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
1726 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
1727 SLOT_CONTEXT_ENTRIES_SHIFT);
1728 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1729 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1730
1731 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1732
1733 return CC_SUCCESS;
1734 }
1735
1736
1737 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1738 uint64_t pictx)
1739 {
1740 dma_addr_t ictx, octx;
1741 uint32_t ictl_ctx[2];
1742 uint32_t iep0_ctx[5];
1743 uint32_t ep0_ctx[5];
1744 uint32_t islot_ctx[4];
1745 uint32_t slot_ctx[4];
1746
1747 trace_usb_xhci_slot_evaluate(slotid);
1748 assert(slotid >= 1 && slotid <= MAXSLOTS);
1749
1750 ictx = xhci_mask64(pictx);
1751 octx = xhci->slots[slotid-1].ctx;
1752
1753 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1754 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1755
1756 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1757
1758 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1759 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1760 ictl_ctx[0], ictl_ctx[1]);
1761 return CC_TRB_ERROR;
1762 }
1763
1764 if (ictl_ctx[1] & 0x1) {
1765 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1766
1767 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1768 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
1769
1770 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1771
1772 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
1773 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
1774 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
1775 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
1776
1777 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1778 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1779
1780 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1781 }
1782
1783 if (ictl_ctx[1] & 0x2) {
1784 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx));
1785
1786 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1787 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
1788 iep0_ctx[3], iep0_ctx[4]);
1789
1790 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1791
1792 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
1793 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
1794
1795 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1796 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1797
1798 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1799 }
1800
1801 return CC_SUCCESS;
1802 }
1803
1804 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
1805 {
1806 uint32_t slot_ctx[4];
1807 dma_addr_t octx;
1808 int i;
1809
1810 trace_usb_xhci_slot_reset(slotid);
1811 assert(slotid >= 1 && slotid <= MAXSLOTS);
1812
1813 octx = xhci->slots[slotid-1].ctx;
1814
1815 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1816
1817 for (i = 2; i <= 31; i++) {
1818 if (xhci->slots[slotid-1].eps[i-1]) {
1819 xhci_disable_ep(xhci, slotid, i);
1820 }
1821 }
1822
1823 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1824 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1825 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
1826 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1827 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1828 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1829
1830 return CC_SUCCESS;
1831 }
1832
1833 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
1834 {
1835 unsigned int slotid;
1836 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
1837 if (slotid < 1 || slotid > MAXSLOTS) {
1838 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
1839 event->ccode = CC_TRB_ERROR;
1840 return 0;
1841 } else if (!xhci->slots[slotid-1].enabled) {
1842 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
1843 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
1844 return 0;
1845 }
1846 return slotid;
1847 }
1848
1849 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
1850 {
1851 dma_addr_t ctx;
1852 uint8_t bw_ctx[MAXPORTS+1];
1853
1854 DPRINTF("xhci_get_port_bandwidth()\n");
1855
1856 ctx = xhci_mask64(pctx);
1857
1858 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
1859
1860 /* TODO: actually implement real values here */
1861 bw_ctx[0] = 0;
1862 memset(&bw_ctx[1], 80, MAXPORTS); /* 80% */
1863 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
1864
1865 return CC_SUCCESS;
1866 }
1867
1868 static uint32_t rotl(uint32_t v, unsigned count)
1869 {
1870 count &= 31;
1871 return (v << count) | (v >> (32 - count));
1872 }
1873
1874
1875 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
1876 {
1877 uint32_t val;
1878 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
1879 val += rotl(lo + 0x49434878, hi & 0x1F);
1880 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
1881 return ~val;
1882 }
1883
1884 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
1885 {
1886 uint32_t buf[8];
1887 uint32_t obuf[8];
1888 dma_addr_t paddr = xhci_mask64(addr);
1889
1890 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
1891
1892 memcpy(obuf, buf, sizeof(obuf));
1893
1894 if ((buf[0] & 0xff) == 2) {
1895 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
1896 obuf[0] |= (buf[2] * buf[3]) & 0xff;
1897 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
1898 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
1899 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
1900 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
1901 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
1902 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
1903 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
1904 }
1905
1906 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
1907 }
1908
1909 static void xhci_process_commands(XHCIState *xhci)
1910 {
1911 XHCITRB trb;
1912 TRBType type;
1913 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
1914 dma_addr_t addr;
1915 unsigned int i, slotid = 0;
1916
1917 DPRINTF("xhci_process_commands()\n");
1918 if (!xhci_running(xhci)) {
1919 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
1920 return;
1921 }
1922
1923 xhci->crcr_low |= CRCR_CRR;
1924
1925 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
1926 event.ptr = addr;
1927 switch (type) {
1928 case CR_ENABLE_SLOT:
1929 for (i = 0; i < MAXSLOTS; i++) {
1930 if (!xhci->slots[i].enabled) {
1931 break;
1932 }
1933 }
1934 if (i >= MAXSLOTS) {
1935 fprintf(stderr, "xhci: no device slots available\n");
1936 event.ccode = CC_NO_SLOTS_ERROR;
1937 } else {
1938 slotid = i+1;
1939 event.ccode = xhci_enable_slot(xhci, slotid);
1940 }
1941 break;
1942 case CR_DISABLE_SLOT:
1943 slotid = xhci_get_slot(xhci, &event, &trb);
1944 if (slotid) {
1945 event.ccode = xhci_disable_slot(xhci, slotid);
1946 }
1947 break;
1948 case CR_ADDRESS_DEVICE:
1949 slotid = xhci_get_slot(xhci, &event, &trb);
1950 if (slotid) {
1951 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
1952 trb.control & TRB_CR_BSR);
1953 }
1954 break;
1955 case CR_CONFIGURE_ENDPOINT:
1956 slotid = xhci_get_slot(xhci, &event, &trb);
1957 if (slotid) {
1958 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
1959 trb.control & TRB_CR_DC);
1960 }
1961 break;
1962 case CR_EVALUATE_CONTEXT:
1963 slotid = xhci_get_slot(xhci, &event, &trb);
1964 if (slotid) {
1965 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
1966 }
1967 break;
1968 case CR_STOP_ENDPOINT:
1969 slotid = xhci_get_slot(xhci, &event, &trb);
1970 if (slotid) {
1971 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
1972 & TRB_CR_EPID_MASK;
1973 event.ccode = xhci_stop_ep(xhci, slotid, epid);
1974 }
1975 break;
1976 case CR_RESET_ENDPOINT:
1977 slotid = xhci_get_slot(xhci, &event, &trb);
1978 if (slotid) {
1979 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
1980 & TRB_CR_EPID_MASK;
1981 event.ccode = xhci_reset_ep(xhci, slotid, epid);
1982 }
1983 break;
1984 case CR_SET_TR_DEQUEUE:
1985 slotid = xhci_get_slot(xhci, &event, &trb);
1986 if (slotid) {
1987 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
1988 & TRB_CR_EPID_MASK;
1989 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
1990 trb.parameter);
1991 }
1992 break;
1993 case CR_RESET_DEVICE:
1994 slotid = xhci_get_slot(xhci, &event, &trb);
1995 if (slotid) {
1996 event.ccode = xhci_reset_slot(xhci, slotid);
1997 }
1998 break;
1999 case CR_GET_PORT_BANDWIDTH:
2000 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2001 break;
2002 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2003 xhci_via_challenge(xhci, trb.parameter);
2004 break;
2005 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2006 event.type = 48; /* NEC reply */
2007 event.length = 0x3025;
2008 break;
2009 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2010 {
2011 uint32_t chi = trb.parameter >> 32;
2012 uint32_t clo = trb.parameter;
2013 uint32_t val = xhci_nec_challenge(chi, clo);
2014 event.length = val & 0xFFFF;
2015 event.epid = val >> 16;
2016 slotid = val >> 24;
2017 event.type = 48; /* NEC reply */
2018 }
2019 break;
2020 default:
2021 fprintf(stderr, "xhci: unimplemented command %d\n", type);
2022 event.ccode = CC_TRB_ERROR;
2023 break;
2024 }
2025 event.slotid = slotid;
2026 xhci_event(xhci, &event);
2027 }
2028 }
2029
2030 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2031 {
2032 int nr = port->port.index + 1;
2033
2034 port->portsc = PORTSC_PP;
2035 if (port->port.dev && port->port.dev->attached && !is_detach) {
2036 port->portsc |= PORTSC_CCS;
2037 switch (port->port.dev->speed) {
2038 case USB_SPEED_LOW:
2039 port->portsc |= PORTSC_SPEED_LOW;
2040 break;
2041 case USB_SPEED_FULL:
2042 port->portsc |= PORTSC_SPEED_FULL;
2043 break;
2044 case USB_SPEED_HIGH:
2045 port->portsc |= PORTSC_SPEED_HIGH;
2046 break;
2047 }
2048 }
2049
2050 if (xhci_running(xhci)) {
2051 port->portsc |= PORTSC_CSC;
2052 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2053 xhci_event(xhci, &ev);
2054 DPRINTF("xhci: port change event for port %d\n", nr);
2055 }
2056 }
2057
2058 static void xhci_reset(DeviceState *dev)
2059 {
2060 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
2061 int i;
2062
2063 trace_usb_xhci_reset();
2064 if (!(xhci->usbsts & USBSTS_HCH)) {
2065 fprintf(stderr, "xhci: reset while running!\n");
2066 }
2067
2068 xhci->usbcmd = 0;
2069 xhci->usbsts = USBSTS_HCH;
2070 xhci->dnctrl = 0;
2071 xhci->crcr_low = 0;
2072 xhci->crcr_high = 0;
2073 xhci->dcbaap_low = 0;
2074 xhci->dcbaap_high = 0;
2075 xhci->config = 0;
2076 xhci->devaddr = 2;
2077
2078 for (i = 0; i < MAXSLOTS; i++) {
2079 xhci_disable_slot(xhci, i+1);
2080 }
2081
2082 for (i = 0; i < MAXPORTS; i++) {
2083 xhci_update_port(xhci, xhci->ports + i, 0);
2084 }
2085
2086 xhci->iman = 0;
2087 xhci->imod = 0;
2088 xhci->erstsz = 0;
2089 xhci->erstba_low = 0;
2090 xhci->erstba_high = 0;
2091 xhci->erdp_low = 0;
2092 xhci->erdp_high = 0;
2093
2094 xhci->er_ep_idx = 0;
2095 xhci->er_pcs = 1;
2096 xhci->er_full = 0;
2097 xhci->ev_buffer_put = 0;
2098 xhci->ev_buffer_get = 0;
2099
2100 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
2101 xhci_mfwrap_update(xhci);
2102 }
2103
2104 static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2105 {
2106 uint32_t ret;
2107
2108 switch (reg) {
2109 case 0x00: /* HCIVERSION, CAPLENGTH */
2110 ret = 0x01000000 | LEN_CAP;
2111 break;
2112 case 0x04: /* HCSPARAMS 1 */
2113 ret = (MAXPORTS<<24) | (MAXINTRS<<8) | MAXSLOTS;
2114 break;
2115 case 0x08: /* HCSPARAMS 2 */
2116 ret = 0x0000000f;
2117 break;
2118 case 0x0c: /* HCSPARAMS 3 */
2119 ret = 0x00000000;
2120 break;
2121 case 0x10: /* HCCPARAMS */
2122 if (sizeof(dma_addr_t) == 4) {
2123 ret = 0x00081000;
2124 } else {
2125 ret = 0x00081001;
2126 }
2127 break;
2128 case 0x14: /* DBOFF */
2129 ret = OFF_DOORBELL;
2130 break;
2131 case 0x18: /* RTSOFF */
2132 ret = OFF_RUNTIME;
2133 break;
2134
2135 /* extended capabilities */
2136 case 0x20: /* Supported Protocol:00 */
2137 ret = 0x02000402; /* USB 2.0 */
2138 break;
2139 case 0x24: /* Supported Protocol:04 */
2140 ret = 0x20425455; /* "USB " */
2141 break;
2142 case 0x28: /* Supported Protocol:08 */
2143 ret = 0x00000001 | (USB2_PORTS<<8);
2144 break;
2145 case 0x2c: /* Supported Protocol:0c */
2146 ret = 0x00000000; /* reserved */
2147 break;
2148 case 0x30: /* Supported Protocol:00 */
2149 ret = 0x03000002; /* USB 3.0 */
2150 break;
2151 case 0x34: /* Supported Protocol:04 */
2152 ret = 0x20425455; /* "USB " */
2153 break;
2154 case 0x38: /* Supported Protocol:08 */
2155 ret = 0x00000000 | (USB2_PORTS+1) | (USB3_PORTS<<8);
2156 break;
2157 case 0x3c: /* Supported Protocol:0c */
2158 ret = 0x00000000; /* reserved */
2159 break;
2160 default:
2161 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2162 ret = 0;
2163 }
2164
2165 trace_usb_xhci_cap_read(reg, ret);
2166 return ret;
2167 }
2168
2169 static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2170 {
2171 uint32_t port = reg >> 4;
2172 uint32_t ret;
2173
2174 if (port >= MAXPORTS) {
2175 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2176 ret = 0;
2177 goto out;
2178 }
2179
2180 switch (reg & 0xf) {
2181 case 0x00: /* PORTSC */
2182 ret = xhci->ports[port].portsc;
2183 break;
2184 case 0x04: /* PORTPMSC */
2185 case 0x08: /* PORTLI */
2186 ret = 0;
2187 break;
2188 case 0x0c: /* reserved */
2189 default:
2190 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2191 port, reg);
2192 ret = 0;
2193 }
2194
2195 out:
2196 trace_usb_xhci_port_read(port, reg & 0x0f, ret);
2197 return ret;
2198 }
2199
2200 static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2201 {
2202 uint32_t port = reg >> 4;
2203 uint32_t portsc;
2204
2205 trace_usb_xhci_port_write(port, reg & 0x0f, val);
2206
2207 if (port >= MAXPORTS) {
2208 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2209 return;
2210 }
2211
2212 switch (reg & 0xf) {
2213 case 0x00: /* PORTSC */
2214 portsc = xhci->ports[port].portsc;
2215 /* write-1-to-clear bits*/
2216 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2217 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2218 if (val & PORTSC_LWS) {
2219 /* overwrite PLS only when LWS=1 */
2220 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2221 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2222 }
2223 /* read/write bits */
2224 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2225 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2226 /* write-1-to-start bits */
2227 if (val & PORTSC_PR) {
2228 DPRINTF("xhci: port %d reset\n", port);
2229 usb_device_reset(xhci->ports[port].port.dev);
2230 portsc |= PORTSC_PRC | PORTSC_PED;
2231 }
2232 xhci->ports[port].portsc = portsc;
2233 break;
2234 case 0x04: /* PORTPMSC */
2235 case 0x08: /* PORTLI */
2236 default:
2237 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2238 port, reg);
2239 }
2240 }
2241
2242 static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2243 {
2244 uint32_t ret;
2245
2246 if (reg >= 0x400) {
2247 return xhci_port_read(xhci, reg - 0x400);
2248 }
2249
2250 switch (reg) {
2251 case 0x00: /* USBCMD */
2252 ret = xhci->usbcmd;
2253 break;
2254 case 0x04: /* USBSTS */
2255 ret = xhci->usbsts;
2256 break;
2257 case 0x08: /* PAGESIZE */
2258 ret = 1; /* 4KiB */
2259 break;
2260 case 0x14: /* DNCTRL */
2261 ret = xhci->dnctrl;
2262 break;
2263 case 0x18: /* CRCR low */
2264 ret = xhci->crcr_low & ~0xe;
2265 break;
2266 case 0x1c: /* CRCR high */
2267 ret = xhci->crcr_high;
2268 break;
2269 case 0x30: /* DCBAAP low */
2270 ret = xhci->dcbaap_low;
2271 break;
2272 case 0x34: /* DCBAAP high */
2273 ret = xhci->dcbaap_high;
2274 break;
2275 case 0x38: /* CONFIG */
2276 ret = xhci->config;
2277 break;
2278 default:
2279 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2280 ret = 0;
2281 }
2282
2283 trace_usb_xhci_oper_read(reg, ret);
2284 return ret;
2285 }
2286
2287 static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2288 {
2289 if (reg >= 0x400) {
2290 xhci_port_write(xhci, reg - 0x400, val);
2291 return;
2292 }
2293
2294 trace_usb_xhci_oper_write(reg, val);
2295
2296 switch (reg) {
2297 case 0x00: /* USBCMD */
2298 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2299 xhci_run(xhci);
2300 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2301 xhci_stop(xhci);
2302 }
2303 xhci->usbcmd = val & 0xc0f;
2304 xhci_mfwrap_update(xhci);
2305 if (val & USBCMD_HCRST) {
2306 xhci_reset(&xhci->pci_dev.qdev);
2307 }
2308 xhci_irq_update(xhci);
2309 break;
2310
2311 case 0x04: /* USBSTS */
2312 /* these bits are write-1-to-clear */
2313 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2314 xhci_irq_update(xhci);
2315 break;
2316
2317 case 0x14: /* DNCTRL */
2318 xhci->dnctrl = val & 0xffff;
2319 break;
2320 case 0x18: /* CRCR low */
2321 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2322 break;
2323 case 0x1c: /* CRCR high */
2324 xhci->crcr_high = val;
2325 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2326 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2327 xhci->crcr_low &= ~CRCR_CRR;
2328 xhci_event(xhci, &event);
2329 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2330 } else {
2331 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2332 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2333 }
2334 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2335 break;
2336 case 0x30: /* DCBAAP low */
2337 xhci->dcbaap_low = val & 0xffffffc0;
2338 break;
2339 case 0x34: /* DCBAAP high */
2340 xhci->dcbaap_high = val;
2341 break;
2342 case 0x38: /* CONFIG */
2343 xhci->config = val & 0xff;
2344 break;
2345 default:
2346 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2347 }
2348 }
2349
2350 static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2351 {
2352 uint32_t ret;
2353
2354 switch (reg) {
2355 case 0x00: /* MFINDEX */
2356 ret = xhci_mfindex_get(xhci) & 0x3fff;
2357 break;
2358 case 0x20: /* IMAN */
2359 ret = xhci->iman;
2360 break;
2361 case 0x24: /* IMOD */
2362 ret = xhci->imod;
2363 break;
2364 case 0x28: /* ERSTSZ */
2365 ret = xhci->erstsz;
2366 break;
2367 case 0x30: /* ERSTBA low */
2368 ret = xhci->erstba_low;
2369 break;
2370 case 0x34: /* ERSTBA high */
2371 ret = xhci->erstba_high;
2372 break;
2373 case 0x38: /* ERDP low */
2374 ret = xhci->erdp_low;
2375 break;
2376 case 0x3c: /* ERDP high */
2377 ret = xhci->erdp_high;
2378 break;
2379 default:
2380 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2381 ret = 0;
2382 }
2383
2384 trace_usb_xhci_runtime_read(reg, ret);
2385 return ret;
2386 }
2387
2388 static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2389 {
2390 trace_usb_xhci_runtime_read(reg, val);
2391
2392 switch (reg) {
2393 case 0x20: /* IMAN */
2394 if (val & IMAN_IP) {
2395 xhci->iman &= ~IMAN_IP;
2396 }
2397 xhci->iman &= ~IMAN_IE;
2398 xhci->iman |= val & IMAN_IE;
2399 xhci_irq_update(xhci);
2400 break;
2401 case 0x24: /* IMOD */
2402 xhci->imod = val;
2403 break;
2404 case 0x28: /* ERSTSZ */
2405 xhci->erstsz = val & 0xffff;
2406 break;
2407 case 0x30: /* ERSTBA low */
2408 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2409 xhci->erstba_low = val & 0xffffffc0; */
2410 xhci->erstba_low = val & 0xfffffff0;
2411 break;
2412 case 0x34: /* ERSTBA high */
2413 xhci->erstba_high = val;
2414 xhci_er_reset(xhci);
2415 break;
2416 case 0x38: /* ERDP low */
2417 if (val & ERDP_EHB) {
2418 xhci->erdp_low &= ~ERDP_EHB;
2419 }
2420 xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB);
2421 break;
2422 case 0x3c: /* ERDP high */
2423 xhci->erdp_high = val;
2424 xhci_events_update(xhci);
2425 break;
2426 default:
2427 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2428 }
2429 }
2430
2431 static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2432 {
2433 /* doorbells always read as 0 */
2434 trace_usb_xhci_doorbell_read(reg, 0);
2435 return 0;
2436 }
2437
2438 static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2439 {
2440 trace_usb_xhci_doorbell_write(reg, val);
2441
2442 if (!xhci_running(xhci)) {
2443 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2444 return;
2445 }
2446
2447 reg >>= 2;
2448
2449 if (reg == 0) {
2450 if (val == 0) {
2451 xhci_process_commands(xhci);
2452 } else {
2453 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2454 }
2455 } else {
2456 if (reg > MAXSLOTS) {
2457 fprintf(stderr, "xhci: bad doorbell %d\n", reg);
2458 } else if (val > 31) {
2459 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2460 } else {
2461 xhci_kick_ep(xhci, reg, val);
2462 }
2463 }
2464 }
2465
2466 static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2467 unsigned size)
2468 {
2469 XHCIState *xhci = ptr;
2470
2471 /* Only aligned reads are allowed on xHCI */
2472 if (addr & 3) {
2473 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
2474 return 0;
2475 }
2476
2477 if (addr < LEN_CAP) {
2478 return xhci_cap_read(xhci, addr);
2479 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2480 return xhci_oper_read(xhci, addr - OFF_OPER);
2481 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2482 return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
2483 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2484 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
2485 } else {
2486 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2487 return 0;
2488 }
2489 }
2490
2491 static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2492 uint64_t val, unsigned size)
2493 {
2494 XHCIState *xhci = ptr;
2495
2496 /* Only aligned writes are allowed on xHCI */
2497 if (addr & 3) {
2498 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
2499 return;
2500 }
2501
2502 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2503 xhci_oper_write(xhci, addr - OFF_OPER, val);
2504 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2505 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
2506 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2507 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
2508 } else {
2509 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2510 }
2511 }
2512
2513 static const MemoryRegionOps xhci_mem_ops = {
2514 .read = xhci_mem_read,
2515 .write = xhci_mem_write,
2516 .valid.min_access_size = 4,
2517 .valid.max_access_size = 4,
2518 .endianness = DEVICE_LITTLE_ENDIAN,
2519 };
2520
2521 static void xhci_attach(USBPort *usbport)
2522 {
2523 XHCIState *xhci = usbport->opaque;
2524 XHCIPort *port = &xhci->ports[usbport->index];
2525
2526 xhci_update_port(xhci, port, 0);
2527 }
2528
2529 static void xhci_detach(USBPort *usbport)
2530 {
2531 XHCIState *xhci = usbport->opaque;
2532 XHCIPort *port = &xhci->ports[usbport->index];
2533
2534 xhci_update_port(xhci, port, 1);
2535 }
2536
2537 static void xhci_wakeup(USBPort *usbport)
2538 {
2539 XHCIState *xhci = usbport->opaque;
2540 XHCIPort *port = &xhci->ports[usbport->index];
2541 int nr = port->port.index + 1;
2542 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2543 uint32_t pls;
2544
2545 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK;
2546 if (pls != 3) {
2547 return;
2548 }
2549 port->portsc |= 0xf << PORTSC_PLS_SHIFT;
2550 if (port->portsc & PORTSC_PLC) {
2551 return;
2552 }
2553 port->portsc |= PORTSC_PLC;
2554 xhci_event(xhci, &ev);
2555 }
2556
2557 static void xhci_complete(USBPort *port, USBPacket *packet)
2558 {
2559 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
2560
2561 xhci_complete_packet(xfer, packet->result);
2562 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2563 }
2564
2565 static void xhci_child_detach(USBPort *port, USBDevice *child)
2566 {
2567 FIXME();
2568 }
2569
2570 static USBPortOps xhci_port_ops = {
2571 .attach = xhci_attach,
2572 .detach = xhci_detach,
2573 .wakeup = xhci_wakeup,
2574 .complete = xhci_complete,
2575 .child_detach = xhci_child_detach,
2576 };
2577
2578 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev)
2579 {
2580 XHCISlot *slot;
2581 int slotid;
2582
2583 for (slotid = 1; slotid <= MAXSLOTS; slotid++) {
2584 slot = &xhci->slots[slotid-1];
2585 if (slot->devaddr == dev->addr) {
2586 return slotid;
2587 }
2588 }
2589 return 0;
2590 }
2591
2592 static int xhci_find_epid(USBEndpoint *ep)
2593 {
2594 if (ep->nr == 0) {
2595 return 1;
2596 }
2597 if (ep->pid == USB_TOKEN_IN) {
2598 return ep->nr * 2 + 1;
2599 } else {
2600 return ep->nr * 2;
2601 }
2602 }
2603
2604 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep)
2605 {
2606 XHCIState *xhci = container_of(bus, XHCIState, bus);
2607 int slotid;
2608
2609 DPRINTF("%s\n", __func__);
2610 slotid = xhci_find_slotid(xhci, ep->dev);
2611 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
2612 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
2613 return;
2614 }
2615 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep));
2616 }
2617
2618 static USBBusOps xhci_bus_ops = {
2619 .wakeup_endpoint = xhci_wakeup_endpoint,
2620 };
2621
2622 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2623 {
2624 int i;
2625
2626 xhci->usbsts = USBSTS_HCH;
2627
2628 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2629
2630 for (i = 0; i < MAXPORTS; i++) {
2631 memset(&xhci->ports[i], 0, sizeof(xhci->ports[i]));
2632 usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i,
2633 &xhci_port_ops,
2634 USB_SPEED_MASK_LOW |
2635 USB_SPEED_MASK_FULL |
2636 USB_SPEED_MASK_HIGH);
2637 }
2638 for (i = 0; i < MAXSLOTS; i++) {
2639 xhci->slots[i].enabled = 0;
2640 }
2641 }
2642
2643 static int usb_xhci_initfn(struct PCIDevice *dev)
2644 {
2645 int ret;
2646
2647 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2648
2649 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
2650 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
2651 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
2652 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2653
2654 usb_xhci_init(xhci, &dev->qdev);
2655
2656 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
2657
2658 xhci->irq = xhci->pci_dev.irq[0];
2659
2660 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2661 "xhci", LEN_REGS);
2662 pci_register_bar(&xhci->pci_dev, 0,
2663 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
2664 &xhci->mem);
2665
2666 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0);
2667 assert(ret >= 0);
2668
2669 if (xhci->msi) {
2670 ret = msi_init(&xhci->pci_dev, 0x70, 1, true, false);
2671 assert(ret >= 0);
2672 }
2673
2674 return 0;
2675 }
2676
2677 static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
2678 int len)
2679 {
2680 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2681
2682 pci_default_write_config(dev, addr, val, len);
2683 if (xhci->msi) {
2684 msi_write_config(dev, addr, val, len);
2685 }
2686 }
2687
2688 static const VMStateDescription vmstate_xhci = {
2689 .name = "xhci",
2690 .unmigratable = 1,
2691 };
2692
2693 static Property xhci_properties[] = {
2694 DEFINE_PROP_UINT32("msi", XHCIState, msi, 0),
2695 DEFINE_PROP_END_OF_LIST(),
2696 };
2697
2698 static void xhci_class_init(ObjectClass *klass, void *data)
2699 {
2700 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2701 DeviceClass *dc = DEVICE_CLASS(klass);
2702
2703 dc->vmsd = &vmstate_xhci;
2704 dc->props = xhci_properties;
2705 dc->reset = xhci_reset;
2706 k->init = usb_xhci_initfn;
2707 k->vendor_id = PCI_VENDOR_ID_NEC;
2708 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
2709 k->class_id = PCI_CLASS_SERIAL_USB;
2710 k->revision = 0x03;
2711 k->is_express = 1;
2712 k->config_write = xhci_write_config;
2713 }
2714
2715 static TypeInfo xhci_info = {
2716 .name = "nec-usb-xhci",
2717 .parent = TYPE_PCI_DEVICE,
2718 .instance_size = sizeof(XHCIState),
2719 .class_init = xhci_class_init,
2720 };
2721
2722 static void xhci_register_types(void)
2723 {
2724 type_register_static(&xhci_info);
2725 }
2726
2727 type_init(xhci_register_types)
Qemu copy for testing