2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu-timer.h"
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
35 #define DPRINTF(...) do {} while (0)
37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
38 __func__, __LINE__); abort(); } while (0)
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
138 #define ERDP_EHB (1<<3)
141 typedef struct XHCITRB
{
160 PLS_COMPILANCE_MODE
= 10,
165 typedef enum TRBType
{
178 CR_CONFIGURE_ENDPOINT
,
186 CR_SET_LATENCY_TOLERANCE
,
187 CR_GET_PORT_BANDWIDTH
,
192 ER_PORT_STATUS_CHANGE
,
193 ER_BANDWIDTH_REQUEST
,
196 ER_DEVICE_NOTIFICATION
,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
204 #define CR_LINK TR_LINK
206 typedef enum TRBCCode
{
209 CC_DATA_BUFFER_ERROR
,
211 CC_USB_TRANSACTION_ERROR
,
217 CC_INVALID_STREAM_TYPE_ERROR
,
218 CC_SLOT_NOT_ENABLED_ERROR
,
219 CC_EP_NOT_ENABLED_ERROR
,
225 CC_BANDWIDTH_OVERRUN
,
226 CC_CONTEXT_STATE_ERROR
,
227 CC_NO_PING_RESPONSE_ERROR
,
228 CC_EVENT_RING_FULL_ERROR
,
229 CC_INCOMPATIBLE_DEVICE_ERROR
,
230 CC_MISSED_SERVICE_ERROR
,
231 CC_COMMAND_RING_STOPPED
,
234 CC_STOPPED_LENGTH_INVALID
,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
236 CC_ISOCH_BUFFER_OVERRUN
= 31,
239 CC_INVALID_STREAM_ID_ERROR
,
240 CC_SECONDARY_BANDWIDTH_ERROR
,
241 CC_SPLIT_TRANSACTION_ERROR
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
249 #define TRB_EV_ED (1<<2)
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
266 #define TRB_TR_DIR (1<<16)
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
276 #define TRB_LK_TC (1<<1)
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
303 typedef struct XHCIState XHCIState
;
305 #define get_field(data, field) \
306 (((data) >> field##_SHIFT) & field##_MASK)
308 #define set_field(data, newval, field) do { \
309 uint32_t val = *data; \
310 val &= ~(field##_MASK << field##_SHIFT); \
311 val |= ((newval) & field##_MASK) << field##_SHIFT; \
315 typedef enum EPType
{
326 typedef struct XHCIRing
{
332 typedef struct XHCIPort
{
342 typedef struct XHCITransfer
{
351 unsigned int iso_pkts
;
357 unsigned int trb_count
;
358 unsigned int trb_alloced
;
364 unsigned int pktsize
;
365 unsigned int cur_pkt
;
367 uint64_t mfindex_kick
;
370 typedef struct XHCIEPContext
{
376 unsigned int next_xfer
;
377 unsigned int comp_xfer
;
378 XHCITransfer transfers
[TD_QUEUE
];
382 unsigned int max_psize
;
385 /* iso xfer scheduling */
386 unsigned int interval
;
387 int64_t mfindex_last
;
388 QEMUTimer
*kick_timer
;
391 typedef struct XHCISlot
{
395 unsigned int devaddr
;
396 XHCIEPContext
* eps
[31];
399 typedef struct XHCIEvent
{
409 typedef struct XHCIInterrupter
{
414 uint32_t erstba_high
;
418 bool msix_used
, er_pcs
, er_full
;
422 unsigned int er_ep_idx
;
424 XHCIEvent ev_buffer
[EV_QUEUE
];
425 unsigned int ev_buffer_put
;
426 unsigned int ev_buffer_get
;
435 MemoryRegion mem_cap
;
436 MemoryRegion mem_oper
;
437 MemoryRegion mem_runtime
;
438 MemoryRegion mem_doorbell
;
440 unsigned int devaddr
;
449 /* Operational Registers */
456 uint32_t dcbaap_high
;
459 USBPort uports
[MAX(MAXPORTS_2
, MAXPORTS_3
)];
460 XHCIPort ports
[MAXPORTS
];
461 XHCISlot slots
[MAXSLOTS
];
464 /* Runtime Registers */
465 int64_t mfindex_start
;
466 QEMUTimer
*mfwrap_timer
;
467 XHCIInterrupter intr
[MAXINTRS
];
472 typedef struct XHCIEvRingSeg
{
480 XHCI_FLAG_USE_MSI
= 1,
484 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
486 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
488 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
489 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
491 static const char *TRBType_names
[] = {
492 [TRB_RESERVED
] = "TRB_RESERVED",
493 [TR_NORMAL
] = "TR_NORMAL",
494 [TR_SETUP
] = "TR_SETUP",
495 [TR_DATA
] = "TR_DATA",
496 [TR_STATUS
] = "TR_STATUS",
497 [TR_ISOCH
] = "TR_ISOCH",
498 [TR_LINK
] = "TR_LINK",
499 [TR_EVDATA
] = "TR_EVDATA",
500 [TR_NOOP
] = "TR_NOOP",
501 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
502 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
503 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
504 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
505 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
506 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
507 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
508 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
509 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
510 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
511 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
512 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
513 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
514 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
515 [CR_NOOP
] = "CR_NOOP",
516 [ER_TRANSFER
] = "ER_TRANSFER",
517 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
518 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
519 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
520 [ER_DOORBELL
] = "ER_DOORBELL",
521 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
522 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
523 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
524 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
525 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
526 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
529 static const char *TRBCCode_names
[] = {
530 [CC_INVALID
] = "CC_INVALID",
531 [CC_SUCCESS
] = "CC_SUCCESS",
532 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
533 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
534 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
535 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
536 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
537 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
538 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
539 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
540 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
541 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
542 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
543 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
544 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
545 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
546 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
547 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
548 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
549 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
550 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
551 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
552 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
553 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
554 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
555 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
556 [CC_STOPPED
] = "CC_STOPPED",
557 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
558 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
559 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
560 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
561 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
562 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
563 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
564 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
565 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
568 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
570 if (index
>= llen
|| list
[index
] == NULL
) {
576 static const char *trb_name(XHCITRB
*trb
)
578 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
579 ARRAY_SIZE(TRBType_names
));
582 static const char *event_name(XHCIEvent
*event
)
584 return lookup_name(event
->ccode
, TRBCCode_names
,
585 ARRAY_SIZE(TRBCCode_names
));
588 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
590 int64_t now
= qemu_get_clock_ns(vm_clock
);
591 return (now
- xhci
->mfindex_start
) / 125000;
594 static void xhci_mfwrap_update(XHCIState
*xhci
)
596 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
597 uint32_t mfindex
, left
;
600 if ((xhci
->usbcmd
& bits
) == bits
) {
601 now
= qemu_get_clock_ns(vm_clock
);
602 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
603 left
= 0x4000 - mfindex
;
604 qemu_mod_timer(xhci
->mfwrap_timer
, now
+ left
* 125000);
606 qemu_del_timer(xhci
->mfwrap_timer
);
610 static void xhci_mfwrap_timer(void *opaque
)
612 XHCIState
*xhci
= opaque
;
613 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
615 xhci_event(xhci
, &wrap
, 0);
616 xhci_mfwrap_update(xhci
);
619 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
621 if (sizeof(dma_addr_t
) == 4) {
624 return low
| (((dma_addr_t
)high
<< 16) << 16);
628 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
630 if (sizeof(dma_addr_t
) == 4) {
631 return addr
& 0xffffffff;
637 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
644 switch (uport
->dev
->speed
) {
648 index
= uport
->index
;
650 case USB_SPEED_SUPER
:
651 index
= uport
->index
+ xhci
->numports_2
;
656 return &xhci
->ports
[index
];
659 static void xhci_intx_update(XHCIState
*xhci
)
663 if (msix_enabled(&xhci
->pci_dev
) ||
664 msi_enabled(&xhci
->pci_dev
)) {
668 if (xhci
->intr
[0].iman
& IMAN_IP
&&
669 xhci
->intr
[0].iman
& IMAN_IE
&&
670 xhci
->usbcmd
& USBCMD_INTE
) {
674 trace_usb_xhci_irq_intx(level
);
675 qemu_set_irq(xhci
->irq
, level
);
678 static void xhci_msix_update(XHCIState
*xhci
, int v
)
682 if (!msix_enabled(&xhci
->pci_dev
)) {
686 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
687 if (enabled
== xhci
->intr
[v
].msix_used
) {
692 trace_usb_xhci_irq_msix_use(v
);
693 msix_vector_use(&xhci
->pci_dev
, v
);
694 xhci
->intr
[v
].msix_used
= true;
696 trace_usb_xhci_irq_msix_unuse(v
);
697 msix_vector_unuse(&xhci
->pci_dev
, v
);
698 xhci
->intr
[v
].msix_used
= false;
702 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
704 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
705 xhci
->intr
[v
].iman
|= IMAN_IP
;
706 xhci
->usbsts
|= USBSTS_EINT
;
708 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
712 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
716 if (msix_enabled(&xhci
->pci_dev
)) {
717 trace_usb_xhci_irq_msix(v
);
718 msix_notify(&xhci
->pci_dev
, v
);
722 if (msi_enabled(&xhci
->pci_dev
)) {
723 trace_usb_xhci_irq_msi(v
);
724 msi_notify(&xhci
->pci_dev
, v
);
729 trace_usb_xhci_irq_intx(1);
730 qemu_set_irq(xhci
->irq
, 1);
734 static inline int xhci_running(XHCIState
*xhci
)
736 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->intr
[0].er_full
;
739 static void xhci_die(XHCIState
*xhci
)
741 xhci
->usbsts
|= USBSTS_HCE
;
742 fprintf(stderr
, "xhci: asserted controller error\n");
745 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
747 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
751 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
752 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
753 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
754 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
756 ev_trb
.control
|= TRB_C
;
758 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
760 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
761 event_name(event
), ev_trb
.parameter
,
762 ev_trb
.status
, ev_trb
.control
);
764 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
765 pci_dma_write(&xhci
->pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
768 if (intr
->er_ep_idx
>= intr
->er_size
) {
770 intr
->er_pcs
= !intr
->er_pcs
;
774 static void xhci_events_update(XHCIState
*xhci
, int v
)
776 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
781 if (xhci
->usbsts
& USBSTS_HCH
) {
785 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
786 if (erdp
< intr
->er_start
||
787 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
788 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
789 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
790 v
, intr
->er_start
, intr
->er_size
);
794 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
795 assert(dp_idx
< intr
->er_size
);
797 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
798 * deadlocks when the ER is full. Hack it by holding off events until
799 * the driver decides to free at least half of the ring */
801 int er_free
= dp_idx
- intr
->er_ep_idx
;
803 er_free
+= intr
->er_size
;
805 if (er_free
< (intr
->er_size
/2)) {
806 DPRINTF("xhci_events_update(): event ring still "
807 "more than half full (hack)\n");
812 while (intr
->ev_buffer_put
!= intr
->ev_buffer_get
) {
813 assert(intr
->er_full
);
814 if (((intr
->er_ep_idx
+1) % intr
->er_size
) == dp_idx
) {
815 DPRINTF("xhci_events_update(): event ring full again\n");
817 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
818 xhci_write_event(xhci
, &full
, v
);
823 XHCIEvent
*event
= &intr
->ev_buffer
[intr
->ev_buffer_get
];
824 xhci_write_event(xhci
, event
, v
);
825 intr
->ev_buffer_get
++;
827 if (intr
->ev_buffer_get
== EV_QUEUE
) {
828 intr
->ev_buffer_get
= 0;
833 xhci_intr_raise(xhci
, v
);
836 if (intr
->er_full
&& intr
->ev_buffer_put
== intr
->ev_buffer_get
) {
837 DPRINTF("xhci_events_update(): event ring no longer full\n");
842 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
844 XHCIInterrupter
*intr
;
848 if (v
>= xhci
->numintrs
) {
849 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
852 intr
= &xhci
->intr
[v
];
855 DPRINTF("xhci_event(): ER full, queueing\n");
856 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
857 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
860 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
861 if (intr
->ev_buffer_put
== EV_QUEUE
) {
862 intr
->ev_buffer_put
= 0;
867 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
868 if (erdp
< intr
->er_start
||
869 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
870 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
871 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
872 v
, intr
->er_start
, intr
->er_size
);
877 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
878 assert(dp_idx
< intr
->er_size
);
880 if ((intr
->er_ep_idx
+1) % intr
->er_size
== dp_idx
) {
881 DPRINTF("xhci_event(): ER full, queueing\n");
883 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
884 xhci_write_event(xhci
, &full
);
887 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
888 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
891 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
892 if (intr
->ev_buffer_put
== EV_QUEUE
) {
893 intr
->ev_buffer_put
= 0;
896 xhci_write_event(xhci
, event
, v
);
899 xhci_intr_raise(xhci
, v
);
902 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
906 ring
->dequeue
= base
;
910 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
915 pci_dma_read(&xhci
->pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
916 trb
->addr
= ring
->dequeue
;
917 trb
->ccs
= ring
->ccs
;
918 le64_to_cpus(&trb
->parameter
);
919 le32_to_cpus(&trb
->status
);
920 le32_to_cpus(&trb
->control
);
922 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
923 trb
->parameter
, trb
->status
, trb
->control
);
925 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
929 type
= TRB_TYPE(*trb
);
931 if (type
!= TR_LINK
) {
933 *addr
= ring
->dequeue
;
935 ring
->dequeue
+= TRB_SIZE
;
938 ring
->dequeue
= xhci_mask64(trb
->parameter
);
939 if (trb
->control
& TRB_LK_TC
) {
940 ring
->ccs
= !ring
->ccs
;
946 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
950 dma_addr_t dequeue
= ring
->dequeue
;
951 bool ccs
= ring
->ccs
;
952 /* hack to bundle together the two/three TDs that make a setup transfer */
953 bool control_td_set
= 0;
957 pci_dma_read(&xhci
->pci_dev
, dequeue
, &trb
, TRB_SIZE
);
958 le64_to_cpus(&trb
.parameter
);
959 le32_to_cpus(&trb
.status
);
960 le32_to_cpus(&trb
.control
);
962 if ((trb
.control
& TRB_C
) != ccs
) {
966 type
= TRB_TYPE(trb
);
968 if (type
== TR_LINK
) {
969 dequeue
= xhci_mask64(trb
.parameter
);
970 if (trb
.control
& TRB_LK_TC
) {
979 if (type
== TR_SETUP
) {
981 } else if (type
== TR_STATUS
) {
985 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
991 static void xhci_er_reset(XHCIState
*xhci
, int v
)
993 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
996 if (intr
->erstsz
== 0) {
1002 /* cache the (sole) event ring segment location */
1003 if (intr
->erstsz
!= 1) {
1004 fprintf(stderr
, "xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
1008 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
1009 pci_dma_read(&xhci
->pci_dev
, erstba
, &seg
, sizeof(seg
));
1010 le32_to_cpus(&seg
.addr_low
);
1011 le32_to_cpus(&seg
.addr_high
);
1012 le32_to_cpus(&seg
.size
);
1013 if (seg
.size
< 16 || seg
.size
> 4096) {
1014 fprintf(stderr
, "xhci: invalid value for segment size: %d\n", seg
.size
);
1018 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
1019 intr
->er_size
= seg
.size
;
1021 intr
->er_ep_idx
= 0;
1025 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
1026 v
, intr
->er_start
, intr
->er_size
);
1029 static void xhci_run(XHCIState
*xhci
)
1031 trace_usb_xhci_run();
1032 xhci
->usbsts
&= ~USBSTS_HCH
;
1033 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
1036 static void xhci_stop(XHCIState
*xhci
)
1038 trace_usb_xhci_stop();
1039 xhci
->usbsts
|= USBSTS_HCH
;
1040 xhci
->crcr_low
&= ~CRCR_CRR
;
1043 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1048 pci_dma_read(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
1049 ctx
[0] &= ~EP_STATE_MASK
;
1051 ctx
[2] = epctx
->ring
.dequeue
| epctx
->ring
.ccs
;
1052 ctx
[3] = (epctx
->ring
.dequeue
>> 16) >> 16;
1053 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1054 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1055 pci_dma_write(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
1056 epctx
->state
= state
;
1059 static void xhci_ep_kick_timer(void *opaque
)
1061 XHCIEPContext
*epctx
= opaque
;
1062 xhci_kick_ep(epctx
->xhci
, epctx
->slotid
, epctx
->epid
);
1065 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1066 unsigned int epid
, dma_addr_t pctx
,
1070 XHCIEPContext
*epctx
;
1074 trace_usb_xhci_ep_enable(slotid
, epid
);
1075 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1076 assert(epid
>= 1 && epid
<= 31);
1078 slot
= &xhci
->slots
[slotid
-1];
1079 if (slot
->eps
[epid
-1]) {
1080 xhci_disable_ep(xhci
, slotid
, epid
);
1083 epctx
= g_malloc(sizeof(XHCIEPContext
));
1084 memset(epctx
, 0, sizeof(XHCIEPContext
));
1086 epctx
->slotid
= slotid
;
1089 slot
->eps
[epid
-1] = epctx
;
1091 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1092 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
);
1093 epctx
->ring
.ccs
= ctx
[2] & 1;
1095 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1096 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid
/2, epid
%2, epctx
->type
);
1098 epctx
->max_psize
= ctx
[1]>>16;
1099 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1100 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1101 epid
/2, epid
%2, epctx
->max_psize
);
1102 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
1103 usb_packet_init(&epctx
->transfers
[i
].packet
);
1106 epctx
->interval
= 1 << (ctx
[0] >> 16) & 0xff;
1107 epctx
->mfindex_last
= 0;
1108 epctx
->kick_timer
= qemu_new_timer_ns(vm_clock
, xhci_ep_kick_timer
, epctx
);
1110 epctx
->state
= EP_RUNNING
;
1111 ctx
[0] &= ~EP_STATE_MASK
;
1112 ctx
[0] |= EP_RUNNING
;
1117 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
)
1121 if (t
->running_async
) {
1122 usb_cancel_packet(&t
->packet
);
1123 t
->running_async
= 0;
1125 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n");
1128 if (t
->running_retry
) {
1129 XHCIEPContext
*epctx
= t
->xhci
->slots
[t
->slotid
-1].eps
[t
->epid
-1];
1131 epctx
->retry
= NULL
;
1132 qemu_del_timer(epctx
->kick_timer
);
1134 t
->running_retry
= 0;
1141 t
->trb_count
= t
->trb_alloced
= 0;
1146 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1150 XHCIEPContext
*epctx
;
1151 int i
, xferi
, killed
= 0;
1152 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1153 assert(epid
>= 1 && epid
<= 31);
1155 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1157 slot
= &xhci
->slots
[slotid
-1];
1159 if (!slot
->eps
[epid
-1]) {
1163 epctx
= slot
->eps
[epid
-1];
1165 xferi
= epctx
->next_xfer
;
1166 for (i
= 0; i
< TD_QUEUE
; i
++) {
1167 killed
+= xhci_ep_nuke_one_xfer(&epctx
->transfers
[xferi
]);
1168 xferi
= (xferi
+ 1) % TD_QUEUE
;
1173 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1177 XHCIEPContext
*epctx
;
1179 trace_usb_xhci_ep_disable(slotid
, epid
);
1180 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1181 assert(epid
>= 1 && epid
<= 31);
1183 slot
= &xhci
->slots
[slotid
-1];
1185 if (!slot
->eps
[epid
-1]) {
1186 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1190 xhci_ep_nuke_xfers(xhci
, slotid
, epid
);
1192 epctx
= slot
->eps
[epid
-1];
1194 xhci_set_ep_state(xhci
, epctx
, EP_DISABLED
);
1196 qemu_free_timer(epctx
->kick_timer
);
1198 slot
->eps
[epid
-1] = NULL
;
1203 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1207 XHCIEPContext
*epctx
;
1209 trace_usb_xhci_ep_stop(slotid
, epid
);
1210 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1212 if (epid
< 1 || epid
> 31) {
1213 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1214 return CC_TRB_ERROR
;
1217 slot
= &xhci
->slots
[slotid
-1];
1219 if (!slot
->eps
[epid
-1]) {
1220 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1221 return CC_EP_NOT_ENABLED_ERROR
;
1224 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1225 fprintf(stderr
, "xhci: FIXME: endpoint stopped w/ xfers running, "
1226 "data might be lost\n");
1229 epctx
= slot
->eps
[epid
-1];
1231 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1236 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1240 XHCIEPContext
*epctx
;
1243 trace_usb_xhci_ep_reset(slotid
, epid
);
1244 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1246 if (epid
< 1 || epid
> 31) {
1247 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1248 return CC_TRB_ERROR
;
1251 slot
= &xhci
->slots
[slotid
-1];
1253 if (!slot
->eps
[epid
-1]) {
1254 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1255 return CC_EP_NOT_ENABLED_ERROR
;
1258 epctx
= slot
->eps
[epid
-1];
1260 if (epctx
->state
!= EP_HALTED
) {
1261 fprintf(stderr
, "xhci: reset EP while EP %d not halted (%d)\n",
1262 epid
, epctx
->state
);
1263 return CC_CONTEXT_STATE_ERROR
;
1266 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1267 fprintf(stderr
, "xhci: FIXME: endpoint reset w/ xfers running, "
1268 "data might be lost\n");
1271 uint8_t ep
= epid
>>1;
1277 dev
= xhci
->slots
[slotid
-1].uport
->dev
;
1279 return CC_USB_TRANSACTION_ERROR
;
1282 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1287 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1288 unsigned int epid
, uint64_t pdequeue
)
1291 XHCIEPContext
*epctx
;
1294 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1296 if (epid
< 1 || epid
> 31) {
1297 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1298 return CC_TRB_ERROR
;
1301 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, pdequeue
);
1302 dequeue
= xhci_mask64(pdequeue
);
1304 slot
= &xhci
->slots
[slotid
-1];
1306 if (!slot
->eps
[epid
-1]) {
1307 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1308 return CC_EP_NOT_ENABLED_ERROR
;
1311 epctx
= slot
->eps
[epid
-1];
1314 if (epctx
->state
!= EP_STOPPED
) {
1315 fprintf(stderr
, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1316 return CC_CONTEXT_STATE_ERROR
;
1319 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1320 epctx
->ring
.ccs
= dequeue
& 1;
1322 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1327 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1329 XHCIState
*xhci
= xfer
->xhci
;
1332 xfer
->int_req
= false;
1333 pci_dma_sglist_init(&xfer
->sgl
, &xhci
->pci_dev
, xfer
->trb_count
);
1334 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1335 XHCITRB
*trb
= &xfer
->trbs
[i
];
1337 unsigned int chunk
= 0;
1339 if (trb
->control
& TRB_TR_IOC
) {
1340 xfer
->int_req
= true;
1343 switch (TRB_TYPE(*trb
)) {
1345 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1346 fprintf(stderr
, "xhci: data direction mismatch for TR_DATA\n");
1352 addr
= xhci_mask64(trb
->parameter
);
1353 chunk
= trb
->status
& 0x1ffff;
1354 if (trb
->control
& TRB_TR_IDT
) {
1355 if (chunk
> 8 || in_xfer
) {
1356 fprintf(stderr
, "xhci: invalid immediate data TRB\n");
1359 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1361 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1370 qemu_sglist_destroy(&xfer
->sgl
);
1375 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1377 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1378 qemu_sglist_destroy(&xfer
->sgl
);
1381 static void xhci_xfer_report(XHCITransfer
*xfer
)
1387 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1388 XHCIState
*xhci
= xfer
->xhci
;
1391 left
= xfer
->packet
.status
? 0 : xfer
->packet
.actual_length
;
1393 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1394 XHCITRB
*trb
= &xfer
->trbs
[i
];
1395 unsigned int chunk
= 0;
1397 switch (TRB_TYPE(*trb
)) {
1401 chunk
= trb
->status
& 0x1ffff;
1404 if (xfer
->status
== CC_SUCCESS
) {
1417 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1418 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1419 (xfer
->status
!= CC_SUCCESS
))) {
1420 event
.slotid
= xfer
->slotid
;
1421 event
.epid
= xfer
->epid
;
1422 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1424 event
.ptr
= trb
->addr
;
1425 if (xfer
->status
== CC_SUCCESS
) {
1426 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1428 event
.ccode
= xfer
->status
;
1430 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1431 event
.ptr
= trb
->parameter
;
1432 event
.flags
|= TRB_EV_ED
;
1433 event
.length
= edtla
& 0xffffff;
1434 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1437 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1439 if (xfer
->status
!= CC_SUCCESS
) {
1446 static void xhci_stall_ep(XHCITransfer
*xfer
)
1448 XHCIState
*xhci
= xfer
->xhci
;
1449 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1450 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1452 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1453 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1454 xhci_set_ep_state(xhci
, epctx
, EP_HALTED
);
1455 DPRINTF("xhci: stalled slot %d ep %d\n", xfer
->slotid
, xfer
->epid
);
1456 DPRINTF("xhci: will continue at "DMA_ADDR_FMT
"\n", epctx
->ring
.dequeue
);
1459 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1460 XHCIEPContext
*epctx
);
1462 static int xhci_setup_packet(XHCITransfer
*xfer
)
1464 XHCIState
*xhci
= xfer
->xhci
;
1469 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1471 if (xfer
->packet
.ep
) {
1472 ep
= xfer
->packet
.ep
;
1475 if (!xhci
->slots
[xfer
->slotid
-1].uport
) {
1476 fprintf(stderr
, "xhci: slot %d has no device\n",
1480 dev
= xhci
->slots
[xfer
->slotid
-1].uport
->dev
;
1481 ep
= usb_ep_get(dev
, dir
, xfer
->epid
>> 1);
1484 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1485 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->trbs
[0].addr
, false,
1487 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1488 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1489 xfer
->packet
.pid
, dev
->addr
, ep
->nr
);
1493 static int xhci_complete_packet(XHCITransfer
*xfer
)
1495 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1496 trace_usb_xhci_xfer_async(xfer
);
1497 xfer
->running_async
= 1;
1498 xfer
->running_retry
= 0;
1500 xfer
->cancelled
= 0;
1502 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1503 trace_usb_xhci_xfer_nak(xfer
);
1504 xfer
->running_async
= 0;
1505 xfer
->running_retry
= 1;
1507 xfer
->cancelled
= 0;
1510 xfer
->running_async
= 0;
1511 xfer
->running_retry
= 0;
1513 xhci_xfer_unmap(xfer
);
1516 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1517 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1518 xfer
->status
= CC_SUCCESS
;
1519 xhci_xfer_report(xfer
);
1524 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1525 switch (xfer
->packet
.status
) {
1527 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1528 xhci_xfer_report(xfer
);
1529 xhci_stall_ep(xfer
);
1532 xfer
->status
= CC_STALL_ERROR
;
1533 xhci_xfer_report(xfer
);
1534 xhci_stall_ep(xfer
);
1537 fprintf(stderr
, "%s: FIXME: status = %d\n", __func__
,
1538 xfer
->packet
.status
);
1544 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1546 XHCITRB
*trb_setup
, *trb_status
;
1547 uint8_t bmRequestType
;
1549 trb_setup
= &xfer
->trbs
[0];
1550 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1552 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
);
1554 /* at most one Event Data TRB allowed after STATUS */
1555 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1559 /* do some sanity checks */
1560 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1561 fprintf(stderr
, "xhci: ep0 first TD not SETUP: %d\n",
1562 TRB_TYPE(*trb_setup
));
1565 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1566 fprintf(stderr
, "xhci: ep0 last TD not STATUS: %d\n",
1567 TRB_TYPE(*trb_status
));
1570 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1571 fprintf(stderr
, "xhci: Setup TRB doesn't have IDT set\n");
1574 if ((trb_setup
->status
& 0x1ffff) != 8) {
1575 fprintf(stderr
, "xhci: Setup TRB has bad length (%d)\n",
1576 (trb_setup
->status
& 0x1ffff));
1580 bmRequestType
= trb_setup
->parameter
;
1582 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1583 xfer
->iso_xfer
= false;
1585 if (xhci_setup_packet(xfer
) < 0) {
1588 xfer
->packet
.parameter
= trb_setup
->parameter
;
1590 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1592 xhci_complete_packet(xfer
);
1593 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1594 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1599 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1600 XHCIEPContext
*epctx
, uint64_t mfindex
)
1602 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1603 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1604 ~(epctx
->interval
-1));
1605 if (asap
>= epctx
->mfindex_last
&&
1606 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1607 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1609 xfer
->mfindex_kick
= asap
;
1612 xfer
->mfindex_kick
= (xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1613 & TRB_TR_FRAMEID_MASK
;
1614 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1615 if (xfer
->mfindex_kick
< mfindex
) {
1616 xfer
->mfindex_kick
+= 0x4000;
1621 static void xhci_check_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1622 XHCIEPContext
*epctx
, uint64_t mfindex
)
1624 if (xfer
->mfindex_kick
> mfindex
) {
1625 qemu_mod_timer(epctx
->kick_timer
, qemu_get_clock_ns(vm_clock
) +
1626 (xfer
->mfindex_kick
- mfindex
) * 125000);
1627 xfer
->running_retry
= 1;
1629 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1630 qemu_del_timer(epctx
->kick_timer
);
1631 xfer
->running_retry
= 0;
1636 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1640 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1642 xfer
->in_xfer
= epctx
->type
>>2;
1644 switch(epctx
->type
) {
1650 xfer
->iso_xfer
= false;
1655 xfer
->iso_xfer
= true;
1656 mfindex
= xhci_mfindex_get(xhci
);
1657 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1658 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1659 if (xfer
->running_retry
) {
1664 fprintf(stderr
, "xhci: unknown or unhandled EP "
1665 "(type %d, in %d, ep %02x)\n",
1666 epctx
->type
, xfer
->in_xfer
, xfer
->epid
);
1670 if (xhci_setup_packet(xfer
) < 0) {
1673 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1675 xhci_complete_packet(xfer
);
1676 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1677 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1682 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1684 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
);
1685 return xhci_submit(xhci
, xfer
, epctx
);
1688 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
, unsigned int epid
)
1690 XHCIEPContext
*epctx
;
1691 USBEndpoint
*ep
= NULL
;
1696 trace_usb_xhci_ep_kick(slotid
, epid
);
1697 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1698 assert(epid
>= 1 && epid
<= 31);
1700 if (!xhci
->slots
[slotid
-1].enabled
) {
1701 fprintf(stderr
, "xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1704 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1706 fprintf(stderr
, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1712 XHCITransfer
*xfer
= epctx
->retry
;
1714 trace_usb_xhci_xfer_retry(xfer
);
1715 assert(xfer
->running_retry
);
1716 if (xfer
->iso_xfer
) {
1717 /* retry delayed iso transfer */
1718 mfindex
= xhci_mfindex_get(xhci
);
1719 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1720 if (xfer
->running_retry
) {
1723 if (xhci_setup_packet(xfer
) < 0) {
1726 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1727 assert(xfer
->packet
.status
!= USB_RET_NAK
);
1728 xhci_complete_packet(xfer
);
1730 /* retry nak'ed transfer */
1731 if (xhci_setup_packet(xfer
) < 0) {
1734 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1735 if (xfer
->packet
.status
== USB_RET_NAK
) {
1738 xhci_complete_packet(xfer
);
1740 assert(!xfer
->running_retry
);
1741 epctx
->retry
= NULL
;
1744 if (epctx
->state
== EP_HALTED
) {
1745 DPRINTF("xhci: ep halted, not running schedule\n");
1749 xhci_set_ep_state(xhci
, epctx
, EP_RUNNING
);
1752 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
1753 if (xfer
->running_async
|| xfer
->running_retry
) {
1756 length
= xhci_ring_chain_length(xhci
, &epctx
->ring
);
1759 } else if (length
== 0) {
1762 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
1763 xfer
->trb_count
= 0;
1764 xfer
->trb_alloced
= 0;
1769 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
1770 xfer
->trb_alloced
= length
;
1772 xfer
->trb_count
= length
;
1774 for (i
= 0; i
< length
; i
++) {
1775 assert(xhci_ring_fetch(xhci
, &epctx
->ring
, &xfer
->trbs
[i
], NULL
));
1779 xfer
->slotid
= slotid
;
1782 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
1783 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1784 ep
= xfer
->packet
.ep
;
1786 fprintf(stderr
, "xhci: error firing CTL transfer\n");
1789 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
1790 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1791 ep
= xfer
->packet
.ep
;
1793 if (!xfer
->iso_xfer
) {
1794 fprintf(stderr
, "xhci: error firing data transfer\n");
1799 if (epctx
->state
== EP_HALTED
) {
1802 if (xfer
->running_retry
) {
1803 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1804 epctx
->retry
= xfer
;
1809 usb_device_flush_ep_queue(ep
->dev
, ep
);
1813 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
1815 trace_usb_xhci_slot_enable(slotid
);
1816 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1817 xhci
->slots
[slotid
-1].enabled
= 1;
1818 xhci
->slots
[slotid
-1].uport
= NULL
;
1819 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
1824 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
1828 trace_usb_xhci_slot_disable(slotid
);
1829 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1831 for (i
= 1; i
<= 31; i
++) {
1832 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1833 xhci_disable_ep(xhci
, slotid
, i
);
1837 xhci
->slots
[slotid
-1].enabled
= 0;
1841 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
1847 port
= (slot_ctx
[1]>>16) & 0xFF;
1848 port
= xhci
->ports
[port
-1].uport
->index
+1;
1849 pos
= snprintf(path
, sizeof(path
), "%d", port
);
1850 for (i
= 0; i
< 5; i
++) {
1851 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
1855 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
1858 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
1859 if (strcmp(uport
->path
, path
) == 0) {
1866 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
1867 uint64_t pictx
, bool bsr
)
1872 dma_addr_t ictx
, octx
, dcbaap
;
1874 uint32_t ictl_ctx
[2];
1875 uint32_t slot_ctx
[4];
1876 uint32_t ep0_ctx
[5];
1880 trace_usb_xhci_slot_address(slotid
);
1881 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1883 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
1884 pci_dma_read(&xhci
->pci_dev
, dcbaap
+ 8*slotid
, &poctx
, sizeof(poctx
));
1885 ictx
= xhci_mask64(pictx
);
1886 octx
= xhci_mask64(le64_to_cpu(poctx
));
1888 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1889 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1891 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1893 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
1894 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1895 ictl_ctx
[0], ictl_ctx
[1]);
1896 return CC_TRB_ERROR
;
1899 pci_dma_read(&xhci
->pci_dev
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
1900 pci_dma_read(&xhci
->pci_dev
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
1902 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1903 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1905 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1906 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1908 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
1909 if (uport
== NULL
) {
1910 fprintf(stderr
, "xhci: port not found\n");
1911 return CC_TRB_ERROR
;
1916 fprintf(stderr
, "xhci: port %s not connected\n", uport
->path
);
1917 return CC_USB_TRANSACTION_ERROR
;
1920 for (i
= 0; i
< xhci
->numslots
; i
++) {
1921 if (i
== slotid
-1) {
1924 if (xhci
->slots
[i
].uport
== uport
) {
1925 fprintf(stderr
, "xhci: port %s already assigned to slot %d\n",
1927 return CC_TRB_ERROR
;
1931 slot
= &xhci
->slots
[slotid
-1];
1932 slot
->uport
= uport
;
1936 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
1938 slot
->devaddr
= xhci
->devaddr
++;
1939 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slot
->devaddr
;
1940 DPRINTF("xhci: device address is %d\n", slot
->devaddr
);
1941 usb_device_reset(dev
);
1942 usb_device_handle_control(dev
, NULL
,
1943 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
1944 slot
->devaddr
, 0, 0, NULL
);
1947 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
1949 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1950 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1951 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1952 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1954 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1955 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
1961 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
1962 uint64_t pictx
, bool dc
)
1964 dma_addr_t ictx
, octx
;
1965 uint32_t ictl_ctx
[2];
1966 uint32_t slot_ctx
[4];
1967 uint32_t islot_ctx
[4];
1972 trace_usb_xhci_slot_configure(slotid
);
1973 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1975 ictx
= xhci_mask64(pictx
);
1976 octx
= xhci
->slots
[slotid
-1].ctx
;
1978 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1979 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1982 for (i
= 2; i
<= 31; i
++) {
1983 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1984 xhci_disable_ep(xhci
, slotid
, i
);
1988 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1989 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1990 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
1991 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1992 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1993 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1998 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2000 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2001 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2002 ictl_ctx
[0], ictl_ctx
[1]);
2003 return CC_TRB_ERROR
;
2006 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2007 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2009 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2010 fprintf(stderr
, "xhci: invalid slot state %08x\n", slot_ctx
[3]);
2011 return CC_CONTEXT_STATE_ERROR
;
2014 for (i
= 2; i
<= 31; i
++) {
2015 if (ictl_ctx
[0] & (1<<i
)) {
2016 xhci_disable_ep(xhci
, slotid
, i
);
2018 if (ictl_ctx
[1] & (1<<i
)) {
2019 pci_dma_read(&xhci
->pci_dev
, ictx
+32+(32*i
), ep_ctx
,
2021 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2022 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2023 ep_ctx
[3], ep_ctx
[4]);
2024 xhci_disable_ep(xhci
, slotid
, i
);
2025 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2026 if (res
!= CC_SUCCESS
) {
2029 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2030 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2031 ep_ctx
[3], ep_ctx
[4]);
2032 pci_dma_write(&xhci
->pci_dev
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2036 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2037 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2038 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2039 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2040 SLOT_CONTEXT_ENTRIES_SHIFT
);
2041 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2042 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2044 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2050 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2053 dma_addr_t ictx
, octx
;
2054 uint32_t ictl_ctx
[2];
2055 uint32_t iep0_ctx
[5];
2056 uint32_t ep0_ctx
[5];
2057 uint32_t islot_ctx
[4];
2058 uint32_t slot_ctx
[4];
2060 trace_usb_xhci_slot_evaluate(slotid
);
2061 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2063 ictx
= xhci_mask64(pictx
);
2064 octx
= xhci
->slots
[slotid
-1].ctx
;
2066 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2067 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2069 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2071 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2072 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2073 ictl_ctx
[0], ictl_ctx
[1]);
2074 return CC_TRB_ERROR
;
2077 if (ictl_ctx
[1] & 0x1) {
2078 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2080 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2081 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2083 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2085 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2086 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2087 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2088 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2090 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2091 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2093 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2096 if (ictl_ctx
[1] & 0x2) {
2097 pci_dma_read(&xhci
->pci_dev
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2099 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2100 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2101 iep0_ctx
[3], iep0_ctx
[4]);
2103 pci_dma_read(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2105 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2106 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2108 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2109 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2111 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2117 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2119 uint32_t slot_ctx
[4];
2123 trace_usb_xhci_slot_reset(slotid
);
2124 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2126 octx
= xhci
->slots
[slotid
-1].ctx
;
2128 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2130 for (i
= 2; i
<= 31; i
++) {
2131 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2132 xhci_disable_ep(xhci
, slotid
, i
);
2136 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2137 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2138 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2139 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2140 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2141 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
2146 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2148 unsigned int slotid
;
2149 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2150 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2151 fprintf(stderr
, "xhci: bad slot id %d\n", slotid
);
2152 event
->ccode
= CC_TRB_ERROR
;
2154 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2155 fprintf(stderr
, "xhci: slot id %d not enabled\n", slotid
);
2156 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2162 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2165 uint8_t bw_ctx
[xhci
->numports
+1];
2167 DPRINTF("xhci_get_port_bandwidth()\n");
2169 ctx
= xhci_mask64(pctx
);
2171 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2173 /* TODO: actually implement real values here */
2175 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2176 pci_dma_write(&xhci
->pci_dev
, ctx
, bw_ctx
, sizeof(bw_ctx
));
2181 static uint32_t rotl(uint32_t v
, unsigned count
)
2184 return (v
<< count
) | (v
>> (32 - count
));
2188 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2191 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2192 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2193 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2197 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2201 dma_addr_t paddr
= xhci_mask64(addr
);
2203 pci_dma_read(&xhci
->pci_dev
, paddr
, &buf
, 32);
2205 memcpy(obuf
, buf
, sizeof(obuf
));
2207 if ((buf
[0] & 0xff) == 2) {
2208 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2209 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2210 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2211 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2212 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2213 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2214 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2215 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2216 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2219 pci_dma_write(&xhci
->pci_dev
, paddr
, &obuf
, 32);
2222 static void xhci_process_commands(XHCIState
*xhci
)
2226 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2228 unsigned int i
, slotid
= 0;
2230 DPRINTF("xhci_process_commands()\n");
2231 if (!xhci_running(xhci
)) {
2232 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2236 xhci
->crcr_low
|= CRCR_CRR
;
2238 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2241 case CR_ENABLE_SLOT
:
2242 for (i
= 0; i
< xhci
->numslots
; i
++) {
2243 if (!xhci
->slots
[i
].enabled
) {
2247 if (i
>= xhci
->numslots
) {
2248 fprintf(stderr
, "xhci: no device slots available\n");
2249 event
.ccode
= CC_NO_SLOTS_ERROR
;
2252 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2255 case CR_DISABLE_SLOT
:
2256 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2258 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2261 case CR_ADDRESS_DEVICE
:
2262 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2264 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2265 trb
.control
& TRB_CR_BSR
);
2268 case CR_CONFIGURE_ENDPOINT
:
2269 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2271 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2272 trb
.control
& TRB_CR_DC
);
2275 case CR_EVALUATE_CONTEXT
:
2276 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2278 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2281 case CR_STOP_ENDPOINT
:
2282 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2284 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2286 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2289 case CR_RESET_ENDPOINT
:
2290 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2292 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2294 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2297 case CR_SET_TR_DEQUEUE
:
2298 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2300 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2302 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
, epid
,
2306 case CR_RESET_DEVICE
:
2307 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2309 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2312 case CR_GET_PORT_BANDWIDTH
:
2313 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2315 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2316 xhci_via_challenge(xhci
, trb
.parameter
);
2318 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2319 event
.type
= 48; /* NEC reply */
2320 event
.length
= 0x3025;
2322 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2324 uint32_t chi
= trb
.parameter
>> 32;
2325 uint32_t clo
= trb
.parameter
;
2326 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2327 event
.length
= val
& 0xFFFF;
2328 event
.epid
= val
>> 16;
2330 event
.type
= 48; /* NEC reply */
2334 fprintf(stderr
, "xhci: unimplemented command %d\n", type
);
2335 event
.ccode
= CC_TRB_ERROR
;
2338 event
.slotid
= slotid
;
2339 xhci_event(xhci
, &event
, 0);
2343 static bool xhci_port_have_device(XHCIPort
*port
)
2345 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2346 return false; /* no device present */
2348 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2349 return false; /* speed mismatch */
2354 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2356 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2357 port
->portnr
<< 24 };
2359 if ((port
->portsc
& bits
) == bits
) {
2362 port
->portsc
|= bits
;
2363 if (!xhci_running(port
->xhci
)) {
2366 xhci_event(port
->xhci
, &ev
, 0);
2369 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2371 uint32_t pls
= PLS_RX_DETECT
;
2373 port
->portsc
= PORTSC_PP
;
2374 if (!is_detach
&& xhci_port_have_device(port
)) {
2375 port
->portsc
|= PORTSC_CCS
;
2376 switch (port
->uport
->dev
->speed
) {
2378 port
->portsc
|= PORTSC_SPEED_LOW
;
2381 case USB_SPEED_FULL
:
2382 port
->portsc
|= PORTSC_SPEED_FULL
;
2385 case USB_SPEED_HIGH
:
2386 port
->portsc
|= PORTSC_SPEED_HIGH
;
2389 case USB_SPEED_SUPER
:
2390 port
->portsc
|= PORTSC_SPEED_SUPER
;
2391 port
->portsc
|= PORTSC_PED
;
2396 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2397 trace_usb_xhci_port_link(port
->portnr
, pls
);
2398 xhci_port_notify(port
, PORTSC_CSC
);
2401 static void xhci_port_reset(XHCIPort
*port
)
2403 trace_usb_xhci_port_reset(port
->portnr
);
2405 if (!xhci_port_have_device(port
)) {
2409 usb_device_reset(port
->uport
->dev
);
2411 switch (port
->uport
->dev
->speed
) {
2413 case USB_SPEED_FULL
:
2414 case USB_SPEED_HIGH
:
2415 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2416 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2417 port
->portsc
|= PORTSC_PED
;
2421 port
->portsc
&= ~PORTSC_PR
;
2422 xhci_port_notify(port
, PORTSC_PRC
);
2425 static void xhci_reset(DeviceState
*dev
)
2427 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
.qdev
, dev
);
2430 trace_usb_xhci_reset();
2431 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2432 fprintf(stderr
, "xhci: reset while running!\n");
2436 xhci
->usbsts
= USBSTS_HCH
;
2439 xhci
->crcr_high
= 0;
2440 xhci
->dcbaap_low
= 0;
2441 xhci
->dcbaap_high
= 0;
2445 for (i
= 0; i
< xhci
->numslots
; i
++) {
2446 xhci_disable_slot(xhci
, i
+1);
2449 for (i
= 0; i
< xhci
->numports
; i
++) {
2450 xhci_port_update(xhci
->ports
+ i
, 0);
2453 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2454 xhci
->intr
[i
].iman
= 0;
2455 xhci
->intr
[i
].imod
= 0;
2456 xhci
->intr
[i
].erstsz
= 0;
2457 xhci
->intr
[i
].erstba_low
= 0;
2458 xhci
->intr
[i
].erstba_high
= 0;
2459 xhci
->intr
[i
].erdp_low
= 0;
2460 xhci
->intr
[i
].erdp_high
= 0;
2461 xhci
->intr
[i
].msix_used
= 0;
2463 xhci
->intr
[i
].er_ep_idx
= 0;
2464 xhci
->intr
[i
].er_pcs
= 1;
2465 xhci
->intr
[i
].er_full
= 0;
2466 xhci
->intr
[i
].ev_buffer_put
= 0;
2467 xhci
->intr
[i
].ev_buffer_get
= 0;
2470 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
2471 xhci_mfwrap_update(xhci
);
2474 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2476 XHCIState
*xhci
= ptr
;
2480 case 0x00: /* HCIVERSION, CAPLENGTH */
2481 ret
= 0x01000000 | LEN_CAP
;
2483 case 0x04: /* HCSPARAMS 1 */
2484 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2485 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2487 case 0x08: /* HCSPARAMS 2 */
2490 case 0x0c: /* HCSPARAMS 3 */
2493 case 0x10: /* HCCPARAMS */
2494 if (sizeof(dma_addr_t
) == 4) {
2500 case 0x14: /* DBOFF */
2503 case 0x18: /* RTSOFF */
2507 /* extended capabilities */
2508 case 0x20: /* Supported Protocol:00 */
2509 ret
= 0x02000402; /* USB 2.0 */
2511 case 0x24: /* Supported Protocol:04 */
2512 ret
= 0x20425355; /* "USB " */
2514 case 0x28: /* Supported Protocol:08 */
2515 ret
= 0x00000001 | (xhci
->numports_2
<<8);
2517 case 0x2c: /* Supported Protocol:0c */
2518 ret
= 0x00000000; /* reserved */
2520 case 0x30: /* Supported Protocol:00 */
2521 ret
= 0x03000002; /* USB 3.0 */
2523 case 0x34: /* Supported Protocol:04 */
2524 ret
= 0x20425355; /* "USB " */
2526 case 0x38: /* Supported Protocol:08 */
2527 ret
= 0x00000000 | (xhci
->numports_2
+1) | (xhci
->numports_3
<<8);
2529 case 0x3c: /* Supported Protocol:0c */
2530 ret
= 0x00000000; /* reserved */
2533 fprintf(stderr
, "xhci_cap_read: reg %d unimplemented\n", (int)reg
);
2537 trace_usb_xhci_cap_read(reg
, ret
);
2541 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2543 XHCIPort
*port
= ptr
;
2547 case 0x00: /* PORTSC */
2550 case 0x04: /* PORTPMSC */
2551 case 0x08: /* PORTLI */
2554 case 0x0c: /* reserved */
2556 fprintf(stderr
, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2557 port
->portnr
, (uint32_t)reg
);
2561 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2565 static void xhci_port_write(void *ptr
, hwaddr reg
,
2566 uint64_t val
, unsigned size
)
2568 XHCIPort
*port
= ptr
;
2571 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2574 case 0x00: /* PORTSC */
2575 portsc
= port
->portsc
;
2576 /* write-1-to-clear bits*/
2577 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2578 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2579 if (val
& PORTSC_LWS
) {
2580 /* overwrite PLS only when LWS=1 */
2581 uint32_t pls
= get_field(val
, PORTSC_PLS
);
2582 set_field(&portsc
, pls
, PORTSC_PLS
);
2583 trace_usb_xhci_port_link(port
->portnr
, pls
);
2585 /* read/write bits */
2586 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2587 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2588 port
->portsc
= portsc
;
2589 /* write-1-to-start bits */
2590 if (val
& PORTSC_PR
) {
2591 xhci_port_reset(port
);
2594 case 0x04: /* PORTPMSC */
2595 case 0x08: /* PORTLI */
2597 fprintf(stderr
, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2598 port
->portnr
, (uint32_t)reg
);
2602 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2604 XHCIState
*xhci
= ptr
;
2608 case 0x00: /* USBCMD */
2611 case 0x04: /* USBSTS */
2614 case 0x08: /* PAGESIZE */
2617 case 0x14: /* DNCTRL */
2620 case 0x18: /* CRCR low */
2621 ret
= xhci
->crcr_low
& ~0xe;
2623 case 0x1c: /* CRCR high */
2624 ret
= xhci
->crcr_high
;
2626 case 0x30: /* DCBAAP low */
2627 ret
= xhci
->dcbaap_low
;
2629 case 0x34: /* DCBAAP high */
2630 ret
= xhci
->dcbaap_high
;
2632 case 0x38: /* CONFIG */
2636 fprintf(stderr
, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg
);
2640 trace_usb_xhci_oper_read(reg
, ret
);
2644 static void xhci_oper_write(void *ptr
, hwaddr reg
,
2645 uint64_t val
, unsigned size
)
2647 XHCIState
*xhci
= ptr
;
2649 trace_usb_xhci_oper_write(reg
, val
);
2652 case 0x00: /* USBCMD */
2653 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2655 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2658 xhci
->usbcmd
= val
& 0xc0f;
2659 xhci_mfwrap_update(xhci
);
2660 if (val
& USBCMD_HCRST
) {
2661 xhci_reset(&xhci
->pci_dev
.qdev
);
2663 xhci_intx_update(xhci
);
2666 case 0x04: /* USBSTS */
2667 /* these bits are write-1-to-clear */
2668 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2669 xhci_intx_update(xhci
);
2672 case 0x14: /* DNCTRL */
2673 xhci
->dnctrl
= val
& 0xffff;
2675 case 0x18: /* CRCR low */
2676 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2678 case 0x1c: /* CRCR high */
2679 xhci
->crcr_high
= val
;
2680 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2681 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2682 xhci
->crcr_low
&= ~CRCR_CRR
;
2683 xhci_event(xhci
, &event
, 0);
2684 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2686 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2687 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2689 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2691 case 0x30: /* DCBAAP low */
2692 xhci
->dcbaap_low
= val
& 0xffffffc0;
2694 case 0x34: /* DCBAAP high */
2695 xhci
->dcbaap_high
= val
;
2697 case 0x38: /* CONFIG */
2698 xhci
->config
= val
& 0xff;
2701 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg
);
2705 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
2708 XHCIState
*xhci
= ptr
;
2713 case 0x00: /* MFINDEX */
2714 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
2717 fprintf(stderr
, "xhci_runtime_read: reg 0x%x unimplemented\n",
2722 int v
= (reg
- 0x20) / 0x20;
2723 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
2724 switch (reg
& 0x1f) {
2725 case 0x00: /* IMAN */
2728 case 0x04: /* IMOD */
2731 case 0x08: /* ERSTSZ */
2734 case 0x10: /* ERSTBA low */
2735 ret
= intr
->erstba_low
;
2737 case 0x14: /* ERSTBA high */
2738 ret
= intr
->erstba_high
;
2740 case 0x18: /* ERDP low */
2741 ret
= intr
->erdp_low
;
2743 case 0x1c: /* ERDP high */
2744 ret
= intr
->erdp_high
;
2749 trace_usb_xhci_runtime_read(reg
, ret
);
2753 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
2754 uint64_t val
, unsigned size
)
2756 XHCIState
*xhci
= ptr
;
2757 int v
= (reg
- 0x20) / 0x20;
2758 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
2759 trace_usb_xhci_runtime_write(reg
, val
);
2762 fprintf(stderr
, "%s: reg 0x%x unimplemented\n", __func__
, (int)reg
);
2766 switch (reg
& 0x1f) {
2767 case 0x00: /* IMAN */
2768 if (val
& IMAN_IP
) {
2769 intr
->iman
&= ~IMAN_IP
;
2771 intr
->iman
&= ~IMAN_IE
;
2772 intr
->iman
|= val
& IMAN_IE
;
2774 xhci_intx_update(xhci
);
2776 xhci_msix_update(xhci
, v
);
2778 case 0x04: /* IMOD */
2781 case 0x08: /* ERSTSZ */
2782 intr
->erstsz
= val
& 0xffff;
2784 case 0x10: /* ERSTBA low */
2785 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2786 intr->erstba_low = val & 0xffffffc0; */
2787 intr
->erstba_low
= val
& 0xfffffff0;
2789 case 0x14: /* ERSTBA high */
2790 intr
->erstba_high
= val
;
2791 xhci_er_reset(xhci
, v
);
2793 case 0x18: /* ERDP low */
2794 if (val
& ERDP_EHB
) {
2795 intr
->erdp_low
&= ~ERDP_EHB
;
2797 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
2799 case 0x1c: /* ERDP high */
2800 intr
->erdp_high
= val
;
2801 xhci_events_update(xhci
, v
);
2804 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n",
2809 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
2812 /* doorbells always read as 0 */
2813 trace_usb_xhci_doorbell_read(reg
, 0);
2817 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
2818 uint64_t val
, unsigned size
)
2820 XHCIState
*xhci
= ptr
;
2822 trace_usb_xhci_doorbell_write(reg
, val
);
2824 if (!xhci_running(xhci
)) {
2825 fprintf(stderr
, "xhci: wrote doorbell while xHC stopped or paused\n");
2833 xhci_process_commands(xhci
);
2835 fprintf(stderr
, "xhci: bad doorbell 0 write: 0x%x\n",
2839 if (reg
> xhci
->numslots
) {
2840 fprintf(stderr
, "xhci: bad doorbell %d\n", (int)reg
);
2841 } else if (val
> 31) {
2842 fprintf(stderr
, "xhci: bad doorbell %d write: 0x%x\n",
2843 (int)reg
, (uint32_t)val
);
2845 xhci_kick_ep(xhci
, reg
, val
);
2850 static const MemoryRegionOps xhci_cap_ops
= {
2851 .read
= xhci_cap_read
,
2852 .valid
.min_access_size
= 1,
2853 .valid
.max_access_size
= 4,
2854 .impl
.min_access_size
= 4,
2855 .impl
.max_access_size
= 4,
2856 .endianness
= DEVICE_LITTLE_ENDIAN
,
2859 static const MemoryRegionOps xhci_oper_ops
= {
2860 .read
= xhci_oper_read
,
2861 .write
= xhci_oper_write
,
2862 .valid
.min_access_size
= 4,
2863 .valid
.max_access_size
= 4,
2864 .endianness
= DEVICE_LITTLE_ENDIAN
,
2867 static const MemoryRegionOps xhci_port_ops
= {
2868 .read
= xhci_port_read
,
2869 .write
= xhci_port_write
,
2870 .valid
.min_access_size
= 4,
2871 .valid
.max_access_size
= 4,
2872 .endianness
= DEVICE_LITTLE_ENDIAN
,
2875 static const MemoryRegionOps xhci_runtime_ops
= {
2876 .read
= xhci_runtime_read
,
2877 .write
= xhci_runtime_write
,
2878 .valid
.min_access_size
= 4,
2879 .valid
.max_access_size
= 4,
2880 .endianness
= DEVICE_LITTLE_ENDIAN
,
2883 static const MemoryRegionOps xhci_doorbell_ops
= {
2884 .read
= xhci_doorbell_read
,
2885 .write
= xhci_doorbell_write
,
2886 .valid
.min_access_size
= 4,
2887 .valid
.max_access_size
= 4,
2888 .endianness
= DEVICE_LITTLE_ENDIAN
,
2891 static void xhci_attach(USBPort
*usbport
)
2893 XHCIState
*xhci
= usbport
->opaque
;
2894 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
2896 xhci_port_update(port
, 0);
2899 static void xhci_detach(USBPort
*usbport
)
2901 XHCIState
*xhci
= usbport
->opaque
;
2902 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
2904 xhci_port_update(port
, 1);
2907 static void xhci_wakeup(USBPort
*usbport
)
2909 XHCIState
*xhci
= usbport
->opaque
;
2910 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
2912 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
2915 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
2916 xhci_port_notify(port
, PORTSC_PLC
);
2919 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
2921 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
2923 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
2924 xhci_ep_nuke_one_xfer(xfer
);
2927 xhci_complete_packet(xfer
);
2928 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
);
2931 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
2933 USBBus
*bus
= usb_bus_from_device(child
);
2934 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
2937 for (i
= 0; i
< xhci
->numslots
; i
++) {
2938 if (xhci
->slots
[i
].uport
== uport
) {
2939 xhci
->slots
[i
].uport
= NULL
;
2944 static USBPortOps xhci_uport_ops
= {
2945 .attach
= xhci_attach
,
2946 .detach
= xhci_detach
,
2947 .wakeup
= xhci_wakeup
,
2948 .complete
= xhci_complete
,
2949 .child_detach
= xhci_child_detach
,
2952 static int xhci_find_slotid(XHCIState
*xhci
, USBDevice
*dev
)
2957 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
2958 slot
= &xhci
->slots
[slotid
-1];
2959 if (slot
->devaddr
== dev
->addr
) {
2966 static int xhci_find_epid(USBEndpoint
*ep
)
2971 if (ep
->pid
== USB_TOKEN_IN
) {
2972 return ep
->nr
* 2 + 1;
2978 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
)
2980 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
2983 DPRINTF("%s\n", __func__
);
2984 slotid
= xhci_find_slotid(xhci
, ep
->dev
);
2985 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
2986 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
2989 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
));
2992 static USBBusOps xhci_bus_ops
= {
2993 .wakeup_endpoint
= xhci_wakeup_endpoint
,
2996 static void usb_xhci_init(XHCIState
*xhci
, DeviceState
*dev
)
2999 int i
, usbports
, speedmask
;
3001 xhci
->usbsts
= USBSTS_HCH
;
3003 if (xhci
->numports_2
> MAXPORTS_2
) {
3004 xhci
->numports_2
= MAXPORTS_2
;
3006 if (xhci
->numports_3
> MAXPORTS_3
) {
3007 xhci
->numports_3
= MAXPORTS_3
;
3009 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3010 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3012 usb_bus_new(&xhci
->bus
, &xhci_bus_ops
, &xhci
->pci_dev
.qdev
);
3014 for (i
= 0; i
< usbports
; i
++) {
3016 if (i
< xhci
->numports_2
) {
3017 port
= &xhci
->ports
[i
];
3018 port
->portnr
= i
+ 1;
3019 port
->uport
= &xhci
->uports
[i
];
3021 USB_SPEED_MASK_LOW
|
3022 USB_SPEED_MASK_FULL
|
3023 USB_SPEED_MASK_HIGH
;
3024 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3025 speedmask
|= port
->speedmask
;
3027 if (i
< xhci
->numports_3
) {
3028 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3029 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3030 port
->uport
= &xhci
->uports
[i
];
3031 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3032 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3033 speedmask
|= port
->speedmask
;
3035 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3036 &xhci_uport_ops
, speedmask
);
3040 static int usb_xhci_initfn(struct PCIDevice
*dev
)
3044 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
3046 xhci
->pci_dev
.config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3047 xhci
->pci_dev
.config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3048 xhci
->pci_dev
.config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3049 xhci
->pci_dev
.config
[0x60] = 0x30; /* release number */
3051 usb_xhci_init(xhci
, &dev
->qdev
);
3053 if (xhci
->numintrs
> MAXINTRS
) {
3054 xhci
->numintrs
= MAXINTRS
;
3056 if (xhci
->numintrs
< 1) {
3059 if (xhci
->numslots
> MAXSLOTS
) {
3060 xhci
->numslots
= MAXSLOTS
;
3062 if (xhci
->numslots
< 1) {
3066 xhci
->mfwrap_timer
= qemu_new_timer_ns(vm_clock
, xhci_mfwrap_timer
, xhci
);
3068 xhci
->irq
= xhci
->pci_dev
.irq
[0];
3070 memory_region_init(&xhci
->mem
, "xhci", LEN_REGS
);
3071 memory_region_init_io(&xhci
->mem_cap
, &xhci_cap_ops
, xhci
,
3072 "capabilities", LEN_CAP
);
3073 memory_region_init_io(&xhci
->mem_oper
, &xhci_oper_ops
, xhci
,
3074 "operational", 0x400);
3075 memory_region_init_io(&xhci
->mem_runtime
, &xhci_runtime_ops
, xhci
,
3076 "runtime", LEN_RUNTIME
);
3077 memory_region_init_io(&xhci
->mem_doorbell
, &xhci_doorbell_ops
, xhci
,
3078 "doorbell", LEN_DOORBELL
);
3080 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3081 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3082 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3083 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3085 for (i
= 0; i
< xhci
->numports
; i
++) {
3086 XHCIPort
*port
= &xhci
->ports
[i
];
3087 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3089 memory_region_init_io(&port
->mem
, &xhci_port_ops
, port
,
3091 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3094 pci_register_bar(&xhci
->pci_dev
, 0,
3095 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3098 ret
= pcie_cap_init(&xhci
->pci_dev
, 0xa0, PCI_EXP_TYPE_ENDPOINT
, 0);
3101 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI
)) {
3102 msi_init(&xhci
->pci_dev
, 0x70, xhci
->numintrs
, true, false);
3104 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI_X
)) {
3105 msix_init(&xhci
->pci_dev
, xhci
->numintrs
,
3106 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3107 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3114 static const VMStateDescription vmstate_xhci
= {
3119 static Property xhci_properties
[] = {
3120 DEFINE_PROP_BIT("msi", XHCIState
, flags
, XHCI_FLAG_USE_MSI
, true),
3121 DEFINE_PROP_BIT("msix", XHCIState
, flags
, XHCI_FLAG_USE_MSI_X
, true),
3122 DEFINE_PROP_UINT32("intrs", XHCIState
, numintrs
, MAXINTRS
),
3123 DEFINE_PROP_UINT32("slots", XHCIState
, numslots
, MAXSLOTS
),
3124 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3125 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3126 DEFINE_PROP_END_OF_LIST(),
3129 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3131 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3132 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3134 dc
->vmsd
= &vmstate_xhci
;
3135 dc
->props
= xhci_properties
;
3136 dc
->reset
= xhci_reset
;
3137 k
->init
= usb_xhci_initfn
;
3138 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
3139 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
3140 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3145 static TypeInfo xhci_info
= {
3146 .name
= "nec-usb-xhci",
3147 .parent
= TYPE_PCI_DEVICE
,
3148 .instance_size
= sizeof(XHCIState
),
3149 .class_init
= xhci_class_init
,
3152 static void xhci_register_types(void)
3154 type_register_static(&xhci_info
);
3157 type_init(xhci_register_types
)