]> git.proxmox.com Git - qemu.git/blob - hw/usb/hcd-xhci.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
xhci: trace: endpoints
[qemu.git] / hw / usb / hcd-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu-timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci.h"
25 #include "hw/msi.h"
26 #include "trace.h"
27
28 //#define DEBUG_XHCI
29 //#define DEBUG_DATA
30
31 #ifdef DEBUG_XHCI
32 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
33 #else
34 #define DPRINTF(...) do {} while (0)
35 #endif
36 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
38
39 #define MAXSLOTS 8
40 #define MAXINTRS 1
41
42 #define USB2_PORTS 4
43 #define USB3_PORTS 4
44
45 #define MAXPORTS (USB2_PORTS+USB3_PORTS)
46
47 #define TD_QUEUE 24
48 #define BG_XFERS 8
49 #define BG_PKTS 8
50
51 /* Very pessimistic, let's hope it's enough for all cases */
52 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
53 /* Do not deliver ER Full events. NEC's driver does some things not bound
54 * to the specs when it gets them */
55 #define ER_FULL_HACK
56
57 #define LEN_CAP 0x40
58 #define OFF_OPER LEN_CAP
59 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
60 #define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
61 #define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
62 #define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
63 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
64
65 /* must be power of 2 */
66 #define LEN_REGS 0x2000
67
68 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
69 # error Increase LEN_REGS
70 #endif
71
72 #if MAXINTRS > 1
73 # error TODO: only one interrupter supported
74 #endif
75
76 /* bit definitions */
77 #define USBCMD_RS (1<<0)
78 #define USBCMD_HCRST (1<<1)
79 #define USBCMD_INTE (1<<2)
80 #define USBCMD_HSEE (1<<3)
81 #define USBCMD_LHCRST (1<<7)
82 #define USBCMD_CSS (1<<8)
83 #define USBCMD_CRS (1<<9)
84 #define USBCMD_EWE (1<<10)
85 #define USBCMD_EU3S (1<<11)
86
87 #define USBSTS_HCH (1<<0)
88 #define USBSTS_HSE (1<<2)
89 #define USBSTS_EINT (1<<3)
90 #define USBSTS_PCD (1<<4)
91 #define USBSTS_SSS (1<<8)
92 #define USBSTS_RSS (1<<9)
93 #define USBSTS_SRE (1<<10)
94 #define USBSTS_CNR (1<<11)
95 #define USBSTS_HCE (1<<12)
96
97
98 #define PORTSC_CCS (1<<0)
99 #define PORTSC_PED (1<<1)
100 #define PORTSC_OCA (1<<3)
101 #define PORTSC_PR (1<<4)
102 #define PORTSC_PLS_SHIFT 5
103 #define PORTSC_PLS_MASK 0xf
104 #define PORTSC_PP (1<<9)
105 #define PORTSC_SPEED_SHIFT 10
106 #define PORTSC_SPEED_MASK 0xf
107 #define PORTSC_SPEED_FULL (1<<10)
108 #define PORTSC_SPEED_LOW (2<<10)
109 #define PORTSC_SPEED_HIGH (3<<10)
110 #define PORTSC_SPEED_SUPER (4<<10)
111 #define PORTSC_PIC_SHIFT 14
112 #define PORTSC_PIC_MASK 0x3
113 #define PORTSC_LWS (1<<16)
114 #define PORTSC_CSC (1<<17)
115 #define PORTSC_PEC (1<<18)
116 #define PORTSC_WRC (1<<19)
117 #define PORTSC_OCC (1<<20)
118 #define PORTSC_PRC (1<<21)
119 #define PORTSC_PLC (1<<22)
120 #define PORTSC_CEC (1<<23)
121 #define PORTSC_CAS (1<<24)
122 #define PORTSC_WCE (1<<25)
123 #define PORTSC_WDE (1<<26)
124 #define PORTSC_WOE (1<<27)
125 #define PORTSC_DR (1<<30)
126 #define PORTSC_WPR (1<<31)
127
128 #define CRCR_RCS (1<<0)
129 #define CRCR_CS (1<<1)
130 #define CRCR_CA (1<<2)
131 #define CRCR_CRR (1<<3)
132
133 #define IMAN_IP (1<<0)
134 #define IMAN_IE (1<<1)
135
136 #define ERDP_EHB (1<<3)
137
138 #define TRB_SIZE 16
139 typedef struct XHCITRB {
140 uint64_t parameter;
141 uint32_t status;
142 uint32_t control;
143 dma_addr_t addr;
144 bool ccs;
145 } XHCITRB;
146
147
148 typedef enum TRBType {
149 TRB_RESERVED = 0,
150 TR_NORMAL,
151 TR_SETUP,
152 TR_DATA,
153 TR_STATUS,
154 TR_ISOCH,
155 TR_LINK,
156 TR_EVDATA,
157 TR_NOOP,
158 CR_ENABLE_SLOT,
159 CR_DISABLE_SLOT,
160 CR_ADDRESS_DEVICE,
161 CR_CONFIGURE_ENDPOINT,
162 CR_EVALUATE_CONTEXT,
163 CR_RESET_ENDPOINT,
164 CR_STOP_ENDPOINT,
165 CR_SET_TR_DEQUEUE,
166 CR_RESET_DEVICE,
167 CR_FORCE_EVENT,
168 CR_NEGOTIATE_BW,
169 CR_SET_LATENCY_TOLERANCE,
170 CR_GET_PORT_BANDWIDTH,
171 CR_FORCE_HEADER,
172 CR_NOOP,
173 ER_TRANSFER = 32,
174 ER_COMMAND_COMPLETE,
175 ER_PORT_STATUS_CHANGE,
176 ER_BANDWIDTH_REQUEST,
177 ER_DOORBELL,
178 ER_HOST_CONTROLLER,
179 ER_DEVICE_NOTIFICATION,
180 ER_MFINDEX_WRAP,
181 /* vendor specific bits */
182 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
183 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
184 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
185 } TRBType;
186
187 #define CR_LINK TR_LINK
188
189 typedef enum TRBCCode {
190 CC_INVALID = 0,
191 CC_SUCCESS,
192 CC_DATA_BUFFER_ERROR,
193 CC_BABBLE_DETECTED,
194 CC_USB_TRANSACTION_ERROR,
195 CC_TRB_ERROR,
196 CC_STALL_ERROR,
197 CC_RESOURCE_ERROR,
198 CC_BANDWIDTH_ERROR,
199 CC_NO_SLOTS_ERROR,
200 CC_INVALID_STREAM_TYPE_ERROR,
201 CC_SLOT_NOT_ENABLED_ERROR,
202 CC_EP_NOT_ENABLED_ERROR,
203 CC_SHORT_PACKET,
204 CC_RING_UNDERRUN,
205 CC_RING_OVERRUN,
206 CC_VF_ER_FULL,
207 CC_PARAMETER_ERROR,
208 CC_BANDWIDTH_OVERRUN,
209 CC_CONTEXT_STATE_ERROR,
210 CC_NO_PING_RESPONSE_ERROR,
211 CC_EVENT_RING_FULL_ERROR,
212 CC_INCOMPATIBLE_DEVICE_ERROR,
213 CC_MISSED_SERVICE_ERROR,
214 CC_COMMAND_RING_STOPPED,
215 CC_COMMAND_ABORTED,
216 CC_STOPPED,
217 CC_STOPPED_LENGTH_INVALID,
218 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
219 CC_ISOCH_BUFFER_OVERRUN = 31,
220 CC_EVENT_LOST_ERROR,
221 CC_UNDEFINED_ERROR,
222 CC_INVALID_STREAM_ID_ERROR,
223 CC_SECONDARY_BANDWIDTH_ERROR,
224 CC_SPLIT_TRANSACTION_ERROR
225 } TRBCCode;
226
227 #define TRB_C (1<<0)
228 #define TRB_TYPE_SHIFT 10
229 #define TRB_TYPE_MASK 0x3f
230 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
231
232 #define TRB_EV_ED (1<<2)
233
234 #define TRB_TR_ENT (1<<1)
235 #define TRB_TR_ISP (1<<2)
236 #define TRB_TR_NS (1<<3)
237 #define TRB_TR_CH (1<<4)
238 #define TRB_TR_IOC (1<<5)
239 #define TRB_TR_IDT (1<<6)
240 #define TRB_TR_TBC_SHIFT 7
241 #define TRB_TR_TBC_MASK 0x3
242 #define TRB_TR_BEI (1<<9)
243 #define TRB_TR_TLBPC_SHIFT 16
244 #define TRB_TR_TLBPC_MASK 0xf
245 #define TRB_TR_FRAMEID_SHIFT 20
246 #define TRB_TR_FRAMEID_MASK 0x7ff
247 #define TRB_TR_SIA (1<<31)
248
249 #define TRB_TR_DIR (1<<16)
250
251 #define TRB_CR_SLOTID_SHIFT 24
252 #define TRB_CR_SLOTID_MASK 0xff
253 #define TRB_CR_EPID_SHIFT 16
254 #define TRB_CR_EPID_MASK 0x1f
255
256 #define TRB_CR_BSR (1<<9)
257 #define TRB_CR_DC (1<<9)
258
259 #define TRB_LK_TC (1<<1)
260
261 #define EP_TYPE_MASK 0x7
262 #define EP_TYPE_SHIFT 3
263
264 #define EP_STATE_MASK 0x7
265 #define EP_DISABLED (0<<0)
266 #define EP_RUNNING (1<<0)
267 #define EP_HALTED (2<<0)
268 #define EP_STOPPED (3<<0)
269 #define EP_ERROR (4<<0)
270
271 #define SLOT_STATE_MASK 0x1f
272 #define SLOT_STATE_SHIFT 27
273 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
274 #define SLOT_ENABLED 0
275 #define SLOT_DEFAULT 1
276 #define SLOT_ADDRESSED 2
277 #define SLOT_CONFIGURED 3
278
279 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
280 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
281
282 typedef enum EPType {
283 ET_INVALID = 0,
284 ET_ISO_OUT,
285 ET_BULK_OUT,
286 ET_INTR_OUT,
287 ET_CONTROL,
288 ET_ISO_IN,
289 ET_BULK_IN,
290 ET_INTR_IN,
291 } EPType;
292
293 typedef struct XHCIRing {
294 dma_addr_t base;
295 dma_addr_t dequeue;
296 bool ccs;
297 } XHCIRing;
298
299 typedef struct XHCIPort {
300 USBPort port;
301 uint32_t portsc;
302 } XHCIPort;
303
304 struct XHCIState;
305 typedef struct XHCIState XHCIState;
306
307 typedef struct XHCITransfer {
308 XHCIState *xhci;
309 USBPacket packet;
310 bool running_async;
311 bool running_retry;
312 bool cancelled;
313 bool complete;
314 bool backgrounded;
315 unsigned int iso_pkts;
316 unsigned int slotid;
317 unsigned int epid;
318 bool in_xfer;
319 bool iso_xfer;
320 bool bg_xfer;
321
322 unsigned int trb_count;
323 unsigned int trb_alloced;
324 XHCITRB *trbs;
325
326 unsigned int data_length;
327 unsigned int data_alloced;
328 uint8_t *data;
329
330 TRBCCode status;
331
332 unsigned int pkts;
333 unsigned int pktsize;
334 unsigned int cur_pkt;
335 } XHCITransfer;
336
337 typedef struct XHCIEPContext {
338 XHCIRing ring;
339 unsigned int next_xfer;
340 unsigned int comp_xfer;
341 XHCITransfer transfers[TD_QUEUE];
342 XHCITransfer *retry;
343 bool bg_running;
344 bool bg_updating;
345 unsigned int next_bg;
346 XHCITransfer bg_transfers[BG_XFERS];
347 EPType type;
348 dma_addr_t pctx;
349 unsigned int max_psize;
350 bool has_bg;
351 uint32_t state;
352 } XHCIEPContext;
353
354 typedef struct XHCISlot {
355 bool enabled;
356 dma_addr_t ctx;
357 unsigned int port;
358 unsigned int devaddr;
359 XHCIEPContext * eps[31];
360 } XHCISlot;
361
362 typedef struct XHCIEvent {
363 TRBType type;
364 TRBCCode ccode;
365 uint64_t ptr;
366 uint32_t length;
367 uint32_t flags;
368 uint8_t slotid;
369 uint8_t epid;
370 } XHCIEvent;
371
372 struct XHCIState {
373 PCIDevice pci_dev;
374 USBBus bus;
375 qemu_irq irq;
376 MemoryRegion mem;
377 const char *name;
378 uint32_t msi;
379 unsigned int devaddr;
380
381 /* Operational Registers */
382 uint32_t usbcmd;
383 uint32_t usbsts;
384 uint32_t dnctrl;
385 uint32_t crcr_low;
386 uint32_t crcr_high;
387 uint32_t dcbaap_low;
388 uint32_t dcbaap_high;
389 uint32_t config;
390
391 XHCIPort ports[MAXPORTS];
392 XHCISlot slots[MAXSLOTS];
393
394 /* Runtime Registers */
395 uint32_t mfindex;
396 /* note: we only support one interrupter */
397 uint32_t iman;
398 uint32_t imod;
399 uint32_t erstsz;
400 uint32_t erstba_low;
401 uint32_t erstba_high;
402 uint32_t erdp_low;
403 uint32_t erdp_high;
404
405 dma_addr_t er_start;
406 uint32_t er_size;
407 bool er_pcs;
408 unsigned int er_ep_idx;
409 bool er_full;
410
411 XHCIEvent ev_buffer[EV_QUEUE];
412 unsigned int ev_buffer_put;
413 unsigned int ev_buffer_get;
414
415 XHCIRing cmd_ring;
416 };
417
418 typedef struct XHCIEvRingSeg {
419 uint32_t addr_low;
420 uint32_t addr_high;
421 uint32_t size;
422 uint32_t rsvd;
423 } XHCIEvRingSeg;
424
425 static const char *TRBType_names[] = {
426 [TRB_RESERVED] = "TRB_RESERVED",
427 [TR_NORMAL] = "TR_NORMAL",
428 [TR_SETUP] = "TR_SETUP",
429 [TR_DATA] = "TR_DATA",
430 [TR_STATUS] = "TR_STATUS",
431 [TR_ISOCH] = "TR_ISOCH",
432 [TR_LINK] = "TR_LINK",
433 [TR_EVDATA] = "TR_EVDATA",
434 [TR_NOOP] = "TR_NOOP",
435 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
436 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
437 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
438 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
439 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
440 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
441 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
442 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
443 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
444 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
445 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
446 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
447 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
448 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
449 [CR_NOOP] = "CR_NOOP",
450 [ER_TRANSFER] = "ER_TRANSFER",
451 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
452 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
453 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
454 [ER_DOORBELL] = "ER_DOORBELL",
455 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
456 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
457 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
458 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
459 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
460 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
461 };
462
463 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
464 {
465 if (index >= llen || list[index] == NULL) {
466 return "???";
467 }
468 return list[index];
469 }
470
471 static const char *trb_name(XHCITRB *trb)
472 {
473 return lookup_name(TRB_TYPE(*trb), TRBType_names,
474 ARRAY_SIZE(TRBType_names));
475 }
476
477 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
478 unsigned int epid);
479
480 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
481 {
482 if (sizeof(dma_addr_t) == 4) {
483 return low;
484 } else {
485 return low | (((dma_addr_t)high << 16) << 16);
486 }
487 }
488
489 static inline dma_addr_t xhci_mask64(uint64_t addr)
490 {
491 if (sizeof(dma_addr_t) == 4) {
492 return addr & 0xffffffff;
493 } else {
494 return addr;
495 }
496 }
497
498 static void xhci_irq_update(XHCIState *xhci)
499 {
500 int level = 0;
501
502 if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
503 xhci->usbcmd & USBCMD_INTE) {
504 level = 1;
505 }
506
507 if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
508 if (level) {
509 trace_usb_xhci_irq_msi(0);
510 msi_notify(&xhci->pci_dev, 0);
511 }
512 } else {
513 trace_usb_xhci_irq_intx(level);
514 qemu_set_irq(xhci->irq, level);
515 }
516 }
517
518 static inline int xhci_running(XHCIState *xhci)
519 {
520 return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
521 }
522
523 static void xhci_die(XHCIState *xhci)
524 {
525 xhci->usbsts |= USBSTS_HCE;
526 fprintf(stderr, "xhci: asserted controller error\n");
527 }
528
529 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event)
530 {
531 XHCITRB ev_trb;
532 dma_addr_t addr;
533
534 ev_trb.parameter = cpu_to_le64(event->ptr);
535 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
536 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
537 event->flags | (event->type << TRB_TYPE_SHIFT);
538 if (xhci->er_pcs) {
539 ev_trb.control |= TRB_C;
540 }
541 ev_trb.control = cpu_to_le32(ev_trb.control);
542
543 trace_usb_xhci_queue_event(xhci->er_ep_idx, trb_name(&ev_trb),
544 ev_trb.parameter, ev_trb.status, ev_trb.control);
545
546 addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx;
547 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
548
549 xhci->er_ep_idx++;
550 if (xhci->er_ep_idx >= xhci->er_size) {
551 xhci->er_ep_idx = 0;
552 xhci->er_pcs = !xhci->er_pcs;
553 }
554 }
555
556 static void xhci_events_update(XHCIState *xhci)
557 {
558 dma_addr_t erdp;
559 unsigned int dp_idx;
560 bool do_irq = 0;
561
562 if (xhci->usbsts & USBSTS_HCH) {
563 return;
564 }
565
566 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
567 if (erdp < xhci->er_start ||
568 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
569 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
570 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
571 xhci->er_start, xhci->er_size);
572 xhci_die(xhci);
573 return;
574 }
575 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
576 assert(dp_idx < xhci->er_size);
577
578 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
579 * deadlocks when the ER is full. Hack it by holding off events until
580 * the driver decides to free at least half of the ring */
581 if (xhci->er_full) {
582 int er_free = dp_idx - xhci->er_ep_idx;
583 if (er_free <= 0) {
584 er_free += xhci->er_size;
585 }
586 if (er_free < (xhci->er_size/2)) {
587 DPRINTF("xhci_events_update(): event ring still "
588 "more than half full (hack)\n");
589 return;
590 }
591 }
592
593 while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
594 assert(xhci->er_full);
595 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) {
596 DPRINTF("xhci_events_update(): event ring full again\n");
597 #ifndef ER_FULL_HACK
598 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
599 xhci_write_event(xhci, &full);
600 #endif
601 do_irq = 1;
602 break;
603 }
604 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get];
605 xhci_write_event(xhci, event);
606 xhci->ev_buffer_get++;
607 do_irq = 1;
608 if (xhci->ev_buffer_get == EV_QUEUE) {
609 xhci->ev_buffer_get = 0;
610 }
611 }
612
613 if (do_irq) {
614 xhci->erdp_low |= ERDP_EHB;
615 xhci->iman |= IMAN_IP;
616 xhci->usbsts |= USBSTS_EINT;
617 xhci_irq_update(xhci);
618 }
619
620 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
621 DPRINTF("xhci_events_update(): event ring no longer full\n");
622 xhci->er_full = 0;
623 }
624 return;
625 }
626
627 static void xhci_event(XHCIState *xhci, XHCIEvent *event)
628 {
629 dma_addr_t erdp;
630 unsigned int dp_idx;
631
632 if (xhci->er_full) {
633 DPRINTF("xhci_event(): ER full, queueing\n");
634 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
635 fprintf(stderr, "xhci: event queue full, dropping event!\n");
636 return;
637 }
638 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
639 if (xhci->ev_buffer_put == EV_QUEUE) {
640 xhci->ev_buffer_put = 0;
641 }
642 return;
643 }
644
645 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
646 if (erdp < xhci->er_start ||
647 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
648 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
649 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
650 xhci->er_start, xhci->er_size);
651 xhci_die(xhci);
652 return;
653 }
654
655 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
656 assert(dp_idx < xhci->er_size);
657
658 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) {
659 DPRINTF("xhci_event(): ER full, queueing\n");
660 #ifndef ER_FULL_HACK
661 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
662 xhci_write_event(xhci, &full);
663 #endif
664 xhci->er_full = 1;
665 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
666 fprintf(stderr, "xhci: event queue full, dropping event!\n");
667 return;
668 }
669 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
670 if (xhci->ev_buffer_put == EV_QUEUE) {
671 xhci->ev_buffer_put = 0;
672 }
673 } else {
674 xhci_write_event(xhci, event);
675 }
676
677 xhci->erdp_low |= ERDP_EHB;
678 xhci->iman |= IMAN_IP;
679 xhci->usbsts |= USBSTS_EINT;
680
681 xhci_irq_update(xhci);
682 }
683
684 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
685 dma_addr_t base)
686 {
687 ring->base = base;
688 ring->dequeue = base;
689 ring->ccs = 1;
690 }
691
692 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
693 dma_addr_t *addr)
694 {
695 while (1) {
696 TRBType type;
697 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
698 trb->addr = ring->dequeue;
699 trb->ccs = ring->ccs;
700 le64_to_cpus(&trb->parameter);
701 le32_to_cpus(&trb->status);
702 le32_to_cpus(&trb->control);
703
704 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
705 trb->parameter, trb->status, trb->control);
706
707 if ((trb->control & TRB_C) != ring->ccs) {
708 return 0;
709 }
710
711 type = TRB_TYPE(*trb);
712
713 if (type != TR_LINK) {
714 if (addr) {
715 *addr = ring->dequeue;
716 }
717 ring->dequeue += TRB_SIZE;
718 return type;
719 } else {
720 ring->dequeue = xhci_mask64(trb->parameter);
721 if (trb->control & TRB_LK_TC) {
722 ring->ccs = !ring->ccs;
723 }
724 }
725 }
726 }
727
728 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
729 {
730 XHCITRB trb;
731 int length = 0;
732 dma_addr_t dequeue = ring->dequeue;
733 bool ccs = ring->ccs;
734 /* hack to bundle together the two/three TDs that make a setup transfer */
735 bool control_td_set = 0;
736
737 while (1) {
738 TRBType type;
739 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
740 le64_to_cpus(&trb.parameter);
741 le32_to_cpus(&trb.status);
742 le32_to_cpus(&trb.control);
743
744 if ((trb.control & TRB_C) != ccs) {
745 return -length;
746 }
747
748 type = TRB_TYPE(trb);
749
750 if (type == TR_LINK) {
751 dequeue = xhci_mask64(trb.parameter);
752 if (trb.control & TRB_LK_TC) {
753 ccs = !ccs;
754 }
755 continue;
756 }
757
758 length += 1;
759 dequeue += TRB_SIZE;
760
761 if (type == TR_SETUP) {
762 control_td_set = 1;
763 } else if (type == TR_STATUS) {
764 control_td_set = 0;
765 }
766
767 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
768 return length;
769 }
770 }
771 }
772
773 static void xhci_er_reset(XHCIState *xhci)
774 {
775 XHCIEvRingSeg seg;
776
777 /* cache the (sole) event ring segment location */
778 if (xhci->erstsz != 1) {
779 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
780 xhci_die(xhci);
781 return;
782 }
783 dma_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high);
784 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
785 le32_to_cpus(&seg.addr_low);
786 le32_to_cpus(&seg.addr_high);
787 le32_to_cpus(&seg.size);
788 if (seg.size < 16 || seg.size > 4096) {
789 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
790 xhci_die(xhci);
791 return;
792 }
793 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
794 xhci->er_size = seg.size;
795
796 xhci->er_ep_idx = 0;
797 xhci->er_pcs = 1;
798 xhci->er_full = 0;
799
800 DPRINTF("xhci: event ring:" DMA_ADDR_FMT " [%d]\n",
801 xhci->er_start, xhci->er_size);
802 }
803
804 static void xhci_run(XHCIState *xhci)
805 {
806 trace_usb_xhci_run();
807 xhci->usbsts &= ~USBSTS_HCH;
808 }
809
810 static void xhci_stop(XHCIState *xhci)
811 {
812 trace_usb_xhci_stop();
813 xhci->usbsts |= USBSTS_HCH;
814 xhci->crcr_low &= ~CRCR_CRR;
815 }
816
817 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
818 uint32_t state)
819 {
820 uint32_t ctx[5];
821 if (epctx->state == state) {
822 return;
823 }
824
825 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
826 ctx[0] &= ~EP_STATE_MASK;
827 ctx[0] |= state;
828 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
829 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
830 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
831 epctx->pctx, state, ctx[3], ctx[2]);
832 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
833 epctx->state = state;
834 }
835
836 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
837 unsigned int epid, dma_addr_t pctx,
838 uint32_t *ctx)
839 {
840 XHCISlot *slot;
841 XHCIEPContext *epctx;
842 dma_addr_t dequeue;
843 int i;
844
845 trace_usb_xhci_ep_enable(slotid, epid);
846 assert(slotid >= 1 && slotid <= MAXSLOTS);
847 assert(epid >= 1 && epid <= 31);
848
849 slot = &xhci->slots[slotid-1];
850 if (slot->eps[epid-1]) {
851 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
852 return CC_TRB_ERROR;
853 }
854
855 epctx = g_malloc(sizeof(XHCIEPContext));
856 memset(epctx, 0, sizeof(XHCIEPContext));
857
858 slot->eps[epid-1] = epctx;
859
860 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
861 xhci_ring_init(xhci, &epctx->ring, dequeue);
862 epctx->ring.ccs = ctx[2] & 1;
863
864 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
865 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
866 epctx->pctx = pctx;
867 epctx->max_psize = ctx[1]>>16;
868 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
869 epctx->has_bg = false;
870 if (epctx->type == ET_ISO_IN) {
871 epctx->has_bg = true;
872 }
873 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
874 epid/2, epid%2, epctx->max_psize);
875 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
876 usb_packet_init(&epctx->transfers[i].packet);
877 }
878
879 epctx->state = EP_RUNNING;
880 ctx[0] &= ~EP_STATE_MASK;
881 ctx[0] |= EP_RUNNING;
882
883 return CC_SUCCESS;
884 }
885
886 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
887 unsigned int epid)
888 {
889 XHCISlot *slot;
890 XHCIEPContext *epctx;
891 int i, xferi, killed = 0;
892 assert(slotid >= 1 && slotid <= MAXSLOTS);
893 assert(epid >= 1 && epid <= 31);
894
895 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
896
897 slot = &xhci->slots[slotid-1];
898
899 if (!slot->eps[epid-1]) {
900 return 0;
901 }
902
903 epctx = slot->eps[epid-1];
904
905 xferi = epctx->next_xfer;
906 for (i = 0; i < TD_QUEUE; i++) {
907 XHCITransfer *t = &epctx->transfers[xferi];
908 if (t->running_async) {
909 usb_cancel_packet(&t->packet);
910 t->running_async = 0;
911 t->cancelled = 1;
912 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
913 killed++;
914 }
915 if (t->running_retry) {
916 t->running_retry = 0;
917 epctx->retry = NULL;
918 }
919 if (t->backgrounded) {
920 t->backgrounded = 0;
921 }
922 if (t->trbs) {
923 g_free(t->trbs);
924 }
925 if (t->data) {
926 g_free(t->data);
927 }
928
929 t->trbs = NULL;
930 t->data = NULL;
931 t->trb_count = t->trb_alloced = 0;
932 t->data_length = t->data_alloced = 0;
933 xferi = (xferi + 1) % TD_QUEUE;
934 }
935 if (epctx->has_bg) {
936 xferi = epctx->next_bg;
937 for (i = 0; i < BG_XFERS; i++) {
938 XHCITransfer *t = &epctx->bg_transfers[xferi];
939 if (t->running_async) {
940 usb_cancel_packet(&t->packet);
941 t->running_async = 0;
942 t->cancelled = 1;
943 DPRINTF("xhci: cancelling bg transfer %d, waiting for it to complete...\n", i);
944 killed++;
945 }
946 if (t->data) {
947 g_free(t->data);
948 }
949
950 t->data = NULL;
951 xferi = (xferi + 1) % BG_XFERS;
952 }
953 }
954 return killed;
955 }
956
957 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
958 unsigned int epid)
959 {
960 XHCISlot *slot;
961 XHCIEPContext *epctx;
962
963 trace_usb_xhci_ep_disable(slotid, epid);
964 assert(slotid >= 1 && slotid <= MAXSLOTS);
965 assert(epid >= 1 && epid <= 31);
966
967 slot = &xhci->slots[slotid-1];
968
969 if (!slot->eps[epid-1]) {
970 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
971 return CC_SUCCESS;
972 }
973
974 xhci_ep_nuke_xfers(xhci, slotid, epid);
975
976 epctx = slot->eps[epid-1];
977
978 xhci_set_ep_state(xhci, epctx, EP_DISABLED);
979
980 g_free(epctx);
981 slot->eps[epid-1] = NULL;
982
983 return CC_SUCCESS;
984 }
985
986 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
987 unsigned int epid)
988 {
989 XHCISlot *slot;
990 XHCIEPContext *epctx;
991
992 trace_usb_xhci_ep_stop(slotid, epid);
993 assert(slotid >= 1 && slotid <= MAXSLOTS);
994
995 if (epid < 1 || epid > 31) {
996 fprintf(stderr, "xhci: bad ep %d\n", epid);
997 return CC_TRB_ERROR;
998 }
999
1000 slot = &xhci->slots[slotid-1];
1001
1002 if (!slot->eps[epid-1]) {
1003 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1004 return CC_EP_NOT_ENABLED_ERROR;
1005 }
1006
1007 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1008 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1009 "data might be lost\n");
1010 }
1011
1012 epctx = slot->eps[epid-1];
1013
1014 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1015
1016 return CC_SUCCESS;
1017 }
1018
1019 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1020 unsigned int epid)
1021 {
1022 XHCISlot *slot;
1023 XHCIEPContext *epctx;
1024 USBDevice *dev;
1025
1026 trace_usb_xhci_ep_reset(slotid, epid);
1027 assert(slotid >= 1 && slotid <= MAXSLOTS);
1028
1029 if (epid < 1 || epid > 31) {
1030 fprintf(stderr, "xhci: bad ep %d\n", epid);
1031 return CC_TRB_ERROR;
1032 }
1033
1034 slot = &xhci->slots[slotid-1];
1035
1036 if (!slot->eps[epid-1]) {
1037 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1038 return CC_EP_NOT_ENABLED_ERROR;
1039 }
1040
1041 epctx = slot->eps[epid-1];
1042
1043 if (epctx->state != EP_HALTED) {
1044 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1045 epid, epctx->state);
1046 return CC_CONTEXT_STATE_ERROR;
1047 }
1048
1049 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1050 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1051 "data might be lost\n");
1052 }
1053
1054 uint8_t ep = epid>>1;
1055
1056 if (epid & 1) {
1057 ep |= 0x80;
1058 }
1059
1060 dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev;
1061 if (!dev) {
1062 return CC_USB_TRANSACTION_ERROR;
1063 }
1064
1065 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1066
1067 return CC_SUCCESS;
1068 }
1069
1070 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1071 unsigned int epid, uint64_t pdequeue)
1072 {
1073 XHCISlot *slot;
1074 XHCIEPContext *epctx;
1075 dma_addr_t dequeue;
1076
1077 assert(slotid >= 1 && slotid <= MAXSLOTS);
1078
1079 if (epid < 1 || epid > 31) {
1080 fprintf(stderr, "xhci: bad ep %d\n", epid);
1081 return CC_TRB_ERROR;
1082 }
1083
1084 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64")\n", slotid, epid, pdequeue);
1085 dequeue = xhci_mask64(pdequeue);
1086
1087 slot = &xhci->slots[slotid-1];
1088
1089 if (!slot->eps[epid-1]) {
1090 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1091 return CC_EP_NOT_ENABLED_ERROR;
1092 }
1093
1094 epctx = slot->eps[epid-1];
1095
1096
1097 if (epctx->state != EP_STOPPED) {
1098 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1099 return CC_CONTEXT_STATE_ERROR;
1100 }
1101
1102 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1103 epctx->ring.ccs = dequeue & 1;
1104
1105 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1106
1107 return CC_SUCCESS;
1108 }
1109
1110 static int xhci_xfer_data(XHCITransfer *xfer, uint8_t *data,
1111 unsigned int length, bool in_xfer, bool out_xfer,
1112 bool report)
1113 {
1114 int i;
1115 uint32_t edtla = 0;
1116 unsigned int transferred = 0;
1117 unsigned int left = length;
1118 bool reported = 0;
1119 bool shortpkt = 0;
1120 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1121 XHCIState *xhci = xfer->xhci;
1122
1123 DPRINTF("xhci_xfer_data(len=%d, in_xfer=%d, out_xfer=%d, report=%d)\n",
1124 length, in_xfer, out_xfer, report);
1125
1126 assert(!(in_xfer && out_xfer));
1127
1128 for (i = 0; i < xfer->trb_count; i++) {
1129 XHCITRB *trb = &xfer->trbs[i];
1130 dma_addr_t addr;
1131 unsigned int chunk = 0;
1132
1133 switch (TRB_TYPE(*trb)) {
1134 case TR_DATA:
1135 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1136 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
1137 xhci_die(xhci);
1138 return transferred;
1139 }
1140 /* fallthrough */
1141 case TR_NORMAL:
1142 case TR_ISOCH:
1143 addr = xhci_mask64(trb->parameter);
1144 chunk = trb->status & 0x1ffff;
1145 if (chunk > left) {
1146 chunk = left;
1147 shortpkt = 1;
1148 }
1149 if (in_xfer || out_xfer) {
1150 if (trb->control & TRB_TR_IDT) {
1151 uint64_t idata;
1152 if (chunk > 8 || in_xfer) {
1153 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1154 xhci_die(xhci);
1155 return transferred;
1156 }
1157 idata = le64_to_cpu(trb->parameter);
1158 memcpy(data, &idata, chunk);
1159 } else {
1160 DPRINTF("xhci_xfer_data: r/w(%d) %d bytes at "
1161 DMA_ADDR_FMT "\n", in_xfer, chunk, addr);
1162 if (in_xfer) {
1163 pci_dma_write(&xhci->pci_dev, addr, data, chunk);
1164 } else {
1165 pci_dma_read(&xhci->pci_dev, addr, data, chunk);
1166 }
1167 #ifdef DEBUG_DATA
1168 unsigned int count = chunk;
1169 int i;
1170 if (count > 16) {
1171 count = 16;
1172 }
1173 DPRINTF(" ::");
1174 for (i = 0; i < count; i++) {
1175 DPRINTF(" %02x", data[i]);
1176 }
1177 DPRINTF("\n");
1178 #endif
1179 }
1180 }
1181 left -= chunk;
1182 data += chunk;
1183 edtla += chunk;
1184 transferred += chunk;
1185 break;
1186 case TR_STATUS:
1187 reported = 0;
1188 shortpkt = 0;
1189 break;
1190 }
1191
1192 if (report && !reported && (trb->control & TRB_TR_IOC ||
1193 (shortpkt && (trb->control & TRB_TR_ISP)))) {
1194 event.slotid = xfer->slotid;
1195 event.epid = xfer->epid;
1196 event.length = (trb->status & 0x1ffff) - chunk;
1197 event.flags = 0;
1198 event.ptr = trb->addr;
1199 if (xfer->status == CC_SUCCESS) {
1200 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1201 } else {
1202 event.ccode = xfer->status;
1203 }
1204 if (TRB_TYPE(*trb) == TR_EVDATA) {
1205 event.ptr = trb->parameter;
1206 event.flags |= TRB_EV_ED;
1207 event.length = edtla & 0xffffff;
1208 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1209 edtla = 0;
1210 }
1211 xhci_event(xhci, &event);
1212 reported = 1;
1213 }
1214 }
1215 return transferred;
1216 }
1217
1218 static void xhci_stall_ep(XHCITransfer *xfer)
1219 {
1220 XHCIState *xhci = xfer->xhci;
1221 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1222 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1223
1224 epctx->ring.dequeue = xfer->trbs[0].addr;
1225 epctx->ring.ccs = xfer->trbs[0].ccs;
1226 xhci_set_ep_state(xhci, epctx, EP_HALTED);
1227 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
1228 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue);
1229 }
1230
1231 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1232 XHCIEPContext *epctx);
1233
1234 static void xhci_bg_update(XHCIState *xhci, XHCIEPContext *epctx)
1235 {
1236 if (epctx->bg_updating) {
1237 return;
1238 }
1239 DPRINTF("xhci_bg_update(%p, %p)\n", xhci, epctx);
1240 assert(epctx->has_bg);
1241 DPRINTF("xhci: fg=%d bg=%d\n", epctx->comp_xfer, epctx->next_bg);
1242 epctx->bg_updating = 1;
1243 while (epctx->transfers[epctx->comp_xfer].backgrounded &&
1244 epctx->bg_transfers[epctx->next_bg].complete) {
1245 XHCITransfer *fg = &epctx->transfers[epctx->comp_xfer];
1246 XHCITransfer *bg = &epctx->bg_transfers[epctx->next_bg];
1247 #if 0
1248 DPRINTF("xhci: completing fg %d from bg %d.%d (stat: %d)\n",
1249 epctx->comp_xfer, epctx->next_bg, bg->cur_pkt,
1250 bg->usbxfer->iso_packet_desc[bg->cur_pkt].status
1251 );
1252 #endif
1253 assert(epctx->type == ET_ISO_IN);
1254 assert(bg->iso_xfer);
1255 assert(bg->in_xfer);
1256 uint8_t *p = bg->data + bg->cur_pkt * bg->pktsize;
1257 #if 0
1258 int len = bg->usbxfer->iso_packet_desc[bg->cur_pkt].actual_length;
1259 fg->status = libusb_to_ccode(bg->usbxfer->iso_packet_desc[bg->cur_pkt].status);
1260 #else
1261 int len = 0;
1262 FIXME();
1263 #endif
1264 fg->complete = 1;
1265 fg->backgrounded = 0;
1266
1267 if (fg->status == CC_STALL_ERROR) {
1268 xhci_stall_ep(fg);
1269 }
1270
1271 xhci_xfer_data(fg, p, len, 1, 0, 1);
1272
1273 epctx->comp_xfer++;
1274 if (epctx->comp_xfer == TD_QUEUE) {
1275 epctx->comp_xfer = 0;
1276 }
1277 DPRINTF("next fg xfer: %d\n", epctx->comp_xfer);
1278 bg->cur_pkt++;
1279 if (bg->cur_pkt == bg->pkts) {
1280 bg->complete = 0;
1281 if (xhci_submit(xhci, bg, epctx) < 0) {
1282 fprintf(stderr, "xhci: bg resubmit failed\n");
1283 }
1284 epctx->next_bg++;
1285 if (epctx->next_bg == BG_XFERS) {
1286 epctx->next_bg = 0;
1287 }
1288 DPRINTF("next bg xfer: %d\n", epctx->next_bg);
1289
1290 xhci_kick_ep(xhci, fg->slotid, fg->epid);
1291 }
1292 }
1293 epctx->bg_updating = 0;
1294 }
1295
1296 #if 0
1297 static void xhci_xfer_cb(struct libusb_transfer *transfer)
1298 {
1299 XHCIState *xhci;
1300 XHCITransfer *xfer;
1301
1302 xfer = (XHCITransfer *)transfer->user_data;
1303 xhci = xfer->xhci;
1304
1305 DPRINTF("xhci_xfer_cb(slot=%d, ep=%d, status=%d)\n", xfer->slotid,
1306 xfer->epid, transfer->status);
1307
1308 assert(xfer->slotid >= 1 && xfer->slotid <= MAXSLOTS);
1309 assert(xfer->epid >= 1 && xfer->epid <= 31);
1310
1311 if (xfer->cancelled) {
1312 DPRINTF("xhci: transfer cancelled, not reporting anything\n");
1313 xfer->running = 0;
1314 return;
1315 }
1316
1317 XHCIEPContext *epctx;
1318 XHCISlot *slot;
1319 slot = &xhci->slots[xfer->slotid-1];
1320 assert(slot->eps[xfer->epid-1]);
1321 epctx = slot->eps[xfer->epid-1];
1322
1323 if (xfer->bg_xfer) {
1324 DPRINTF("xhci: background transfer, updating\n");
1325 xfer->complete = 1;
1326 xfer->running = 0;
1327 xhci_bg_update(xhci, epctx);
1328 return;
1329 }
1330
1331 if (xfer->iso_xfer) {
1332 transfer->status = transfer->iso_packet_desc[0].status;
1333 transfer->actual_length = transfer->iso_packet_desc[0].actual_length;
1334 }
1335
1336 xfer->status = libusb_to_ccode(transfer->status);
1337
1338 xfer->complete = 1;
1339 xfer->running = 0;
1340
1341 if (transfer->status == LIBUSB_TRANSFER_STALL)
1342 xhci_stall_ep(xhci, epctx, xfer);
1343
1344 DPRINTF("xhci: transfer actual length = %d\n", transfer->actual_length);
1345
1346 if (xfer->in_xfer) {
1347 if (xfer->epid == 1) {
1348 xhci_xfer_data(xhci, xfer, xfer->data + 8,
1349 transfer->actual_length, 1, 0, 1);
1350 } else {
1351 xhci_xfer_data(xhci, xfer, xfer->data,
1352 transfer->actual_length, 1, 0, 1);
1353 }
1354 } else {
1355 xhci_xfer_data(xhci, xfer, NULL, transfer->actual_length, 0, 0, 1);
1356 }
1357
1358 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1359 }
1360
1361 static int xhci_hle_control(XHCIState *xhci, XHCITransfer *xfer,
1362 uint8_t bmRequestType, uint8_t bRequest,
1363 uint16_t wValue, uint16_t wIndex, uint16_t wLength)
1364 {
1365 uint16_t type_req = (bmRequestType << 8) | bRequest;
1366
1367 switch (type_req) {
1368 case 0x0000 | USB_REQ_SET_CONFIGURATION:
1369 DPRINTF("xhci: HLE switch configuration\n");
1370 return xhci_switch_config(xhci, xfer->slotid, wValue) == 0;
1371 case 0x0100 | USB_REQ_SET_INTERFACE:
1372 DPRINTF("xhci: HLE set interface altsetting\n");
1373 return xhci_set_iface_alt(xhci, xfer->slotid, wIndex, wValue) == 0;
1374 case 0x0200 | USB_REQ_CLEAR_FEATURE:
1375 if (wValue == 0) { // endpoint halt
1376 DPRINTF("xhci: HLE clear halt\n");
1377 return xhci_clear_halt(xhci, xfer->slotid, wIndex);
1378 }
1379 case 0x0000 | USB_REQ_SET_ADDRESS:
1380 fprintf(stderr, "xhci: warn: illegal SET_ADDRESS request\n");
1381 return 0;
1382 default:
1383 return 0;
1384 }
1385 }
1386 #endif
1387
1388 static int xhci_setup_packet(XHCITransfer *xfer, USBDevice *dev)
1389 {
1390 USBEndpoint *ep;
1391 int dir;
1392
1393 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1394 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1395 usb_packet_setup(&xfer->packet, dir, ep);
1396 usb_packet_addbuf(&xfer->packet, xfer->data, xfer->data_length);
1397 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1398 xfer->packet.pid, dev->addr, ep->nr);
1399 return 0;
1400 }
1401
1402 static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1403 {
1404 if (ret == USB_RET_ASYNC) {
1405 xfer->running_async = 1;
1406 xfer->running_retry = 0;
1407 xfer->complete = 0;
1408 xfer->cancelled = 0;
1409 return 0;
1410 } else if (ret == USB_RET_NAK) {
1411 xfer->running_async = 0;
1412 xfer->running_retry = 1;
1413 xfer->complete = 0;
1414 xfer->cancelled = 0;
1415 return 0;
1416 } else {
1417 xfer->running_async = 0;
1418 xfer->running_retry = 0;
1419 xfer->complete = 1;
1420 }
1421
1422 if (ret >= 0) {
1423 xfer->status = CC_SUCCESS;
1424 xhci_xfer_data(xfer, xfer->data, ret, xfer->in_xfer, 0, 1);
1425 return 0;
1426 }
1427
1428 /* error */
1429 switch (ret) {
1430 case USB_RET_NODEV:
1431 xfer->status = CC_USB_TRANSACTION_ERROR;
1432 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1433 xhci_stall_ep(xfer);
1434 break;
1435 case USB_RET_STALL:
1436 xfer->status = CC_STALL_ERROR;
1437 xhci_xfer_data(xfer, xfer->data, 0, xfer->in_xfer, 0, 1);
1438 xhci_stall_ep(xfer);
1439 break;
1440 default:
1441 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1442 FIXME();
1443 }
1444 return 0;
1445 }
1446
1447 static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
1448 {
1449 if (!(port->portsc & PORTSC_PED)) {
1450 return NULL;
1451 }
1452 return usb_find_device(&port->port, addr);
1453 }
1454
1455 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1456 {
1457 XHCITRB *trb_setup, *trb_status;
1458 uint8_t bmRequestType;
1459 uint16_t wLength;
1460 XHCIPort *port;
1461 USBDevice *dev;
1462 int ret;
1463
1464 DPRINTF("xhci_fire_ctl_transfer(slot=%d)\n", xfer->slotid);
1465
1466 trb_setup = &xfer->trbs[0];
1467 trb_status = &xfer->trbs[xfer->trb_count-1];
1468
1469 /* at most one Event Data TRB allowed after STATUS */
1470 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1471 trb_status--;
1472 }
1473
1474 /* do some sanity checks */
1475 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1476 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1477 TRB_TYPE(*trb_setup));
1478 return -1;
1479 }
1480 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1481 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1482 TRB_TYPE(*trb_status));
1483 return -1;
1484 }
1485 if (!(trb_setup->control & TRB_TR_IDT)) {
1486 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1487 return -1;
1488 }
1489 if ((trb_setup->status & 0x1ffff) != 8) {
1490 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1491 (trb_setup->status & 0x1ffff));
1492 return -1;
1493 }
1494
1495 bmRequestType = trb_setup->parameter;
1496 wLength = trb_setup->parameter >> 48;
1497
1498 if (xfer->data && xfer->data_alloced < wLength) {
1499 xfer->data_alloced = 0;
1500 g_free(xfer->data);
1501 xfer->data = NULL;
1502 }
1503 if (!xfer->data) {
1504 DPRINTF("xhci: alloc %d bytes data\n", wLength);
1505 xfer->data = g_malloc(wLength+1);
1506 xfer->data_alloced = wLength;
1507 }
1508 xfer->data_length = wLength;
1509
1510 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1511 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1512 if (!dev) {
1513 fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1514 xhci->slots[xfer->slotid-1].port);
1515 return -1;
1516 }
1517
1518 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1519 xfer->iso_xfer = false;
1520
1521 xhci_setup_packet(xfer, dev);
1522 xfer->packet.parameter = trb_setup->parameter;
1523 if (!xfer->in_xfer) {
1524 xhci_xfer_data(xfer, xfer->data, wLength, 0, 1, 0);
1525 }
1526
1527 ret = usb_handle_packet(dev, &xfer->packet);
1528
1529 xhci_complete_packet(xfer, ret);
1530 if (!xfer->running_async && !xfer->running_retry) {
1531 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1532 }
1533 return 0;
1534 }
1535
1536 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1537 {
1538 XHCIPort *port;
1539 USBDevice *dev;
1540 int ret;
1541
1542 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1543
1544 xfer->in_xfer = epctx->type>>2;
1545
1546 if (xfer->data && xfer->data_alloced < xfer->data_length) {
1547 xfer->data_alloced = 0;
1548 g_free(xfer->data);
1549 xfer->data = NULL;
1550 }
1551 if (!xfer->data && xfer->data_length) {
1552 DPRINTF("xhci: alloc %d bytes data\n", xfer->data_length);
1553 xfer->data = g_malloc(xfer->data_length);
1554 xfer->data_alloced = xfer->data_length;
1555 }
1556 if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {
1557 if (!xfer->bg_xfer) {
1558 xfer->pkts = 1;
1559 }
1560 } else {
1561 xfer->pkts = 0;
1562 }
1563
1564 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1565 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1566 if (!dev) {
1567 fprintf(stderr, "xhci: slot %d port %d has no device\n", xfer->slotid,
1568 xhci->slots[xfer->slotid-1].port);
1569 return -1;
1570 }
1571
1572 xhci_setup_packet(xfer, dev);
1573
1574 switch(epctx->type) {
1575 case ET_INTR_OUT:
1576 case ET_INTR_IN:
1577 case ET_BULK_OUT:
1578 case ET_BULK_IN:
1579 break;
1580 case ET_ISO_OUT:
1581 case ET_ISO_IN:
1582 FIXME();
1583 break;
1584 default:
1585 fprintf(stderr, "xhci: unknown or unhandled EP "
1586 "(type %d, in %d, ep %02x)\n",
1587 epctx->type, xfer->in_xfer, xfer->epid);
1588 return -1;
1589 }
1590
1591 if (!xfer->in_xfer) {
1592 xhci_xfer_data(xfer, xfer->data, xfer->data_length, 0, 1, 0);
1593 }
1594 ret = usb_handle_packet(dev, &xfer->packet);
1595
1596 xhci_complete_packet(xfer, ret);
1597 if (!xfer->running_async && !xfer->running_retry) {
1598 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1599 }
1600 return 0;
1601 }
1602
1603 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1604 {
1605 int i;
1606 unsigned int length = 0;
1607 XHCITRB *trb;
1608
1609 DPRINTF("xhci_fire_transfer(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1610
1611 for (i = 0; i < xfer->trb_count; i++) {
1612 trb = &xfer->trbs[i];
1613 if (TRB_TYPE(*trb) == TR_NORMAL || TRB_TYPE(*trb) == TR_ISOCH) {
1614 length += trb->status & 0x1ffff;
1615 }
1616 }
1617 DPRINTF("xhci: total TD length=%d\n", length);
1618
1619 if (!epctx->has_bg) {
1620 xfer->data_length = length;
1621 xfer->backgrounded = 0;
1622 return xhci_submit(xhci, xfer, epctx);
1623 } else {
1624 if (!epctx->bg_running) {
1625 for (i = 0; i < BG_XFERS; i++) {
1626 XHCITransfer *t = &epctx->bg_transfers[i];
1627 t->xhci = xhci;
1628 t->epid = xfer->epid;
1629 t->slotid = xfer->slotid;
1630 t->pkts = BG_PKTS;
1631 t->pktsize = epctx->max_psize;
1632 t->data_length = t->pkts * t->pktsize;
1633 t->bg_xfer = 1;
1634 if (xhci_submit(xhci, t, epctx) < 0) {
1635 fprintf(stderr, "xhci: bg submit failed\n");
1636 return -1;
1637 }
1638 }
1639 epctx->bg_running = 1;
1640 }
1641 xfer->backgrounded = 1;
1642 xhci_bg_update(xhci, epctx);
1643 return 0;
1644 }
1645 }
1646
1647 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1648 {
1649 XHCIEPContext *epctx;
1650 int length;
1651 int i;
1652
1653 trace_usb_xhci_ep_kick(slotid, epid);
1654 assert(slotid >= 1 && slotid <= MAXSLOTS);
1655 assert(epid >= 1 && epid <= 31);
1656
1657 if (!xhci->slots[slotid-1].enabled) {
1658 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1659 return;
1660 }
1661 epctx = xhci->slots[slotid-1].eps[epid-1];
1662 if (!epctx) {
1663 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1664 epid, slotid);
1665 return;
1666 }
1667
1668 if (epctx->retry) {
1669 /* retry nak'ed transfer */
1670 XHCITransfer *xfer = epctx->retry;
1671 int result;
1672
1673 DPRINTF("xhci: retry nack'ed transfer ...\n");
1674 assert(xfer->running_retry);
1675 xhci_setup_packet(xfer, xfer->packet.ep->dev);
1676 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1677 if (result == USB_RET_NAK) {
1678 DPRINTF("xhci: ... xfer still nacked\n");
1679 return;
1680 }
1681 DPRINTF("xhci: ... result %d\n", result);
1682 xhci_complete_packet(xfer, result);
1683 assert(!xfer->running_retry);
1684 epctx->retry = NULL;
1685 }
1686
1687 if (epctx->state == EP_HALTED) {
1688 DPRINTF("xhci: ep halted, not running schedule\n");
1689 return;
1690 }
1691
1692 xhci_set_ep_state(xhci, epctx, EP_RUNNING);
1693
1694 while (1) {
1695 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
1696 if (xfer->running_async || xfer->running_retry || xfer->backgrounded) {
1697 break;
1698 }
1699 length = xhci_ring_chain_length(xhci, &epctx->ring);
1700 if (length < 0) {
1701 break;
1702 } else if (length == 0) {
1703 break;
1704 }
1705 if (xfer->trbs && xfer->trb_alloced < length) {
1706 xfer->trb_count = 0;
1707 xfer->trb_alloced = 0;
1708 g_free(xfer->trbs);
1709 xfer->trbs = NULL;
1710 }
1711 if (!xfer->trbs) {
1712 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1713 xfer->trb_alloced = length;
1714 }
1715 xfer->trb_count = length;
1716
1717 for (i = 0; i < length; i++) {
1718 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
1719 }
1720 xfer->xhci = xhci;
1721 xfer->epid = epid;
1722 xfer->slotid = slotid;
1723
1724 if (epid == 1) {
1725 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1726 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1727 } else {
1728 fprintf(stderr, "xhci: error firing CTL transfer\n");
1729 }
1730 } else {
1731 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1732 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1733 } else {
1734 fprintf(stderr, "xhci: error firing data transfer\n");
1735 }
1736 }
1737
1738 if (epctx->state == EP_HALTED) {
1739 break;
1740 }
1741 if (xfer->running_retry) {
1742 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1743 epctx->retry = xfer;
1744 break;
1745 }
1746 }
1747 }
1748
1749 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1750 {
1751 assert(slotid >= 1 && slotid <= MAXSLOTS);
1752 DPRINTF("xhci_enable_slot(%d)\n", slotid);
1753 xhci->slots[slotid-1].enabled = 1;
1754 xhci->slots[slotid-1].port = 0;
1755 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1756
1757 return CC_SUCCESS;
1758 }
1759
1760 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1761 {
1762 int i;
1763
1764 assert(slotid >= 1 && slotid <= MAXSLOTS);
1765 DPRINTF("xhci_disable_slot(%d)\n", slotid);
1766
1767 for (i = 1; i <= 31; i++) {
1768 if (xhci->slots[slotid-1].eps[i-1]) {
1769 xhci_disable_ep(xhci, slotid, i);
1770 }
1771 }
1772
1773 xhci->slots[slotid-1].enabled = 0;
1774 return CC_SUCCESS;
1775 }
1776
1777 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1778 uint64_t pictx, bool bsr)
1779 {
1780 XHCISlot *slot;
1781 USBDevice *dev;
1782 dma_addr_t ictx, octx, dcbaap;
1783 uint64_t poctx;
1784 uint32_t ictl_ctx[2];
1785 uint32_t slot_ctx[4];
1786 uint32_t ep0_ctx[5];
1787 unsigned int port;
1788 int i;
1789 TRBCCode res;
1790
1791 assert(slotid >= 1 && slotid <= MAXSLOTS);
1792 DPRINTF("xhci_address_slot(%d)\n", slotid);
1793
1794 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
1795 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx));
1796 ictx = xhci_mask64(pictx);
1797 octx = xhci_mask64(le64_to_cpu(poctx));
1798
1799 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1800 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1801
1802 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1803
1804 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1805 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1806 ictl_ctx[0], ictl_ctx[1]);
1807 return CC_TRB_ERROR;
1808 }
1809
1810 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx));
1811 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx));
1812
1813 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1814 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1815
1816 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1817 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1818
1819 port = (slot_ctx[1]>>16) & 0xFF;
1820 dev = xhci->ports[port-1].port.dev;
1821
1822 if (port < 1 || port > MAXPORTS) {
1823 fprintf(stderr, "xhci: bad port %d\n", port);
1824 return CC_TRB_ERROR;
1825 } else if (!dev) {
1826 fprintf(stderr, "xhci: port %d not connected\n", port);
1827 return CC_USB_TRANSACTION_ERROR;
1828 }
1829
1830 for (i = 0; i < MAXSLOTS; i++) {
1831 if (xhci->slots[i].port == port) {
1832 fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
1833 port, i+1);
1834 return CC_TRB_ERROR;
1835 }
1836 }
1837
1838 slot = &xhci->slots[slotid-1];
1839 slot->port = port;
1840 slot->ctx = octx;
1841
1842 if (bsr) {
1843 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
1844 } else {
1845 slot->devaddr = xhci->devaddr++;
1846 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
1847 DPRINTF("xhci: device address is %d\n", slot->devaddr);
1848 usb_device_handle_control(dev, NULL,
1849 DeviceOutRequest | USB_REQ_SET_ADDRESS,
1850 slot->devaddr, 0, 0, NULL);
1851 }
1852
1853 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1854
1855 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1856 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1857 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1858 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1859
1860 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1861 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1862
1863 return res;
1864 }
1865
1866
1867 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1868 uint64_t pictx, bool dc)
1869 {
1870 dma_addr_t ictx, octx;
1871 uint32_t ictl_ctx[2];
1872 uint32_t slot_ctx[4];
1873 uint32_t islot_ctx[4];
1874 uint32_t ep_ctx[5];
1875 int i;
1876 TRBCCode res;
1877
1878 assert(slotid >= 1 && slotid <= MAXSLOTS);
1879 DPRINTF("xhci_configure_slot(%d)\n", slotid);
1880
1881 ictx = xhci_mask64(pictx);
1882 octx = xhci->slots[slotid-1].ctx;
1883
1884 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1885 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1886
1887 if (dc) {
1888 for (i = 2; i <= 31; i++) {
1889 if (xhci->slots[slotid-1].eps[i-1]) {
1890 xhci_disable_ep(xhci, slotid, i);
1891 }
1892 }
1893
1894 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1895 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1896 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
1897 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1898 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1899 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1900
1901 return CC_SUCCESS;
1902 }
1903
1904 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1905
1906 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1907 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1908 ictl_ctx[0], ictl_ctx[1]);
1909 return CC_TRB_ERROR;
1910 }
1911
1912 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1913 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1914
1915 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
1916 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1917 return CC_CONTEXT_STATE_ERROR;
1918 }
1919
1920 for (i = 2; i <= 31; i++) {
1921 if (ictl_ctx[0] & (1<<i)) {
1922 xhci_disable_ep(xhci, slotid, i);
1923 }
1924 if (ictl_ctx[1] & (1<<i)) {
1925 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx,
1926 sizeof(ep_ctx));
1927 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1928 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1929 ep_ctx[3], ep_ctx[4]);
1930 xhci_disable_ep(xhci, slotid, i);
1931 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1932 if (res != CC_SUCCESS) {
1933 return res;
1934 }
1935 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1936 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1937 ep_ctx[3], ep_ctx[4]);
1938 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx));
1939 }
1940 }
1941
1942 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1943 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
1944 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
1945 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
1946 SLOT_CONTEXT_ENTRIES_SHIFT);
1947 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1948 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1949
1950 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1951
1952 return CC_SUCCESS;
1953 }
1954
1955
1956 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1957 uint64_t pictx)
1958 {
1959 dma_addr_t ictx, octx;
1960 uint32_t ictl_ctx[2];
1961 uint32_t iep0_ctx[5];
1962 uint32_t ep0_ctx[5];
1963 uint32_t islot_ctx[4];
1964 uint32_t slot_ctx[4];
1965
1966 assert(slotid >= 1 && slotid <= MAXSLOTS);
1967 DPRINTF("xhci_evaluate_slot(%d)\n", slotid);
1968
1969 ictx = xhci_mask64(pictx);
1970 octx = xhci->slots[slotid-1].ctx;
1971
1972 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1973 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1974
1975 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1976
1977 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1978 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1979 ictl_ctx[0], ictl_ctx[1]);
1980 return CC_TRB_ERROR;
1981 }
1982
1983 if (ictl_ctx[1] & 0x1) {
1984 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1985
1986 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1987 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
1988
1989 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1990
1991 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
1992 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
1993 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
1994 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
1995
1996 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1997 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1998
1999 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
2000 }
2001
2002 if (ictl_ctx[1] & 0x2) {
2003 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2004
2005 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2006 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2007 iep0_ctx[3], iep0_ctx[4]);
2008
2009 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
2010
2011 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2012 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2013
2014 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2015 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2016
2017 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
2018 }
2019
2020 return CC_SUCCESS;
2021 }
2022
2023 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2024 {
2025 uint32_t slot_ctx[4];
2026 dma_addr_t octx;
2027 int i;
2028
2029 assert(slotid >= 1 && slotid <= MAXSLOTS);
2030 DPRINTF("xhci_reset_slot(%d)\n", slotid);
2031
2032 octx = xhci->slots[slotid-1].ctx;
2033
2034 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2035
2036 for (i = 2; i <= 31; i++) {
2037 if (xhci->slots[slotid-1].eps[i-1]) {
2038 xhci_disable_ep(xhci, slotid, i);
2039 }
2040 }
2041
2042 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
2043 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2044 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2045 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2046 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2047 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
2048
2049 return CC_SUCCESS;
2050 }
2051
2052 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2053 {
2054 unsigned int slotid;
2055 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2056 if (slotid < 1 || slotid > MAXSLOTS) {
2057 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
2058 event->ccode = CC_TRB_ERROR;
2059 return 0;
2060 } else if (!xhci->slots[slotid-1].enabled) {
2061 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
2062 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2063 return 0;
2064 }
2065 return slotid;
2066 }
2067
2068 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2069 {
2070 dma_addr_t ctx;
2071 uint8_t bw_ctx[MAXPORTS+1];
2072
2073 DPRINTF("xhci_get_port_bandwidth()\n");
2074
2075 ctx = xhci_mask64(pctx);
2076
2077 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2078
2079 /* TODO: actually implement real values here */
2080 bw_ctx[0] = 0;
2081 memset(&bw_ctx[1], 80, MAXPORTS); /* 80% */
2082 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
2083
2084 return CC_SUCCESS;
2085 }
2086
2087 static uint32_t rotl(uint32_t v, unsigned count)
2088 {
2089 count &= 31;
2090 return (v << count) | (v >> (32 - count));
2091 }
2092
2093
2094 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2095 {
2096 uint32_t val;
2097 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2098 val += rotl(lo + 0x49434878, hi & 0x1F);
2099 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2100 return ~val;
2101 }
2102
2103 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2104 {
2105 uint32_t buf[8];
2106 uint32_t obuf[8];
2107 dma_addr_t paddr = xhci_mask64(addr);
2108
2109 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
2110
2111 memcpy(obuf, buf, sizeof(obuf));
2112
2113 if ((buf[0] & 0xff) == 2) {
2114 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2115 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2116 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2117 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2118 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2119 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2120 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2121 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2122 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2123 }
2124
2125 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
2126 }
2127
2128 static void xhci_process_commands(XHCIState *xhci)
2129 {
2130 XHCITRB trb;
2131 TRBType type;
2132 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2133 dma_addr_t addr;
2134 unsigned int i, slotid = 0;
2135
2136 DPRINTF("xhci_process_commands()\n");
2137 if (!xhci_running(xhci)) {
2138 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2139 return;
2140 }
2141
2142 xhci->crcr_low |= CRCR_CRR;
2143
2144 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2145 event.ptr = addr;
2146 switch (type) {
2147 case CR_ENABLE_SLOT:
2148 for (i = 0; i < MAXSLOTS; i++) {
2149 if (!xhci->slots[i].enabled) {
2150 break;
2151 }
2152 }
2153 if (i >= MAXSLOTS) {
2154 fprintf(stderr, "xhci: no device slots available\n");
2155 event.ccode = CC_NO_SLOTS_ERROR;
2156 } else {
2157 slotid = i+1;
2158 event.ccode = xhci_enable_slot(xhci, slotid);
2159 }
2160 break;
2161 case CR_DISABLE_SLOT:
2162 slotid = xhci_get_slot(xhci, &event, &trb);
2163 if (slotid) {
2164 event.ccode = xhci_disable_slot(xhci, slotid);
2165 }
2166 break;
2167 case CR_ADDRESS_DEVICE:
2168 slotid = xhci_get_slot(xhci, &event, &trb);
2169 if (slotid) {
2170 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2171 trb.control & TRB_CR_BSR);
2172 }
2173 break;
2174 case CR_CONFIGURE_ENDPOINT:
2175 slotid = xhci_get_slot(xhci, &event, &trb);
2176 if (slotid) {
2177 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2178 trb.control & TRB_CR_DC);
2179 }
2180 break;
2181 case CR_EVALUATE_CONTEXT:
2182 slotid = xhci_get_slot(xhci, &event, &trb);
2183 if (slotid) {
2184 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2185 }
2186 break;
2187 case CR_STOP_ENDPOINT:
2188 slotid = xhci_get_slot(xhci, &event, &trb);
2189 if (slotid) {
2190 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2191 & TRB_CR_EPID_MASK;
2192 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2193 }
2194 break;
2195 case CR_RESET_ENDPOINT:
2196 slotid = xhci_get_slot(xhci, &event, &trb);
2197 if (slotid) {
2198 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2199 & TRB_CR_EPID_MASK;
2200 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2201 }
2202 break;
2203 case CR_SET_TR_DEQUEUE:
2204 slotid = xhci_get_slot(xhci, &event, &trb);
2205 if (slotid) {
2206 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2207 & TRB_CR_EPID_MASK;
2208 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
2209 trb.parameter);
2210 }
2211 break;
2212 case CR_RESET_DEVICE:
2213 slotid = xhci_get_slot(xhci, &event, &trb);
2214 if (slotid) {
2215 event.ccode = xhci_reset_slot(xhci, slotid);
2216 }
2217 break;
2218 case CR_GET_PORT_BANDWIDTH:
2219 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2220 break;
2221 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2222 xhci_via_challenge(xhci, trb.parameter);
2223 break;
2224 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2225 event.type = 48; /* NEC reply */
2226 event.length = 0x3025;
2227 break;
2228 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2229 {
2230 uint32_t chi = trb.parameter >> 32;
2231 uint32_t clo = trb.parameter;
2232 uint32_t val = xhci_nec_challenge(chi, clo);
2233 event.length = val & 0xFFFF;
2234 event.epid = val >> 16;
2235 slotid = val >> 24;
2236 event.type = 48; /* NEC reply */
2237 }
2238 break;
2239 default:
2240 fprintf(stderr, "xhci: unimplemented command %d\n", type);
2241 event.ccode = CC_TRB_ERROR;
2242 break;
2243 }
2244 event.slotid = slotid;
2245 xhci_event(xhci, &event);
2246 }
2247 }
2248
2249 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2250 {
2251 int nr = port->port.index + 1;
2252
2253 port->portsc = PORTSC_PP;
2254 if (port->port.dev && port->port.dev->attached && !is_detach) {
2255 port->portsc |= PORTSC_CCS;
2256 switch (port->port.dev->speed) {
2257 case USB_SPEED_LOW:
2258 port->portsc |= PORTSC_SPEED_LOW;
2259 break;
2260 case USB_SPEED_FULL:
2261 port->portsc |= PORTSC_SPEED_FULL;
2262 break;
2263 case USB_SPEED_HIGH:
2264 port->portsc |= PORTSC_SPEED_HIGH;
2265 break;
2266 }
2267 }
2268
2269 if (xhci_running(xhci)) {
2270 port->portsc |= PORTSC_CSC;
2271 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2272 xhci_event(xhci, &ev);
2273 DPRINTF("xhci: port change event for port %d\n", nr);
2274 }
2275 }
2276
2277 static void xhci_reset(DeviceState *dev)
2278 {
2279 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
2280 int i;
2281
2282 trace_usb_xhci_reset();
2283 if (!(xhci->usbsts & USBSTS_HCH)) {
2284 fprintf(stderr, "xhci: reset while running!\n");
2285 }
2286
2287 xhci->usbcmd = 0;
2288 xhci->usbsts = USBSTS_HCH;
2289 xhci->dnctrl = 0;
2290 xhci->crcr_low = 0;
2291 xhci->crcr_high = 0;
2292 xhci->dcbaap_low = 0;
2293 xhci->dcbaap_high = 0;
2294 xhci->config = 0;
2295 xhci->devaddr = 2;
2296
2297 for (i = 0; i < MAXSLOTS; i++) {
2298 xhci_disable_slot(xhci, i+1);
2299 }
2300
2301 for (i = 0; i < MAXPORTS; i++) {
2302 xhci_update_port(xhci, xhci->ports + i, 0);
2303 }
2304
2305 xhci->mfindex = 0;
2306 xhci->iman = 0;
2307 xhci->imod = 0;
2308 xhci->erstsz = 0;
2309 xhci->erstba_low = 0;
2310 xhci->erstba_high = 0;
2311 xhci->erdp_low = 0;
2312 xhci->erdp_high = 0;
2313
2314 xhci->er_ep_idx = 0;
2315 xhci->er_pcs = 1;
2316 xhci->er_full = 0;
2317 xhci->ev_buffer_put = 0;
2318 xhci->ev_buffer_get = 0;
2319 }
2320
2321 static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2322 {
2323 uint32_t ret;
2324
2325 switch (reg) {
2326 case 0x00: /* HCIVERSION, CAPLENGTH */
2327 ret = 0x01000000 | LEN_CAP;
2328 break;
2329 case 0x04: /* HCSPARAMS 1 */
2330 ret = (MAXPORTS<<24) | (MAXINTRS<<8) | MAXSLOTS;
2331 break;
2332 case 0x08: /* HCSPARAMS 2 */
2333 ret = 0x0000000f;
2334 break;
2335 case 0x0c: /* HCSPARAMS 3 */
2336 ret = 0x00000000;
2337 break;
2338 case 0x10: /* HCCPARAMS */
2339 if (sizeof(dma_addr_t) == 4) {
2340 ret = 0x00081000;
2341 } else {
2342 ret = 0x00081001;
2343 }
2344 break;
2345 case 0x14: /* DBOFF */
2346 ret = OFF_DOORBELL;
2347 break;
2348 case 0x18: /* RTSOFF */
2349 ret = OFF_RUNTIME;
2350 break;
2351
2352 /* extended capabilities */
2353 case 0x20: /* Supported Protocol:00 */
2354 ret = 0x02000402; /* USB 2.0 */
2355 break;
2356 case 0x24: /* Supported Protocol:04 */
2357 ret = 0x20425455; /* "USB " */
2358 break;
2359 case 0x28: /* Supported Protocol:08 */
2360 ret = 0x00000001 | (USB2_PORTS<<8);
2361 break;
2362 case 0x2c: /* Supported Protocol:0c */
2363 ret = 0x00000000; /* reserved */
2364 break;
2365 case 0x30: /* Supported Protocol:00 */
2366 ret = 0x03000002; /* USB 3.0 */
2367 break;
2368 case 0x34: /* Supported Protocol:04 */
2369 ret = 0x20425455; /* "USB " */
2370 break;
2371 case 0x38: /* Supported Protocol:08 */
2372 ret = 0x00000000 | (USB2_PORTS+1) | (USB3_PORTS<<8);
2373 break;
2374 case 0x3c: /* Supported Protocol:0c */
2375 ret = 0x00000000; /* reserved */
2376 break;
2377 default:
2378 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2379 ret = 0;
2380 }
2381
2382 trace_usb_xhci_cap_read(reg, ret);
2383 return ret;
2384 }
2385
2386 static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2387 {
2388 uint32_t port = reg >> 4;
2389 uint32_t ret;
2390
2391 if (port >= MAXPORTS) {
2392 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2393 ret = 0;
2394 goto out;
2395 }
2396
2397 switch (reg & 0xf) {
2398 case 0x00: /* PORTSC */
2399 ret = xhci->ports[port].portsc;
2400 break;
2401 case 0x04: /* PORTPMSC */
2402 case 0x08: /* PORTLI */
2403 ret = 0;
2404 break;
2405 case 0x0c: /* reserved */
2406 default:
2407 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2408 port, reg);
2409 ret = 0;
2410 }
2411
2412 out:
2413 trace_usb_xhci_port_read(port, reg & 0x0f, ret);
2414 return ret;
2415 }
2416
2417 static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2418 {
2419 uint32_t port = reg >> 4;
2420 uint32_t portsc;
2421
2422 trace_usb_xhci_port_write(port, reg & 0x0f, val);
2423
2424 if (port >= MAXPORTS) {
2425 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2426 return;
2427 }
2428
2429 switch (reg & 0xf) {
2430 case 0x00: /* PORTSC */
2431 portsc = xhci->ports[port].portsc;
2432 /* write-1-to-clear bits*/
2433 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2434 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2435 if (val & PORTSC_LWS) {
2436 /* overwrite PLS only when LWS=1 */
2437 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2438 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2439 }
2440 /* read/write bits */
2441 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2442 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2443 /* write-1-to-start bits */
2444 if (val & PORTSC_PR) {
2445 DPRINTF("xhci: port %d reset\n", port);
2446 usb_device_reset(xhci->ports[port].port.dev);
2447 portsc |= PORTSC_PRC | PORTSC_PED;
2448 }
2449 xhci->ports[port].portsc = portsc;
2450 break;
2451 case 0x04: /* PORTPMSC */
2452 case 0x08: /* PORTLI */
2453 default:
2454 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2455 port, reg);
2456 }
2457 }
2458
2459 static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2460 {
2461 uint32_t ret;
2462
2463 if (reg >= 0x400) {
2464 return xhci_port_read(xhci, reg - 0x400);
2465 }
2466
2467 switch (reg) {
2468 case 0x00: /* USBCMD */
2469 ret = xhci->usbcmd;
2470 break;
2471 case 0x04: /* USBSTS */
2472 ret = xhci->usbsts;
2473 break;
2474 case 0x08: /* PAGESIZE */
2475 ret = 1; /* 4KiB */
2476 break;
2477 case 0x14: /* DNCTRL */
2478 ret = xhci->dnctrl;
2479 break;
2480 case 0x18: /* CRCR low */
2481 ret = xhci->crcr_low & ~0xe;
2482 break;
2483 case 0x1c: /* CRCR high */
2484 ret = xhci->crcr_high;
2485 break;
2486 case 0x30: /* DCBAAP low */
2487 ret = xhci->dcbaap_low;
2488 break;
2489 case 0x34: /* DCBAAP high */
2490 ret = xhci->dcbaap_high;
2491 break;
2492 case 0x38: /* CONFIG */
2493 ret = xhci->config;
2494 break;
2495 default:
2496 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2497 ret = 0;
2498 }
2499
2500 trace_usb_xhci_oper_read(reg, ret);
2501 return ret;
2502 }
2503
2504 static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2505 {
2506 if (reg >= 0x400) {
2507 xhci_port_write(xhci, reg - 0x400, val);
2508 return;
2509 }
2510
2511 trace_usb_xhci_oper_write(reg, val);
2512
2513 switch (reg) {
2514 case 0x00: /* USBCMD */
2515 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2516 xhci_run(xhci);
2517 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2518 xhci_stop(xhci);
2519 }
2520 xhci->usbcmd = val & 0xc0f;
2521 if (val & USBCMD_HCRST) {
2522 xhci_reset(&xhci->pci_dev.qdev);
2523 }
2524 xhci_irq_update(xhci);
2525 break;
2526
2527 case 0x04: /* USBSTS */
2528 /* these bits are write-1-to-clear */
2529 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2530 xhci_irq_update(xhci);
2531 break;
2532
2533 case 0x14: /* DNCTRL */
2534 xhci->dnctrl = val & 0xffff;
2535 break;
2536 case 0x18: /* CRCR low */
2537 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2538 break;
2539 case 0x1c: /* CRCR high */
2540 xhci->crcr_high = val;
2541 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2542 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2543 xhci->crcr_low &= ~CRCR_CRR;
2544 xhci_event(xhci, &event);
2545 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2546 } else {
2547 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2548 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2549 }
2550 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2551 break;
2552 case 0x30: /* DCBAAP low */
2553 xhci->dcbaap_low = val & 0xffffffc0;
2554 break;
2555 case 0x34: /* DCBAAP high */
2556 xhci->dcbaap_high = val;
2557 break;
2558 case 0x38: /* CONFIG */
2559 xhci->config = val & 0xff;
2560 break;
2561 default:
2562 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2563 }
2564 }
2565
2566 static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2567 {
2568 uint32_t ret;
2569
2570 switch (reg) {
2571 case 0x00: /* MFINDEX */
2572 fprintf(stderr, "xhci_runtime_read: MFINDEX not yet implemented\n");
2573 ret = xhci->mfindex;
2574 break;
2575 case 0x20: /* IMAN */
2576 ret = xhci->iman;
2577 break;
2578 case 0x24: /* IMOD */
2579 ret = xhci->imod;
2580 break;
2581 case 0x28: /* ERSTSZ */
2582 ret = xhci->erstsz;
2583 break;
2584 case 0x30: /* ERSTBA low */
2585 ret = xhci->erstba_low;
2586 break;
2587 case 0x34: /* ERSTBA high */
2588 ret = xhci->erstba_high;
2589 break;
2590 case 0x38: /* ERDP low */
2591 ret = xhci->erdp_low;
2592 break;
2593 case 0x3c: /* ERDP high */
2594 ret = xhci->erdp_high;
2595 break;
2596 default:
2597 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2598 ret = 0;
2599 }
2600
2601 trace_usb_xhci_runtime_read(reg, ret);
2602 return ret;
2603 }
2604
2605 static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2606 {
2607 trace_usb_xhci_runtime_read(reg, val);
2608
2609 switch (reg) {
2610 case 0x20: /* IMAN */
2611 if (val & IMAN_IP) {
2612 xhci->iman &= ~IMAN_IP;
2613 }
2614 xhci->iman &= ~IMAN_IE;
2615 xhci->iman |= val & IMAN_IE;
2616 xhci_irq_update(xhci);
2617 break;
2618 case 0x24: /* IMOD */
2619 xhci->imod = val;
2620 break;
2621 case 0x28: /* ERSTSZ */
2622 xhci->erstsz = val & 0xffff;
2623 break;
2624 case 0x30: /* ERSTBA low */
2625 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2626 xhci->erstba_low = val & 0xffffffc0; */
2627 xhci->erstba_low = val & 0xfffffff0;
2628 break;
2629 case 0x34: /* ERSTBA high */
2630 xhci->erstba_high = val;
2631 xhci_er_reset(xhci);
2632 break;
2633 case 0x38: /* ERDP low */
2634 if (val & ERDP_EHB) {
2635 xhci->erdp_low &= ~ERDP_EHB;
2636 }
2637 xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB);
2638 break;
2639 case 0x3c: /* ERDP high */
2640 xhci->erdp_high = val;
2641 xhci_events_update(xhci);
2642 break;
2643 default:
2644 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2645 }
2646 }
2647
2648 static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2649 {
2650 /* doorbells always read as 0 */
2651 trace_usb_xhci_doorbell_read(reg, 0);
2652 return 0;
2653 }
2654
2655 static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2656 {
2657 trace_usb_xhci_doorbell_write(reg, val);
2658
2659 if (!xhci_running(xhci)) {
2660 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2661 return;
2662 }
2663
2664 reg >>= 2;
2665
2666 if (reg == 0) {
2667 if (val == 0) {
2668 xhci_process_commands(xhci);
2669 } else {
2670 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2671 }
2672 } else {
2673 if (reg > MAXSLOTS) {
2674 fprintf(stderr, "xhci: bad doorbell %d\n", reg);
2675 } else if (val > 31) {
2676 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2677 } else {
2678 xhci_kick_ep(xhci, reg, val);
2679 }
2680 }
2681 }
2682
2683 static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2684 unsigned size)
2685 {
2686 XHCIState *xhci = ptr;
2687
2688 /* Only aligned reads are allowed on xHCI */
2689 if (addr & 3) {
2690 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
2691 return 0;
2692 }
2693
2694 if (addr < LEN_CAP) {
2695 return xhci_cap_read(xhci, addr);
2696 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2697 return xhci_oper_read(xhci, addr - OFF_OPER);
2698 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2699 return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
2700 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2701 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
2702 } else {
2703 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2704 return 0;
2705 }
2706 }
2707
2708 static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2709 uint64_t val, unsigned size)
2710 {
2711 XHCIState *xhci = ptr;
2712
2713 /* Only aligned writes are allowed on xHCI */
2714 if (addr & 3) {
2715 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
2716 return;
2717 }
2718
2719 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2720 xhci_oper_write(xhci, addr - OFF_OPER, val);
2721 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2722 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
2723 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2724 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
2725 } else {
2726 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2727 }
2728 }
2729
2730 static const MemoryRegionOps xhci_mem_ops = {
2731 .read = xhci_mem_read,
2732 .write = xhci_mem_write,
2733 .valid.min_access_size = 4,
2734 .valid.max_access_size = 4,
2735 .endianness = DEVICE_LITTLE_ENDIAN,
2736 };
2737
2738 static void xhci_attach(USBPort *usbport)
2739 {
2740 XHCIState *xhci = usbport->opaque;
2741 XHCIPort *port = &xhci->ports[usbport->index];
2742
2743 xhci_update_port(xhci, port, 0);
2744 }
2745
2746 static void xhci_detach(USBPort *usbport)
2747 {
2748 XHCIState *xhci = usbport->opaque;
2749 XHCIPort *port = &xhci->ports[usbport->index];
2750
2751 xhci_update_port(xhci, port, 1);
2752 }
2753
2754 static void xhci_wakeup(USBPort *usbport)
2755 {
2756 XHCIState *xhci = usbport->opaque;
2757 XHCIPort *port = &xhci->ports[usbport->index];
2758 int nr = port->port.index + 1;
2759 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2760 uint32_t pls;
2761
2762 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK;
2763 if (pls != 3) {
2764 return;
2765 }
2766 port->portsc |= 0xf << PORTSC_PLS_SHIFT;
2767 if (port->portsc & PORTSC_PLC) {
2768 return;
2769 }
2770 port->portsc |= PORTSC_PLC;
2771 xhci_event(xhci, &ev);
2772 }
2773
2774 static void xhci_complete(USBPort *port, USBPacket *packet)
2775 {
2776 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
2777
2778 xhci_complete_packet(xfer, packet->result);
2779 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2780 }
2781
2782 static void xhci_child_detach(USBPort *port, USBDevice *child)
2783 {
2784 FIXME();
2785 }
2786
2787 static USBPortOps xhci_port_ops = {
2788 .attach = xhci_attach,
2789 .detach = xhci_detach,
2790 .wakeup = xhci_wakeup,
2791 .complete = xhci_complete,
2792 .child_detach = xhci_child_detach,
2793 };
2794
2795 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev)
2796 {
2797 XHCISlot *slot;
2798 int slotid;
2799
2800 for (slotid = 1; slotid <= MAXSLOTS; slotid++) {
2801 slot = &xhci->slots[slotid-1];
2802 if (slot->devaddr == dev->addr) {
2803 return slotid;
2804 }
2805 }
2806 return 0;
2807 }
2808
2809 static int xhci_find_epid(USBEndpoint *ep)
2810 {
2811 if (ep->nr == 0) {
2812 return 1;
2813 }
2814 if (ep->pid == USB_TOKEN_IN) {
2815 return ep->nr * 2 + 1;
2816 } else {
2817 return ep->nr * 2;
2818 }
2819 }
2820
2821 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep)
2822 {
2823 XHCIState *xhci = container_of(bus, XHCIState, bus);
2824 int slotid;
2825
2826 DPRINTF("%s\n", __func__);
2827 slotid = xhci_find_slotid(xhci, ep->dev);
2828 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
2829 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
2830 return;
2831 }
2832 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep));
2833 }
2834
2835 static USBBusOps xhci_bus_ops = {
2836 .wakeup_endpoint = xhci_wakeup_endpoint,
2837 };
2838
2839 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2840 {
2841 int i;
2842
2843 xhci->usbsts = USBSTS_HCH;
2844
2845 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2846
2847 for (i = 0; i < MAXPORTS; i++) {
2848 memset(&xhci->ports[i], 0, sizeof(xhci->ports[i]));
2849 usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i,
2850 &xhci_port_ops,
2851 USB_SPEED_MASK_LOW |
2852 USB_SPEED_MASK_FULL |
2853 USB_SPEED_MASK_HIGH);
2854 }
2855 for (i = 0; i < MAXSLOTS; i++) {
2856 xhci->slots[i].enabled = 0;
2857 }
2858 }
2859
2860 static int usb_xhci_initfn(struct PCIDevice *dev)
2861 {
2862 int ret;
2863
2864 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2865
2866 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
2867 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
2868 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
2869 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2870
2871 usb_xhci_init(xhci, &dev->qdev);
2872
2873 xhci->irq = xhci->pci_dev.irq[0];
2874
2875 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2876 "xhci", LEN_REGS);
2877 pci_register_bar(&xhci->pci_dev, 0,
2878 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
2879 &xhci->mem);
2880
2881 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0);
2882 assert(ret >= 0);
2883
2884 if (xhci->msi) {
2885 ret = msi_init(&xhci->pci_dev, 0x70, 1, true, false);
2886 assert(ret >= 0);
2887 }
2888
2889 return 0;
2890 }
2891
2892 static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
2893 int len)
2894 {
2895 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2896
2897 pci_default_write_config(dev, addr, val, len);
2898 if (xhci->msi) {
2899 msi_write_config(dev, addr, val, len);
2900 }
2901 }
2902
2903 static const VMStateDescription vmstate_xhci = {
2904 .name = "xhci",
2905 .unmigratable = 1,
2906 };
2907
2908 static Property xhci_properties[] = {
2909 DEFINE_PROP_UINT32("msi", XHCIState, msi, 0),
2910 DEFINE_PROP_END_OF_LIST(),
2911 };
2912
2913 static void xhci_class_init(ObjectClass *klass, void *data)
2914 {
2915 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2916 DeviceClass *dc = DEVICE_CLASS(klass);
2917
2918 dc->vmsd = &vmstate_xhci;
2919 dc->props = xhci_properties;
2920 dc->reset = xhci_reset;
2921 k->init = usb_xhci_initfn;
2922 k->vendor_id = PCI_VENDOR_ID_NEC;
2923 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
2924 k->class_id = PCI_CLASS_SERIAL_USB;
2925 k->revision = 0x03;
2926 k->is_express = 1;
2927 k->config_write = xhci_write_config;
2928 }
2929
2930 static TypeInfo xhci_info = {
2931 .name = "nec-usb-xhci",
2932 .parent = TYPE_PCI_DEVICE,
2933 .instance_size = sizeof(XHCIState),
2934 .class_init = xhci_class_init,
2935 };
2936
2937 static void xhci_register_types(void)
2938 {
2939 type_register_static(&xhci_info);
2940 }
2941
2942 type_init(xhci_register_types)
Qemu copy for testing