2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu-timer.h"
32 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34 #define DPRINTF(...) do {} while (0)
36 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
45 #define MAXPORTS (USB2_PORTS+USB3_PORTS)
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
56 #define OFF_OPER LEN_CAP
57 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
58 #define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
59 #define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
60 #define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
61 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
63 /* must be power of 2 */
64 #define LEN_REGS 0x2000
66 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
67 # error Increase LEN_REGS
71 # error TODO: only one interrupter supported
75 #define USBCMD_RS (1<<0)
76 #define USBCMD_HCRST (1<<1)
77 #define USBCMD_INTE (1<<2)
78 #define USBCMD_HSEE (1<<3)
79 #define USBCMD_LHCRST (1<<7)
80 #define USBCMD_CSS (1<<8)
81 #define USBCMD_CRS (1<<9)
82 #define USBCMD_EWE (1<<10)
83 #define USBCMD_EU3S (1<<11)
85 #define USBSTS_HCH (1<<0)
86 #define USBSTS_HSE (1<<2)
87 #define USBSTS_EINT (1<<3)
88 #define USBSTS_PCD (1<<4)
89 #define USBSTS_SSS (1<<8)
90 #define USBSTS_RSS (1<<9)
91 #define USBSTS_SRE (1<<10)
92 #define USBSTS_CNR (1<<11)
93 #define USBSTS_HCE (1<<12)
96 #define PORTSC_CCS (1<<0)
97 #define PORTSC_PED (1<<1)
98 #define PORTSC_OCA (1<<3)
99 #define PORTSC_PR (1<<4)
100 #define PORTSC_PLS_SHIFT 5
101 #define PORTSC_PLS_MASK 0xf
102 #define PORTSC_PP (1<<9)
103 #define PORTSC_SPEED_SHIFT 10
104 #define PORTSC_SPEED_MASK 0xf
105 #define PORTSC_SPEED_FULL (1<<10)
106 #define PORTSC_SPEED_LOW (2<<10)
107 #define PORTSC_SPEED_HIGH (3<<10)
108 #define PORTSC_SPEED_SUPER (4<<10)
109 #define PORTSC_PIC_SHIFT 14
110 #define PORTSC_PIC_MASK 0x3
111 #define PORTSC_LWS (1<<16)
112 #define PORTSC_CSC (1<<17)
113 #define PORTSC_PEC (1<<18)
114 #define PORTSC_WRC (1<<19)
115 #define PORTSC_OCC (1<<20)
116 #define PORTSC_PRC (1<<21)
117 #define PORTSC_PLC (1<<22)
118 #define PORTSC_CEC (1<<23)
119 #define PORTSC_CAS (1<<24)
120 #define PORTSC_WCE (1<<25)
121 #define PORTSC_WDE (1<<26)
122 #define PORTSC_WOE (1<<27)
123 #define PORTSC_DR (1<<30)
124 #define PORTSC_WPR (1<<31)
126 #define CRCR_RCS (1<<0)
127 #define CRCR_CS (1<<1)
128 #define CRCR_CA (1<<2)
129 #define CRCR_CRR (1<<3)
131 #define IMAN_IP (1<<0)
132 #define IMAN_IE (1<<1)
134 #define ERDP_EHB (1<<3)
137 typedef struct XHCITRB
{
146 typedef enum TRBType
{
159 CR_CONFIGURE_ENDPOINT
,
167 CR_SET_LATENCY_TOLERANCE
,
168 CR_GET_PORT_BANDWIDTH
,
173 ER_PORT_STATUS_CHANGE
,
174 ER_BANDWIDTH_REQUEST
,
177 ER_DEVICE_NOTIFICATION
,
179 /* vendor specific bits */
180 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
181 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
182 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
185 #define CR_LINK TR_LINK
187 typedef enum TRBCCode
{
190 CC_DATA_BUFFER_ERROR
,
192 CC_USB_TRANSACTION_ERROR
,
198 CC_INVALID_STREAM_TYPE_ERROR
,
199 CC_SLOT_NOT_ENABLED_ERROR
,
200 CC_EP_NOT_ENABLED_ERROR
,
206 CC_BANDWIDTH_OVERRUN
,
207 CC_CONTEXT_STATE_ERROR
,
208 CC_NO_PING_RESPONSE_ERROR
,
209 CC_EVENT_RING_FULL_ERROR
,
210 CC_INCOMPATIBLE_DEVICE_ERROR
,
211 CC_MISSED_SERVICE_ERROR
,
212 CC_COMMAND_RING_STOPPED
,
215 CC_STOPPED_LENGTH_INVALID
,
216 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
217 CC_ISOCH_BUFFER_OVERRUN
= 31,
220 CC_INVALID_STREAM_ID_ERROR
,
221 CC_SECONDARY_BANDWIDTH_ERROR
,
222 CC_SPLIT_TRANSACTION_ERROR
226 #define TRB_TYPE_SHIFT 10
227 #define TRB_TYPE_MASK 0x3f
228 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
230 #define TRB_EV_ED (1<<2)
232 #define TRB_TR_ENT (1<<1)
233 #define TRB_TR_ISP (1<<2)
234 #define TRB_TR_NS (1<<3)
235 #define TRB_TR_CH (1<<4)
236 #define TRB_TR_IOC (1<<5)
237 #define TRB_TR_IDT (1<<6)
238 #define TRB_TR_TBC_SHIFT 7
239 #define TRB_TR_TBC_MASK 0x3
240 #define TRB_TR_BEI (1<<9)
241 #define TRB_TR_TLBPC_SHIFT 16
242 #define TRB_TR_TLBPC_MASK 0xf
243 #define TRB_TR_FRAMEID_SHIFT 20
244 #define TRB_TR_FRAMEID_MASK 0x7ff
245 #define TRB_TR_SIA (1<<31)
247 #define TRB_TR_DIR (1<<16)
249 #define TRB_CR_SLOTID_SHIFT 24
250 #define TRB_CR_SLOTID_MASK 0xff
251 #define TRB_CR_EPID_SHIFT 16
252 #define TRB_CR_EPID_MASK 0x1f
254 #define TRB_CR_BSR (1<<9)
255 #define TRB_CR_DC (1<<9)
257 #define TRB_LK_TC (1<<1)
259 #define EP_TYPE_MASK 0x7
260 #define EP_TYPE_SHIFT 3
262 #define EP_STATE_MASK 0x7
263 #define EP_DISABLED (0<<0)
264 #define EP_RUNNING (1<<0)
265 #define EP_HALTED (2<<0)
266 #define EP_STOPPED (3<<0)
267 #define EP_ERROR (4<<0)
269 #define SLOT_STATE_MASK 0x1f
270 #define SLOT_STATE_SHIFT 27
271 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
272 #define SLOT_ENABLED 0
273 #define SLOT_DEFAULT 1
274 #define SLOT_ADDRESSED 2
275 #define SLOT_CONFIGURED 3
277 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
278 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
280 typedef enum EPType
{
291 typedef struct XHCIRing
{
297 typedef struct XHCIPort
{
303 typedef struct XHCIState XHCIState
;
305 typedef struct XHCITransfer
{
313 unsigned int iso_pkts
;
319 unsigned int trb_count
;
320 unsigned int trb_alloced
;
326 unsigned int pktsize
;
327 unsigned int cur_pkt
;
329 uint64_t mfindex_kick
;
332 typedef struct XHCIEPContext
{
338 unsigned int next_xfer
;
339 unsigned int comp_xfer
;
340 XHCITransfer transfers
[TD_QUEUE
];
344 unsigned int max_psize
;
347 /* iso xfer scheduling */
348 unsigned int interval
;
349 int64_t mfindex_last
;
350 QEMUTimer
*kick_timer
;
353 typedef struct XHCISlot
{
357 unsigned int devaddr
;
358 XHCIEPContext
* eps
[31];
361 typedef struct XHCIEvent
{
378 unsigned int devaddr
;
380 /* Operational Registers */
387 uint32_t dcbaap_high
;
390 XHCIPort ports
[MAXPORTS
];
391 XHCISlot slots
[MAXSLOTS
];
393 /* Runtime Registers */
398 uint32_t erstba_high
;
402 int64_t mfindex_start
;
403 QEMUTimer
*mfwrap_timer
;
408 unsigned int er_ep_idx
;
411 XHCIEvent ev_buffer
[EV_QUEUE
];
412 unsigned int ev_buffer_put
;
413 unsigned int ev_buffer_get
;
418 typedef struct XHCIEvRingSeg
{
425 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
427 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
);
428 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
);
430 static const char *TRBType_names
[] = {
431 [TRB_RESERVED
] = "TRB_RESERVED",
432 [TR_NORMAL
] = "TR_NORMAL",
433 [TR_SETUP
] = "TR_SETUP",
434 [TR_DATA
] = "TR_DATA",
435 [TR_STATUS
] = "TR_STATUS",
436 [TR_ISOCH
] = "TR_ISOCH",
437 [TR_LINK
] = "TR_LINK",
438 [TR_EVDATA
] = "TR_EVDATA",
439 [TR_NOOP
] = "TR_NOOP",
440 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
441 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
442 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
443 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
444 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
445 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
446 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
447 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
448 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
449 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
450 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
451 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
452 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
453 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
454 [CR_NOOP
] = "CR_NOOP",
455 [ER_TRANSFER
] = "ER_TRANSFER",
456 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
457 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
458 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
459 [ER_DOORBELL
] = "ER_DOORBELL",
460 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
461 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
462 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
463 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
464 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
465 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
468 static const char *TRBCCode_names
[] = {
469 [CC_INVALID
] = "CC_INVALID",
470 [CC_SUCCESS
] = "CC_SUCCESS",
471 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
472 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
473 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
474 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
475 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
476 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
477 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
478 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
479 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
480 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
481 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
482 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
483 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
484 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
485 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
486 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
487 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
488 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
489 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
490 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
491 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
492 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
493 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
494 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
495 [CC_STOPPED
] = "CC_STOPPED",
496 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
497 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
498 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
499 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
500 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
501 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
502 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
503 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
504 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
507 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
509 if (index
>= llen
|| list
[index
] == NULL
) {
515 static const char *trb_name(XHCITRB
*trb
)
517 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
518 ARRAY_SIZE(TRBType_names
));
521 static const char *event_name(XHCIEvent
*event
)
523 return lookup_name(event
->ccode
, TRBCCode_names
,
524 ARRAY_SIZE(TRBCCode_names
));
527 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
529 int64_t now
= qemu_get_clock_ns(vm_clock
);
530 return (now
- xhci
->mfindex_start
) / 125000;
533 static void xhci_mfwrap_update(XHCIState
*xhci
)
535 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
536 uint32_t mfindex
, left
;
539 if ((xhci
->usbcmd
& bits
) == bits
) {
540 now
= qemu_get_clock_ns(vm_clock
);
541 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
542 left
= 0x4000 - mfindex
;
543 qemu_mod_timer(xhci
->mfwrap_timer
, now
+ left
* 125000);
545 qemu_del_timer(xhci
->mfwrap_timer
);
549 static void xhci_mfwrap_timer(void *opaque
)
551 XHCIState
*xhci
= opaque
;
552 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
554 xhci_event(xhci
, &wrap
);
555 xhci_mfwrap_update(xhci
);
558 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
560 if (sizeof(dma_addr_t
) == 4) {
563 return low
| (((dma_addr_t
)high
<< 16) << 16);
567 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
569 if (sizeof(dma_addr_t
) == 4) {
570 return addr
& 0xffffffff;
576 static void xhci_irq_update(XHCIState
*xhci
)
580 if (xhci
->iman
& IMAN_IP
&& xhci
->iman
& IMAN_IE
&&
581 xhci
->usbcmd
& USBCMD_INTE
) {
585 if (xhci
->msi
&& msi_enabled(&xhci
->pci_dev
)) {
587 trace_usb_xhci_irq_msi(0);
588 msi_notify(&xhci
->pci_dev
, 0);
591 trace_usb_xhci_irq_intx(level
);
592 qemu_set_irq(xhci
->irq
, level
);
596 static inline int xhci_running(XHCIState
*xhci
)
598 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->er_full
;
601 static void xhci_die(XHCIState
*xhci
)
603 xhci
->usbsts
|= USBSTS_HCE
;
604 fprintf(stderr
, "xhci: asserted controller error\n");
607 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
)
612 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
613 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
614 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
615 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
617 ev_trb
.control
|= TRB_C
;
619 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
621 trace_usb_xhci_queue_event(xhci
->er_ep_idx
, trb_name(&ev_trb
),
622 event_name(event
), ev_trb
.parameter
,
623 ev_trb
.status
, ev_trb
.control
);
625 addr
= xhci
->er_start
+ TRB_SIZE
*xhci
->er_ep_idx
;
626 pci_dma_write(&xhci
->pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
629 if (xhci
->er_ep_idx
>= xhci
->er_size
) {
631 xhci
->er_pcs
= !xhci
->er_pcs
;
635 static void xhci_events_update(XHCIState
*xhci
)
641 if (xhci
->usbsts
& USBSTS_HCH
) {
645 erdp
= xhci_addr64(xhci
->erdp_low
, xhci
->erdp_high
);
646 if (erdp
< xhci
->er_start
||
647 erdp
>= (xhci
->er_start
+ TRB_SIZE
*xhci
->er_size
)) {
648 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
649 fprintf(stderr
, "xhci: ER at "DMA_ADDR_FMT
" len %d\n",
650 xhci
->er_start
, xhci
->er_size
);
654 dp_idx
= (erdp
- xhci
->er_start
) / TRB_SIZE
;
655 assert(dp_idx
< xhci
->er_size
);
657 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
658 * deadlocks when the ER is full. Hack it by holding off events until
659 * the driver decides to free at least half of the ring */
661 int er_free
= dp_idx
- xhci
->er_ep_idx
;
663 er_free
+= xhci
->er_size
;
665 if (er_free
< (xhci
->er_size
/2)) {
666 DPRINTF("xhci_events_update(): event ring still "
667 "more than half full (hack)\n");
672 while (xhci
->ev_buffer_put
!= xhci
->ev_buffer_get
) {
673 assert(xhci
->er_full
);
674 if (((xhci
->er_ep_idx
+1) % xhci
->er_size
) == dp_idx
) {
675 DPRINTF("xhci_events_update(): event ring full again\n");
677 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
678 xhci_write_event(xhci
, &full
);
683 XHCIEvent
*event
= &xhci
->ev_buffer
[xhci
->ev_buffer_get
];
684 xhci_write_event(xhci
, event
);
685 xhci
->ev_buffer_get
++;
687 if (xhci
->ev_buffer_get
== EV_QUEUE
) {
688 xhci
->ev_buffer_get
= 0;
693 xhci
->erdp_low
|= ERDP_EHB
;
694 xhci
->iman
|= IMAN_IP
;
695 xhci
->usbsts
|= USBSTS_EINT
;
696 xhci_irq_update(xhci
);
699 if (xhci
->er_full
&& xhci
->ev_buffer_put
== xhci
->ev_buffer_get
) {
700 DPRINTF("xhci_events_update(): event ring no longer full\n");
706 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
)
712 DPRINTF("xhci_event(): ER full, queueing\n");
713 if (((xhci
->ev_buffer_put
+1) % EV_QUEUE
) == xhci
->ev_buffer_get
) {
714 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
717 xhci
->ev_buffer
[xhci
->ev_buffer_put
++] = *event
;
718 if (xhci
->ev_buffer_put
== EV_QUEUE
) {
719 xhci
->ev_buffer_put
= 0;
724 erdp
= xhci_addr64(xhci
->erdp_low
, xhci
->erdp_high
);
725 if (erdp
< xhci
->er_start
||
726 erdp
>= (xhci
->er_start
+ TRB_SIZE
*xhci
->er_size
)) {
727 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
728 fprintf(stderr
, "xhci: ER at "DMA_ADDR_FMT
" len %d\n",
729 xhci
->er_start
, xhci
->er_size
);
734 dp_idx
= (erdp
- xhci
->er_start
) / TRB_SIZE
;
735 assert(dp_idx
< xhci
->er_size
);
737 if ((xhci
->er_ep_idx
+1) % xhci
->er_size
== dp_idx
) {
738 DPRINTF("xhci_event(): ER full, queueing\n");
740 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
741 xhci_write_event(xhci
, &full
);
744 if (((xhci
->ev_buffer_put
+1) % EV_QUEUE
) == xhci
->ev_buffer_get
) {
745 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
748 xhci
->ev_buffer
[xhci
->ev_buffer_put
++] = *event
;
749 if (xhci
->ev_buffer_put
== EV_QUEUE
) {
750 xhci
->ev_buffer_put
= 0;
753 xhci_write_event(xhci
, event
);
756 xhci
->erdp_low
|= ERDP_EHB
;
757 xhci
->iman
|= IMAN_IP
;
758 xhci
->usbsts
|= USBSTS_EINT
;
760 xhci_irq_update(xhci
);
763 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
767 ring
->dequeue
= base
;
771 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
776 pci_dma_read(&xhci
->pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
777 trb
->addr
= ring
->dequeue
;
778 trb
->ccs
= ring
->ccs
;
779 le64_to_cpus(&trb
->parameter
);
780 le32_to_cpus(&trb
->status
);
781 le32_to_cpus(&trb
->control
);
783 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
784 trb
->parameter
, trb
->status
, trb
->control
);
786 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
790 type
= TRB_TYPE(*trb
);
792 if (type
!= TR_LINK
) {
794 *addr
= ring
->dequeue
;
796 ring
->dequeue
+= TRB_SIZE
;
799 ring
->dequeue
= xhci_mask64(trb
->parameter
);
800 if (trb
->control
& TRB_LK_TC
) {
801 ring
->ccs
= !ring
->ccs
;
807 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
811 dma_addr_t dequeue
= ring
->dequeue
;
812 bool ccs
= ring
->ccs
;
813 /* hack to bundle together the two/three TDs that make a setup transfer */
814 bool control_td_set
= 0;
818 pci_dma_read(&xhci
->pci_dev
, dequeue
, &trb
, TRB_SIZE
);
819 le64_to_cpus(&trb
.parameter
);
820 le32_to_cpus(&trb
.status
);
821 le32_to_cpus(&trb
.control
);
823 if ((trb
.control
& TRB_C
) != ccs
) {
827 type
= TRB_TYPE(trb
);
829 if (type
== TR_LINK
) {
830 dequeue
= xhci_mask64(trb
.parameter
);
831 if (trb
.control
& TRB_LK_TC
) {
840 if (type
== TR_SETUP
) {
842 } else if (type
== TR_STATUS
) {
846 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
852 static void xhci_er_reset(XHCIState
*xhci
)
856 /* cache the (sole) event ring segment location */
857 if (xhci
->erstsz
!= 1) {
858 fprintf(stderr
, "xhci: invalid value for ERSTSZ: %d\n", xhci
->erstsz
);
862 dma_addr_t erstba
= xhci_addr64(xhci
->erstba_low
, xhci
->erstba_high
);
863 pci_dma_read(&xhci
->pci_dev
, erstba
, &seg
, sizeof(seg
));
864 le32_to_cpus(&seg
.addr_low
);
865 le32_to_cpus(&seg
.addr_high
);
866 le32_to_cpus(&seg
.size
);
867 if (seg
.size
< 16 || seg
.size
> 4096) {
868 fprintf(stderr
, "xhci: invalid value for segment size: %d\n", seg
.size
);
872 xhci
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
873 xhci
->er_size
= seg
.size
;
879 DPRINTF("xhci: event ring:" DMA_ADDR_FMT
" [%d]\n",
880 xhci
->er_start
, xhci
->er_size
);
883 static void xhci_run(XHCIState
*xhci
)
885 trace_usb_xhci_run();
886 xhci
->usbsts
&= ~USBSTS_HCH
;
887 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
890 static void xhci_stop(XHCIState
*xhci
)
892 trace_usb_xhci_stop();
893 xhci
->usbsts
|= USBSTS_HCH
;
894 xhci
->crcr_low
&= ~CRCR_CRR
;
897 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
901 if (epctx
->state
== state
) {
905 pci_dma_read(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
906 ctx
[0] &= ~EP_STATE_MASK
;
908 ctx
[2] = epctx
->ring
.dequeue
| epctx
->ring
.ccs
;
909 ctx
[3] = (epctx
->ring
.dequeue
>> 16) >> 16;
910 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
911 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
912 pci_dma_write(&xhci
->pci_dev
, epctx
->pctx
, ctx
, sizeof(ctx
));
913 epctx
->state
= state
;
916 static void xhci_ep_kick_timer(void *opaque
)
918 XHCIEPContext
*epctx
= opaque
;
919 xhci_kick_ep(epctx
->xhci
, epctx
->slotid
, epctx
->epid
);
922 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
923 unsigned int epid
, dma_addr_t pctx
,
927 XHCIEPContext
*epctx
;
931 trace_usb_xhci_ep_enable(slotid
, epid
);
932 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
933 assert(epid
>= 1 && epid
<= 31);
935 slot
= &xhci
->slots
[slotid
-1];
936 if (slot
->eps
[epid
-1]) {
937 fprintf(stderr
, "xhci: slot %d ep %d already enabled!\n", slotid
, epid
);
941 epctx
= g_malloc(sizeof(XHCIEPContext
));
942 memset(epctx
, 0, sizeof(XHCIEPContext
));
944 epctx
->slotid
= slotid
;
947 slot
->eps
[epid
-1] = epctx
;
949 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
950 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
);
951 epctx
->ring
.ccs
= ctx
[2] & 1;
953 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
954 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid
/2, epid
%2, epctx
->type
);
956 epctx
->max_psize
= ctx
[1]>>16;
957 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
958 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
959 epid
/2, epid
%2, epctx
->max_psize
);
960 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
961 usb_packet_init(&epctx
->transfers
[i
].packet
);
964 epctx
->interval
= 1 << (ctx
[0] >> 16) & 0xff;
965 epctx
->mfindex_last
= 0;
966 epctx
->kick_timer
= qemu_new_timer_ns(vm_clock
, xhci_ep_kick_timer
, epctx
);
968 epctx
->state
= EP_RUNNING
;
969 ctx
[0] &= ~EP_STATE_MASK
;
970 ctx
[0] |= EP_RUNNING
;
975 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
979 XHCIEPContext
*epctx
;
980 int i
, xferi
, killed
= 0;
981 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
982 assert(epid
>= 1 && epid
<= 31);
984 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
986 slot
= &xhci
->slots
[slotid
-1];
988 if (!slot
->eps
[epid
-1]) {
992 epctx
= slot
->eps
[epid
-1];
994 xferi
= epctx
->next_xfer
;
995 for (i
= 0; i
< TD_QUEUE
; i
++) {
996 XHCITransfer
*t
= &epctx
->transfers
[xferi
];
997 if (t
->running_async
) {
998 usb_cancel_packet(&t
->packet
);
999 t
->running_async
= 0;
1001 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i
);
1004 if (t
->running_retry
) {
1005 t
->running_retry
= 0;
1006 epctx
->retry
= NULL
;
1007 qemu_del_timer(epctx
->kick_timer
);
1014 t
->trb_count
= t
->trb_alloced
= 0;
1015 xferi
= (xferi
+ 1) % TD_QUEUE
;
1020 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1024 XHCIEPContext
*epctx
;
1026 trace_usb_xhci_ep_disable(slotid
, epid
);
1027 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1028 assert(epid
>= 1 && epid
<= 31);
1030 slot
= &xhci
->slots
[slotid
-1];
1032 if (!slot
->eps
[epid
-1]) {
1033 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1037 xhci_ep_nuke_xfers(xhci
, slotid
, epid
);
1039 epctx
= slot
->eps
[epid
-1];
1041 xhci_set_ep_state(xhci
, epctx
, EP_DISABLED
);
1043 qemu_free_timer(epctx
->kick_timer
);
1045 slot
->eps
[epid
-1] = NULL
;
1050 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1054 XHCIEPContext
*epctx
;
1056 trace_usb_xhci_ep_stop(slotid
, epid
);
1057 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1059 if (epid
< 1 || epid
> 31) {
1060 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1061 return CC_TRB_ERROR
;
1064 slot
= &xhci
->slots
[slotid
-1];
1066 if (!slot
->eps
[epid
-1]) {
1067 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1068 return CC_EP_NOT_ENABLED_ERROR
;
1071 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1072 fprintf(stderr
, "xhci: FIXME: endpoint stopped w/ xfers running, "
1073 "data might be lost\n");
1076 epctx
= slot
->eps
[epid
-1];
1078 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1083 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1087 XHCIEPContext
*epctx
;
1090 trace_usb_xhci_ep_reset(slotid
, epid
);
1091 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1093 if (epid
< 1 || epid
> 31) {
1094 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1095 return CC_TRB_ERROR
;
1098 slot
= &xhci
->slots
[slotid
-1];
1100 if (!slot
->eps
[epid
-1]) {
1101 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1102 return CC_EP_NOT_ENABLED_ERROR
;
1105 epctx
= slot
->eps
[epid
-1];
1107 if (epctx
->state
!= EP_HALTED
) {
1108 fprintf(stderr
, "xhci: reset EP while EP %d not halted (%d)\n",
1109 epid
, epctx
->state
);
1110 return CC_CONTEXT_STATE_ERROR
;
1113 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1114 fprintf(stderr
, "xhci: FIXME: endpoint reset w/ xfers running, "
1115 "data might be lost\n");
1118 uint8_t ep
= epid
>>1;
1124 dev
= xhci
->ports
[xhci
->slots
[slotid
-1].port
-1].port
.dev
;
1126 return CC_USB_TRANSACTION_ERROR
;
1129 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1134 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1135 unsigned int epid
, uint64_t pdequeue
)
1138 XHCIEPContext
*epctx
;
1141 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1143 if (epid
< 1 || epid
> 31) {
1144 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1145 return CC_TRB_ERROR
;
1148 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, pdequeue
);
1149 dequeue
= xhci_mask64(pdequeue
);
1151 slot
= &xhci
->slots
[slotid
-1];
1153 if (!slot
->eps
[epid
-1]) {
1154 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1155 return CC_EP_NOT_ENABLED_ERROR
;
1158 epctx
= slot
->eps
[epid
-1];
1161 if (epctx
->state
!= EP_STOPPED
) {
1162 fprintf(stderr
, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1163 return CC_CONTEXT_STATE_ERROR
;
1166 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1167 epctx
->ring
.ccs
= dequeue
& 1;
1169 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1174 static int xhci_xfer_map(XHCITransfer
*xfer
)
1176 int in_xfer
= (xfer
->packet
.pid
== USB_TOKEN_IN
);
1177 XHCIState
*xhci
= xfer
->xhci
;
1180 pci_dma_sglist_init(&xfer
->sgl
, &xhci
->pci_dev
, xfer
->trb_count
);
1181 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1182 XHCITRB
*trb
= &xfer
->trbs
[i
];
1184 unsigned int chunk
= 0;
1186 switch (TRB_TYPE(*trb
)) {
1188 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1189 fprintf(stderr
, "xhci: data direction mismatch for TR_DATA\n");
1195 addr
= xhci_mask64(trb
->parameter
);
1196 chunk
= trb
->status
& 0x1ffff;
1197 if (trb
->control
& TRB_TR_IDT
) {
1198 if (chunk
> 8 || in_xfer
) {
1199 fprintf(stderr
, "xhci: invalid immediate data TRB\n");
1202 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1204 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1210 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1214 qemu_sglist_destroy(&xfer
->sgl
);
1219 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1221 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1222 qemu_sglist_destroy(&xfer
->sgl
);
1225 static void xhci_xfer_report(XHCITransfer
*xfer
)
1231 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1232 XHCIState
*xhci
= xfer
->xhci
;
1235 left
= xfer
->packet
.result
< 0 ? 0 : xfer
->packet
.result
;
1237 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1238 XHCITRB
*trb
= &xfer
->trbs
[i
];
1239 unsigned int chunk
= 0;
1241 switch (TRB_TYPE(*trb
)) {
1245 chunk
= trb
->status
& 0x1ffff;
1248 if (xfer
->status
== CC_SUCCESS
) {
1261 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1262 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1263 (xfer
->status
!= CC_SUCCESS
))) {
1264 event
.slotid
= xfer
->slotid
;
1265 event
.epid
= xfer
->epid
;
1266 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1268 event
.ptr
= trb
->addr
;
1269 if (xfer
->status
== CC_SUCCESS
) {
1270 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1272 event
.ccode
= xfer
->status
;
1274 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1275 event
.ptr
= trb
->parameter
;
1276 event
.flags
|= TRB_EV_ED
;
1277 event
.length
= edtla
& 0xffffff;
1278 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1281 xhci_event(xhci
, &event
);
1283 if (xfer
->status
!= CC_SUCCESS
) {
1290 static void xhci_stall_ep(XHCITransfer
*xfer
)
1292 XHCIState
*xhci
= xfer
->xhci
;
1293 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1294 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1296 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1297 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1298 xhci_set_ep_state(xhci
, epctx
, EP_HALTED
);
1299 DPRINTF("xhci: stalled slot %d ep %d\n", xfer
->slotid
, xfer
->epid
);
1300 DPRINTF("xhci: will continue at "DMA_ADDR_FMT
"\n", epctx
->ring
.dequeue
);
1303 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1304 XHCIEPContext
*epctx
);
1306 static USBDevice
*xhci_find_device(XHCIPort
*port
, uint8_t addr
)
1308 if (!(port
->portsc
& PORTSC_PED
)) {
1311 return usb_find_device(&port
->port
, addr
);
1314 static int xhci_setup_packet(XHCITransfer
*xfer
)
1316 XHCIState
*xhci
= xfer
->xhci
;
1322 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1324 if (xfer
->packet
.ep
) {
1325 ep
= xfer
->packet
.ep
;
1328 port
= &xhci
->ports
[xhci
->slots
[xfer
->slotid
-1].port
-1];
1329 dev
= xhci_find_device(port
, xhci
->slots
[xfer
->slotid
-1].devaddr
);
1331 fprintf(stderr
, "xhci: slot %d port %d has no device\n",
1332 xfer
->slotid
, xhci
->slots
[xfer
->slotid
-1].port
);
1335 ep
= usb_ep_get(dev
, dir
, xfer
->epid
>> 1);
1338 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->trbs
[0].addr
);
1339 xhci_xfer_map(xfer
);
1340 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1341 xfer
->packet
.pid
, dev
->addr
, ep
->nr
);
1345 static int xhci_complete_packet(XHCITransfer
*xfer
, int ret
)
1347 if (ret
== USB_RET_ASYNC
) {
1348 trace_usb_xhci_xfer_async(xfer
);
1349 xfer
->running_async
= 1;
1350 xfer
->running_retry
= 0;
1352 xfer
->cancelled
= 0;
1354 } else if (ret
== USB_RET_NAK
) {
1355 trace_usb_xhci_xfer_nak(xfer
);
1356 xfer
->running_async
= 0;
1357 xfer
->running_retry
= 1;
1359 xfer
->cancelled
= 0;
1362 xfer
->running_async
= 0;
1363 xfer
->running_retry
= 0;
1365 xhci_xfer_unmap(xfer
);
1369 trace_usb_xhci_xfer_success(xfer
, ret
);
1370 xfer
->status
= CC_SUCCESS
;
1371 xhci_xfer_report(xfer
);
1376 trace_usb_xhci_xfer_error(xfer
, ret
);
1379 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1380 xhci_xfer_report(xfer
);
1381 xhci_stall_ep(xfer
);
1384 xfer
->status
= CC_STALL_ERROR
;
1385 xhci_xfer_report(xfer
);
1386 xhci_stall_ep(xfer
);
1389 fprintf(stderr
, "%s: FIXME: ret = %d\n", __FUNCTION__
, ret
);
1395 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1397 XHCITRB
*trb_setup
, *trb_status
;
1398 uint8_t bmRequestType
;
1401 trb_setup
= &xfer
->trbs
[0];
1402 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1404 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
);
1406 /* at most one Event Data TRB allowed after STATUS */
1407 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1411 /* do some sanity checks */
1412 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1413 fprintf(stderr
, "xhci: ep0 first TD not SETUP: %d\n",
1414 TRB_TYPE(*trb_setup
));
1417 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1418 fprintf(stderr
, "xhci: ep0 last TD not STATUS: %d\n",
1419 TRB_TYPE(*trb_status
));
1422 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1423 fprintf(stderr
, "xhci: Setup TRB doesn't have IDT set\n");
1426 if ((trb_setup
->status
& 0x1ffff) != 8) {
1427 fprintf(stderr
, "xhci: Setup TRB has bad length (%d)\n",
1428 (trb_setup
->status
& 0x1ffff));
1432 bmRequestType
= trb_setup
->parameter
;
1434 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1435 xfer
->iso_xfer
= false;
1437 if (xhci_setup_packet(xfer
) < 0) {
1440 xfer
->packet
.parameter
= trb_setup
->parameter
;
1442 ret
= usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1444 xhci_complete_packet(xfer
, ret
);
1445 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1446 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1451 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1452 XHCIEPContext
*epctx
, uint64_t mfindex
)
1454 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1455 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1456 ~(epctx
->interval
-1));
1457 if (asap
>= epctx
->mfindex_last
&&
1458 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1459 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1461 xfer
->mfindex_kick
= asap
;
1464 xfer
->mfindex_kick
= (xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1465 & TRB_TR_FRAMEID_MASK
;
1466 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1467 if (xfer
->mfindex_kick
< mfindex
) {
1468 xfer
->mfindex_kick
+= 0x4000;
1473 static void xhci_check_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1474 XHCIEPContext
*epctx
, uint64_t mfindex
)
1476 if (xfer
->mfindex_kick
> mfindex
) {
1477 qemu_mod_timer(epctx
->kick_timer
, qemu_get_clock_ns(vm_clock
) +
1478 (xfer
->mfindex_kick
- mfindex
) * 125000);
1479 xfer
->running_retry
= 1;
1481 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1482 qemu_del_timer(epctx
->kick_timer
);
1483 xfer
->running_retry
= 0;
1488 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1493 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1495 xfer
->in_xfer
= epctx
->type
>>2;
1497 switch(epctx
->type
) {
1503 xfer
->iso_xfer
= false;
1508 xfer
->iso_xfer
= true;
1509 mfindex
= xhci_mfindex_get(xhci
);
1510 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1511 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1512 if (xfer
->running_retry
) {
1517 fprintf(stderr
, "xhci: unknown or unhandled EP "
1518 "(type %d, in %d, ep %02x)\n",
1519 epctx
->type
, xfer
->in_xfer
, xfer
->epid
);
1523 if (xhci_setup_packet(xfer
) < 0) {
1526 ret
= usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1528 xhci_complete_packet(xfer
, ret
);
1529 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1530 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1535 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1537 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
);
1538 return xhci_submit(xhci
, xfer
, epctx
);
1541 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
, unsigned int epid
)
1543 XHCIEPContext
*epctx
;
1548 trace_usb_xhci_ep_kick(slotid
, epid
);
1549 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1550 assert(epid
>= 1 && epid
<= 31);
1552 if (!xhci
->slots
[slotid
-1].enabled
) {
1553 fprintf(stderr
, "xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1556 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1558 fprintf(stderr
, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1564 XHCITransfer
*xfer
= epctx
->retry
;
1567 trace_usb_xhci_xfer_retry(xfer
);
1568 assert(xfer
->running_retry
);
1569 if (xfer
->iso_xfer
) {
1570 /* retry delayed iso transfer */
1571 mfindex
= xhci_mfindex_get(xhci
);
1572 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1573 if (xfer
->running_retry
) {
1576 if (xhci_setup_packet(xfer
) < 0) {
1579 result
= usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1580 assert(result
!= USB_RET_NAK
);
1581 xhci_complete_packet(xfer
, result
);
1583 /* retry nak'ed transfer */
1584 if (xhci_setup_packet(xfer
) < 0) {
1587 result
= usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1588 if (result
== USB_RET_NAK
) {
1591 xhci_complete_packet(xfer
, result
);
1593 assert(!xfer
->running_retry
);
1594 epctx
->retry
= NULL
;
1597 if (epctx
->state
== EP_HALTED
) {
1598 DPRINTF("xhci: ep halted, not running schedule\n");
1602 xhci_set_ep_state(xhci
, epctx
, EP_RUNNING
);
1605 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
1606 if (xfer
->running_async
|| xfer
->running_retry
) {
1609 length
= xhci_ring_chain_length(xhci
, &epctx
->ring
);
1612 } else if (length
== 0) {
1615 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
1616 xfer
->trb_count
= 0;
1617 xfer
->trb_alloced
= 0;
1622 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
1623 xfer
->trb_alloced
= length
;
1625 xfer
->trb_count
= length
;
1627 for (i
= 0; i
< length
; i
++) {
1628 assert(xhci_ring_fetch(xhci
, &epctx
->ring
, &xfer
->trbs
[i
], NULL
));
1632 xfer
->slotid
= slotid
;
1635 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
1636 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1638 fprintf(stderr
, "xhci: error firing CTL transfer\n");
1641 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
1642 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1644 if (!xfer
->iso_xfer
) {
1645 fprintf(stderr
, "xhci: error firing data transfer\n");
1650 if (epctx
->state
== EP_HALTED
) {
1653 if (xfer
->running_retry
) {
1654 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1655 epctx
->retry
= xfer
;
1661 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
1663 trace_usb_xhci_slot_enable(slotid
);
1664 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1665 xhci
->slots
[slotid
-1].enabled
= 1;
1666 xhci
->slots
[slotid
-1].port
= 0;
1667 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
1672 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
1676 trace_usb_xhci_slot_disable(slotid
);
1677 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1679 for (i
= 1; i
<= 31; i
++) {
1680 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1681 xhci_disable_ep(xhci
, slotid
, i
);
1685 xhci
->slots
[slotid
-1].enabled
= 0;
1689 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
1690 uint64_t pictx
, bool bsr
)
1694 dma_addr_t ictx
, octx
, dcbaap
;
1696 uint32_t ictl_ctx
[2];
1697 uint32_t slot_ctx
[4];
1698 uint32_t ep0_ctx
[5];
1703 trace_usb_xhci_slot_address(slotid
);
1704 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1706 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
1707 pci_dma_read(&xhci
->pci_dev
, dcbaap
+ 8*slotid
, &poctx
, sizeof(poctx
));
1708 ictx
= xhci_mask64(pictx
);
1709 octx
= xhci_mask64(le64_to_cpu(poctx
));
1711 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1712 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1714 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1716 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
1717 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1718 ictl_ctx
[0], ictl_ctx
[1]);
1719 return CC_TRB_ERROR
;
1722 pci_dma_read(&xhci
->pci_dev
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
1723 pci_dma_read(&xhci
->pci_dev
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
1725 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1726 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1728 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1729 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1731 port
= (slot_ctx
[1]>>16) & 0xFF;
1732 dev
= xhci
->ports
[port
-1].port
.dev
;
1734 if (port
< 1 || port
> MAXPORTS
) {
1735 fprintf(stderr
, "xhci: bad port %d\n", port
);
1736 return CC_TRB_ERROR
;
1738 fprintf(stderr
, "xhci: port %d not connected\n", port
);
1739 return CC_USB_TRANSACTION_ERROR
;
1742 for (i
= 0; i
< MAXSLOTS
; i
++) {
1743 if (xhci
->slots
[i
].port
== port
) {
1744 fprintf(stderr
, "xhci: port %d already assigned to slot %d\n",
1746 return CC_TRB_ERROR
;
1750 slot
= &xhci
->slots
[slotid
-1];
1755 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
1757 slot
->devaddr
= xhci
->devaddr
++;
1758 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slot
->devaddr
;
1759 DPRINTF("xhci: device address is %d\n", slot
->devaddr
);
1760 usb_device_handle_control(dev
, NULL
,
1761 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
1762 slot
->devaddr
, 0, 0, NULL
);
1765 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
1767 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1768 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1769 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1770 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1772 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1773 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
1779 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
1780 uint64_t pictx
, bool dc
)
1782 dma_addr_t ictx
, octx
;
1783 uint32_t ictl_ctx
[2];
1784 uint32_t slot_ctx
[4];
1785 uint32_t islot_ctx
[4];
1790 trace_usb_xhci_slot_configure(slotid
);
1791 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1793 ictx
= xhci_mask64(pictx
);
1794 octx
= xhci
->slots
[slotid
-1].ctx
;
1796 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1797 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1800 for (i
= 2; i
<= 31; i
++) {
1801 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1802 xhci_disable_ep(xhci
, slotid
, i
);
1806 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1807 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1808 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
1809 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1810 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1811 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1816 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1818 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
1819 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1820 ictl_ctx
[0], ictl_ctx
[1]);
1821 return CC_TRB_ERROR
;
1824 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
1825 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1827 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
1828 fprintf(stderr
, "xhci: invalid slot state %08x\n", slot_ctx
[3]);
1829 return CC_CONTEXT_STATE_ERROR
;
1832 for (i
= 2; i
<= 31; i
++) {
1833 if (ictl_ctx
[0] & (1<<i
)) {
1834 xhci_disable_ep(xhci
, slotid
, i
);
1836 if (ictl_ctx
[1] & (1<<i
)) {
1837 pci_dma_read(&xhci
->pci_dev
, ictx
+32+(32*i
), ep_ctx
,
1839 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1840 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
1841 ep_ctx
[3], ep_ctx
[4]);
1842 xhci_disable_ep(xhci
, slotid
, i
);
1843 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
1844 if (res
!= CC_SUCCESS
) {
1847 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1848 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
1849 ep_ctx
[3], ep_ctx
[4]);
1850 pci_dma_write(&xhci
->pci_dev
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
1854 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1855 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
1856 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
1857 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
1858 SLOT_CONTEXT_ENTRIES_SHIFT
);
1859 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1860 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1862 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1868 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
1871 dma_addr_t ictx
, octx
;
1872 uint32_t ictl_ctx
[2];
1873 uint32_t iep0_ctx
[5];
1874 uint32_t ep0_ctx
[5];
1875 uint32_t islot_ctx
[4];
1876 uint32_t slot_ctx
[4];
1878 trace_usb_xhci_slot_evaluate(slotid
);
1879 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1881 ictx
= xhci_mask64(pictx
);
1882 octx
= xhci
->slots
[slotid
-1].ctx
;
1884 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1885 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1887 pci_dma_read(&xhci
->pci_dev
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1889 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
1890 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1891 ictl_ctx
[0], ictl_ctx
[1]);
1892 return CC_TRB_ERROR
;
1895 if (ictl_ctx
[1] & 0x1) {
1896 pci_dma_read(&xhci
->pci_dev
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
1898 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1899 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
1901 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1903 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
1904 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
1905 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
1906 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
1908 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1909 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1911 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1914 if (ictl_ctx
[1] & 0x2) {
1915 pci_dma_read(&xhci
->pci_dev
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
1917 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1918 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
1919 iep0_ctx
[3], iep0_ctx
[4]);
1921 pci_dma_read(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
1923 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
1924 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
1926 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1927 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1929 pci_dma_write(&xhci
->pci_dev
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
1935 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
1937 uint32_t slot_ctx
[4];
1941 trace_usb_xhci_slot_reset(slotid
);
1942 assert(slotid
>= 1 && slotid
<= MAXSLOTS
);
1944 octx
= xhci
->slots
[slotid
-1].ctx
;
1946 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1948 for (i
= 2; i
<= 31; i
++) {
1949 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1950 xhci_disable_ep(xhci
, slotid
, i
);
1954 pci_dma_read(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1955 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
1956 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
1957 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1958 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1959 pci_dma_write(&xhci
->pci_dev
, octx
, slot_ctx
, sizeof(slot_ctx
));
1964 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
1966 unsigned int slotid
;
1967 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
1968 if (slotid
< 1 || slotid
> MAXSLOTS
) {
1969 fprintf(stderr
, "xhci: bad slot id %d\n", slotid
);
1970 event
->ccode
= CC_TRB_ERROR
;
1972 } else if (!xhci
->slots
[slotid
-1].enabled
) {
1973 fprintf(stderr
, "xhci: slot id %d not enabled\n", slotid
);
1974 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
1980 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
1983 uint8_t bw_ctx
[MAXPORTS
+1];
1985 DPRINTF("xhci_get_port_bandwidth()\n");
1987 ctx
= xhci_mask64(pctx
);
1989 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
1991 /* TODO: actually implement real values here */
1993 memset(&bw_ctx
[1], 80, MAXPORTS
); /* 80% */
1994 pci_dma_write(&xhci
->pci_dev
, ctx
, bw_ctx
, sizeof(bw_ctx
));
1999 static uint32_t rotl(uint32_t v
, unsigned count
)
2002 return (v
<< count
) | (v
>> (32 - count
));
2006 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2009 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2010 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2011 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2015 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2019 dma_addr_t paddr
= xhci_mask64(addr
);
2021 pci_dma_read(&xhci
->pci_dev
, paddr
, &buf
, 32);
2023 memcpy(obuf
, buf
, sizeof(obuf
));
2025 if ((buf
[0] & 0xff) == 2) {
2026 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2027 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2028 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2029 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2030 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2031 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2032 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2033 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2034 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2037 pci_dma_write(&xhci
->pci_dev
, paddr
, &obuf
, 32);
2040 static void xhci_process_commands(XHCIState
*xhci
)
2044 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2046 unsigned int i
, slotid
= 0;
2048 DPRINTF("xhci_process_commands()\n");
2049 if (!xhci_running(xhci
)) {
2050 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2054 xhci
->crcr_low
|= CRCR_CRR
;
2056 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2059 case CR_ENABLE_SLOT
:
2060 for (i
= 0; i
< MAXSLOTS
; i
++) {
2061 if (!xhci
->slots
[i
].enabled
) {
2065 if (i
>= MAXSLOTS
) {
2066 fprintf(stderr
, "xhci: no device slots available\n");
2067 event
.ccode
= CC_NO_SLOTS_ERROR
;
2070 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2073 case CR_DISABLE_SLOT
:
2074 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2076 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2079 case CR_ADDRESS_DEVICE
:
2080 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2082 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2083 trb
.control
& TRB_CR_BSR
);
2086 case CR_CONFIGURE_ENDPOINT
:
2087 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2089 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2090 trb
.control
& TRB_CR_DC
);
2093 case CR_EVALUATE_CONTEXT
:
2094 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2096 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2099 case CR_STOP_ENDPOINT
:
2100 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2102 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2104 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2107 case CR_RESET_ENDPOINT
:
2108 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2110 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2112 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2115 case CR_SET_TR_DEQUEUE
:
2116 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2118 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2120 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
, epid
,
2124 case CR_RESET_DEVICE
:
2125 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2127 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2130 case CR_GET_PORT_BANDWIDTH
:
2131 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2133 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2134 xhci_via_challenge(xhci
, trb
.parameter
);
2136 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2137 event
.type
= 48; /* NEC reply */
2138 event
.length
= 0x3025;
2140 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2142 uint32_t chi
= trb
.parameter
>> 32;
2143 uint32_t clo
= trb
.parameter
;
2144 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2145 event
.length
= val
& 0xFFFF;
2146 event
.epid
= val
>> 16;
2148 event
.type
= 48; /* NEC reply */
2152 fprintf(stderr
, "xhci: unimplemented command %d\n", type
);
2153 event
.ccode
= CC_TRB_ERROR
;
2156 event
.slotid
= slotid
;
2157 xhci_event(xhci
, &event
);
2161 static void xhci_update_port(XHCIState
*xhci
, XHCIPort
*port
, int is_detach
)
2163 int nr
= port
->port
.index
+ 1;
2165 port
->portsc
= PORTSC_PP
;
2166 if (port
->port
.dev
&& port
->port
.dev
->attached
&& !is_detach
) {
2167 port
->portsc
|= PORTSC_CCS
;
2168 switch (port
->port
.dev
->speed
) {
2170 port
->portsc
|= PORTSC_SPEED_LOW
;
2172 case USB_SPEED_FULL
:
2173 port
->portsc
|= PORTSC_SPEED_FULL
;
2175 case USB_SPEED_HIGH
:
2176 port
->portsc
|= PORTSC_SPEED_HIGH
;
2181 if (xhci_running(xhci
)) {
2182 port
->portsc
|= PORTSC_CSC
;
2183 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
, nr
<< 24};
2184 xhci_event(xhci
, &ev
);
2185 DPRINTF("xhci: port change event for port %d\n", nr
);
2189 static void xhci_reset(DeviceState
*dev
)
2191 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
.qdev
, dev
);
2194 trace_usb_xhci_reset();
2195 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2196 fprintf(stderr
, "xhci: reset while running!\n");
2200 xhci
->usbsts
= USBSTS_HCH
;
2203 xhci
->crcr_high
= 0;
2204 xhci
->dcbaap_low
= 0;
2205 xhci
->dcbaap_high
= 0;
2209 for (i
= 0; i
< MAXSLOTS
; i
++) {
2210 xhci_disable_slot(xhci
, i
+1);
2213 for (i
= 0; i
< MAXPORTS
; i
++) {
2214 xhci_update_port(xhci
, xhci
->ports
+ i
, 0);
2220 xhci
->erstba_low
= 0;
2221 xhci
->erstba_high
= 0;
2223 xhci
->erdp_high
= 0;
2225 xhci
->er_ep_idx
= 0;
2228 xhci
->ev_buffer_put
= 0;
2229 xhci
->ev_buffer_get
= 0;
2231 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
2232 xhci_mfwrap_update(xhci
);
2235 static uint32_t xhci_cap_read(XHCIState
*xhci
, uint32_t reg
)
2240 case 0x00: /* HCIVERSION, CAPLENGTH */
2241 ret
= 0x01000000 | LEN_CAP
;
2243 case 0x04: /* HCSPARAMS 1 */
2244 ret
= (MAXPORTS
<<24) | (MAXINTRS
<<8) | MAXSLOTS
;
2246 case 0x08: /* HCSPARAMS 2 */
2249 case 0x0c: /* HCSPARAMS 3 */
2252 case 0x10: /* HCCPARAMS */
2253 if (sizeof(dma_addr_t
) == 4) {
2259 case 0x14: /* DBOFF */
2262 case 0x18: /* RTSOFF */
2266 /* extended capabilities */
2267 case 0x20: /* Supported Protocol:00 */
2268 ret
= 0x02000402; /* USB 2.0 */
2270 case 0x24: /* Supported Protocol:04 */
2271 ret
= 0x20425455; /* "USB " */
2273 case 0x28: /* Supported Protocol:08 */
2274 ret
= 0x00000001 | (USB2_PORTS
<<8);
2276 case 0x2c: /* Supported Protocol:0c */
2277 ret
= 0x00000000; /* reserved */
2279 case 0x30: /* Supported Protocol:00 */
2280 ret
= 0x03000002; /* USB 3.0 */
2282 case 0x34: /* Supported Protocol:04 */
2283 ret
= 0x20425455; /* "USB " */
2285 case 0x38: /* Supported Protocol:08 */
2286 ret
= 0x00000000 | (USB2_PORTS
+1) | (USB3_PORTS
<<8);
2288 case 0x3c: /* Supported Protocol:0c */
2289 ret
= 0x00000000; /* reserved */
2292 fprintf(stderr
, "xhci_cap_read: reg %d unimplemented\n", reg
);
2296 trace_usb_xhci_cap_read(reg
, ret
);
2300 static uint32_t xhci_port_read(XHCIState
*xhci
, uint32_t reg
)
2302 uint32_t port
= reg
>> 4;
2305 if (port
>= MAXPORTS
) {
2306 fprintf(stderr
, "xhci_port_read: port %d out of bounds\n", port
);
2311 switch (reg
& 0xf) {
2312 case 0x00: /* PORTSC */
2313 ret
= xhci
->ports
[port
].portsc
;
2315 case 0x04: /* PORTPMSC */
2316 case 0x08: /* PORTLI */
2319 case 0x0c: /* reserved */
2321 fprintf(stderr
, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2327 trace_usb_xhci_port_read(port
, reg
& 0x0f, ret
);
2331 static void xhci_port_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2333 uint32_t port
= reg
>> 4;
2336 trace_usb_xhci_port_write(port
, reg
& 0x0f, val
);
2338 if (port
>= MAXPORTS
) {
2339 fprintf(stderr
, "xhci_port_read: port %d out of bounds\n", port
);
2343 switch (reg
& 0xf) {
2344 case 0x00: /* PORTSC */
2345 portsc
= xhci
->ports
[port
].portsc
;
2346 /* write-1-to-clear bits*/
2347 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2348 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2349 if (val
& PORTSC_LWS
) {
2350 /* overwrite PLS only when LWS=1 */
2351 portsc
&= ~(PORTSC_PLS_MASK
<< PORTSC_PLS_SHIFT
);
2352 portsc
|= val
& (PORTSC_PLS_MASK
<< PORTSC_PLS_SHIFT
);
2354 /* read/write bits */
2355 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2356 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2357 /* write-1-to-start bits */
2358 if (val
& PORTSC_PR
) {
2359 DPRINTF("xhci: port %d reset\n", port
);
2360 usb_device_reset(xhci
->ports
[port
].port
.dev
);
2361 portsc
|= PORTSC_PRC
| PORTSC_PED
;
2363 xhci
->ports
[port
].portsc
= portsc
;
2365 case 0x04: /* PORTPMSC */
2366 case 0x08: /* PORTLI */
2368 fprintf(stderr
, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2373 static uint32_t xhci_oper_read(XHCIState
*xhci
, uint32_t reg
)
2378 return xhci_port_read(xhci
, reg
- 0x400);
2382 case 0x00: /* USBCMD */
2385 case 0x04: /* USBSTS */
2388 case 0x08: /* PAGESIZE */
2391 case 0x14: /* DNCTRL */
2394 case 0x18: /* CRCR low */
2395 ret
= xhci
->crcr_low
& ~0xe;
2397 case 0x1c: /* CRCR high */
2398 ret
= xhci
->crcr_high
;
2400 case 0x30: /* DCBAAP low */
2401 ret
= xhci
->dcbaap_low
;
2403 case 0x34: /* DCBAAP high */
2404 ret
= xhci
->dcbaap_high
;
2406 case 0x38: /* CONFIG */
2410 fprintf(stderr
, "xhci_oper_read: reg 0x%x unimplemented\n", reg
);
2414 trace_usb_xhci_oper_read(reg
, ret
);
2418 static void xhci_oper_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2421 xhci_port_write(xhci
, reg
- 0x400, val
);
2425 trace_usb_xhci_oper_write(reg
, val
);
2428 case 0x00: /* USBCMD */
2429 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2431 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2434 xhci
->usbcmd
= val
& 0xc0f;
2435 xhci_mfwrap_update(xhci
);
2436 if (val
& USBCMD_HCRST
) {
2437 xhci_reset(&xhci
->pci_dev
.qdev
);
2439 xhci_irq_update(xhci
);
2442 case 0x04: /* USBSTS */
2443 /* these bits are write-1-to-clear */
2444 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2445 xhci_irq_update(xhci
);
2448 case 0x14: /* DNCTRL */
2449 xhci
->dnctrl
= val
& 0xffff;
2451 case 0x18: /* CRCR low */
2452 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2454 case 0x1c: /* CRCR high */
2455 xhci
->crcr_high
= val
;
2456 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2457 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2458 xhci
->crcr_low
&= ~CRCR_CRR
;
2459 xhci_event(xhci
, &event
);
2460 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2462 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2463 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2465 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2467 case 0x30: /* DCBAAP low */
2468 xhci
->dcbaap_low
= val
& 0xffffffc0;
2470 case 0x34: /* DCBAAP high */
2471 xhci
->dcbaap_high
= val
;
2473 case 0x38: /* CONFIG */
2474 xhci
->config
= val
& 0xff;
2477 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", reg
);
2481 static uint32_t xhci_runtime_read(XHCIState
*xhci
, uint32_t reg
)
2486 case 0x00: /* MFINDEX */
2487 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
2489 case 0x20: /* IMAN */
2492 case 0x24: /* IMOD */
2495 case 0x28: /* ERSTSZ */
2498 case 0x30: /* ERSTBA low */
2499 ret
= xhci
->erstba_low
;
2501 case 0x34: /* ERSTBA high */
2502 ret
= xhci
->erstba_high
;
2504 case 0x38: /* ERDP low */
2505 ret
= xhci
->erdp_low
;
2507 case 0x3c: /* ERDP high */
2508 ret
= xhci
->erdp_high
;
2511 fprintf(stderr
, "xhci_runtime_read: reg 0x%x unimplemented\n", reg
);
2515 trace_usb_xhci_runtime_read(reg
, ret
);
2519 static void xhci_runtime_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2521 trace_usb_xhci_runtime_read(reg
, val
);
2524 case 0x20: /* IMAN */
2525 if (val
& IMAN_IP
) {
2526 xhci
->iman
&= ~IMAN_IP
;
2528 xhci
->iman
&= ~IMAN_IE
;
2529 xhci
->iman
|= val
& IMAN_IE
;
2530 xhci_irq_update(xhci
);
2532 case 0x24: /* IMOD */
2535 case 0x28: /* ERSTSZ */
2536 xhci
->erstsz
= val
& 0xffff;
2538 case 0x30: /* ERSTBA low */
2539 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2540 xhci->erstba_low = val & 0xffffffc0; */
2541 xhci
->erstba_low
= val
& 0xfffffff0;
2543 case 0x34: /* ERSTBA high */
2544 xhci
->erstba_high
= val
;
2545 xhci_er_reset(xhci
);
2547 case 0x38: /* ERDP low */
2548 if (val
& ERDP_EHB
) {
2549 xhci
->erdp_low
&= ~ERDP_EHB
;
2551 xhci
->erdp_low
= (val
& ~ERDP_EHB
) | (xhci
->erdp_low
& ERDP_EHB
);
2553 case 0x3c: /* ERDP high */
2554 xhci
->erdp_high
= val
;
2555 xhci_events_update(xhci
);
2558 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", reg
);
2562 static uint32_t xhci_doorbell_read(XHCIState
*xhci
, uint32_t reg
)
2564 /* doorbells always read as 0 */
2565 trace_usb_xhci_doorbell_read(reg
, 0);
2569 static void xhci_doorbell_write(XHCIState
*xhci
, uint32_t reg
, uint32_t val
)
2571 trace_usb_xhci_doorbell_write(reg
, val
);
2573 if (!xhci_running(xhci
)) {
2574 fprintf(stderr
, "xhci: wrote doorbell while xHC stopped or paused\n");
2582 xhci_process_commands(xhci
);
2584 fprintf(stderr
, "xhci: bad doorbell 0 write: 0x%x\n", val
);
2587 if (reg
> MAXSLOTS
) {
2588 fprintf(stderr
, "xhci: bad doorbell %d\n", reg
);
2589 } else if (val
> 31) {
2590 fprintf(stderr
, "xhci: bad doorbell %d write: 0x%x\n", reg
, val
);
2592 xhci_kick_ep(xhci
, reg
, val
);
2597 static uint64_t xhci_mem_read(void *ptr
, target_phys_addr_t addr
,
2600 XHCIState
*xhci
= ptr
;
2602 /* Only aligned reads are allowed on xHCI */
2604 fprintf(stderr
, "xhci_mem_read: Mis-aligned read\n");
2608 if (addr
< LEN_CAP
) {
2609 return xhci_cap_read(xhci
, addr
);
2610 } else if (addr
>= OFF_OPER
&& addr
< (OFF_OPER
+ LEN_OPER
)) {
2611 return xhci_oper_read(xhci
, addr
- OFF_OPER
);
2612 } else if (addr
>= OFF_RUNTIME
&& addr
< (OFF_RUNTIME
+ LEN_RUNTIME
)) {
2613 return xhci_runtime_read(xhci
, addr
- OFF_RUNTIME
);
2614 } else if (addr
>= OFF_DOORBELL
&& addr
< (OFF_DOORBELL
+ LEN_DOORBELL
)) {
2615 return xhci_doorbell_read(xhci
, addr
- OFF_DOORBELL
);
2617 fprintf(stderr
, "xhci_mem_read: Bad offset %x\n", (int)addr
);
2622 static void xhci_mem_write(void *ptr
, target_phys_addr_t addr
,
2623 uint64_t val
, unsigned size
)
2625 XHCIState
*xhci
= ptr
;
2627 /* Only aligned writes are allowed on xHCI */
2629 fprintf(stderr
, "xhci_mem_write: Mis-aligned write\n");
2633 if (addr
>= OFF_OPER
&& addr
< (OFF_OPER
+ LEN_OPER
)) {
2634 xhci_oper_write(xhci
, addr
- OFF_OPER
, val
);
2635 } else if (addr
>= OFF_RUNTIME
&& addr
< (OFF_RUNTIME
+ LEN_RUNTIME
)) {
2636 xhci_runtime_write(xhci
, addr
- OFF_RUNTIME
, val
);
2637 } else if (addr
>= OFF_DOORBELL
&& addr
< (OFF_DOORBELL
+ LEN_DOORBELL
)) {
2638 xhci_doorbell_write(xhci
, addr
- OFF_DOORBELL
, val
);
2640 fprintf(stderr
, "xhci_mem_write: Bad offset %x\n", (int)addr
);
2644 static const MemoryRegionOps xhci_mem_ops
= {
2645 .read
= xhci_mem_read
,
2646 .write
= xhci_mem_write
,
2647 .valid
.min_access_size
= 4,
2648 .valid
.max_access_size
= 4,
2649 .endianness
= DEVICE_LITTLE_ENDIAN
,
2652 static void xhci_attach(USBPort
*usbport
)
2654 XHCIState
*xhci
= usbport
->opaque
;
2655 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2657 xhci_update_port(xhci
, port
, 0);
2660 static void xhci_detach(USBPort
*usbport
)
2662 XHCIState
*xhci
= usbport
->opaque
;
2663 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2665 xhci_update_port(xhci
, port
, 1);
2668 static void xhci_wakeup(USBPort
*usbport
)
2670 XHCIState
*xhci
= usbport
->opaque
;
2671 XHCIPort
*port
= &xhci
->ports
[usbport
->index
];
2672 int nr
= port
->port
.index
+ 1;
2673 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
, nr
<< 24};
2676 pls
= (port
->portsc
>> PORTSC_PLS_SHIFT
) & PORTSC_PLS_MASK
;
2680 port
->portsc
|= 0xf << PORTSC_PLS_SHIFT
;
2681 if (port
->portsc
& PORTSC_PLC
) {
2684 port
->portsc
|= PORTSC_PLC
;
2685 xhci_event(xhci
, &ev
);
2688 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
2690 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
2692 xhci_complete_packet(xfer
, packet
->result
);
2693 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
);
2696 static void xhci_child_detach(USBPort
*port
, USBDevice
*child
)
2701 static USBPortOps xhci_port_ops
= {
2702 .attach
= xhci_attach
,
2703 .detach
= xhci_detach
,
2704 .wakeup
= xhci_wakeup
,
2705 .complete
= xhci_complete
,
2706 .child_detach
= xhci_child_detach
,
2709 static int xhci_find_slotid(XHCIState
*xhci
, USBDevice
*dev
)
2714 for (slotid
= 1; slotid
<= MAXSLOTS
; slotid
++) {
2715 slot
= &xhci
->slots
[slotid
-1];
2716 if (slot
->devaddr
== dev
->addr
) {
2723 static int xhci_find_epid(USBEndpoint
*ep
)
2728 if (ep
->pid
== USB_TOKEN_IN
) {
2729 return ep
->nr
* 2 + 1;
2735 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
)
2737 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
2740 DPRINTF("%s\n", __func__
);
2741 slotid
= xhci_find_slotid(xhci
, ep
->dev
);
2742 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
2743 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
2746 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
));
2749 static USBBusOps xhci_bus_ops
= {
2750 .wakeup_endpoint
= xhci_wakeup_endpoint
,
2753 static void usb_xhci_init(XHCIState
*xhci
, DeviceState
*dev
)
2757 xhci
->usbsts
= USBSTS_HCH
;
2759 usb_bus_new(&xhci
->bus
, &xhci_bus_ops
, &xhci
->pci_dev
.qdev
);
2761 for (i
= 0; i
< MAXPORTS
; i
++) {
2762 memset(&xhci
->ports
[i
], 0, sizeof(xhci
->ports
[i
]));
2763 usb_register_port(&xhci
->bus
, &xhci
->ports
[i
].port
, xhci
, i
,
2765 USB_SPEED_MASK_LOW
|
2766 USB_SPEED_MASK_FULL
|
2767 USB_SPEED_MASK_HIGH
);
2769 for (i
= 0; i
< MAXSLOTS
; i
++) {
2770 xhci
->slots
[i
].enabled
= 0;
2774 static int usb_xhci_initfn(struct PCIDevice
*dev
)
2778 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
2780 xhci
->pci_dev
.config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
2781 xhci
->pci_dev
.config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
2782 xhci
->pci_dev
.config
[PCI_CACHE_LINE_SIZE
] = 0x10;
2783 xhci
->pci_dev
.config
[0x60] = 0x30; /* release number */
2785 usb_xhci_init(xhci
, &dev
->qdev
);
2787 xhci
->mfwrap_timer
= qemu_new_timer_ns(vm_clock
, xhci_mfwrap_timer
, xhci
);
2789 xhci
->irq
= xhci
->pci_dev
.irq
[0];
2791 memory_region_init_io(&xhci
->mem
, &xhci_mem_ops
, xhci
,
2793 pci_register_bar(&xhci
->pci_dev
, 0,
2794 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
2797 ret
= pcie_cap_init(&xhci
->pci_dev
, 0xa0, PCI_EXP_TYPE_ENDPOINT
, 0);
2801 ret
= msi_init(&xhci
->pci_dev
, 0x70, 1, true, false);
2808 static void xhci_write_config(PCIDevice
*dev
, uint32_t addr
, uint32_t val
,
2811 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
2813 pci_default_write_config(dev
, addr
, val
, len
);
2815 msi_write_config(dev
, addr
, val
, len
);
2819 static const VMStateDescription vmstate_xhci
= {
2824 static Property xhci_properties
[] = {
2825 DEFINE_PROP_UINT32("msi", XHCIState
, msi
, 0),
2826 DEFINE_PROP_END_OF_LIST(),
2829 static void xhci_class_init(ObjectClass
*klass
, void *data
)
2831 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2832 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2834 dc
->vmsd
= &vmstate_xhci
;
2835 dc
->props
= xhci_properties
;
2836 dc
->reset
= xhci_reset
;
2837 k
->init
= usb_xhci_initfn
;
2838 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
2839 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
2840 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2843 k
->config_write
= xhci_write_config
;
2846 static TypeInfo xhci_info
= {
2847 .name
= "nec-usb-xhci",
2848 .parent
= TYPE_PCI_DEVICE
,
2849 .instance_size
= sizeof(XHCIState
),
2850 .class_init
= xhci_class_init
,
2853 static void xhci_register_types(void)
2855 type_register_static(&xhci_info
);
2858 type_init(xhci_register_types
)