2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
25 * o Downstream port handoff
29 #include "qemu-timer.h"
38 #define DPRINTF printf
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
46 #define MMIO_SIZE 0x1000
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
100 #define CONFIGFLAG OPREGBASE + 0x0040
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
106 * Bits that are reserved or are read-only are masked out of values
107 * written to us by software
109 #define PORTSC_RO_MASK 0x007021c4
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
141 /* Internal periodic / asynchronous schedule state machine states
148 /* The following states are internal to the state machine function
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
173 /* EHCI spec version 1.0 Section 3.3
175 typedef struct EHCIitd
{
178 uint32_t transact
[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 #define ITD_BUFPTR_MULT_SH 0
204 /* EHCI spec version 1.0 Section 3.4
206 typedef struct EHCIsitd
{
207 uint32_t next
; // Standard next link pointer
209 #define SITD_EPCHAR_IO (1 << 31)
210 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
211 #define SITD_EPCHAR_PORTNUM_SH 24
212 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
213 #define SITD_EPCHAR_HUBADDR_SH 16
214 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
215 #define SITD_EPCHAR_EPNUM_SH 8
216 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
219 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
220 #define SITD_UFRAME_CMASK_SH 8
221 #define SITD_UFRAME_SMASK_MASK 0x000000ff
224 #define SITD_RESULTS_IOC (1 << 31)
225 #define SITD_RESULTS_PGSEL (1 << 30)
226 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
227 #define SITD_RESULTS_TYBYTES_SH 16
228 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
229 #define SITD_RESULTS_CPROGMASK_SH 8
230 #define SITD_RESULTS_ACTIVE (1 << 7)
231 #define SITD_RESULTS_ERR (1 << 6)
232 #define SITD_RESULTS_DBERR (1 << 5)
233 #define SITD_RESULTS_BABBLE (1 << 4)
234 #define SITD_RESULTS_XACTERR (1 << 3)
235 #define SITD_RESULTS_MISSEDUF (1 << 2)
236 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
239 #define SITD_BUFPTR_MASK 0xfffff000
240 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
241 #define SITD_BUFPTR_TPOS_MASK 0x00000018
242 #define SITD_BUFPTR_TPOS_SH 3
243 #define SITD_BUFPTR_TCNT_MASK 0x00000007
245 uint32_t backptr
; // Standard next link pointer
248 /* EHCI spec version 1.0 Section 3.5
250 typedef struct EHCIqtd
{
251 uint32_t next
; // Standard next link pointer
252 uint32_t altnext
; // Standard next link pointer
254 #define QTD_TOKEN_DTOGGLE (1 << 31)
255 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
256 #define QTD_TOKEN_TBYTES_SH 16
257 #define QTD_TOKEN_IOC (1 << 15)
258 #define QTD_TOKEN_CPAGE_MASK 0x00007000
259 #define QTD_TOKEN_CPAGE_SH 12
260 #define QTD_TOKEN_CERR_MASK 0x00000c00
261 #define QTD_TOKEN_CERR_SH 10
262 #define QTD_TOKEN_PID_MASK 0x00000300
263 #define QTD_TOKEN_PID_SH 8
264 #define QTD_TOKEN_ACTIVE (1 << 7)
265 #define QTD_TOKEN_HALT (1 << 6)
266 #define QTD_TOKEN_DBERR (1 << 5)
267 #define QTD_TOKEN_BABBLE (1 << 4)
268 #define QTD_TOKEN_XACTERR (1 << 3)
269 #define QTD_TOKEN_MISSEDUF (1 << 2)
270 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
271 #define QTD_TOKEN_PING (1 << 0)
273 uint32_t bufptr
[5]; // Standard buffer pointer
274 #define QTD_BUFPTR_MASK 0xfffff000
277 /* EHCI spec version 1.0 Section 3.6
279 typedef struct EHCIqh
{
280 uint32_t next
; // Standard next link pointer
282 /* endpoint characteristics */
284 #define QH_EPCHAR_RL_MASK 0xf0000000
285 #define QH_EPCHAR_RL_SH 28
286 #define QH_EPCHAR_C (1 << 27)
287 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
288 #define QH_EPCHAR_MPLEN_SH 16
289 #define QH_EPCHAR_H (1 << 15)
290 #define QH_EPCHAR_DTC (1 << 14)
291 #define QH_EPCHAR_EPS_MASK 0x00003000
292 #define QH_EPCHAR_EPS_SH 12
293 #define EHCI_QH_EPS_FULL 0
294 #define EHCI_QH_EPS_LOW 1
295 #define EHCI_QH_EPS_HIGH 2
296 #define EHCI_QH_EPS_RESERVED 3
298 #define QH_EPCHAR_EP_MASK 0x00000f00
299 #define QH_EPCHAR_EP_SH 8
300 #define QH_EPCHAR_I (1 << 7)
301 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
302 #define QH_EPCHAR_DEVADDR_SH 0
304 /* endpoint capabilities */
306 #define QH_EPCAP_MULT_MASK 0xc0000000
307 #define QH_EPCAP_MULT_SH 30
308 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
309 #define QH_EPCAP_PORTNUM_SH 23
310 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
311 #define QH_EPCAP_HUBADDR_SH 16
312 #define QH_EPCAP_CMASK_MASK 0x0000ff00
313 #define QH_EPCAP_CMASK_SH 8
314 #define QH_EPCAP_SMASK_MASK 0x000000ff
315 #define QH_EPCAP_SMASK_SH 0
317 uint32_t current_qtd
; // Standard next link pointer
318 uint32_t next_qtd
; // Standard next link pointer
319 uint32_t altnext_qtd
;
320 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
321 #define QH_ALTNEXT_NAKCNT_SH 1
323 uint32_t token
; // Same as QTD token
324 uint32_t bufptr
[5]; // Standard buffer pointer
325 #define BUFPTR_CPROGMASK_MASK 0x000000ff
326 #define BUFPTR_FRAMETAG_MASK 0x0000001f
327 #define BUFPTR_SBYTES_MASK 0x00000fe0
328 #define BUFPTR_SBYTES_SH 5
331 /* EHCI spec version 1.0 Section 3.7
333 typedef struct EHCIfstn
{
334 uint32_t next
; // Standard next link pointer
335 uint32_t backptr
; // Standard next link pointer
338 typedef struct EHCIQueue EHCIQueue
;
339 typedef struct EHCIState EHCIState
;
349 QTAILQ_ENTRY(EHCIQueue
) next
;
354 /* cached data from guest - needs to be flushed
355 * when guest removes an entry (doorbell, handshake sequence)
357 EHCIqh qh
; // copy of current QH (being worked on)
358 uint32_t qhaddr
; // address QH read from
359 EHCIqtd qtd
; // copy of current QTD (being worked on)
360 uint32_t qtdaddr
; // address QTD read from
363 uint8_t buffer
[BUFF_SIZE
];
366 enum async_state async
;
374 target_phys_addr_t mem_base
;
382 * EHCI spec version 1.0 Section 2.3
383 * Host Controller Operational Registers
386 uint8_t mmio
[MMIO_SIZE
];
388 uint8_t cap
[OPREGBASE
];
393 uint32_t ctrldssegment
;
394 uint32_t periodiclistbase
;
395 uint32_t asynclistaddr
;
398 uint32_t portsc
[NB_PORTS
];
403 * Internal states, shadow registers, etc
406 QEMUTimer
*frame_timer
;
407 int attach_poll_counter
;
408 int astate
; // Current state in asynchronous schedule
409 int pstate
; // Current state in periodic schedule
410 USBPort ports
[NB_PORTS
];
411 uint32_t usbsts_pending
;
412 QTAILQ_HEAD(, EHCIQueue
) queues
;
414 uint32_t a_fetch_addr
; // which address to look at next
415 uint32_t p_fetch_addr
; // which address to look at next
418 uint8_t ibuffer
[BUFF_SIZE
];
421 uint64_t last_run_ns
;
424 #define SET_LAST_RUN_CLOCK(s) \
425 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
427 /* nifty macros from Arnon's EHCI version */
428 #define get_field(data, field) \
429 (((data) & field##_MASK) >> field##_SH)
431 #define set_field(data, newval, field) do { \
432 uint32_t val = *data; \
433 val &= ~ field##_MASK; \
434 val |= ((newval) << field##_SH) & field##_MASK; \
438 static const char *ehci_state_names
[] = {
439 [ EST_INACTIVE
] = "INACTIVE",
440 [ EST_ACTIVE
] = "ACTIVE",
441 [ EST_EXECUTING
] = "EXECUTING",
442 [ EST_SLEEPING
] = "SLEEPING",
443 [ EST_WAITLISTHEAD
] = "WAITLISTHEAD",
444 [ EST_FETCHENTRY
] = "FETCH ENTRY",
445 [ EST_FETCHQH
] = "FETCH QH",
446 [ EST_FETCHITD
] = "FETCH ITD",
447 [ EST_ADVANCEQUEUE
] = "ADVANCEQUEUE",
448 [ EST_FETCHQTD
] = "FETCH QTD",
449 [ EST_EXECUTE
] = "EXECUTE",
450 [ EST_WRITEBACK
] = "WRITEBACK",
451 [ EST_HORIZONTALQH
] = "HORIZONTALQH",
454 static const char *ehci_mmio_names
[] = {
455 [ CAPLENGTH
] = "CAPLENGTH",
456 [ HCIVERSION
] = "HCIVERSION",
457 [ HCSPARAMS
] = "HCSPARAMS",
458 [ HCCPARAMS
] = "HCCPARAMS",
459 [ USBCMD
] = "USBCMD",
460 [ USBSTS
] = "USBSTS",
461 [ USBINTR
] = "USBINTR",
462 [ FRINDEX
] = "FRINDEX",
463 [ PERIODICLISTBASE
] = "P-LIST BASE",
464 [ ASYNCLISTADDR
] = "A-LIST ADDR",
465 [ PORTSC_BEGIN
] = "PORTSC #0",
466 [ PORTSC_BEGIN
+ 4] = "PORTSC #1",
467 [ PORTSC_BEGIN
+ 8] = "PORTSC #2",
468 [ PORTSC_BEGIN
+ 12] = "PORTSC #3",
469 [ CONFIGFLAG
] = "CONFIGFLAG",
472 static const char *nr2str(const char **n
, size_t len
, uint32_t nr
)
474 if (nr
< len
&& n
[nr
] != NULL
) {
481 static const char *state2str(uint32_t state
)
483 return nr2str(ehci_state_names
, ARRAY_SIZE(ehci_state_names
), state
);
486 static const char *addr2str(target_phys_addr_t addr
)
488 return nr2str(ehci_mmio_names
, ARRAY_SIZE(ehci_mmio_names
), addr
);
491 static void ehci_trace_usbsts(uint32_t mask
, int state
)
494 if (mask
& USBSTS_INT
) {
495 trace_usb_ehci_usbsts("INT", state
);
497 if (mask
& USBSTS_ERRINT
) {
498 trace_usb_ehci_usbsts("ERRINT", state
);
500 if (mask
& USBSTS_PCD
) {
501 trace_usb_ehci_usbsts("PCD", state
);
503 if (mask
& USBSTS_FLR
) {
504 trace_usb_ehci_usbsts("FLR", state
);
506 if (mask
& USBSTS_HSE
) {
507 trace_usb_ehci_usbsts("HSE", state
);
509 if (mask
& USBSTS_IAA
) {
510 trace_usb_ehci_usbsts("IAA", state
);
514 if (mask
& USBSTS_HALT
) {
515 trace_usb_ehci_usbsts("HALT", state
);
517 if (mask
& USBSTS_REC
) {
518 trace_usb_ehci_usbsts("REC", state
);
520 if (mask
& USBSTS_PSS
) {
521 trace_usb_ehci_usbsts("PSS", state
);
523 if (mask
& USBSTS_ASS
) {
524 trace_usb_ehci_usbsts("ASS", state
);
528 static inline void ehci_set_usbsts(EHCIState
*s
, int mask
)
530 if ((s
->usbsts
& mask
) == mask
) {
533 ehci_trace_usbsts(mask
, 1);
537 static inline void ehci_clear_usbsts(EHCIState
*s
, int mask
)
539 if ((s
->usbsts
& mask
) == 0) {
542 ehci_trace_usbsts(mask
, 0);
546 static inline void ehci_set_interrupt(EHCIState
*s
, int intr
)
550 // TODO honour interrupt threshold requests
552 ehci_set_usbsts(s
, intr
);
554 if ((s
->usbsts
& USBINTR_MASK
) & s
->usbintr
) {
558 qemu_set_irq(s
->irq
, level
);
561 static inline void ehci_record_interrupt(EHCIState
*s
, int intr
)
563 s
->usbsts_pending
|= intr
;
566 static inline void ehci_commit_interrupt(EHCIState
*s
)
568 if (!s
->usbsts_pending
) {
571 ehci_set_interrupt(s
, s
->usbsts_pending
);
572 s
->usbsts_pending
= 0;
575 static void ehci_set_state(EHCIState
*s
, int async
, int state
)
578 trace_usb_ehci_state("async", state2str(state
));
581 trace_usb_ehci_state("periodic", state2str(state
));
586 static int ehci_get_state(EHCIState
*s
, int async
)
588 return async
? s
->astate
: s
->pstate
;
591 static void ehci_set_fetch_addr(EHCIState
*s
, int async
, uint32_t addr
)
594 s
->a_fetch_addr
= addr
;
596 s
->p_fetch_addr
= addr
;
600 static int ehci_get_fetch_addr(EHCIState
*s
, int async
)
602 return async
? s
->a_fetch_addr
: s
->p_fetch_addr
;
605 static void ehci_trace_qh(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqh
*qh
)
607 /* need three here due to argument count limits */
608 trace_usb_ehci_qh_ptrs(q
, addr
, qh
->next
,
609 qh
->current_qtd
, qh
->next_qtd
, qh
->altnext_qtd
);
610 trace_usb_ehci_qh_fields(addr
,
611 get_field(qh
->epchar
, QH_EPCHAR_RL
),
612 get_field(qh
->epchar
, QH_EPCHAR_MPLEN
),
613 get_field(qh
->epchar
, QH_EPCHAR_EPS
),
614 get_field(qh
->epchar
, QH_EPCHAR_EP
),
615 get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
));
616 trace_usb_ehci_qh_bits(addr
,
617 (bool)(qh
->epchar
& QH_EPCHAR_C
),
618 (bool)(qh
->epchar
& QH_EPCHAR_H
),
619 (bool)(qh
->epchar
& QH_EPCHAR_DTC
),
620 (bool)(qh
->epchar
& QH_EPCHAR_I
));
623 static void ehci_trace_qtd(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqtd
*qtd
)
625 /* need three here due to argument count limits */
626 trace_usb_ehci_qtd_ptrs(q
, addr
, qtd
->next
, qtd
->altnext
);
627 trace_usb_ehci_qtd_fields(addr
,
628 get_field(qtd
->token
, QTD_TOKEN_TBYTES
),
629 get_field(qtd
->token
, QTD_TOKEN_CPAGE
),
630 get_field(qtd
->token
, QTD_TOKEN_CERR
),
631 get_field(qtd
->token
, QTD_TOKEN_PID
));
632 trace_usb_ehci_qtd_bits(addr
,
633 (bool)(qtd
->token
& QTD_TOKEN_IOC
),
634 (bool)(qtd
->token
& QTD_TOKEN_ACTIVE
),
635 (bool)(qtd
->token
& QTD_TOKEN_HALT
),
636 (bool)(qtd
->token
& QTD_TOKEN_BABBLE
),
637 (bool)(qtd
->token
& QTD_TOKEN_XACTERR
));
640 static void ehci_trace_itd(EHCIState
*s
, target_phys_addr_t addr
, EHCIitd
*itd
)
642 trace_usb_ehci_itd(addr
, itd
->next
,
643 get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
),
644 get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
),
645 get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
),
646 get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
));
649 /* queue management */
651 static EHCIQueue
*ehci_alloc_queue(EHCIState
*ehci
, int async
)
655 q
= qemu_mallocz(sizeof(*q
));
657 q
->async_schedule
= async
;
658 QTAILQ_INSERT_HEAD(&ehci
->queues
, q
, next
);
659 trace_usb_ehci_queue_action(q
, "alloc");
663 static void ehci_free_queue(EHCIQueue
*q
)
665 trace_usb_ehci_queue_action(q
, "free");
666 if (q
->async
== EHCI_ASYNC_INFLIGHT
) {
667 usb_cancel_packet(&q
->packet
);
669 QTAILQ_REMOVE(&q
->ehci
->queues
, q
, next
);
673 static EHCIQueue
*ehci_find_queue_by_qh(EHCIState
*ehci
, uint32_t addr
)
677 QTAILQ_FOREACH(q
, &ehci
->queues
, next
) {
678 if (addr
== q
->qhaddr
) {
685 static void ehci_queues_rip_unused(EHCIState
*ehci
)
689 QTAILQ_FOREACH_SAFE(q
, &ehci
->queues
, next
, tmp
) {
692 q
->ts
= ehci
->last_run_ns
;
695 if (ehci
->last_run_ns
< q
->ts
+ 250000000) {
696 /* allow 0.25 sec idle */
703 static void ehci_queues_rip_device(EHCIState
*ehci
, USBDevice
*dev
)
707 QTAILQ_FOREACH_SAFE(q
, &ehci
->queues
, next
, tmp
) {
708 if (q
->packet
.owner
!= dev
) {
715 static void ehci_queues_rip_all(EHCIState
*ehci
)
719 QTAILQ_FOREACH_SAFE(q
, &ehci
->queues
, next
, tmp
) {
724 /* Attach or detach a device on root hub */
726 static void ehci_attach(USBPort
*port
)
728 EHCIState
*s
= port
->opaque
;
729 uint32_t *portsc
= &s
->portsc
[port
->index
];
731 trace_usb_ehci_port_attach(port
->index
, port
->dev
->product_desc
);
733 *portsc
|= PORTSC_CONNECT
;
734 *portsc
|= PORTSC_CSC
;
737 * If a high speed device is attached then we own this port(indicated
738 * by zero in the PORTSC_POWNER bit field) so set the status bit
739 * and set an interrupt if enabled.
741 if ( !(*portsc
& PORTSC_POWNER
)) {
742 ehci_set_interrupt(s
, USBSTS_PCD
);
746 static void ehci_detach(USBPort
*port
)
748 EHCIState
*s
= port
->opaque
;
749 uint32_t *portsc
= &s
->portsc
[port
->index
];
751 trace_usb_ehci_port_detach(port
->index
);
753 ehci_queues_rip_device(s
, port
->dev
);
755 *portsc
&= ~PORTSC_CONNECT
;
756 *portsc
|= PORTSC_CSC
;
759 * If a high speed device is attached then we own this port(indicated
760 * by zero in the PORTSC_POWNER bit field) so set the status bit
761 * and set an interrupt if enabled.
763 if ( !(*portsc
& PORTSC_POWNER
)) {
764 ehci_set_interrupt(s
, USBSTS_PCD
);
768 static void ehci_child_detach(USBPort
*port
, USBDevice
*child
)
770 EHCIState
*s
= port
->opaque
;
772 ehci_queues_rip_device(s
, child
);
775 /* 4.1 host controller initialization */
776 static void ehci_reset(void *opaque
)
778 EHCIState
*s
= opaque
;
781 trace_usb_ehci_reset();
783 memset(&s
->mmio
[OPREGBASE
], 0x00, MMIO_SIZE
- OPREGBASE
);
785 s
->usbcmd
= NB_MAXINTRATE
<< USBCMD_ITC_SH
;
786 s
->usbsts
= USBSTS_HALT
;
788 s
->astate
= EST_INACTIVE
;
789 s
->pstate
= EST_INACTIVE
;
791 s
->attach_poll_counter
= 0;
793 for(i
= 0; i
< NB_PORTS
; i
++) {
794 s
->portsc
[i
] = PORTSC_POWNER
| PORTSC_PPOWER
;
796 if (s
->ports
[i
].dev
) {
797 usb_attach(&s
->ports
[i
], s
->ports
[i
].dev
);
800 ehci_queues_rip_all(s
);
803 static uint32_t ehci_mem_readb(void *ptr
, target_phys_addr_t addr
)
813 static uint32_t ehci_mem_readw(void *ptr
, target_phys_addr_t addr
)
818 val
= s
->mmio
[addr
] | (s
->mmio
[addr
+1] << 8);
823 static uint32_t ehci_mem_readl(void *ptr
, target_phys_addr_t addr
)
828 val
= s
->mmio
[addr
] | (s
->mmio
[addr
+1] << 8) |
829 (s
->mmio
[addr
+2] << 16) | (s
->mmio
[addr
+3] << 24);
831 trace_usb_ehci_mmio_readl(addr
, addr2str(addr
), val
);
835 static void ehci_mem_writeb(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
837 fprintf(stderr
, "EHCI doesn't handle byte writes to MMIO\n");
841 static void ehci_mem_writew(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
843 fprintf(stderr
, "EHCI doesn't handle 16-bit writes to MMIO\n");
847 static void handle_port_status_write(EHCIState
*s
, int port
, uint32_t val
)
849 uint32_t *portsc
= &s
->portsc
[port
];
851 USBDevice
*dev
= s
->ports
[port
].dev
;
853 rwc
= val
& PORTSC_RWC_MASK
;
854 val
&= PORTSC_RO_MASK
;
856 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
860 if ((val
& PORTSC_PRESET
) && !(*portsc
& PORTSC_PRESET
)) {
861 trace_usb_ehci_port_reset(port
, 1);
864 if (!(val
& PORTSC_PRESET
) &&(*portsc
& PORTSC_PRESET
)) {
865 trace_usb_ehci_port_reset(port
, 0);
866 usb_attach(&s
->ports
[port
], dev
);
868 // TODO how to handle reset of ports with no device
870 usb_send_msg(dev
, USB_MSG_RESET
);
873 if (s
->ports
[port
].dev
) {
874 *portsc
&= ~PORTSC_CSC
;
877 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
878 * to SW that this port has a high speed device attached
880 * TODO - when to disable?
886 *portsc
&= ~PORTSC_RO_MASK
;
890 static void ehci_mem_writel(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
893 uint32_t *mmio
= (uint32_t *)(&s
->mmio
[addr
]);
894 uint32_t old
= *mmio
;
897 trace_usb_ehci_mmio_writel(addr
, addr2str(addr
), val
);
899 /* Only aligned reads are allowed on OHCI */
901 fprintf(stderr
, "usb-ehci: Mis-aligned write to addr 0x"
902 TARGET_FMT_plx
"\n", addr
);
906 if (addr
>= PORTSC
&& addr
< PORTSC
+ 4 * NB_PORTS
) {
907 handle_port_status_write(s
, (addr
-PORTSC
)/4, val
);
908 trace_usb_ehci_mmio_change(addr
, addr2str(addr
), *mmio
, old
);
912 if (addr
< OPREGBASE
) {
913 fprintf(stderr
, "usb-ehci: write attempt to read-only register"
914 TARGET_FMT_plx
"\n", addr
);
919 /* Do any register specific pre-write processing here. */
922 if ((val
& USBCMD_RUNSTOP
) && !(s
->usbcmd
& USBCMD_RUNSTOP
)) {
923 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
924 SET_LAST_RUN_CLOCK(s
);
925 ehci_clear_usbsts(s
, USBSTS_HALT
);
928 if (!(val
& USBCMD_RUNSTOP
) && (s
->usbcmd
& USBCMD_RUNSTOP
)) {
929 qemu_del_timer(s
->frame_timer
);
930 // TODO - should finish out some stuff before setting halt
931 ehci_set_usbsts(s
, USBSTS_HALT
);
934 if (val
& USBCMD_HCRESET
) {
936 val
&= ~USBCMD_HCRESET
;
939 /* not supporting dynamic frame list size at the moment */
940 if ((val
& USBCMD_FLS
) && !(s
->usbcmd
& USBCMD_FLS
)) {
941 fprintf(stderr
, "attempt to set frame list size -- value %d\n",
948 val
&= USBSTS_RO_MASK
; // bits 6 thru 31 are RO
949 ehci_clear_usbsts(s
, val
); // bits 0 thru 5 are R/WC
951 ehci_set_interrupt(s
, 0);
965 for(i
= 0; i
< NB_PORTS
; i
++)
966 s
->portsc
[i
] &= ~PORTSC_POWNER
;
970 case PERIODICLISTBASE
:
971 if ((s
->usbcmd
& USBCMD_PSE
) && (s
->usbcmd
& USBCMD_RUNSTOP
)) {
973 "ehci: PERIODIC list base register set while periodic schedule\n"
974 " is enabled and HC is enabled\n");
979 if ((s
->usbcmd
& USBCMD_ASE
) && (s
->usbcmd
& USBCMD_RUNSTOP
)) {
981 "ehci: ASYNC list address register set while async schedule\n"
982 " is enabled and HC is enabled\n");
988 trace_usb_ehci_mmio_change(addr
, addr2str(addr
), *mmio
, old
);
992 // TODO : Put in common header file, duplication from usb-ohci.c
994 /* Get an array of dwords from main memory */
995 static inline int get_dwords(uint32_t addr
, uint32_t *buf
, int num
)
999 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1000 cpu_physical_memory_rw(addr
,(uint8_t *)buf
, sizeof(*buf
), 0);
1001 *buf
= le32_to_cpu(*buf
);
1007 /* Put an array of dwords in to main memory */
1008 static inline int put_dwords(uint32_t addr
, uint32_t *buf
, int num
)
1012 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1013 uint32_t tmp
= cpu_to_le32(*buf
);
1014 cpu_physical_memory_rw(addr
,(uint8_t *)&tmp
, sizeof(tmp
), 1);
1022 static int ehci_qh_do_overlay(EHCIQueue
*q
)
1030 // remember values in fields to preserve in qh after overlay
1032 dtoggle
= q
->qh
.token
& QTD_TOKEN_DTOGGLE
;
1033 ping
= q
->qh
.token
& QTD_TOKEN_PING
;
1035 q
->qh
.current_qtd
= q
->qtdaddr
;
1036 q
->qh
.next_qtd
= q
->qtd
.next
;
1037 q
->qh
.altnext_qtd
= q
->qtd
.altnext
;
1038 q
->qh
.token
= q
->qtd
.token
;
1041 eps
= get_field(q
->qh
.epchar
, QH_EPCHAR_EPS
);
1042 if (eps
== EHCI_QH_EPS_HIGH
) {
1043 q
->qh
.token
&= ~QTD_TOKEN_PING
;
1044 q
->qh
.token
|= ping
;
1047 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1048 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1050 for (i
= 0; i
< 5; i
++) {
1051 q
->qh
.bufptr
[i
] = q
->qtd
.bufptr
[i
];
1054 if (!(q
->qh
.epchar
& QH_EPCHAR_DTC
)) {
1055 // preserve QH DT bit
1056 q
->qh
.token
&= ~QTD_TOKEN_DTOGGLE
;
1057 q
->qh
.token
|= dtoggle
;
1060 q
->qh
.bufptr
[1] &= ~BUFPTR_CPROGMASK_MASK
;
1061 q
->qh
.bufptr
[2] &= ~BUFPTR_FRAMETAG_MASK
;
1063 put_dwords(NLPTR_GET(q
->qhaddr
), (uint32_t *) &q
->qh
, sizeof(EHCIqh
) >> 2);
1068 static int ehci_buffer_rw(EHCIQueue
*q
, int bytes
, int rw
)
1080 cpage
= get_field(q
->qh
.token
, QTD_TOKEN_CPAGE
);
1082 fprintf(stderr
, "cpage out of range (%d)\n", cpage
);
1083 return USB_RET_PROCERR
;
1086 offset
= q
->qh
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1089 /* start and end of this page */
1090 head
= q
->qh
.bufptr
[cpage
] & QTD_BUFPTR_MASK
;
1091 tail
= head
+ ~QTD_BUFPTR_MASK
+ 1;
1092 /* add offset into page */
1095 if (bytes
<= (tail
- head
)) {
1096 tail
= head
+ bytes
;
1099 trace_usb_ehci_data(rw
, cpage
, offset
, head
, tail
-head
, bufpos
);
1100 cpu_physical_memory_rw(head
, q
->buffer
+ bufpos
, tail
- head
, rw
);
1102 bufpos
+= (tail
- head
);
1103 offset
+= (tail
- head
);
1104 bytes
-= (tail
- head
);
1110 } while (bytes
> 0);
1113 set_field(&q
->qh
.token
, cpage
, QTD_TOKEN_CPAGE
);
1115 /* save offset into cpage */
1116 q
->qh
.bufptr
[0] &= QTD_BUFPTR_MASK
;
1117 q
->qh
.bufptr
[0] |= offset
;
1122 static void ehci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
1124 EHCIQueue
*q
= container_of(packet
, EHCIQueue
, packet
);
1126 trace_usb_ehci_queue_action(q
, "wakeup");
1127 assert(q
->async
== EHCI_ASYNC_INFLIGHT
);
1128 q
->async
= EHCI_ASYNC_FINISHED
;
1129 q
->usb_status
= packet
->len
;
1132 static void ehci_execute_complete(EHCIQueue
*q
)
1136 assert(q
->async
!= EHCI_ASYNC_INFLIGHT
);
1137 q
->async
= EHCI_ASYNC_NONE
;
1139 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1140 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->usb_status
);
1142 if (q
->usb_status
< 0) {
1144 /* TO-DO: put this is in a function that can be invoked below as well */
1145 c_err
= get_field(q
->qh
.token
, QTD_TOKEN_CERR
);
1147 set_field(&q
->qh
.token
, c_err
, QTD_TOKEN_CERR
);
1149 switch(q
->usb_status
) {
1151 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_XACTERR
);
1152 ehci_record_interrupt(q
->ehci
, USBSTS_ERRINT
);
1155 q
->qh
.token
|= QTD_TOKEN_HALT
;
1156 ehci_record_interrupt(q
->ehci
, USBSTS_ERRINT
);
1160 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1161 if ((q
->pid
== USB_TOKEN_IN
) && reload
) {
1162 int nakcnt
= get_field(q
->qh
.altnext_qtd
, QH_ALTNEXT_NAKCNT
);
1164 set_field(&q
->qh
.altnext_qtd
, nakcnt
, QH_ALTNEXT_NAKCNT
);
1165 } else if (!reload
) {
1169 case USB_RET_BABBLE
:
1170 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1171 ehci_record_interrupt(q
->ehci
, USBSTS_ERRINT
);
1174 /* should not be triggerable */
1175 fprintf(stderr
, "USB invalid response %d to handle\n", q
->usb_status
);
1180 // DPRINTF("Short packet condition\n");
1181 // TODO check 4.12 for splits
1183 if ((q
->usb_status
> q
->tbytes
) && (q
->pid
== USB_TOKEN_IN
)) {
1184 q
->usb_status
= USB_RET_BABBLE
;
1188 if (q
->tbytes
&& q
->pid
== USB_TOKEN_IN
) {
1189 if (ehci_buffer_rw(q
, q
->usb_status
, 1) != 0) {
1190 q
->usb_status
= USB_RET_PROCERR
;
1193 q
->tbytes
-= q
->usb_status
;
1198 DPRINTF("updating tbytes to %d\n", q
->tbytes
);
1199 set_field(&q
->qh
.token
, q
->tbytes
, QTD_TOKEN_TBYTES
);
1202 q
->qh
.token
^= QTD_TOKEN_DTOGGLE
;
1203 q
->qh
.token
&= ~QTD_TOKEN_ACTIVE
;
1205 if ((q
->usb_status
>= 0) && (q
->qh
.token
& QTD_TOKEN_IOC
)) {
1206 ehci_record_interrupt(q
->ehci
, USBSTS_INT
);
1212 static int ehci_execute(EHCIQueue
*q
)
1221 if ( !(q
->qh
.token
& QTD_TOKEN_ACTIVE
)) {
1222 fprintf(stderr
, "Attempting to execute inactive QH\n");
1223 return USB_RET_PROCERR
;
1226 q
->tbytes
= (q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) >> QTD_TOKEN_TBYTES_SH
;
1227 if (q
->tbytes
> BUFF_SIZE
) {
1228 fprintf(stderr
, "Request for more bytes than allowed\n");
1229 return USB_RET_PROCERR
;
1232 q
->pid
= (q
->qh
.token
& QTD_TOKEN_PID_MASK
) >> QTD_TOKEN_PID_SH
;
1234 case 0: q
->pid
= USB_TOKEN_OUT
; break;
1235 case 1: q
->pid
= USB_TOKEN_IN
; break;
1236 case 2: q
->pid
= USB_TOKEN_SETUP
; break;
1237 default: fprintf(stderr
, "bad token\n"); break;
1240 if ((q
->tbytes
&& q
->pid
!= USB_TOKEN_IN
) &&
1241 (ehci_buffer_rw(q
, q
->tbytes
, 0) != 0)) {
1242 return USB_RET_PROCERR
;
1245 endp
= get_field(q
->qh
.epchar
, QH_EPCHAR_EP
);
1246 devadr
= get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
);
1248 ret
= USB_RET_NODEV
;
1250 // TO-DO: associating device with ehci port
1251 for(i
= 0; i
< NB_PORTS
; i
++) {
1252 port
= &q
->ehci
->ports
[i
];
1255 // TODO sometime we will also need to check if we are the port owner
1257 if (!(q
->ehci
->portsc
[i
] &(PORTSC_CONNECT
))) {
1258 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1259 i
, q
->ehci
->portsc
[i
]);
1263 q
->packet
.pid
= q
->pid
;
1264 q
->packet
.devaddr
= devadr
;
1265 q
->packet
.devep
= endp
;
1266 q
->packet
.data
= q
->buffer
;
1267 q
->packet
.len
= q
->tbytes
;
1269 ret
= usb_handle_packet(dev
, &q
->packet
);
1271 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1272 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->pid
,
1273 q
->packet
.len
, q
->tbytes
, endp
, ret
);
1275 if (ret
!= USB_RET_NODEV
) {
1280 if (ret
> BUFF_SIZE
) {
1281 fprintf(stderr
, "ret from usb_handle_packet > BUFF_SIZE\n");
1282 return USB_RET_PROCERR
;
1291 static int ehci_process_itd(EHCIState
*ehci
,
1297 uint32_t i
, j
, len
, len1
, len2
, pid
, dir
, devaddr
, endp
;
1298 uint32_t pg
, off
, ptr1
, ptr2
, max
, mult
;
1300 dir
=(itd
->bufptr
[1] & ITD_BUFPTR_DIRECTION
);
1301 devaddr
= get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
);
1302 endp
= get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
);
1303 max
= get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
);
1304 mult
= get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
);
1306 for(i
= 0; i
< 8; i
++) {
1307 if (itd
->transact
[i
] & ITD_XACT_ACTIVE
) {
1308 pg
= get_field(itd
->transact
[i
], ITD_XACT_PGSEL
);
1309 off
= itd
->transact
[i
] & ITD_XACT_OFFSET_MASK
;
1310 ptr1
= (itd
->bufptr
[pg
] & ITD_BUFPTR_MASK
);
1311 ptr2
= (itd
->bufptr
[pg
+1] & ITD_BUFPTR_MASK
);
1312 len
= get_field(itd
->transact
[i
], ITD_XACT_LENGTH
);
1314 if (len
> max
* mult
) {
1318 if (len
> BUFF_SIZE
) {
1319 return USB_RET_PROCERR
;
1322 if (off
+ len
> 4096) {
1323 /* transfer crosses page border */
1324 len2
= off
+ len
- 4096;
1332 pid
= USB_TOKEN_OUT
;
1333 trace_usb_ehci_data(0, pg
, off
, ptr1
+ off
, len1
, 0);
1334 cpu_physical_memory_rw(ptr1
+ off
, &ehci
->ibuffer
[0], len1
, 0);
1336 trace_usb_ehci_data(0, pg
+1, 0, ptr2
, len2
, len1
);
1337 cpu_physical_memory_rw(ptr2
, &ehci
->ibuffer
[len1
], len2
, 0);
1343 ret
= USB_RET_NODEV
;
1345 for (j
= 0; j
< NB_PORTS
; j
++) {
1346 port
= &ehci
->ports
[j
];
1349 // TODO sometime we will also need to check if we are the port owner
1351 if (!(ehci
->portsc
[j
] &(PORTSC_CONNECT
))) {
1355 ehci
->ipacket
.pid
= pid
;
1356 ehci
->ipacket
.devaddr
= devaddr
;
1357 ehci
->ipacket
.devep
= endp
;
1358 ehci
->ipacket
.data
= ehci
->ibuffer
;
1359 ehci
->ipacket
.len
= len
;
1361 ret
= usb_handle_packet(dev
, &ehci
->ipacket
);
1363 if (ret
!= USB_RET_NODEV
) {
1369 /* In isoch, there is no facility to indicate a NAK so let's
1370 * instead just complete a zero-byte transaction. Setting
1371 * DBERR seems too draconian.
1374 if (ret
== USB_RET_NAK
) {
1375 if (ehci
->isoch_pause
> 0) {
1376 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1377 ehci
->isoch_pause
--;
1379 } else if (ehci
->isoch_pause
== -1) {
1380 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1381 // Pause frindex for up to 50 msec waiting for data from
1383 ehci
->isoch_pause
= 50;
1386 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1390 DPRINTF("ISOCH: received ACK, clearing pause\n");
1391 ehci
->isoch_pause
= -1;
1394 if (ret
== USB_RET_NAK
) {
1402 set_field(&itd
->transact
[i
], len
- ret
, ITD_XACT_LENGTH
);
1408 if (len2
> ret
- len1
) {
1412 trace_usb_ehci_data(1, pg
, off
, ptr1
+ off
, len1
, 0);
1413 cpu_physical_memory_rw(ptr1
+ off
, &ehci
->ibuffer
[0], len1
, 1);
1416 trace_usb_ehci_data(1, pg
+1, 0, ptr2
, len2
, len1
);
1417 cpu_physical_memory_rw(ptr2
, &ehci
->ibuffer
[len1
], len2
, 1);
1419 set_field(&itd
->transact
[i
], ret
, ITD_XACT_LENGTH
);
1422 if (itd
->transact
[i
] & ITD_XACT_IOC
) {
1423 ehci_record_interrupt(ehci
, USBSTS_INT
);
1426 itd
->transact
[i
] &= ~ITD_XACT_ACTIVE
;
1432 /* This state is the entry point for asynchronous schedule
1433 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1435 static int ehci_state_waitlisthead(EHCIState
*ehci
, int async
)
1440 uint32_t entry
= ehci
->asynclistaddr
;
1442 /* set reclamation flag at start event (4.8.6) */
1444 ehci_set_usbsts(ehci
, USBSTS_REC
);
1447 ehci_queues_rip_unused(ehci
);
1449 /* Find the head of the list (4.9.1.1) */
1450 for(i
= 0; i
< MAX_QH
; i
++) {
1451 get_dwords(NLPTR_GET(entry
), (uint32_t *) &qh
, sizeof(EHCIqh
) >> 2);
1452 ehci_trace_qh(NULL
, NLPTR_GET(entry
), &qh
);
1454 if (qh
.epchar
& QH_EPCHAR_H
) {
1456 entry
|= (NLPTR_TYPE_QH
<< 1);
1459 ehci_set_fetch_addr(ehci
, async
, entry
);
1460 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1466 if (entry
== ehci
->asynclistaddr
) {
1471 /* no head found for list. */
1473 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1480 /* This state is the entry point for periodic schedule processing as
1481 * well as being a continuation state for async processing.
1483 static int ehci_state_fetchentry(EHCIState
*ehci
, int async
)
1486 uint32_t entry
= ehci_get_fetch_addr(ehci
, async
);
1488 if (entry
< 0x1000) {
1489 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry
);
1490 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1494 /* section 4.8, only QH in async schedule */
1495 if (async
&& (NLPTR_TYPE_GET(entry
) != NLPTR_TYPE_QH
)) {
1496 fprintf(stderr
, "non queue head request in async schedule\n");
1500 switch (NLPTR_TYPE_GET(entry
)) {
1502 ehci_set_state(ehci
, async
, EST_FETCHQH
);
1506 case NLPTR_TYPE_ITD
:
1507 ehci_set_state(ehci
, async
, EST_FETCHITD
);
1512 // TODO: handle siTD and FSTN types
1513 fprintf(stderr
, "FETCHENTRY: entry at %X is of type %d "
1514 "which is not supported yet\n", entry
, NLPTR_TYPE_GET(entry
));
1522 static EHCIQueue
*ehci_state_fetchqh(EHCIState
*ehci
, int async
)
1528 entry
= ehci_get_fetch_addr(ehci
, async
);
1529 q
= ehci_find_queue_by_qh(ehci
, entry
);
1531 q
= ehci_alloc_queue(ehci
, async
);
1537 /* we are going in circles -- stop processing */
1538 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1543 get_dwords(NLPTR_GET(q
->qhaddr
), (uint32_t *) &q
->qh
, sizeof(EHCIqh
) >> 2);
1544 ehci_trace_qh(q
, NLPTR_GET(q
->qhaddr
), &q
->qh
);
1546 if (q
->async
== EHCI_ASYNC_INFLIGHT
) {
1547 /* I/O still in progress -- skip queue */
1548 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1551 if (q
->async
== EHCI_ASYNC_FINISHED
) {
1552 /* I/O finished -- continue processing queue */
1553 trace_usb_ehci_queue_action(q
, "resume");
1554 ehci_set_state(ehci
, async
, EST_EXECUTING
);
1558 if (async
&& (q
->qh
.epchar
& QH_EPCHAR_H
)) {
1560 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1561 if (ehci
->usbsts
& USBSTS_REC
) {
1562 ehci_clear_usbsts(ehci
, USBSTS_REC
);
1564 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1565 " - done processing\n", q
->qhaddr
);
1566 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1573 if (q
->qhaddr
!= q
->qh
.next
) {
1574 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1576 q
->qh
.epchar
& QH_EPCHAR_H
,
1577 q
->qh
.token
& QTD_TOKEN_HALT
,
1578 q
->qh
.token
& QTD_TOKEN_ACTIVE
,
1583 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1585 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1588 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1589 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1591 } else if ((q
->qh
.token
& QTD_TOKEN_ACTIVE
) && (q
->qh
.current_qtd
> 0x1000)) {
1592 q
->qtdaddr
= q
->qh
.current_qtd
;
1593 ehci_set_state(ehci
, async
, EST_FETCHQTD
);
1596 /* EHCI spec version 1.0 Section 4.10.2 */
1597 ehci_set_state(ehci
, async
, EST_ADVANCEQUEUE
);
1604 static int ehci_state_fetchitd(EHCIState
*ehci
, int async
)
1610 entry
= ehci_get_fetch_addr(ehci
, async
);
1612 get_dwords(NLPTR_GET(entry
),(uint32_t *) &itd
,
1613 sizeof(EHCIitd
) >> 2);
1614 ehci_trace_itd(ehci
, entry
, &itd
);
1616 if (ehci_process_itd(ehci
, &itd
) != 0) {
1620 put_dwords(NLPTR_GET(entry
), (uint32_t *) &itd
,
1621 sizeof(EHCIitd
) >> 2);
1622 ehci_set_fetch_addr(ehci
, async
, itd
.next
);
1623 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1628 /* Section 4.10.2 - paragraph 3 */
1629 static int ehci_state_advqueue(EHCIQueue
*q
, int async
)
1632 /* TO-DO: 4.10.2 - paragraph 2
1633 * if I-bit is set to 1 and QH is not active
1634 * go to horizontal QH
1637 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1643 * want data and alt-next qTD is valid
1645 if (((q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) != 0) &&
1646 (q
->qh
.altnext_qtd
> 0x1000) &&
1647 (NLPTR_TBIT(q
->qh
.altnext_qtd
) == 0)) {
1648 q
->qtdaddr
= q
->qh
.altnext_qtd
;
1649 ehci_set_state(q
->ehci
, async
, EST_FETCHQTD
);
1654 } else if ((q
->qh
.next_qtd
> 0x1000) &&
1655 (NLPTR_TBIT(q
->qh
.next_qtd
) == 0)) {
1656 q
->qtdaddr
= q
->qh
.next_qtd
;
1657 ehci_set_state(q
->ehci
, async
, EST_FETCHQTD
);
1660 * no valid qTD, try next QH
1663 ehci_set_state(q
->ehci
, async
, EST_HORIZONTALQH
);
1669 /* Section 4.10.2 - paragraph 4 */
1670 static int ehci_state_fetchqtd(EHCIQueue
*q
, int async
)
1674 get_dwords(NLPTR_GET(q
->qtdaddr
),(uint32_t *) &q
->qtd
, sizeof(EHCIqtd
) >> 2);
1675 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), &q
->qtd
);
1677 if (q
->qtd
.token
& QTD_TOKEN_ACTIVE
) {
1678 ehci_set_state(q
->ehci
, async
, EST_EXECUTE
);
1681 ehci_set_state(q
->ehci
, async
, EST_HORIZONTALQH
);
1688 static int ehci_state_horizqh(EHCIQueue
*q
, int async
)
1692 if (ehci_get_fetch_addr(q
->ehci
, async
) != q
->qh
.next
) {
1693 ehci_set_fetch_addr(q
->ehci
, async
, q
->qh
.next
);
1694 ehci_set_state(q
->ehci
, async
, EST_FETCHENTRY
);
1697 ehci_set_state(q
->ehci
, async
, EST_ACTIVE
);
1704 * Write the qh back to guest physical memory. This step isn't
1705 * in the EHCI spec but we need to do it since we don't share
1706 * physical memory with our guest VM.
1708 * The first three dwords are read-only for the EHCI, so skip them
1709 * when writing back the qh.
1711 static void ehci_flush_qh(EHCIQueue
*q
)
1713 uint32_t *qh
= (uint32_t *) &q
->qh
;
1714 uint32_t dwords
= sizeof(EHCIqh
) >> 2;
1715 uint32_t addr
= NLPTR_GET(q
->qhaddr
);
1717 put_dwords(addr
+ 3 * sizeof(uint32_t), qh
+ 3, dwords
- 3);
1720 static int ehci_state_execute(EHCIQueue
*q
, int async
)
1726 if (ehci_qh_do_overlay(q
) != 0) {
1730 smask
= get_field(q
->qh
.epcap
, QH_EPCAP_SMASK
);
1733 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1734 nakcnt
= get_field(q
->qh
.altnext_qtd
, QH_ALTNEXT_NAKCNT
);
1735 if (reload
&& !nakcnt
) {
1736 ehci_set_state(q
->ehci
, async
, EST_HORIZONTALQH
);
1742 // TODO verify enough time remains in the uframe as in 4.4.1.1
1743 // TODO write back ptr to async list when done or out of time
1744 // TODO Windows does not seem to ever set the MULT field
1747 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
1749 ehci_set_state(q
->ehci
, async
, EST_HORIZONTALQH
);
1756 ehci_set_usbsts(q
->ehci
, USBSTS_REC
);
1759 q
->usb_status
= ehci_execute(q
);
1760 if (q
->usb_status
== USB_RET_PROCERR
) {
1764 if (q
->usb_status
== USB_RET_ASYNC
) {
1766 trace_usb_ehci_queue_action(q
, "suspend");
1767 q
->async
= EHCI_ASYNC_INFLIGHT
;
1768 ehci_set_state(q
->ehci
, async
, EST_HORIZONTALQH
);
1773 ehci_set_state(q
->ehci
, async
, EST_EXECUTING
);
1780 static int ehci_state_executing(EHCIQueue
*q
, int async
)
1785 ehci_execute_complete(q
);
1786 if (q
->usb_status
== USB_RET_ASYNC
) {
1789 if (q
->usb_status
== USB_RET_PROCERR
) {
1796 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
1798 set_field(&q
->qh
.epcap
, transactCtr
, QH_EPCAP_MULT
);
1799 // 4.10.3, bottom of page 82, should exit this state when transaction
1800 // counter decrements to 0
1803 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1805 nakcnt
= get_field(q
->qh
.altnext_qtd
, QH_ALTNEXT_NAKCNT
);
1806 if (q
->usb_status
== USB_RET_NAK
) {
1813 set_field(&q
->qh
.altnext_qtd
, nakcnt
, QH_ALTNEXT_NAKCNT
);
1817 if ((q
->usb_status
== USB_RET_NAK
) || (q
->qh
.token
& QTD_TOKEN_ACTIVE
)) {
1818 ehci_set_state(q
->ehci
, async
, EST_HORIZONTALQH
);
1820 ehci_set_state(q
->ehci
, async
, EST_WRITEBACK
);
1831 static int ehci_state_writeback(EHCIQueue
*q
, int async
)
1835 /* Write back the QTD from the QH area */
1836 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), (EHCIqtd
*) &q
->qh
.next_qtd
);
1837 put_dwords(NLPTR_GET(q
->qtdaddr
),(uint32_t *) &q
->qh
.next_qtd
,
1838 sizeof(EHCIqtd
) >> 2);
1841 * EHCI specs say go horizontal here.
1843 * We can also advance the queue here for performance reasons. We
1844 * need to take care to only take that shortcut in case we've
1845 * processed the qtd just written back without errors, i.e. halt
1848 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1849 ehci_set_state(q
->ehci
, async
, EST_HORIZONTALQH
);
1852 ehci_set_state(q
->ehci
, async
, EST_ADVANCEQUEUE
);
1859 * This is the state machine that is common to both async and periodic
1862 static void ehci_advance_state(EHCIState
*ehci
,
1865 EHCIQueue
*q
= NULL
;
1870 if (ehci_get_state(ehci
, async
) == EST_FETCHQH
) {
1872 /* if we are roaming a lot of QH without executing a qTD
1873 * something is wrong with the linked list. TO-DO: why is
1876 assert(iter
< MAX_ITERATIONS
);
1878 if (iter
> MAX_ITERATIONS
) {
1879 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1880 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1885 switch(ehci_get_state(ehci
, async
)) {
1886 case EST_WAITLISTHEAD
:
1887 again
= ehci_state_waitlisthead(ehci
, async
);
1890 case EST_FETCHENTRY
:
1891 again
= ehci_state_fetchentry(ehci
, async
);
1895 q
= ehci_state_fetchqh(ehci
, async
);
1900 again
= ehci_state_fetchitd(ehci
, async
);
1903 case EST_ADVANCEQUEUE
:
1904 again
= ehci_state_advqueue(q
, async
);
1908 again
= ehci_state_fetchqtd(q
, async
);
1911 case EST_HORIZONTALQH
:
1912 again
= ehci_state_horizqh(q
, async
);
1917 again
= ehci_state_execute(q
, async
);
1922 again
= ehci_state_executing(q
, async
);
1926 again
= ehci_state_writeback(q
, async
);
1930 fprintf(stderr
, "Bad state!\n");
1937 fprintf(stderr
, "processing error - resetting ehci HC\n");
1945 ehci_commit_interrupt(ehci
);
1948 static void ehci_advance_async_state(EHCIState
*ehci
)
1952 switch(ehci_get_state(ehci
, async
)) {
1954 if (!(ehci
->usbcmd
& USBCMD_ASE
)) {
1957 ehci_set_usbsts(ehci
, USBSTS_ASS
);
1958 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1959 // No break, fall through to ACTIVE
1962 if ( !(ehci
->usbcmd
& USBCMD_ASE
)) {
1963 ehci_clear_usbsts(ehci
, USBSTS_ASS
);
1964 ehci_set_state(ehci
, async
, EST_INACTIVE
);
1968 /* If the doorbell is set, the guest wants to make a change to the
1969 * schedule. The host controller needs to release cached data.
1972 if (ehci
->usbcmd
& USBCMD_IAAD
) {
1973 DPRINTF("ASYNC: doorbell request acknowledged\n");
1974 ehci
->usbcmd
&= ~USBCMD_IAAD
;
1975 ehci_set_interrupt(ehci
, USBSTS_IAA
);
1979 /* make sure guest has acknowledged */
1980 /* TO-DO: is this really needed? */
1981 if (ehci
->usbsts
& USBSTS_IAA
) {
1982 DPRINTF("IAA status bit still set.\n");
1986 /* check that address register has been set */
1987 if (ehci
->asynclistaddr
== 0) {
1991 ehci_set_state(ehci
, async
, EST_WAITLISTHEAD
);
1992 ehci_advance_state(ehci
, async
);
1996 /* this should only be due to a developer mistake */
1997 fprintf(stderr
, "ehci: Bad asynchronous state %d. "
1998 "Resetting to active\n", ehci
->astate
);
2003 static void ehci_advance_periodic_state(EHCIState
*ehci
)
2011 switch(ehci_get_state(ehci
, async
)) {
2013 if ( !(ehci
->frindex
& 7) && (ehci
->usbcmd
& USBCMD_PSE
)) {
2014 ehci_set_usbsts(ehci
, USBSTS_PSS
);
2015 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2016 // No break, fall through to ACTIVE
2021 if ( !(ehci
->frindex
& 7) && !(ehci
->usbcmd
& USBCMD_PSE
)) {
2022 ehci_clear_usbsts(ehci
, USBSTS_PSS
);
2023 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2027 list
= ehci
->periodiclistbase
& 0xfffff000;
2028 /* check that register has been set */
2032 list
|= ((ehci
->frindex
& 0x1ff8) >> 1);
2034 cpu_physical_memory_rw(list
, (uint8_t *) &entry
, sizeof entry
, 0);
2035 entry
= le32_to_cpu(entry
);
2037 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2038 ehci
->frindex
/ 8, list
, entry
);
2039 ehci_set_fetch_addr(ehci
, async
,entry
);
2040 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
2041 ehci_advance_state(ehci
, async
);
2045 /* this should only be due to a developer mistake */
2046 fprintf(stderr
, "ehci: Bad periodic state %d. "
2047 "Resetting to active\n", ehci
->pstate
);
2052 static void ehci_frame_timer(void *opaque
)
2054 EHCIState
*ehci
= opaque
;
2055 int64_t expire_time
, t_now
;
2056 uint64_t ns_elapsed
;
2059 int skipped_frames
= 0;
2061 t_now
= qemu_get_clock_ns(vm_clock
);
2062 expire_time
= t_now
+ (get_ticks_per_sec() / ehci
->freq
);
2064 ns_elapsed
= t_now
- ehci
->last_run_ns
;
2065 frames
= ns_elapsed
/ FRAME_TIMER_NS
;
2067 for (i
= 0; i
< frames
; i
++) {
2068 if ( !(ehci
->usbsts
& USBSTS_HALT
)) {
2069 if (ehci
->isoch_pause
<= 0) {
2073 if (ehci
->frindex
> 0x00001fff) {
2075 ehci_set_interrupt(ehci
, USBSTS_FLR
);
2078 ehci
->sofv
= (ehci
->frindex
- 1) >> 3;
2079 ehci
->sofv
&= 0x000003ff;
2082 if (frames
- i
> ehci
->maxframes
) {
2085 ehci_advance_periodic_state(ehci
);
2088 ehci
->last_run_ns
+= FRAME_TIMER_NS
;
2092 if (skipped_frames
) {
2093 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames
);
2097 /* Async is not inside loop since it executes everything it can once
2100 ehci_advance_async_state(ehci
);
2102 qemu_mod_timer(ehci
->frame_timer
, expire_time
);
2105 static CPUReadMemoryFunc
*ehci_readfn
[3]={
2111 static CPUWriteMemoryFunc
*ehci_writefn
[3]={
2117 static void ehci_map(PCIDevice
*pci_dev
, int region_num
,
2118 pcibus_t addr
, pcibus_t size
, int type
)
2120 EHCIState
*s
=(EHCIState
*)pci_dev
;
2122 DPRINTF("ehci_map: region %d, addr %08" PRIx64
", size %" PRId64
", s->mem %08X\n",
2123 region_num
, addr
, size
, s
->mem
);
2125 cpu_register_physical_memory(addr
, size
, s
->mem
);
2128 static int usb_ehci_initfn(PCIDevice
*dev
);
2130 static USBPortOps ehci_port_ops
= {
2131 .attach
= ehci_attach
,
2132 .detach
= ehci_detach
,
2133 .child_detach
= ehci_child_detach
,
2134 .complete
= ehci_async_complete_packet
,
2137 static USBBusOps ehci_bus_ops
= {
2140 static PCIDeviceInfo ehci_info
= {
2141 .qdev
.name
= "usb-ehci",
2142 .qdev
.size
= sizeof(EHCIState
),
2143 .init
= usb_ehci_initfn
,
2144 .vendor_id
= PCI_VENDOR_ID_INTEL
,
2145 .device_id
= PCI_DEVICE_ID_INTEL_82801D
,
2147 .class_id
= PCI_CLASS_SERIAL_USB
,
2148 .qdev
.props
= (Property
[]) {
2149 DEFINE_PROP_UINT32("freq", EHCIState
, freq
, FRAME_TIMER_FREQ
),
2150 DEFINE_PROP_UINT32("maxframes", EHCIState
, maxframes
, 128),
2151 DEFINE_PROP_END_OF_LIST(),
2155 static int usb_ehci_initfn(PCIDevice
*dev
)
2157 EHCIState
*s
= DO_UPCAST(EHCIState
, dev
, dev
);
2158 uint8_t *pci_conf
= s
->dev
.config
;
2161 pci_set_byte(&pci_conf
[PCI_CLASS_PROG
], 0x20);
2163 /* capabilities pointer */
2164 pci_set_byte(&pci_conf
[PCI_CAPABILITY_LIST
], 0x00);
2165 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2167 pci_set_byte(&pci_conf
[PCI_INTERRUPT_PIN
], 4); // interrupt pin 3
2168 pci_set_byte(&pci_conf
[PCI_MIN_GNT
], 0);
2169 pci_set_byte(&pci_conf
[PCI_MAX_LAT
], 0);
2171 // pci_conf[0x50] = 0x01; // power management caps
2173 pci_set_byte(&pci_conf
[USB_SBRN
], USB_RELEASE_2
); // release number (2.1.4)
2174 pci_set_byte(&pci_conf
[0x61], 0x20); // frame length adjustment (2.1.5)
2175 pci_set_word(&pci_conf
[0x62], 0x00); // port wake up capability (2.1.6)
2177 pci_conf
[0x64] = 0x00;
2178 pci_conf
[0x65] = 0x00;
2179 pci_conf
[0x66] = 0x00;
2180 pci_conf
[0x67] = 0x00;
2181 pci_conf
[0x68] = 0x01;
2182 pci_conf
[0x69] = 0x00;
2183 pci_conf
[0x6a] = 0x00;
2184 pci_conf
[0x6b] = 0x00; // USBLEGSUP
2185 pci_conf
[0x6c] = 0x00;
2186 pci_conf
[0x6d] = 0x00;
2187 pci_conf
[0x6e] = 0x00;
2188 pci_conf
[0x6f] = 0xc0; // USBLEFCTLSTS
2190 // 2.2 host controller interface version
2191 s
->mmio
[0x00] = (uint8_t) OPREGBASE
;
2192 s
->mmio
[0x01] = 0x00;
2193 s
->mmio
[0x02] = 0x00;
2194 s
->mmio
[0x03] = 0x01; // HC version
2195 s
->mmio
[0x04] = NB_PORTS
; // Number of downstream ports
2196 s
->mmio
[0x05] = 0x00; // No companion ports at present
2197 s
->mmio
[0x06] = 0x00;
2198 s
->mmio
[0x07] = 0x00;
2199 s
->mmio
[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2200 s
->mmio
[0x09] = 0x68; // EECP
2201 s
->mmio
[0x0a] = 0x00;
2202 s
->mmio
[0x0b] = 0x00;
2204 s
->irq
= s
->dev
.irq
[3];
2206 usb_bus_new(&s
->bus
, &ehci_bus_ops
, &s
->dev
.qdev
);
2207 for(i
= 0; i
< NB_PORTS
; i
++) {
2208 usb_register_port(&s
->bus
, &s
->ports
[i
], s
, i
, &ehci_port_ops
,
2209 USB_SPEED_MASK_HIGH
);
2210 s
->ports
[i
].dev
= 0;
2213 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, ehci_frame_timer
, s
);
2214 QTAILQ_INIT(&s
->queues
);
2216 qemu_register_reset(ehci_reset
, s
);
2218 s
->mem
= cpu_register_io_memory(ehci_readfn
, ehci_writefn
, s
,
2219 DEVICE_LITTLE_ENDIAN
);
2221 pci_register_bar(&s
->dev
, 0, MMIO_SIZE
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
2224 fprintf(stderr
, "*** EHCI support is under development ***\n");
2229 static void ehci_register(void)
2231 pci_qdev_register(&ehci_info
);
2233 device_init(ehci_register
);
2236 * vim: expandtab ts=4