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usb-ehci: trace port state
[qemu.git] / hw / usb-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33 #include "trace.h"
34
35 #define EHCI_DEBUG 0
36
37 #if EHCI_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
42
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
45
46 #define MMIO_SIZE 0x1000
47
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
59
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87 /*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
93
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
99
100 #define CONFIGFLAG OPREGBASE + 0x0040
101
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
105 /*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109 #define PORTSC_RO_MASK 0x007021c5
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
140
141 /* Internal periodic / asynchronous schedule state machine states
142 */
143 typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159 } EHCI_STATES;
160
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173 /* EHCI spec version 1.0 Section 3.3
174 */
175 typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct {
338 PCIDevice dev;
339 qemu_irq irq;
340 target_phys_addr_t mem_base;
341 int mem;
342 int num_ports;
343 /*
344 * EHCI spec version 1.0 Section 2.3
345 * Host Controller Operational Registers
346 */
347 union {
348 uint8_t mmio[MMIO_SIZE];
349 struct {
350 uint8_t cap[OPREGBASE];
351 uint32_t usbcmd;
352 uint32_t usbsts;
353 uint32_t usbintr;
354 uint32_t frindex;
355 uint32_t ctrldssegment;
356 uint32_t periodiclistbase;
357 uint32_t asynclistaddr;
358 uint32_t notused[9];
359 uint32_t configflag;
360 uint32_t portsc[NB_PORTS];
361 };
362 };
363 /*
364 * Internal states, shadow registers, etc
365 */
366 uint32_t sofv;
367 QEMUTimer *frame_timer;
368 int attach_poll_counter;
369 int astate; // Current state in asynchronous schedule
370 int pstate; // Current state in periodic schedule
371 USBPort ports[NB_PORTS];
372 uint8_t buffer[BUFF_SIZE];
373 uint32_t usbsts_pending;
374
375 /* cached data from guest - needs to be flushed
376 * when guest removes an entry (doorbell, handshake sequence)
377 */
378 EHCIqh qh; // copy of current QH (being worked on)
379 uint32_t qhaddr; // address QH read from
380
381 EHCIqtd qtd; // copy of current QTD (being worked on)
382 uint32_t qtdaddr; // address QTD read from
383
384 uint32_t itdaddr; // current ITD
385
386 uint32_t fetch_addr; // which address to look at next
387
388 USBBus bus;
389 USBPacket usb_packet;
390 int async_complete;
391 uint32_t tbytes;
392 int pid;
393 int exec_status;
394 int isoch_pause;
395 uint32_t last_run_usec;
396 uint32_t frame_end_usec;
397 } EHCIState;
398
399 #define SET_LAST_RUN_CLOCK(s) \
400 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
401
402 /* nifty macros from Arnon's EHCI version */
403 #define get_field(data, field) \
404 (((data) & field##_MASK) >> field##_SH)
405
406 #define set_field(data, newval, field) do { \
407 uint32_t val = *data; \
408 val &= ~ field##_MASK; \
409 val |= ((newval) << field##_SH) & field##_MASK; \
410 *data = val; \
411 } while(0)
412
413 static const char *ehci_state_names[] = {
414 [ EST_INACTIVE ] = "INACTIVE",
415 [ EST_ACTIVE ] = "ACTIVE",
416 [ EST_EXECUTING ] = "EXECUTING",
417 [ EST_SLEEPING ] = "SLEEPING",
418 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
419 [ EST_FETCHENTRY ] = "FETCH ENTRY",
420 [ EST_FETCHQH ] = "FETCH QH",
421 [ EST_FETCHITD ] = "FETCH ITD",
422 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
423 [ EST_FETCHQTD ] = "FETCH QTD",
424 [ EST_EXECUTE ] = "EXECUTE",
425 [ EST_WRITEBACK ] = "WRITEBACK",
426 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
427 };
428
429 static const char *ehci_mmio_names[] = {
430 [ CAPLENGTH ] = "CAPLENGTH",
431 [ HCIVERSION ] = "HCIVERSION",
432 [ HCSPARAMS ] = "HCSPARAMS",
433 [ HCCPARAMS ] = "HCCPARAMS",
434 [ USBCMD ] = "USBCMD",
435 [ USBSTS ] = "USBSTS",
436 [ USBINTR ] = "USBINTR",
437 [ FRINDEX ] = "FRINDEX",
438 [ PERIODICLISTBASE ] = "P-LIST BASE",
439 [ ASYNCLISTADDR ] = "A-LIST ADDR",
440 [ PORTSC_BEGIN ] = "PORTSC #0",
441 [ PORTSC_BEGIN + 4] = "PORTSC #1",
442 [ PORTSC_BEGIN + 8] = "PORTSC #2",
443 [ PORTSC_BEGIN + 12] = "PORTSC #3",
444 [ CONFIGFLAG ] = "CONFIGFLAG",
445 };
446
447 static const char *nr2str(const char **n, size_t len, uint32_t nr)
448 {
449 if (nr < len && n[nr] != NULL) {
450 return n[nr];
451 } else {
452 return "unknown";
453 }
454 }
455
456 static const char *state2str(uint32_t state)
457 {
458 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
459 }
460
461 static const char *addr2str(target_phys_addr_t addr)
462 {
463 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
464 }
465
466 static void ehci_trace_usbsts(uint32_t mask, int state)
467 {
468 /* interrupts */
469 if (mask & USBSTS_INT) {
470 trace_usb_ehci_usbsts("INT", state);
471 }
472 if (mask & USBSTS_ERRINT) {
473 trace_usb_ehci_usbsts("ERRINT", state);
474 }
475 if (mask & USBSTS_PCD) {
476 trace_usb_ehci_usbsts("PCD", state);
477 }
478 if (mask & USBSTS_FLR) {
479 trace_usb_ehci_usbsts("FLR", state);
480 }
481 if (mask & USBSTS_HSE) {
482 trace_usb_ehci_usbsts("HSE", state);
483 }
484 if (mask & USBSTS_IAA) {
485 trace_usb_ehci_usbsts("IAA", state);
486 }
487
488 /* status */
489 if (mask & USBSTS_HALT) {
490 trace_usb_ehci_usbsts("HALT", state);
491 }
492 if (mask & USBSTS_REC) {
493 trace_usb_ehci_usbsts("REC", state);
494 }
495 if (mask & USBSTS_PSS) {
496 trace_usb_ehci_usbsts("PSS", state);
497 }
498 if (mask & USBSTS_ASS) {
499 trace_usb_ehci_usbsts("ASS", state);
500 }
501 }
502
503 static inline void ehci_set_usbsts(EHCIState *s, int mask)
504 {
505 if ((s->usbsts & mask) == mask) {
506 return;
507 }
508 ehci_trace_usbsts(mask, 1);
509 s->usbsts |= mask;
510 }
511
512 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
513 {
514 if ((s->usbsts & mask) == 0) {
515 return;
516 }
517 ehci_trace_usbsts(mask, 0);
518 s->usbsts &= ~mask;
519 }
520
521 static inline void ehci_set_interrupt(EHCIState *s, int intr)
522 {
523 int level = 0;
524
525 // TODO honour interrupt threshold requests
526
527 ehci_set_usbsts(s, intr);
528
529 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
530 level = 1;
531 }
532
533 qemu_set_irq(s->irq, level);
534 }
535
536 static inline void ehci_record_interrupt(EHCIState *s, int intr)
537 {
538 s->usbsts_pending |= intr;
539 }
540
541 static inline void ehci_commit_interrupt(EHCIState *s)
542 {
543 if (!s->usbsts_pending) {
544 return;
545 }
546 ehci_set_interrupt(s, s->usbsts_pending);
547 s->usbsts_pending = 0;
548 }
549
550 static void ehci_set_state(EHCIState *s, int async, int state)
551 {
552 if (async) {
553 trace_usb_ehci_state("async", state2str(state));
554 s->astate = state;
555 } else {
556 trace_usb_ehci_state("periodic", state2str(state));
557 s->pstate = state;
558 }
559 }
560
561 static int ehci_get_state(EHCIState *s, int async)
562 {
563 return async ? s->astate : s->pstate;
564 }
565
566 static void ehci_trace_qh(EHCIState *s, target_phys_addr_t addr, EHCIqh *qh)
567 {
568 trace_usb_ehci_qh(addr, qh->next,
569 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
570 get_field(qh->epchar, QH_EPCHAR_RL),
571 get_field(qh->epchar, QH_EPCHAR_MPLEN),
572 get_field(qh->epchar, QH_EPCHAR_EPS),
573 get_field(qh->epchar, QH_EPCHAR_EP),
574 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
575 (bool)(qh->epchar & QH_EPCHAR_C),
576 (bool)(qh->epchar & QH_EPCHAR_H),
577 (bool)(qh->epchar & QH_EPCHAR_DTC),
578 (bool)(qh->epchar & QH_EPCHAR_I));
579 }
580
581 static void ehci_trace_qtd(EHCIState *s, target_phys_addr_t addr, EHCIqtd *qtd)
582 {
583 trace_usb_ehci_qtd(addr, qtd->next, qtd->altnext,
584 get_field(qtd->token, QTD_TOKEN_TBYTES),
585 get_field(qtd->token, QTD_TOKEN_CPAGE),
586 get_field(qtd->token, QTD_TOKEN_CERR),
587 get_field(qtd->token, QTD_TOKEN_PID),
588 (bool)(qtd->token & QTD_TOKEN_IOC),
589 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
590 (bool)(qtd->token & QTD_TOKEN_HALT),
591 (bool)(qtd->token & QTD_TOKEN_BABBLE),
592 (bool)(qtd->token & QTD_TOKEN_XACTERR));
593 }
594
595 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
596 {
597 trace_usb_ehci_itd(addr, itd->next);
598 }
599
600 /* Attach or detach a device on root hub */
601
602 static void ehci_attach(USBPort *port)
603 {
604 EHCIState *s = port->opaque;
605 uint32_t *portsc = &s->portsc[port->index];
606
607 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
608
609 *portsc |= PORTSC_CONNECT;
610 *portsc |= PORTSC_CSC;
611
612 /*
613 * If a high speed device is attached then we own this port(indicated
614 * by zero in the PORTSC_POWNER bit field) so set the status bit
615 * and set an interrupt if enabled.
616 */
617 if ( !(*portsc & PORTSC_POWNER)) {
618 ehci_set_interrupt(s, USBSTS_PCD);
619 }
620 }
621
622 static void ehci_detach(USBPort *port)
623 {
624 EHCIState *s = port->opaque;
625 uint32_t *portsc = &s->portsc[port->index];
626
627 trace_usb_ehci_port_detach(port->index);
628
629 *portsc &= ~PORTSC_CONNECT;
630 *portsc |= PORTSC_CSC;
631
632 /*
633 * If a high speed device is attached then we own this port(indicated
634 * by zero in the PORTSC_POWNER bit field) so set the status bit
635 * and set an interrupt if enabled.
636 */
637 if ( !(*portsc & PORTSC_POWNER)) {
638 ehci_set_interrupt(s, USBSTS_PCD);
639 }
640 }
641
642 /* 4.1 host controller initialization */
643 static void ehci_reset(void *opaque)
644 {
645 EHCIState *s = opaque;
646 uint8_t *pci_conf;
647 int i;
648
649 trace_usb_ehci_reset();
650 pci_conf = s->dev.config;
651
652 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
653
654 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
655 s->usbsts = USBSTS_HALT;
656
657 s->astate = EST_INACTIVE;
658 s->pstate = EST_INACTIVE;
659 s->async_complete = 0;
660 s->isoch_pause = -1;
661 s->attach_poll_counter = 0;
662
663 for(i = 0; i < NB_PORTS; i++) {
664 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
665
666 if (s->ports[i].dev) {
667 usb_attach(&s->ports[i], s->ports[i].dev);
668 }
669 }
670 }
671
672 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
673 {
674 EHCIState *s = ptr;
675 uint32_t val;
676
677 val = s->mmio[addr];
678
679 return val;
680 }
681
682 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
683 {
684 EHCIState *s = ptr;
685 uint32_t val;
686
687 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
688
689 return val;
690 }
691
692 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
693 {
694 EHCIState *s = ptr;
695 uint32_t val;
696
697 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
698 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
699
700 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
701 return val;
702 }
703
704 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
705 {
706 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
707 exit(1);
708 }
709
710 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
711 {
712 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
713 exit(1);
714 }
715
716 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
717 {
718 uint32_t *portsc = &s->portsc[port];
719 int rwc;
720 USBDevice *dev = s->ports[port].dev;
721
722 DPRINTF("port_status_write: "
723 "PORTSC (port %d) curr %08X new %08X rw-clear %08X rw %08X\n",
724 port, *portsc, val, (val & PORTSC_RWC_MASK), val & PORTSC_RO_MASK);
725
726 rwc = val & PORTSC_RWC_MASK;
727 val &= PORTSC_RO_MASK;
728
729 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
730
731 *portsc &= ~rwc;
732
733 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
734 trace_usb_ehci_port_reset(port, 1);
735 }
736
737 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
738 trace_usb_ehci_port_reset(port, 0);
739 usb_attach(&s->ports[port], dev);
740
741 // TODO how to handle reset of ports with no device
742 if (dev) {
743 usb_send_msg(dev, USB_MSG_RESET);
744 }
745
746 if (s->ports[port].dev) {
747 DPRINTF("port_status_write: "
748 "Device was connected before reset, clearing CSC bit\n");
749 *portsc &= ~PORTSC_CSC;
750 }
751
752 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
753 * to SW that this port has a high speed device attached
754 *
755 * TODO - when to disable?
756 */
757 val |= PORTSC_PED;
758 val |= PORTSC_PEDC;
759 }
760
761 *portsc &= ~PORTSC_RO_MASK;
762 *portsc |= val;
763 DPRINTF("port_status_write: Port %d status set to 0x%08x\n", port, *portsc);
764 }
765
766 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
767 {
768 EHCIState *s = ptr;
769 int i;
770
771 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val,
772 *(uint32_t *)(&s->mmio[addr]));
773
774 /* Only aligned reads are allowed on OHCI */
775 if (addr & 3) {
776 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
777 TARGET_FMT_plx "\n", addr);
778 return;
779 }
780
781 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
782 handle_port_status_write(s, (addr-PORTSC)/4, val);
783 return;
784 }
785
786 if (addr < OPREGBASE) {
787 fprintf(stderr, "usb-ehci: write attempt to read-only register"
788 TARGET_FMT_plx "\n", addr);
789 return;
790 }
791
792
793 /* Do any register specific pre-write processing here. */
794 switch(addr) {
795 case USBCMD:
796 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
797 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
798 SET_LAST_RUN_CLOCK(s);
799 ehci_clear_usbsts(s, USBSTS_HALT);
800 }
801
802 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
803 qemu_del_timer(s->frame_timer);
804 // TODO - should finish out some stuff before setting halt
805 ehci_set_usbsts(s, USBSTS_HALT);
806 }
807
808 if (val & USBCMD_HCRESET) {
809 ehci_reset(s);
810 val &= ~USBCMD_HCRESET;
811 }
812
813 /* not supporting dynamic frame list size at the moment */
814 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
815 fprintf(stderr, "attempt to set frame list size -- value %d\n",
816 val & USBCMD_FLS);
817 val &= ~USBCMD_FLS;
818 }
819 break;
820
821 case USBSTS:
822 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
823 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
824 val = s->usbsts;
825 ehci_set_interrupt(s, 0);
826 break;
827
828 case USBINTR:
829 val &= USBINTR_MASK;
830 break;
831
832 case FRINDEX:
833 s->sofv = val >> 3;
834 break;
835
836 case CONFIGFLAG:
837 val &= 0x1;
838 if (val) {
839 for(i = 0; i < NB_PORTS; i++)
840 s->portsc[i] &= ~PORTSC_POWNER;
841 }
842 break;
843
844 case PERIODICLISTBASE:
845 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
846 fprintf(stderr,
847 "ehci: PERIODIC list base register set while periodic schedule\n"
848 " is enabled and HC is enabled\n");
849 }
850 break;
851
852 case ASYNCLISTADDR:
853 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
854 fprintf(stderr,
855 "ehci: ASYNC list address register set while async schedule\n"
856 " is enabled and HC is enabled\n");
857 }
858 break;
859 }
860
861 *(uint32_t *)(&s->mmio[addr]) = val;
862 }
863
864
865 // TODO : Put in common header file, duplication from usb-ohci.c
866
867 /* Get an array of dwords from main memory */
868 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
869 {
870 int i;
871
872 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
873 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
874 *buf = le32_to_cpu(*buf);
875 }
876
877 return 1;
878 }
879
880 /* Put an array of dwords in to main memory */
881 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
882 {
883 int i;
884
885 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
886 uint32_t tmp = cpu_to_le32(*buf);
887 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
888 }
889
890 return 1;
891 }
892
893 // 4.10.2
894
895 static int ehci_qh_do_overlay(EHCIState *ehci, EHCIqh *qh, EHCIqtd *qtd)
896 {
897 int i;
898 int dtoggle;
899 int ping;
900 int eps;
901 int reload;
902
903 // remember values in fields to preserve in qh after overlay
904
905 dtoggle = qh->token & QTD_TOKEN_DTOGGLE;
906 ping = qh->token & QTD_TOKEN_PING;
907
908 DPRINTF("setting qh.current from %08X to 0x%08X\n", qh->current_qtd,
909 ehci->qtdaddr);
910 qh->current_qtd = ehci->qtdaddr;
911 qh->next_qtd = qtd->next;
912 qh->altnext_qtd = qtd->altnext;
913 qh->token = qtd->token;
914
915
916 eps = get_field(qh->epchar, QH_EPCHAR_EPS);
917 if (eps == EHCI_QH_EPS_HIGH) {
918 qh->token &= ~QTD_TOKEN_PING;
919 qh->token |= ping;
920 }
921
922 reload = get_field(qh->epchar, QH_EPCHAR_RL);
923 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
924
925 for (i = 0; i < 5; i++) {
926 qh->bufptr[i] = qtd->bufptr[i];
927 }
928
929 if (!(qh->epchar & QH_EPCHAR_DTC)) {
930 // preserve QH DT bit
931 qh->token &= ~QTD_TOKEN_DTOGGLE;
932 qh->token |= dtoggle;
933 }
934
935 qh->bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
936 qh->bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
937
938 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
939
940 return 0;
941 }
942
943 static int ehci_buffer_rw(uint8_t *buffer, EHCIqh *qh, int bytes, int rw)
944 {
945 int bufpos = 0;
946 int cpage, offset;
947 uint32_t head;
948 uint32_t tail;
949
950
951 if (!bytes) {
952 return 0;
953 }
954
955 cpage = get_field(qh->token, QTD_TOKEN_CPAGE);
956 if (cpage > 4) {
957 fprintf(stderr, "cpage out of range (%d)\n", cpage);
958 return USB_RET_PROCERR;
959 }
960
961 offset = qh->bufptr[0] & ~QTD_BUFPTR_MASK;
962 DPRINTF("ehci_buffer_rw: %sing %d bytes %08x cpage %d offset %d\n",
963 rw ? "writ" : "read", bytes, qh->bufptr[0], cpage, offset);
964
965 do {
966 /* start and end of this page */
967 head = qh->bufptr[cpage] & QTD_BUFPTR_MASK;
968 tail = head + ~QTD_BUFPTR_MASK + 1;
969 /* add offset into page */
970 head |= offset;
971
972 if (bytes <= (tail - head)) {
973 tail = head + bytes;
974 }
975
976 DPRINTF("DATA %s cpage:%d head:%08X tail:%08X target:%08X\n",
977 rw ? "WRITE" : "READ ", cpage, head, tail, bufpos);
978
979 cpu_physical_memory_rw(head, &buffer[bufpos], tail - head, rw);
980
981 bufpos += (tail - head);
982 bytes -= (tail - head);
983
984 if (bytes > 0) {
985 cpage++;
986 offset = 0;
987 }
988 } while (bytes > 0);
989
990 /* save cpage */
991 set_field(&qh->token, cpage, QTD_TOKEN_CPAGE);
992
993 /* save offset into cpage */
994 offset = tail - head;
995 qh->bufptr[0] &= ~QTD_BUFPTR_MASK;
996 qh->bufptr[0] |= offset;
997
998 return 0;
999 }
1000
1001 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
1002 {
1003 EHCIState *ehci = container_of(packet, EHCIState, usb_packet);
1004
1005 DPRINTF("Async packet complete\n");
1006 ehci->async_complete = 1;
1007 ehci->exec_status = packet->len;
1008 }
1009
1010 static int ehci_execute_complete(EHCIState *ehci, EHCIqh *qh, int ret)
1011 {
1012 int c_err, reload;
1013
1014 if (ret == USB_RET_ASYNC && !ehci->async_complete) {
1015 DPRINTF("not done yet\n");
1016 return ret;
1017 }
1018
1019 ehci->async_complete = 0;
1020
1021 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1022 ehci->qhaddr, qh->next, ehci->qtdaddr, ret);
1023
1024 if (ret < 0) {
1025 err:
1026 /* TO-DO: put this is in a function that can be invoked below as well */
1027 c_err = get_field(qh->token, QTD_TOKEN_CERR);
1028 c_err--;
1029 set_field(&qh->token, c_err, QTD_TOKEN_CERR);
1030
1031 switch(ret) {
1032 case USB_RET_NODEV:
1033 fprintf(stderr, "USB no device\n");
1034 break;
1035 case USB_RET_STALL:
1036 fprintf(stderr, "USB stall\n");
1037 qh->token |= QTD_TOKEN_HALT;
1038 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1039 break;
1040 case USB_RET_NAK:
1041 /* 4.10.3 */
1042 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1043 if ((ehci->pid == USB_TOKEN_IN) && reload) {
1044 int nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1045 nakcnt--;
1046 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1047 } else if (!reload) {
1048 return USB_RET_NAK;
1049 }
1050 break;
1051 case USB_RET_BABBLE:
1052 fprintf(stderr, "USB babble TODO\n");
1053 qh->token |= QTD_TOKEN_BABBLE;
1054 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1055 break;
1056 default:
1057 fprintf(stderr, "USB invalid response %d to handle\n", ret);
1058 /* TO-DO: transaction error */
1059 ret = USB_RET_PROCERR;
1060 break;
1061 }
1062 } else {
1063 // DPRINTF("Short packet condition\n");
1064 // TODO check 4.12 for splits
1065
1066 if ((ret > ehci->tbytes) && (ehci->pid == USB_TOKEN_IN)) {
1067 ret = USB_RET_BABBLE;
1068 goto err;
1069 }
1070
1071 if (ehci->tbytes && ehci->pid == USB_TOKEN_IN) {
1072 if (ehci_buffer_rw(ehci->buffer, qh, ret, 1) != 0) {
1073 return USB_RET_PROCERR;
1074 }
1075 ehci->tbytes -= ret;
1076 } else {
1077 ehci->tbytes = 0;
1078 }
1079
1080 DPRINTF("updating tbytes to %d\n", ehci->tbytes);
1081 set_field(&qh->token, ehci->tbytes, QTD_TOKEN_TBYTES);
1082 }
1083
1084 qh->token ^= QTD_TOKEN_DTOGGLE;
1085 qh->token &= ~QTD_TOKEN_ACTIVE;
1086
1087 if ((ret >= 0) && (qh->token & QTD_TOKEN_IOC)) {
1088 ehci_record_interrupt(ehci, USBSTS_INT);
1089 }
1090
1091 return ret;
1092 }
1093
1094 // 4.10.3
1095
1096 static int ehci_execute(EHCIState *ehci, EHCIqh *qh)
1097 {
1098 USBPort *port;
1099 USBDevice *dev;
1100 int ret;
1101 int i;
1102 int endp;
1103 int devadr;
1104
1105 if ( !(qh->token & QTD_TOKEN_ACTIVE)) {
1106 fprintf(stderr, "Attempting to execute inactive QH\n");
1107 return USB_RET_PROCERR;
1108 }
1109
1110 ehci->tbytes = (qh->token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1111 if (ehci->tbytes > BUFF_SIZE) {
1112 fprintf(stderr, "Request for more bytes than allowed\n");
1113 return USB_RET_PROCERR;
1114 }
1115
1116 ehci->pid = (qh->token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1117 switch(ehci->pid) {
1118 case 0: ehci->pid = USB_TOKEN_OUT; break;
1119 case 1: ehci->pid = USB_TOKEN_IN; break;
1120 case 2: ehci->pid = USB_TOKEN_SETUP; break;
1121 default: fprintf(stderr, "bad token\n"); break;
1122 }
1123
1124 if ((ehci->tbytes && ehci->pid != USB_TOKEN_IN) &&
1125 (ehci_buffer_rw(ehci->buffer, qh, ehci->tbytes, 0) != 0)) {
1126 return USB_RET_PROCERR;
1127 }
1128
1129 endp = get_field(qh->epchar, QH_EPCHAR_EP);
1130 devadr = get_field(qh->epchar, QH_EPCHAR_DEVADDR);
1131
1132 ret = USB_RET_NODEV;
1133
1134 // TO-DO: associating device with ehci port
1135 for(i = 0; i < NB_PORTS; i++) {
1136 port = &ehci->ports[i];
1137 dev = port->dev;
1138
1139 // TODO sometime we will also need to check if we are the port owner
1140
1141 if (!(ehci->portsc[i] &(PORTSC_CONNECT))) {
1142 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1143 i, ehci->portsc[i]);
1144 continue;
1145 }
1146
1147 ehci->usb_packet.pid = ehci->pid;
1148 ehci->usb_packet.devaddr = devadr;
1149 ehci->usb_packet.devep = endp;
1150 ehci->usb_packet.data = ehci->buffer;
1151 ehci->usb_packet.len = ehci->tbytes;
1152
1153 ret = usb_handle_packet(dev, &ehci->usb_packet);
1154
1155 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1156 ehci->qhaddr, qh->next, ehci->qtdaddr, ehci->pid,
1157 ehci->usb_packet.len, ehci->tbytes, endp, ret);
1158
1159 if (ret != USB_RET_NODEV) {
1160 break;
1161 }
1162 }
1163
1164 if (ret > BUFF_SIZE) {
1165 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1166 return USB_RET_PROCERR;
1167 }
1168
1169 if (ret == USB_RET_ASYNC) {
1170 ehci->async_complete = 0;
1171 }
1172
1173 return ret;
1174 }
1175
1176 /* 4.7.2
1177 */
1178
1179 static int ehci_process_itd(EHCIState *ehci,
1180 EHCIitd *itd)
1181 {
1182 USBPort *port;
1183 USBDevice *dev;
1184 int ret;
1185 int i, j;
1186 int ptr;
1187 int pid;
1188 int pg;
1189 int len;
1190 int dir;
1191 int devadr;
1192 int endp;
1193 int maxpkt;
1194
1195 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1196 devadr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1197 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1198 maxpkt = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1199
1200 for(i = 0; i < 8; i++) {
1201 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1202 DPRINTF("ISOCHRONOUS active for frame %d, interval %d\n",
1203 ehci->frindex >> 3, i);
1204
1205 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1206 ptr = (itd->bufptr[pg] & ITD_BUFPTR_MASK) |
1207 (itd->transact[i] & ITD_XACT_OFFSET_MASK);
1208 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1209
1210 if (len > BUFF_SIZE) {
1211 return USB_RET_PROCERR;
1212 }
1213
1214 DPRINTF("ISOCH: buffer %08X len %d\n", ptr, len);
1215
1216 if (!dir) {
1217 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 0);
1218 pid = USB_TOKEN_OUT;
1219 } else
1220 pid = USB_TOKEN_IN;
1221
1222 ret = USB_RET_NODEV;
1223
1224 for (j = 0; j < NB_PORTS; j++) {
1225 port = &ehci->ports[j];
1226 dev = port->dev;
1227
1228 // TODO sometime we will also need to check if we are the port owner
1229
1230 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1231 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1232 j, ehci->portsc[j]);
1233 continue;
1234 }
1235
1236 ehci->usb_packet.pid = ehci->pid;
1237 ehci->usb_packet.devaddr = devadr;
1238 ehci->usb_packet.devep = endp;
1239 ehci->usb_packet.data = ehci->buffer;
1240 ehci->usb_packet.len = len;
1241
1242 DPRINTF("calling usb_handle_packet\n");
1243 ret = usb_handle_packet(dev, &ehci->usb_packet);
1244
1245 if (ret != USB_RET_NODEV) {
1246 break;
1247 }
1248 }
1249
1250 /* In isoch, there is no facility to indicate a NAK so let's
1251 * instead just complete a zero-byte transaction. Setting
1252 * DBERR seems too draconian.
1253 */
1254
1255 if (ret == USB_RET_NAK) {
1256 if (ehci->isoch_pause > 0) {
1257 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1258 ehci->isoch_pause--;
1259 return 0;
1260 } else if (ehci->isoch_pause == -1) {
1261 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1262 // Pause frindex for up to 50 msec waiting for data from
1263 // remote
1264 ehci->isoch_pause = 50;
1265 return 0;
1266 } else {
1267 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1268 ret = 0;
1269 }
1270 } else {
1271 DPRINTF("ISOCH: received ACK, clearing pause\n");
1272 ehci->isoch_pause = -1;
1273 }
1274
1275 if (ret >= 0) {
1276 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1277
1278 if (itd->transact[i] & ITD_XACT_IOC) {
1279 ehci_record_interrupt(ehci, USBSTS_INT);
1280 }
1281 }
1282
1283 if (ret >= 0 && dir) {
1284 cpu_physical_memory_rw(ptr, &ehci->buffer[0], len, 1);
1285
1286 if (ret != len) {
1287 DPRINTF("ISOCH IN expected %d, got %d\n",
1288 len, ret);
1289 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1290 }
1291 }
1292 }
1293 }
1294 return 0;
1295 }
1296
1297 /* This state is the entry point for asynchronous schedule
1298 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1299 */
1300 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1301 {
1302 EHCIqh *qh = &ehci->qh;
1303 int i = 0;
1304 int again = 0;
1305 uint32_t entry = ehci->asynclistaddr;
1306
1307 /* set reclamation flag at start event (4.8.6) */
1308 if (async) {
1309 ehci_set_usbsts(ehci, USBSTS_REC);
1310 }
1311
1312 /* Find the head of the list (4.9.1.1) */
1313 for(i = 0; i < MAX_QH; i++) {
1314 get_dwords(NLPTR_GET(entry), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1315 ehci_trace_qh(ehci, NLPTR_GET(entry), qh);
1316
1317 if (qh->epchar & QH_EPCHAR_H) {
1318 if (async) {
1319 entry |= (NLPTR_TYPE_QH << 1);
1320 }
1321
1322 ehci->fetch_addr = entry;
1323 ehci_set_state(ehci, async, EST_FETCHENTRY);
1324 again = 1;
1325 goto out;
1326 }
1327
1328 entry = qh->next;
1329 if (entry == ehci->asynclistaddr) {
1330 break;
1331 }
1332 }
1333
1334 /* no head found for list. */
1335
1336 ehci_set_state(ehci, async, EST_ACTIVE);
1337
1338 out:
1339 return again;
1340 }
1341
1342
1343 /* This state is the entry point for periodic schedule processing as
1344 * well as being a continuation state for async processing.
1345 */
1346 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1347 {
1348 int again = 0;
1349 uint32_t entry = ehci->fetch_addr;
1350
1351 #if EHCI_DEBUG == 0
1352 if (qemu_get_clock_ns(vm_clock) / 1000 >= ehci->frame_end_usec) {
1353 if (async) {
1354 DPRINTF("FETCHENTRY: FRAME timer elapsed, exit state machine\n");
1355 goto out;
1356 } else {
1357 DPRINTF("FETCHENTRY: WARNING "
1358 "- frame timer elapsed during periodic\n");
1359 }
1360 }
1361 #endif
1362 if (entry < 0x1000) {
1363 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1364 ehci_set_state(ehci, async, EST_ACTIVE);
1365 goto out;
1366 }
1367
1368 /* section 4.8, only QH in async schedule */
1369 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1370 fprintf(stderr, "non queue head request in async schedule\n");
1371 return -1;
1372 }
1373
1374 switch (NLPTR_TYPE_GET(entry)) {
1375 case NLPTR_TYPE_QH:
1376 ehci_set_state(ehci, async, EST_FETCHQH);
1377 ehci->qhaddr = entry;
1378 again = 1;
1379 break;
1380
1381 case NLPTR_TYPE_ITD:
1382 ehci_set_state(ehci, async, EST_FETCHITD);
1383 ehci->itdaddr = entry;
1384 again = 1;
1385 break;
1386
1387 default:
1388 // TODO: handle siTD and FSTN types
1389 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1390 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1391 return -1;
1392 }
1393
1394 out:
1395 return again;
1396 }
1397
1398 static int ehci_state_fetchqh(EHCIState *ehci, int async)
1399 {
1400 EHCIqh *qh = &ehci->qh;
1401 int reload;
1402 int again = 0;
1403
1404 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1405 ehci_trace_qh(ehci, NLPTR_GET(ehci->qhaddr), qh);
1406
1407 if (async && (qh->epchar & QH_EPCHAR_H)) {
1408
1409 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1410 if (ehci->usbsts & USBSTS_REC) {
1411 ehci_clear_usbsts(ehci, USBSTS_REC);
1412 } else {
1413 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1414 " - done processing\n", ehci->qhaddr);
1415 ehci_set_state(ehci, async, EST_ACTIVE);
1416 goto out;
1417 }
1418 }
1419
1420 #if EHCI_DEBUG
1421 if (ehci->qhaddr != qh->next) {
1422 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1423 ehci->qhaddr,
1424 qh->epchar & QH_EPCHAR_H,
1425 qh->token & QTD_TOKEN_HALT,
1426 qh->token & QTD_TOKEN_ACTIVE,
1427 qh->next);
1428 }
1429 #endif
1430
1431 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1432 if (reload) {
1433 set_field(&qh->altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1434 }
1435
1436 if (qh->token & QTD_TOKEN_HALT) {
1437 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1438 again = 1;
1439
1440 } else if ((qh->token & QTD_TOKEN_ACTIVE) && (qh->current_qtd > 0x1000)) {
1441 ehci->qtdaddr = qh->current_qtd;
1442 ehci_set_state(ehci, async, EST_FETCHQTD);
1443 again = 1;
1444
1445 } else {
1446 /* EHCI spec version 1.0 Section 4.10.2 */
1447 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1448 again = 1;
1449 }
1450
1451 out:
1452 return again;
1453 }
1454
1455 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1456 {
1457 EHCIitd itd;
1458
1459 get_dwords(NLPTR_GET(ehci->itdaddr),(uint32_t *) &itd,
1460 sizeof(EHCIitd) >> 2);
1461 ehci_trace_itd(ehci, ehci->itdaddr, &itd);
1462
1463 if (ehci_process_itd(ehci, &itd) != 0) {
1464 return -1;
1465 }
1466
1467 put_dwords(NLPTR_GET(ehci->itdaddr), (uint32_t *) &itd,
1468 sizeof(EHCIitd) >> 2);
1469 ehci->fetch_addr = itd.next;
1470 ehci_set_state(ehci, async, EST_FETCHENTRY);
1471
1472 return 1;
1473 }
1474
1475 /* Section 4.10.2 - paragraph 3 */
1476 static int ehci_state_advqueue(EHCIState *ehci, int async)
1477 {
1478 #if 0
1479 /* TO-DO: 4.10.2 - paragraph 2
1480 * if I-bit is set to 1 and QH is not active
1481 * go to horizontal QH
1482 */
1483 if (I-bit set) {
1484 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1485 goto out;
1486 }
1487 #endif
1488
1489 /*
1490 * want data and alt-next qTD is valid
1491 */
1492 if (((ehci->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1493 (ehci->qh.altnext_qtd > 0x1000) &&
1494 (NLPTR_TBIT(ehci->qh.altnext_qtd) == 0)) {
1495 ehci->qtdaddr = ehci->qh.altnext_qtd;
1496 ehci_set_state(ehci, async, EST_FETCHQTD);
1497
1498 /*
1499 * next qTD is valid
1500 */
1501 } else if ((ehci->qh.next_qtd > 0x1000) &&
1502 (NLPTR_TBIT(ehci->qh.next_qtd) == 0)) {
1503 ehci->qtdaddr = ehci->qh.next_qtd;
1504 ehci_set_state(ehci, async, EST_FETCHQTD);
1505
1506 /*
1507 * no valid qTD, try next QH
1508 */
1509 } else {
1510 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1511 }
1512
1513 return 1;
1514 }
1515
1516 /* Section 4.10.2 - paragraph 4 */
1517 static int ehci_state_fetchqtd(EHCIState *ehci, int async)
1518 {
1519 EHCIqtd *qtd = &ehci->qtd;
1520 int again = 0;
1521
1522 get_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) qtd, sizeof(EHCIqtd) >> 2);
1523 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), qtd);
1524
1525 if (qtd->token & QTD_TOKEN_ACTIVE) {
1526 ehci_set_state(ehci, async, EST_EXECUTE);
1527 again = 1;
1528 } else {
1529 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1530 again = 1;
1531 }
1532
1533 return again;
1534 }
1535
1536 static int ehci_state_horizqh(EHCIState *ehci, int async)
1537 {
1538 int again = 0;
1539
1540 if (ehci->fetch_addr != ehci->qh.next) {
1541 ehci->fetch_addr = ehci->qh.next;
1542 ehci_set_state(ehci, async, EST_FETCHENTRY);
1543 again = 1;
1544 } else {
1545 ehci_set_state(ehci, async, EST_ACTIVE);
1546 }
1547
1548 return again;
1549 }
1550
1551 static int ehci_state_execute(EHCIState *ehci, int async)
1552 {
1553 EHCIqh *qh = &ehci->qh;
1554 EHCIqtd *qtd = &ehci->qtd;
1555 int again = 0;
1556 int reload, nakcnt;
1557 int smask;
1558
1559 if (ehci_qh_do_overlay(ehci, qh, qtd) != 0) {
1560 return -1;
1561 }
1562
1563 smask = get_field(qh->epcap, QH_EPCAP_SMASK);
1564
1565 if (!smask) {
1566 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1567 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1568 if (reload && !nakcnt) {
1569 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1570 again = 1;
1571 goto out;
1572 }
1573 }
1574
1575 // TODO verify enough time remains in the uframe as in 4.4.1.1
1576 // TODO write back ptr to async list when done or out of time
1577 // TODO Windows does not seem to ever set the MULT field
1578
1579 if (!async) {
1580 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1581 if (!transactCtr) {
1582 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1583 again = 1;
1584 goto out;
1585 }
1586 }
1587
1588 if (async) {
1589 ehci_set_usbsts(ehci, USBSTS_REC);
1590 }
1591
1592 ehci->exec_status = ehci_execute(ehci, qh);
1593 if (ehci->exec_status == USB_RET_PROCERR) {
1594 again = -1;
1595 goto out;
1596 }
1597 ehci_set_state(ehci, async, EST_EXECUTING);
1598
1599 if (ehci->exec_status != USB_RET_ASYNC) {
1600 again = 1;
1601 }
1602
1603 out:
1604 return again;
1605 }
1606
1607 static int ehci_state_executing(EHCIState *ehci, int async)
1608 {
1609 EHCIqh *qh = &ehci->qh;
1610 int again = 0;
1611 int reload, nakcnt;
1612
1613 ehci->exec_status = ehci_execute_complete(ehci, qh, ehci->exec_status);
1614 if (ehci->exec_status == USB_RET_ASYNC) {
1615 goto out;
1616 }
1617 if (ehci->exec_status == USB_RET_PROCERR) {
1618 again = -1;
1619 goto out;
1620 }
1621
1622 // 4.10.3
1623 if (!async) {
1624 int transactCtr = get_field(qh->epcap, QH_EPCAP_MULT);
1625 transactCtr--;
1626 set_field(&qh->epcap, transactCtr, QH_EPCAP_MULT);
1627 // 4.10.3, bottom of page 82, should exit this state when transaction
1628 // counter decrements to 0
1629 }
1630
1631
1632 reload = get_field(qh->epchar, QH_EPCHAR_RL);
1633 if (reload) {
1634 nakcnt = get_field(qh->altnext_qtd, QH_ALTNEXT_NAKCNT);
1635 if (ehci->exec_status == USB_RET_NAK) {
1636 if (nakcnt) {
1637 nakcnt--;
1638 }
1639 } else {
1640 nakcnt = reload;
1641 }
1642 set_field(&qh->altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1643 }
1644
1645 /*
1646 * Write the qh back to guest physical memory. This step isn't
1647 * in the EHCI spec but we need to do it since we don't share
1648 * physical memory with our guest VM.
1649 */
1650 put_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) qh, sizeof(EHCIqh) >> 2);
1651
1652 /* 4.10.5 */
1653 if ((ehci->exec_status == USB_RET_NAK) || (qh->token & QTD_TOKEN_ACTIVE)) {
1654 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1655 } else {
1656 ehci_set_state(ehci, async, EST_WRITEBACK);
1657 }
1658
1659 again = 1;
1660
1661 out:
1662 return again;
1663 }
1664
1665
1666 static int ehci_state_writeback(EHCIState *ehci, int async)
1667 {
1668 EHCIqh *qh = &ehci->qh;
1669 int again = 0;
1670
1671 /* Write back the QTD from the QH area */
1672 ehci_trace_qtd(ehci, NLPTR_GET(ehci->qtdaddr), (EHCIqtd*) &qh->next_qtd);
1673 put_dwords(NLPTR_GET(ehci->qtdaddr),(uint32_t *) &qh->next_qtd,
1674 sizeof(EHCIqtd) >> 2);
1675
1676 /* TODO confirm next state. For now, keep going if async
1677 * but stop after one qtd if periodic
1678 */
1679 //if (async) {
1680 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1681 again = 1;
1682 //} else {
1683 // ehci_set_state(ehci, async, EST_ACTIVE);
1684 //}
1685 return again;
1686 }
1687
1688 /*
1689 * This is the state machine that is common to both async and periodic
1690 */
1691
1692 static void ehci_advance_state(EHCIState *ehci,
1693 int async)
1694 {
1695 int again;
1696 int iter = 0;
1697
1698 do {
1699 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1700 iter++;
1701 /* if we are roaming a lot of QH without executing a qTD
1702 * something is wrong with the linked list. TO-DO: why is
1703 * this hack needed?
1704 */
1705 if (iter > MAX_ITERATIONS) {
1706 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1707 ehci_set_state(ehci, async, EST_ACTIVE);
1708 break;
1709 }
1710 }
1711 switch(ehci_get_state(ehci, async)) {
1712 case EST_WAITLISTHEAD:
1713 again = ehci_state_waitlisthead(ehci, async);
1714 break;
1715
1716 case EST_FETCHENTRY:
1717 again = ehci_state_fetchentry(ehci, async);
1718 break;
1719
1720 case EST_FETCHQH:
1721 again = ehci_state_fetchqh(ehci, async);
1722 break;
1723
1724 case EST_FETCHITD:
1725 again = ehci_state_fetchitd(ehci, async);
1726 break;
1727
1728 case EST_ADVANCEQUEUE:
1729 again = ehci_state_advqueue(ehci, async);
1730 break;
1731
1732 case EST_FETCHQTD:
1733 again = ehci_state_fetchqtd(ehci, async);
1734 break;
1735
1736 case EST_HORIZONTALQH:
1737 again = ehci_state_horizqh(ehci, async);
1738 break;
1739
1740 case EST_EXECUTE:
1741 iter = 0;
1742 again = ehci_state_execute(ehci, async);
1743 break;
1744
1745 case EST_EXECUTING:
1746 again = ehci_state_executing(ehci, async);
1747 break;
1748
1749 case EST_WRITEBACK:
1750 again = ehci_state_writeback(ehci, async);
1751 break;
1752
1753 default:
1754 fprintf(stderr, "Bad state!\n");
1755 again = -1;
1756 break;
1757 }
1758
1759 if (again < 0) {
1760 fprintf(stderr, "processing error - resetting ehci HC\n");
1761 ehci_reset(ehci);
1762 again = 0;
1763 }
1764 }
1765 while (again);
1766
1767 ehci_commit_interrupt(ehci);
1768 }
1769
1770 static void ehci_advance_async_state(EHCIState *ehci)
1771 {
1772 EHCIqh qh;
1773 int async = 1;
1774
1775 switch(ehci_get_state(ehci, async)) {
1776 case EST_INACTIVE:
1777 if (!(ehci->usbcmd & USBCMD_ASE)) {
1778 break;
1779 }
1780 ehci_set_usbsts(ehci, USBSTS_ASS);
1781 ehci_set_state(ehci, async, EST_ACTIVE);
1782 // No break, fall through to ACTIVE
1783
1784 case EST_ACTIVE:
1785 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1786 ehci_clear_usbsts(ehci, USBSTS_ASS);
1787 ehci_set_state(ehci, async, EST_INACTIVE);
1788 break;
1789 }
1790
1791 /* If the doorbell is set, the guest wants to make a change to the
1792 * schedule. The host controller needs to release cached data.
1793 * (section 4.8.2)
1794 */
1795 if (ehci->usbcmd & USBCMD_IAAD) {
1796 DPRINTF("ASYNC: doorbell request acknowledged\n");
1797 ehci->usbcmd &= ~USBCMD_IAAD;
1798 ehci_set_interrupt(ehci, USBSTS_IAA);
1799 break;
1800 }
1801
1802 /* make sure guest has acknowledged */
1803 /* TO-DO: is this really needed? */
1804 if (ehci->usbsts & USBSTS_IAA) {
1805 DPRINTF("IAA status bit still set.\n");
1806 break;
1807 }
1808
1809 /* check that address register has been set */
1810 if (ehci->asynclistaddr == 0) {
1811 break;
1812 }
1813
1814 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
1815 /* fall through */
1816
1817 case EST_FETCHENTRY:
1818 /* fall through */
1819
1820 case EST_EXECUTING:
1821 get_dwords(NLPTR_GET(ehci->qhaddr), (uint32_t *) &qh,
1822 sizeof(EHCIqh) >> 2);
1823 ehci_advance_state(ehci, async);
1824 break;
1825
1826 default:
1827 /* this should only be due to a developer mistake */
1828 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1829 "Resetting to active\n", ehci->astate);
1830 ehci_set_state(ehci, async, EST_ACTIVE);
1831 }
1832 }
1833
1834 static void ehci_advance_periodic_state(EHCIState *ehci)
1835 {
1836 uint32_t entry;
1837 uint32_t list;
1838 int async = 0;
1839
1840 // 4.6
1841
1842 switch(ehci_get_state(ehci, async)) {
1843 case EST_INACTIVE:
1844 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
1845 ehci_set_usbsts(ehci, USBSTS_PSS);
1846 ehci_set_state(ehci, async, EST_ACTIVE);
1847 // No break, fall through to ACTIVE
1848 } else
1849 break;
1850
1851 case EST_ACTIVE:
1852 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
1853 ehci_clear_usbsts(ehci, USBSTS_PSS);
1854 ehci_set_state(ehci, async, EST_INACTIVE);
1855 break;
1856 }
1857
1858 list = ehci->periodiclistbase & 0xfffff000;
1859 /* check that register has been set */
1860 if (list == 0) {
1861 break;
1862 }
1863 list |= ((ehci->frindex & 0x1ff8) >> 1);
1864
1865 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
1866 entry = le32_to_cpu(entry);
1867
1868 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
1869 ehci->frindex / 8, list, entry);
1870 ehci->fetch_addr = entry;
1871 ehci_set_state(ehci, async, EST_FETCHENTRY);
1872 ehci_advance_state(ehci, async);
1873 break;
1874
1875 case EST_EXECUTING:
1876 DPRINTF("PERIODIC state adv for executing\n");
1877 ehci_advance_state(ehci, async);
1878 break;
1879
1880 default:
1881 /* this should only be due to a developer mistake */
1882 fprintf(stderr, "ehci: Bad periodic state %d. "
1883 "Resetting to active\n", ehci->pstate);
1884 ehci_set_state(ehci, async, EST_ACTIVE);
1885 }
1886 }
1887
1888 static void ehci_frame_timer(void *opaque)
1889 {
1890 EHCIState *ehci = opaque;
1891 int64_t expire_time, t_now;
1892 int usec_elapsed;
1893 int frames;
1894 int usec_now;
1895 int i;
1896 int skipped_frames = 0;
1897
1898
1899 t_now = qemu_get_clock_ns(vm_clock);
1900 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
1901 if (expire_time == t_now) {
1902 expire_time++;
1903 }
1904
1905 usec_now = t_now / 1000;
1906 usec_elapsed = usec_now - ehci->last_run_usec;
1907 frames = usec_elapsed / FRAME_TIMER_USEC;
1908 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
1909
1910 for (i = 0; i < frames; i++) {
1911 if ( !(ehci->usbsts & USBSTS_HALT)) {
1912 if (ehci->isoch_pause <= 0) {
1913 ehci->frindex += 8;
1914 }
1915
1916 if (ehci->frindex > 0x00001fff) {
1917 ehci->frindex = 0;
1918 ehci_set_interrupt(ehci, USBSTS_FLR);
1919 }
1920
1921 ehci->sofv = (ehci->frindex - 1) >> 3;
1922 ehci->sofv &= 0x000003ff;
1923 }
1924
1925 if (frames - i > 10) {
1926 skipped_frames++;
1927 } else {
1928 // TODO could this cause periodic frames to get skipped if async
1929 // active?
1930 if (ehci_get_state(ehci, 1) != EST_EXECUTING) {
1931 ehci_advance_periodic_state(ehci);
1932 }
1933 }
1934
1935 ehci->last_run_usec += FRAME_TIMER_USEC;
1936 }
1937
1938 #if 0
1939 if (skipped_frames) {
1940 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
1941 }
1942 #endif
1943
1944 /* Async is not inside loop since it executes everything it can once
1945 * called
1946 */
1947 if (ehci_get_state(ehci, 0) != EST_EXECUTING) {
1948 ehci_advance_async_state(ehci);
1949 }
1950
1951 qemu_mod_timer(ehci->frame_timer, expire_time);
1952 }
1953
1954 static CPUReadMemoryFunc *ehci_readfn[3]={
1955 ehci_mem_readb,
1956 ehci_mem_readw,
1957 ehci_mem_readl
1958 };
1959
1960 static CPUWriteMemoryFunc *ehci_writefn[3]={
1961 ehci_mem_writeb,
1962 ehci_mem_writew,
1963 ehci_mem_writel
1964 };
1965
1966 static void ehci_map(PCIDevice *pci_dev, int region_num,
1967 pcibus_t addr, pcibus_t size, int type)
1968 {
1969 EHCIState *s =(EHCIState *)pci_dev;
1970
1971 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
1972 region_num, addr, size, s->mem);
1973 s->mem_base = addr;
1974 cpu_register_physical_memory(addr, size, s->mem);
1975 }
1976
1977 static int usb_ehci_initfn(PCIDevice *dev);
1978
1979 static USBPortOps ehci_port_ops = {
1980 .attach = ehci_attach,
1981 .detach = ehci_detach,
1982 .complete = ehci_async_complete_packet,
1983 };
1984
1985 static PCIDeviceInfo ehci_info = {
1986 .qdev.name = "usb-ehci",
1987 .qdev.size = sizeof(EHCIState),
1988 .init = usb_ehci_initfn,
1989 };
1990
1991 static int usb_ehci_initfn(PCIDevice *dev)
1992 {
1993 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
1994 uint8_t *pci_conf = s->dev.config;
1995 int i;
1996
1997 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1998 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
1999 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
2000 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2001 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
2002 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
2003
2004 /* capabilities pointer */
2005 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2006 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2007
2008 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2009 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2010 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2011
2012 // pci_conf[0x50] = 0x01; // power management caps
2013
2014 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2015 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2016 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2017
2018 pci_conf[0x64] = 0x00;
2019 pci_conf[0x65] = 0x00;
2020 pci_conf[0x66] = 0x00;
2021 pci_conf[0x67] = 0x00;
2022 pci_conf[0x68] = 0x01;
2023 pci_conf[0x69] = 0x00;
2024 pci_conf[0x6a] = 0x00;
2025 pci_conf[0x6b] = 0x00; // USBLEGSUP
2026 pci_conf[0x6c] = 0x00;
2027 pci_conf[0x6d] = 0x00;
2028 pci_conf[0x6e] = 0x00;
2029 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2030
2031 // 2.2 host controller interface version
2032 s->mmio[0x00] = (uint8_t) OPREGBASE;
2033 s->mmio[0x01] = 0x00;
2034 s->mmio[0x02] = 0x00;
2035 s->mmio[0x03] = 0x01; // HC version
2036 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2037 s->mmio[0x05] = 0x00; // No companion ports at present
2038 s->mmio[0x06] = 0x00;
2039 s->mmio[0x07] = 0x00;
2040 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2041 s->mmio[0x09] = 0x68; // EECP
2042 s->mmio[0x0a] = 0x00;
2043 s->mmio[0x0b] = 0x00;
2044
2045 s->irq = s->dev.irq[3];
2046
2047 usb_bus_new(&s->bus, &s->dev.qdev);
2048 for(i = 0; i < NB_PORTS; i++) {
2049 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2050 USB_SPEED_MASK_HIGH);
2051 usb_port_location(&s->ports[i], NULL, i+1);
2052 s->ports[i].dev = 0;
2053 }
2054
2055 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2056
2057 qemu_register_reset(ehci_reset, s);
2058
2059 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2060 DEVICE_LITTLE_ENDIAN);
2061
2062 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2063 ehci_map);
2064
2065 fprintf(stderr, "*** EHCI support is under development ***\n");
2066
2067 return 0;
2068 }
2069
2070 static void ehci_register(void)
2071 {
2072 pci_qdev_register(&ehci_info);
2073 }
2074 device_init(ehci_register);
2075
2076 /*
2077 * vim: expandtab ts=4
2078 */
Qemu copy for testing