2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
32 /* Dump packet contents. */
33 //#define DEBUG_PACKET
34 /* This causes frames to occur 1000x slower */
35 //#define OHCI_TIME_WARP 1
38 #define dprintf printf
43 /* Number of Downstream Ports on the root hub. */
45 #define OHCI_MAX_PORTS 15
47 static int64_t usb_frame_time
;
48 static int64_t usb_bit_time
;
50 typedef struct OHCIPort
{
56 struct PCIDevice pci_dev
;
57 target_phys_addr_t mem_base
;
65 /* Control partition */
70 /* memory pointer partition */
72 uint32_t ctrl_head
, ctrl_cur
;
73 uint32_t bulk_head
, bulk_cur
;
78 /* Frame counter partition */
83 uint16_t frame_number
;
88 /* Root Hub partition */
89 uint32_t rhdesc_a
, rhdesc_b
;
91 OHCIPort rhport
[OHCI_MAX_PORTS
];
94 /* Host Controller Communications Area */
101 /* Bitfields for the first word of an Endpoint Desciptor. */
102 #define OHCI_ED_FA_SHIFT 0
103 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
104 #define OHCI_ED_EN_SHIFT 7
105 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
106 #define OHCI_ED_D_SHIFT 11
107 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
108 #define OHCI_ED_S (1<<13)
109 #define OHCI_ED_K (1<<14)
110 #define OHCI_ED_F (1<<15)
111 #define OHCI_ED_MPS_SHIFT 7
112 #define OHCI_ED_MPS_MASK (0xf<<OHCI_ED_FA_SHIFT)
114 /* Flags in the head field of an Endpoint Desciptor. */
118 /* Bitfields for the first word of a Transfer Desciptor. */
119 #define OHCI_TD_R (1<<18)
120 #define OHCI_TD_DP_SHIFT 19
121 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
122 #define OHCI_TD_DI_SHIFT 21
123 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
124 #define OHCI_TD_T0 (1<<24)
125 #define OHCI_TD_T1 (1<<24)
126 #define OHCI_TD_EC_SHIFT 26
127 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
128 #define OHCI_TD_CC_SHIFT 28
129 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
131 #define OHCI_DPTR_MASK 0xfffffff0
133 #define OHCI_BM(val, field) \
134 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
136 #define OHCI_SET_BM(val, field, newval) do { \
137 val &= ~OHCI_##field##_MASK; \
138 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
141 /* endpoint descriptor */
149 /* General transfer descriptor */
157 #define USB_HZ 12000000
159 /* OHCI Local stuff */
160 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
161 #define OHCI_CTL_PLE (1<<2)
162 #define OHCI_CTL_IE (1<<3)
163 #define OHCI_CTL_CLE (1<<4)
164 #define OHCI_CTL_BLE (1<<5)
165 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
166 #define OHCI_USB_RESET 0x00
167 #define OHCI_USB_RESUME 0x40
168 #define OHCI_USB_OPERATIONAL 0x80
169 #define OHCI_USB_SUSPEND 0xc0
170 #define OHCI_CTL_IR (1<<8)
171 #define OHCI_CTL_RWC (1<<9)
172 #define OHCI_CTL_RWE (1<<10)
174 #define OHCI_STATUS_HCR (1<<0)
175 #define OHCI_STATUS_CLF (1<<1)
176 #define OHCI_STATUS_BLF (1<<2)
177 #define OHCI_STATUS_OCR (1<<3)
178 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
180 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
181 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
182 #define OHCI_INTR_SF (1<<2) /* Start of frame */
183 #define OHCI_INTR_RD (1<<3) /* Resume detect */
184 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
185 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
186 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
187 #define OHCI_INTR_OC (1<<30) /* Ownership change */
188 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
190 #define OHCI_HCCA_SIZE 0x100
191 #define OHCI_HCCA_MASK 0xffffff00
193 #define OHCI_EDPTR_MASK 0xfffffff0
195 #define OHCI_FMI_FI 0x00003fff
196 #define OHCI_FMI_FSMPS 0xffff0000
197 #define OHCI_FMI_FIT 0x80000000
199 #define OHCI_FR_RT (1<<31)
201 #define OHCI_LS_THRESH 0x628
203 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
204 #define OHCI_RHA_PSM (1<<8)
205 #define OHCI_RHA_NPS (1<<9)
206 #define OHCI_RHA_DT (1<<10)
207 #define OHCI_RHA_OCPM (1<<11)
208 #define OHCI_RHA_NOCP (1<<12)
209 #define OHCI_RHA_POTPGT_MASK 0xff000000
211 #define OHCI_RHS_LPS (1<<0)
212 #define OHCI_RHS_OCI (1<<1)
213 #define OHCI_RHS_DRWE (1<<15)
214 #define OHCI_RHS_LPSC (1<<16)
215 #define OHCI_RHS_OCIC (1<<17)
216 #define OHCI_RHS_CRWE (1<<31)
218 #define OHCI_PORT_CCS (1<<0)
219 #define OHCI_PORT_PES (1<<1)
220 #define OHCI_PORT_PSS (1<<2)
221 #define OHCI_PORT_POCI (1<<3)
222 #define OHCI_PORT_PRS (1<<4)
223 #define OHCI_PORT_PPS (1<<8)
224 #define OHCI_PORT_LSDA (1<<9)
225 #define OHCI_PORT_CSC (1<<16)
226 #define OHCI_PORT_PESC (1<<17)
227 #define OHCI_PORT_PSSC (1<<18)
228 #define OHCI_PORT_OCIC (1<<19)
229 #define OHCI_PORT_PRSC (1<<20)
230 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
231 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
233 #define OHCI_TD_DIR_SETUP 0x0
234 #define OHCI_TD_DIR_OUT 0x1
235 #define OHCI_TD_DIR_IN 0x2
236 #define OHCI_TD_DIR_RESERVED 0x3
238 #define OHCI_CC_NOERROR 0x0
239 #define OHCI_CC_CRC 0x1
240 #define OHCI_CC_BITSTUFFING 0x2
241 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
242 #define OHCI_CC_STALL 0x4
243 #define OHCI_CC_DEVICENOTRESPONDING 0x5
244 #define OHCI_CC_PIDCHECKFAILURE 0x6
245 #define OHCI_CC_UNDEXPETEDPID 0x7
246 #define OHCI_CC_DATAOVERRUN 0x8
247 #define OHCI_CC_DATAUNDERRUN 0x9
248 #define OHCI_CC_BUFFEROVERRUN 0xc
249 #define OHCI_CC_BUFFERUNDERRUN 0xd
251 static void ohci_attach(USBPort
*port1
, USBDevice
*dev
)
253 OHCIState
*s
= port1
->opaque
;
254 OHCIPort
*port
= &s
->rhport
[port1
->index
];
257 if (port
->port
.dev
) {
258 usb_attach(port1
, NULL
);
260 /* set connect status */
261 if (!(port
->ctrl
& OHCI_PORT_CCS
)) {
262 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
265 if (dev
->speed
== USB_SPEED_LOW
)
266 port
->ctrl
|= OHCI_PORT_LSDA
;
268 port
->ctrl
&= ~OHCI_PORT_LSDA
;
269 port
->port
.dev
= dev
;
270 /* send the attach message */
271 dev
->handle_packet(dev
,
272 USB_MSG_ATTACH
, 0, 0, NULL
, 0);
273 dprintf("usb-ohci: Attached port %d\n", port1
->index
);
275 /* set connect status */
276 if (!(port
->ctrl
& OHCI_PORT_CCS
)) {
277 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
280 if (port
->ctrl
& OHCI_PORT_PES
) {
281 port
->ctrl
&= ~OHCI_PORT_PES
;
282 port
->ctrl
|= OHCI_PORT_PESC
;
284 dev
= port
->port
.dev
;
286 /* send the detach message */
287 dev
->handle_packet(dev
,
288 USB_MSG_DETACH
, 0, 0, NULL
, 0);
290 port
->port
.dev
= NULL
;
291 dprintf("usb-ohci: Detached port %d\n", port1
->index
);
295 /* Reset the controller */
296 static void ohci_reset(OHCIState
*ohci
)
303 ohci
->intr_status
= 0;
304 ohci
->intr
= OHCI_INTR_MIE
;
307 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
308 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
311 ohci
->done_count
= 7;
313 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
314 * I took the value linux sets ...
316 ohci
->fsmps
= 0x2778;
320 ohci
->frame_number
= 0;
322 ohci
->lst
= OHCI_LS_THRESH
;
324 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
325 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
328 for (i
= 0; i
< ohci
->num_ports
; i
++)
330 port
= &ohci
->rhport
[i
];
333 ohci_attach(&port
->port
, port
->port
.dev
);
335 dprintf("usb-ohci: Reset %s\n", ohci
->pci_dev
.name
);
338 /* Update IRQ levels */
339 static inline void ohci_intr_update(OHCIState
*ohci
)
343 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
344 (ohci
->intr_status
& ohci
->intr
))
347 pci_set_irq(&ohci
->pci_dev
, 0, level
);
350 /* Set an interrupt */
351 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
353 ohci
->intr_status
|= intr
;
354 ohci_intr_update(ohci
);
357 /* Get an array of dwords from main memory */
358 static inline int get_dwords(uint32_t addr
, uint32_t *buf
, int num
)
362 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
363 cpu_physical_memory_rw(addr
, (uint8_t *)buf
, sizeof(*buf
), 0);
364 *buf
= le32_to_cpu(*buf
);
370 /* Put an array of dwords in to main memory */
371 static inline int put_dwords(uint32_t addr
, uint32_t *buf
, int num
)
375 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
376 uint32_t tmp
= cpu_to_le32(*buf
);
377 cpu_physical_memory_rw(addr
, (uint8_t *)&tmp
, sizeof(tmp
), 1);
383 static inline int ohci_read_ed(uint32_t addr
, struct ohci_ed
*ed
)
385 return get_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
388 static inline int ohci_read_td(uint32_t addr
, struct ohci_td
*td
)
390 return get_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
393 static inline int ohci_put_ed(uint32_t addr
, struct ohci_ed
*ed
)
395 return put_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
398 static inline int ohci_put_td(uint32_t addr
, struct ohci_td
*td
)
400 return put_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
403 /* Read/Write the contents of a TD from/to main memory. */
404 static void ohci_copy_td(struct ohci_td
*td
, uint8_t *buf
, int len
, int write
)
410 n
= 0x1000 - (ptr
& 0xfff);
413 cpu_physical_memory_rw(ptr
, buf
, n
, write
);
416 ptr
= td
->be
& ~0xfffu
;
417 cpu_physical_memory_rw(ptr
, buf
, len
- n
, write
);
420 /* Service a transport descriptor.
421 Returns nonzero to terminate processing of this endpoint. */
423 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
437 addr
= ed
->head
& OHCI_DPTR_MASK
;
438 if (!ohci_read_td(addr
, &td
)) {
439 fprintf(stderr
, "usb-ohci: TD read error at %x\n", addr
);
443 dir
= OHCI_BM(ed
->flags
, ED_D
);
445 case OHCI_TD_DIR_OUT
:
450 dir
= OHCI_BM(td
.flags
, TD_DP
);
459 case OHCI_TD_DIR_OUT
:
463 case OHCI_TD_DIR_SETUP
:
465 pid
= USB_TOKEN_SETUP
;
468 fprintf(stderr
, "usb-ohci: Bad direction\n");
471 if (td
.cbp
&& td
.be
) {
472 len
= (td
.be
- td
.cbp
) + 1;
473 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
474 ohci_copy_td(&td
, buf
, len
, 0);
478 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
480 dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
481 addr
, len
, str
, flag_r
, td
.cbp
, td
.be
);
483 if (len
>= 0 && dir
!= OHCI_TD_DIR_IN
) {
485 for (i
= 0; i
< len
; i
++)
486 printf(" %.2x", buf
[i
]);
491 for (i
= 0; i
< ohci
->num_ports
; i
++) {
492 dev
= ohci
->rhport
[i
].port
.dev
;
493 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0)
496 ret
= dev
->handle_packet(dev
, pid
, OHCI_BM(ed
->flags
, ED_FA
),
497 OHCI_BM(ed
->flags
, ED_EN
), buf
, len
);
498 if (ret
!= USB_RET_NODEV
)
502 dprintf("ret=%d\n", ret
);
505 if (dir
== OHCI_TD_DIR_IN
) {
506 ohci_copy_td(&td
, buf
, ret
, 1);
509 for (i
= 0; i
< ret
; i
++)
510 printf(" %.2x", buf
[i
]);
519 if (ret
== len
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
520 /* Transmission succeeded. */
525 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
527 td
.cbp
|= td
.be
& ~0xfff;
530 td
.flags
|= OHCI_TD_T1
;
531 td
.flags
^= OHCI_TD_T0
;
532 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
533 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
535 ed
->head
&= ~OHCI_ED_C
;
536 if (td
.flags
& OHCI_TD_T0
)
537 ed
->head
|= OHCI_ED_C
;
540 dprintf("usb-ohci: Underrun\n");
541 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
545 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
547 dprintf("usb-ohci: got NAK\n");
550 dprintf("usb-ohci: got STALL\n");
551 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
554 dprintf("usb-ohci: got BABBLE\n");
555 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
558 fprintf(stderr
, "usb-ohci: Bad device response %d\n", ret
);
559 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
560 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
564 ed
->head
|= OHCI_ED_H
;
568 ed
->head
&= ~OHCI_DPTR_MASK
;
569 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
570 td
.next
= ohci
->done
;
572 i
= OHCI_BM(td
.flags
, TD_DI
);
573 if (i
< ohci
->done_count
)
574 ohci
->done_count
= i
;
575 ohci_put_td(addr
, &td
);
576 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
579 /* Service an endpoint list. Returns nonzero if active TD were found. */
580 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
)
592 for (cur
= head
; cur
; cur
= next_ed
) {
593 if (!ohci_read_ed(cur
, &ed
)) {
594 fprintf(stderr
, "usb-ohci: ED read error at %x\n", cur
);
598 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
600 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
))
603 /* Skip isochronous endpoints. */
604 if (ed
.flags
& OHCI_ED_F
)
607 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
609 dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
610 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur
,
611 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
612 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
613 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
614 OHCI_BM(ed
.flags
, ED_MPS
), (ed
.head
& OHCI_ED_H
) != 0,
615 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
616 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
620 if (ohci_service_td(ohci
, &ed
))
624 ohci_put_ed(cur
, &ed
);
630 /* Generate a SOF event, and set a timer for EOF */
631 static void ohci_sof(OHCIState
*ohci
)
633 ohci
->sof_time
= qemu_get_clock(vm_clock
);
634 qemu_mod_timer(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
635 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
638 /* Do frame processing on frame boundary */
639 static void ohci_frame_boundary(void *opaque
)
641 OHCIState
*ohci
= opaque
;
642 struct ohci_hcca hcca
;
644 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 0);
646 /* Process all the lists at the end of the frame */
647 if (ohci
->ctl
& OHCI_CTL_PLE
) {
650 n
= ohci
->frame_number
& 0x1f;
651 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]));
653 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
654 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
)
655 dprintf("usb-ohci: head %x, cur %x\n", ohci
->ctrl_head
, ohci
->ctrl_cur
);
656 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
)) {
658 ohci
->status
&= ~OHCI_STATUS_CLF
;
662 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
663 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
)) {
665 ohci
->status
&= ~OHCI_STATUS_BLF
;
669 /* Frame boundary, so do EOF stuf here */
670 ohci
->frt
= ohci
->fit
;
672 /* XXX: endianness */
673 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
674 hcca
.frame
= cpu_to_le32(ohci
->frame_number
);
676 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
679 if (ohci
->intr
& ohci
->intr_status
)
681 hcca
.done
= cpu_to_le32(ohci
->done
);
683 ohci
->done_count
= 7;
684 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
687 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
690 /* Do SOF stuff here */
694 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 1);
697 /* Start sending SOF tokens across the USB bus, lists are processed in
700 static int ohci_bus_start(OHCIState
*ohci
)
702 ohci
->eof_timer
= qemu_new_timer(vm_clock
,
706 if (ohci
->eof_timer
== NULL
) {
707 fprintf(stderr
, "usb-ohci: %s: qemu_new_timer failed\n",
709 /* TODO: Signal unrecoverable error */
713 dprintf("usb-ohci: %s: USB Operational\n", ohci
->pci_dev
.name
);
720 /* Stop sending SOF tokens on the bus */
721 static void ohci_bus_stop(OHCIState
*ohci
)
724 qemu_del_timer(ohci
->eof_timer
);
727 /* Sets a flag in a port status register but only set it if the port is
728 * connected, if not set ConnectStatusChange flag. If flag is enabled
731 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
735 /* writing a 0 has no effect */
739 /* If CurrentConnectStatus is cleared we set
740 * ConnectStatusChange
742 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
743 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
744 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
745 /* TODO: CSC is a wakeup event */
750 if (ohci
->rhport
[i
].ctrl
& val
)
754 ohci
->rhport
[i
].ctrl
|= val
;
759 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
760 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
764 if (val
!= ohci
->fi
) {
765 dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
766 ohci
->pci_dev
.name
, ohci
->fi
, ohci
->fi
);
772 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
775 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
777 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
784 /* Set HcControlRegister */
785 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
790 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
792 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
794 /* no state change */
795 if (old_state
== new_state
)
799 case OHCI_USB_OPERATIONAL
:
800 ohci_bus_start(ohci
);
802 case OHCI_USB_SUSPEND
:
804 dprintf("usb-ohci: %s: USB Suspended\n", ohci
->pci_dev
.name
);
806 case OHCI_USB_RESUME
:
807 dprintf("usb-ohci: %s: USB Resume\n", ohci
->pci_dev
.name
);
810 dprintf("usb-ohci: %s: USB Reset\n", ohci
->pci_dev
.name
);
815 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
820 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
821 return (ohci
->frt
<< 31);
823 /* Being in USB operational state guarnatees sof_time was
826 tks
= qemu_get_clock(vm_clock
) - ohci
->sof_time
;
828 /* avoid muldiv if possible */
829 if (tks
>= usb_frame_time
)
830 return (ohci
->frt
<< 31);
832 tks
= muldiv64(1, tks
, usb_bit_time
);
833 fr
= (uint16_t)(ohci
->fi
- tks
);
835 return (ohci
->frt
<< 31) | fr
;
839 /* Set root hub status */
840 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
844 old_state
= ohci
->rhstatus
;
846 /* write 1 to clear OCIC */
847 if (val
& OHCI_RHS_OCIC
)
848 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
850 if (val
& OHCI_RHS_LPS
) {
853 for (i
= 0; i
< ohci
->num_ports
; i
++)
854 ohci_port_power(ohci
, i
, 0);
855 dprintf("usb-ohci: powered down all ports\n");
858 if (val
& OHCI_RHS_LPSC
) {
861 for (i
= 0; i
< ohci
->num_ports
; i
++)
862 ohci_port_power(ohci
, i
, 1);
863 dprintf("usb-ohci: powered up all ports\n");
866 if (val
& OHCI_RHS_DRWE
)
867 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
869 if (val
& OHCI_RHS_CRWE
)
870 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
872 if (old_state
!= ohci
->rhstatus
)
873 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
876 /* Set root hub port status */
877 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
882 port
= &ohci
->rhport
[portnum
];
883 old_state
= port
->ctrl
;
885 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
886 if (val
& OHCI_PORT_WTC
)
887 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
889 if (val
& OHCI_PORT_CCS
)
890 port
->ctrl
&= ~OHCI_PORT_PES
;
892 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
894 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
))
895 dprintf("usb-ohci: port %d: SUSPEND\n", portnum
);
897 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
898 dprintf("usb-ohci: port %d: RESET\n", portnum
);
899 port
->port
.dev
->handle_packet(port
->port
.dev
, USB_MSG_RESET
,
901 port
->ctrl
&= ~OHCI_PORT_PRS
;
902 /* ??? Should this also set OHCI_PORT_PESC. */
903 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
906 /* Invert order here to ensure in ambiguous case, device is
909 if (val
& OHCI_PORT_LSDA
)
910 ohci_port_power(ohci
, portnum
, 0);
911 if (val
& OHCI_PORT_PPS
)
912 ohci_port_power(ohci
, portnum
, 1);
914 if (old_state
!= port
->ctrl
)
915 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
920 static uint32_t ohci_mem_read(void *ptr
, target_phys_addr_t addr
)
922 OHCIState
*ohci
= ptr
;
924 addr
-= ohci
->mem_base
;
926 /* Only aligned reads are allowed on OHCI */
928 fprintf(stderr
, "usb-ohci: Mis-aligned read\n");
932 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
934 return ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
938 case 0: /* HcRevision */
941 case 1: /* HcControl */
944 case 2: /* HcCommandStatus */
947 case 3: /* HcInterruptStatus */
948 return ohci
->intr_status
;
950 case 4: /* HcInterruptEnable */
951 case 5: /* HcInterruptDisable */
957 case 7: /* HcPeriodCurrentED */
958 return ohci
->per_cur
;
960 case 8: /* HcControlHeadED */
961 return ohci
->ctrl_head
;
963 case 9: /* HcControlCurrentED */
964 return ohci
->ctrl_cur
;
966 case 10: /* HcBulkHeadED */
967 return ohci
->bulk_head
;
969 case 11: /* HcBulkCurrentED */
970 return ohci
->bulk_cur
;
972 case 12: /* HcDoneHead */
975 case 13: /* HcFmInterval */
976 return (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
978 case 14: /* HcFmRemaining */
979 return ohci_get_frame_remaining(ohci
);
981 case 15: /* HcFmNumber */
982 return ohci
->frame_number
;
984 case 16: /* HcPeriodicStart */
987 case 17: /* HcLSThreshold */
990 case 18: /* HcRhDescriptorA */
991 return ohci
->rhdesc_a
;
993 case 19: /* HcRhDescriptorB */
994 return ohci
->rhdesc_b
;
996 case 20: /* HcRhStatus */
997 return ohci
->rhstatus
;
1000 fprintf(stderr
, "ohci_read: Bad offset %x\n", (int)addr
);
1005 static void ohci_mem_write(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1007 OHCIState
*ohci
= ptr
;
1009 addr
-= ohci
->mem_base
;
1011 /* Only aligned reads are allowed on OHCI */
1013 fprintf(stderr
, "usb-ohci: Mis-aligned write\n");
1017 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1018 /* HcRhPortStatus */
1019 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1023 switch (addr
>> 2) {
1024 case 1: /* HcControl */
1025 ohci_set_ctl(ohci
, val
);
1028 case 2: /* HcCommandStatus */
1029 /* SOC is read-only */
1030 val
= (val
& ~OHCI_STATUS_SOC
);
1032 /* Bits written as '0' remain unchanged in the register */
1033 ohci
->status
|= val
;
1035 if (ohci
->status
& OHCI_STATUS_HCR
)
1039 case 3: /* HcInterruptStatus */
1040 ohci
->intr_status
&= ~val
;
1041 ohci_intr_update(ohci
);
1044 case 4: /* HcInterruptEnable */
1046 ohci_intr_update(ohci
);
1049 case 5: /* HcInterruptDisable */
1051 ohci_intr_update(ohci
);
1054 case 6: /* HcHCCA */
1055 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1058 case 8: /* HcControlHeadED */
1059 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1062 case 9: /* HcControlCurrentED */
1063 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1066 case 10: /* HcBulkHeadED */
1067 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1070 case 11: /* HcBulkCurrentED */
1071 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1074 case 13: /* HcFmInterval */
1075 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1076 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1077 ohci_set_frame_interval(ohci
, val
);
1080 case 16: /* HcPeriodicStart */
1081 ohci
->pstart
= val
& 0xffff;
1084 case 17: /* HcLSThreshold */
1085 ohci
->lst
= val
& 0xffff;
1088 case 18: /* HcRhDescriptorA */
1089 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1090 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1093 case 19: /* HcRhDescriptorB */
1096 case 20: /* HcRhStatus */
1097 ohci_set_hub_status(ohci
, val
);
1101 fprintf(stderr
, "ohci_write: Bad offset %x\n", (int)addr
);
1106 /* Only dword reads are defined on OHCI register space */
1107 static CPUReadMemoryFunc
*ohci_readfn
[3]={
1113 /* Only dword writes are defined on OHCI register space */
1114 static CPUWriteMemoryFunc
*ohci_writefn
[3]={
1120 static void ohci_mapfunc(PCIDevice
*pci_dev
, int i
,
1121 uint32_t addr
, uint32_t size
, int type
)
1123 OHCIState
*ohci
= (OHCIState
*)pci_dev
;
1124 ohci
->mem_base
= addr
;
1125 cpu_register_physical_memory(addr
, size
, ohci
->mem
);
1128 void usb_ohci_init(struct PCIBus
*bus
, int num_ports
, int devfn
)
1136 if (usb_frame_time
== 0) {
1138 usb_frame_time
= ticks_per_sec
;
1139 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
/1000);
1141 usb_frame_time
= muldiv64(1, ticks_per_sec
, 1000);
1142 if (ticks_per_sec
>= USB_HZ
) {
1143 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
);
1148 dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1149 usb_frame_time
, usb_bit_time
);
1152 ohci
= (OHCIState
*)pci_register_device(bus
, "OHCI USB", sizeof(*ohci
),
1155 fprintf(stderr
, "usb-ohci: Failed to register PCI device\n");
1159 ohci
->pci_dev
.config
[0x00] = vid
& 0xff;
1160 ohci
->pci_dev
.config
[0x01] = (vid
>> 8) & 0xff;
1161 ohci
->pci_dev
.config
[0x02] = did
& 0xff;
1162 ohci
->pci_dev
.config
[0x03] = (did
>> 8) & 0xff;
1163 ohci
->pci_dev
.config
[0x09] = 0x10; /* OHCI */
1164 ohci
->pci_dev
.config
[0x0a] = 0x3;
1165 ohci
->pci_dev
.config
[0x0b] = 0xc;
1166 ohci
->pci_dev
.config
[0x3d] = 0x01; /* interrupt pin 1 */
1168 ohci
->mem
= cpu_register_io_memory(0, ohci_readfn
, ohci_writefn
, ohci
);
1170 pci_register_io_region((struct PCIDevice
*)ohci
, 0, 256,
1171 PCI_ADDRESS_SPACE_MEM
, ohci_mapfunc
);
1173 ohci
->num_ports
= num_ports
;
1174 for (i
= 0; i
< num_ports
; i
++) {
1175 qemu_register_usb_port(&ohci
->rhport
[i
].port
, ohci
, i
, ohci_attach
);