hw/usb-ohci.c

   1 /*
   2  * QEMU USB OHCI Emulation
   3  * Copyright (c) 2004 Gianni Tedesco
   4  * Copyright (c) 2006 CodeSourcery
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  * TODO:
  21  *  o Isochronous transfers
  22  *  o Allocate bandwidth in frames properly
  23  *  o Disable timers when nothing needs to be done, or remove timer usage
  24  *    all together.
  25  *  o Handle unrecoverable errors properly
  26  *  o BIOS work to boot from USB storage
  27 */
  28
  29 #include "vl.h"
  30
  31 //#define DEBUG_OHCI
  32 /* Dump packet contents.  */
  33 //#define DEBUG_PACKET
  34 /* This causes frames to occur 1000x slower */
  35 //#define OHCI_TIME_WARP 1
  36
  37 #ifdef DEBUG_OHCI
  38 #define dprintf printf
  39 #else
  40 #define dprintf(...)
  41 #endif
  42
  43 /* Number of Downstream Ports on the root hub.  */
  44
  45 #define OHCI_MAX_PORTS 15
  46
  47 static int64_t usb_frame_time;
  48 static int64_t usb_bit_time;
  49
  50 typedef struct OHCIPort {
  51     USBPort port;
  52     uint32_t ctrl;
  53 } OHCIPort;
  54
  55 typedef struct {
  56     struct PCIDevice pci_dev;
  57     target_phys_addr_t mem_base;
  58     int mem;
  59     int num_ports;
  60
  61     QEMUTimer *eof_timer;
  62     int64_t sof_time;
  63
  64     /* OHCI state */
  65     /* Control partition */
  66     uint32_t ctl, status;
  67     uint32_t intr_status;
  68     uint32_t intr;
  69
  70     /* memory pointer partition */
  71     uint32_t hcca;
  72     uint32_t ctrl_head, ctrl_cur;
  73     uint32_t bulk_head, bulk_cur;
  74     uint32_t per_cur;
  75     uint32_t done;
  76     int done_count;
  77
  78     /* Frame counter partition */
  79     uint32_t fsmps:15;
  80     uint32_t fit:1;
  81     uint32_t fi:14;
  82     uint32_t frt:1;
  83     uint16_t frame_number;
  84     uint16_t padding;
  85     uint32_t pstart;
  86     uint32_t lst;
  87
  88     /* Root Hub partition */
  89     uint32_t rhdesc_a, rhdesc_b;
  90     uint32_t rhstatus;
  91     OHCIPort rhport[OHCI_MAX_PORTS];
  92 } OHCIState;
  93
  94 /* Host Controller Communications Area */
  95 struct ohci_hcca {
  96     uint32_t intr[32];
  97     uint16_t frame, pad;
  98     uint32_t done;
  99 };
 100
 101 /* Bitfields for the first word of an Endpoint Desciptor.  */
 102 #define OHCI_ED_FA_SHIFT  0
 103 #define OHCI_ED_FA_MASK   (0x7f<<OHCI_ED_FA_SHIFT)
 104 #define OHCI_ED_EN_SHIFT  7
 105 #define OHCI_ED_EN_MASK   (0xf<<OHCI_ED_EN_SHIFT)
 106 #define OHCI_ED_D_SHIFT   11
 107 #define OHCI_ED_D_MASK    (3<<OHCI_ED_D_SHIFT)
 108 #define OHCI_ED_S         (1<<13)
 109 #define OHCI_ED_K         (1<<14)
 110 #define OHCI_ED_F         (1<<15)
 111 #define OHCI_ED_MPS_SHIFT 7
 112 #define OHCI_ED_MPS_MASK  (0xf<<OHCI_ED_FA_SHIFT)
 113
 114 /* Flags in the head field of an Endpoint Desciptor.  */
 115 #define OHCI_ED_H         1
 116 #define OHCI_ED_C         2
 117
 118 /* Bitfields for the first word of a Transfer Desciptor.  */
 119 #define OHCI_TD_R         (1<<18)
 120 #define OHCI_TD_DP_SHIFT  19
 121 #define OHCI_TD_DP_MASK   (3<<OHCI_TD_DP_SHIFT)
 122 #define OHCI_TD_DI_SHIFT  21
 123 #define OHCI_TD_DI_MASK   (7<<OHCI_TD_DI_SHIFT)
 124 #define OHCI_TD_T0        (1<<24)
 125 #define OHCI_TD_T1        (1<<24)
 126 #define OHCI_TD_EC_SHIFT  26
 127 #define OHCI_TD_EC_MASK   (3<<OHCI_TD_EC_SHIFT)
 128 #define OHCI_TD_CC_SHIFT  28
 129 #define OHCI_TD_CC_MASK   (0xf<<OHCI_TD_CC_SHIFT)
 130
 131 #define OHCI_DPTR_MASK    0xfffffff0
 132
 133 #define OHCI_BM(val, field) \
 134   (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
 135
 136 #define OHCI_SET_BM(val, field, newval) do { \
 137     val &= ~OHCI_##field##_MASK; \
 138     val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
 139     } while(0)
 140
 141 /* endpoint descriptor */
 142 struct ohci_ed {
 143     uint32_t flags;
 144     uint32_t tail;
 145     uint32_t head;
 146     uint32_t next;
 147 };
 148
 149 /* General transfer descriptor */
 150 struct ohci_td {
 151     uint32_t flags;
 152     uint32_t cbp;
 153     uint32_t next;
 154     uint32_t be;
 155 };
 156
 157 #define USB_HZ                      12000000
 158
 159 /* OHCI Local stuff */
 160 #define OHCI_CTL_CBSR         ((1<<0)|(1<<1))
 161 #define OHCI_CTL_PLE          (1<<2)
 162 #define OHCI_CTL_IE           (1<<3)
 163 #define OHCI_CTL_CLE          (1<<4)
 164 #define OHCI_CTL_BLE          (1<<5)
 165 #define OHCI_CTL_HCFS         ((1<<6)|(1<<7))
 166 #define  OHCI_USB_RESET       0x00
 167 #define  OHCI_USB_RESUME      0x40
 168 #define  OHCI_USB_OPERATIONAL 0x80
 169 #define  OHCI_USB_SUSPEND     0xc0
 170 #define OHCI_CTL_IR           (1<<8)
 171 #define OHCI_CTL_RWC          (1<<9)
 172 #define OHCI_CTL_RWE          (1<<10)
 173
 174 #define OHCI_STATUS_HCR       (1<<0)
 175 #define OHCI_STATUS_CLF       (1<<1)
 176 #define OHCI_STATUS_BLF       (1<<2)
 177 #define OHCI_STATUS_OCR       (1<<3)
 178 #define OHCI_STATUS_SOC       ((1<<6)|(1<<7))
 179
 180 #define OHCI_INTR_SO          (1<<0) /* Scheduling overrun */
 181 #define OHCI_INTR_WD          (1<<1) /* HcDoneHead writeback */
 182 #define OHCI_INTR_SF          (1<<2) /* Start of frame */
 183 #define OHCI_INTR_RD          (1<<3) /* Resume detect */
 184 #define OHCI_INTR_UE          (1<<4) /* Unrecoverable error */
 185 #define OHCI_INTR_FNO         (1<<5) /* Frame number overflow */
 186 #define OHCI_INTR_RHSC        (1<<6) /* Root hub status change */
 187 #define OHCI_INTR_OC          (1<<30) /* Ownership change */
 188 #define OHCI_INTR_MIE         (1<<31) /* Master Interrupt Enable */
 189
 190 #define OHCI_HCCA_SIZE        0x100
 191 #define OHCI_HCCA_MASK        0xffffff00
 192
 193 #define OHCI_EDPTR_MASK       0xfffffff0
 194
 195 #define OHCI_FMI_FI           0x00003fff
 196 #define OHCI_FMI_FSMPS        0xffff0000
 197 #define OHCI_FMI_FIT          0x80000000
 198
 199 #define OHCI_FR_RT            (1<<31)
 200
 201 #define OHCI_LS_THRESH        0x628
 202
 203 #define OHCI_RHA_RW_MASK      0x00000000 /* Mask of supported features.  */
 204 #define OHCI_RHA_PSM          (1<<8)
 205 #define OHCI_RHA_NPS          (1<<9)
 206 #define OHCI_RHA_DT           (1<<10)
 207 #define OHCI_RHA_OCPM         (1<<11)
 208 #define OHCI_RHA_NOCP         (1<<12)
 209 #define OHCI_RHA_POTPGT_MASK  0xff000000
 210
 211 #define OHCI_RHS_LPS          (1<<0)
 212 #define OHCI_RHS_OCI          (1<<1)
 213 #define OHCI_RHS_DRWE         (1<<15)
 214 #define OHCI_RHS_LPSC         (1<<16)
 215 #define OHCI_RHS_OCIC         (1<<17)
 216 #define OHCI_RHS_CRWE         (1<<31)
 217
 218 #define OHCI_PORT_CCS         (1<<0)
 219 #define OHCI_PORT_PES         (1<<1)
 220 #define OHCI_PORT_PSS         (1<<2)
 221 #define OHCI_PORT_POCI        (1<<3)
 222 #define OHCI_PORT_PRS         (1<<4)
 223 #define OHCI_PORT_PPS         (1<<8)
 224 #define OHCI_PORT_LSDA        (1<<9)
 225 #define OHCI_PORT_CSC         (1<<16)
 226 #define OHCI_PORT_PESC        (1<<17)
 227 #define OHCI_PORT_PSSC        (1<<18)
 228 #define OHCI_PORT_OCIC        (1<<19)
 229 #define OHCI_PORT_PRSC        (1<<20)
 230 #define OHCI_PORT_WTC         (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
 231                                |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
 232
 233 #define OHCI_TD_DIR_SETUP     0x0
 234 #define OHCI_TD_DIR_OUT       0x1
 235 #define OHCI_TD_DIR_IN        0x2
 236 #define OHCI_TD_DIR_RESERVED  0x3
 237
 238 #define OHCI_CC_NOERROR             0x0
 239 #define OHCI_CC_CRC                 0x1
 240 #define OHCI_CC_BITSTUFFING         0x2
 241 #define OHCI_CC_DATATOGGLEMISMATCH  0x3
 242 #define OHCI_CC_STALL               0x4
 243 #define OHCI_CC_DEVICENOTRESPONDING 0x5
 244 #define OHCI_CC_PIDCHECKFAILURE     0x6
 245 #define OHCI_CC_UNDEXPETEDPID       0x7
 246 #define OHCI_CC_DATAOVERRUN         0x8
 247 #define OHCI_CC_DATAUNDERRUN        0x9
 248 #define OHCI_CC_BUFFEROVERRUN       0xc
 249 #define OHCI_CC_BUFFERUNDERRUN      0xd
 250
 251 /* Update IRQ levels */
 252 static inline void ohci_intr_update(OHCIState *ohci)
 253 {
 254     int level = 0;
 255
 256     if ((ohci->intr & OHCI_INTR_MIE) &&
 257         (ohci->intr_status & ohci->intr))
 258         level = 1;
 259
 260     pci_set_irq(&ohci->pci_dev, 0, level);
 261 }
 262
 263 /* Set an interrupt */
 264 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
 265 {
 266     ohci->intr_status |= intr;
 267     ohci_intr_update(ohci);
 268 }
 269
 270 /* Attach or detach a device on a root hub port.  */
 271 static void ohci_attach(USBPort *port1, USBDevice *dev)
 272 {
 273     OHCIState *s = port1->opaque;
 274     OHCIPort *port = &s->rhport[port1->index];
 275     uint32_t old_state = port->ctrl;
 276
 277     if (dev) {
 278         if (port->port.dev) {
 279             usb_attach(port1, NULL);
 280         }
 281         /* set connect status */
 282         port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
 283
 284         /* update speed */
 285         if (dev->speed == USB_SPEED_LOW)
 286             port->ctrl |= OHCI_PORT_LSDA;
 287         else
 288             port->ctrl &= ~OHCI_PORT_LSDA;
 289         port->port.dev = dev;
 290         /* send the attach message */
 291         dev->handle_packet(dev,
 292                            USB_MSG_ATTACH, 0, 0, NULL, 0);
 293         dprintf("usb-ohci: Attached port %d\n", port1->index);
 294     } else {
 295         /* set connect status */
 296         if (port->ctrl & OHCI_PORT_CCS) {
 297             port->ctrl &= ~OHCI_PORT_CCS;
 298             port->ctrl |= OHCI_PORT_CSC;
 299         }
 300         /* disable port */
 301         if (port->ctrl & OHCI_PORT_PES) {
 302             port->ctrl &= ~OHCI_PORT_PES;
 303             port->ctrl |= OHCI_PORT_PESC;
 304         }
 305         dev = port->port.dev;
 306         if (dev) {
 307             /* send the detach message */
 308             dev->handle_packet(dev,
 309                                USB_MSG_DETACH, 0, 0, NULL, 0);
 310         }
 311         port->port.dev = NULL;
 312         dprintf("usb-ohci: Detached port %d\n", port1->index);
 313     }
 314
 315     if (old_state != port->ctrl)
 316         ohci_set_interrupt(s, OHCI_INTR_RHSC);
 317 }
 318
 319 /* Reset the controller */
 320 static void ohci_reset(OHCIState *ohci)
 321 {
 322     OHCIPort *port;
 323     int i;
 324
 325     ohci->ctl = 0;
 326     ohci->status = 0;
 327     ohci->intr_status = 0;
 328     ohci->intr = OHCI_INTR_MIE;
 329
 330     ohci->hcca = 0;
 331     ohci->ctrl_head = ohci->ctrl_cur = 0;
 332     ohci->bulk_head = ohci->bulk_cur = 0;
 333     ohci->per_cur = 0;
 334     ohci->done = 0;
 335     ohci->done_count = 7;
 336
 337     /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
 338      * I took the value linux sets ...
 339      */
 340     ohci->fsmps = 0x2778;
 341     ohci->fi = 0x2edf;
 342     ohci->fit = 0;
 343     ohci->frt = 0;
 344     ohci->frame_number = 0;
 345     ohci->pstart = 0;
 346     ohci->lst = OHCI_LS_THRESH;
 347
 348     ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
 349     ohci->rhdesc_b = 0x0; /* Impl. specific */
 350     ohci->rhstatus = 0;
 351
 352     for (i = 0; i < ohci->num_ports; i++)
 353       {
 354         port = &ohci->rhport[i];
 355         port->ctrl = 0;
 356         if (port->port.dev)
 357             ohci_attach(&port->port, port->port.dev);
 358       }
 359     dprintf("usb-ohci: Reset %s\n", ohci->pci_dev.name);
 360 }
 361
 362 /* Get an array of dwords from main memory */
 363 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
 364 {
 365     int i;
 366
 367     for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
 368         cpu_physical_memory_rw(addr, (uint8_t *)buf, sizeof(*buf), 0);
 369         *buf = le32_to_cpu(*buf);
 370     }
 371
 372     return 1;
 373 }
 374
 375 /* Put an array of dwords in to main memory */
 376 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
 377 {
 378     int i;
 379
 380     for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
 381         uint32_t tmp = cpu_to_le32(*buf);
 382         cpu_physical_memory_rw(addr, (uint8_t *)&tmp, sizeof(tmp), 1);
 383     }
 384
 385     return 1;
 386 }
 387
 388 static inline int ohci_read_ed(uint32_t addr, struct ohci_ed *ed)
 389 {
 390     return get_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
 391 }
 392
 393 static inline int ohci_read_td(uint32_t addr, struct ohci_td *td)
 394 {
 395     return get_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
 396 }
 397
 398 static inline int ohci_put_ed(uint32_t addr, struct ohci_ed *ed)
 399 {
 400     return put_dwords(addr, (uint32_t *)ed, sizeof(*ed) >> 2);
 401 }
 402
 403 static inline int ohci_put_td(uint32_t addr, struct ohci_td *td)
 404 {
 405     return put_dwords(addr, (uint32_t *)td, sizeof(*td) >> 2);
 406 }
 407
 408 /* Read/Write the contents of a TD from/to main memory.  */
 409 static void ohci_copy_td(struct ohci_td *td, uint8_t *buf, int len, int write)
 410 {
 411     uint32_t ptr;
 412     uint32_t n;
 413
 414     ptr = td->cbp;
 415     n = 0x1000 - (ptr & 0xfff);
 416     if (n > len)
 417         n = len;
 418     cpu_physical_memory_rw(ptr, buf, n, write);
 419     if (n == len)
 420         return;
 421     ptr = td->be & ~0xfffu;
 422     cpu_physical_memory_rw(ptr, buf, len - n, write);
 423 }
 424
 425 /* Service a transport descriptor.
 426    Returns nonzero to terminate processing of this endpoint.  */
 427
 428 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
 429 {
 430     int dir;
 431     size_t len = 0;
 432     uint8_t buf[8192];
 433     char *str = NULL;
 434     int pid;
 435     int ret;
 436     int i;
 437     USBDevice *dev;
 438     struct ohci_td td;
 439     uint32_t addr;
 440     int flag_r;
 441
 442     addr = ed->head & OHCI_DPTR_MASK;
 443     if (!ohci_read_td(addr, &td)) {
 444         fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
 445         return 0;
 446     }
 447
 448     dir = OHCI_BM(ed->flags, ED_D);
 449     switch (dir) {
 450     case OHCI_TD_DIR_OUT:
 451     case OHCI_TD_DIR_IN:
 452         /* Same value.  */
 453         break;
 454     default:
 455         dir = OHCI_BM(td.flags, TD_DP);
 456         break;
 457     }
 458
 459     switch (dir) {
 460     case OHCI_TD_DIR_IN:
 461         str = "in";
 462         pid = USB_TOKEN_IN;
 463         break;
 464     case OHCI_TD_DIR_OUT:
 465         str = "out";
 466         pid = USB_TOKEN_OUT;
 467         break;
 468     case OHCI_TD_DIR_SETUP:
 469         str = "setup";
 470         pid = USB_TOKEN_SETUP;
 471         break;
 472     default:
 473         fprintf(stderr, "usb-ohci: Bad direction\n");
 474         return 1;
 475     }
 476     if (td.cbp && td.be) {
 477         len = (td.be - td.cbp) + 1;
 478         if (len && dir != OHCI_TD_DIR_IN) {
 479             ohci_copy_td(&td, buf, len, 0);
 480         }
 481     }
 482
 483     flag_r = (td.flags & OHCI_TD_R) != 0;
 484 #ifdef DEBUG_PACKET
 485     dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
 486             addr, len, str, flag_r, td.cbp, td.be);
 487
 488     if (len >= 0 && dir != OHCI_TD_DIR_IN) {
 489         dprintf("  data:");
 490         for (i = 0; i < len; i++)
 491             printf(" %.2x", buf[i]);
 492         dprintf("\n");
 493     }
 494 #endif
 495     ret = USB_RET_NODEV;
 496     for (i = 0; i < ohci->num_ports; i++) {
 497         dev = ohci->rhport[i].port.dev;
 498         if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
 499             continue;
 500
 501         ret = dev->handle_packet(dev, pid, OHCI_BM(ed->flags, ED_FA),
 502                                  OHCI_BM(ed->flags, ED_EN), buf, len);
 503         if (ret != USB_RET_NODEV)
 504             break;
 505     }
 506 #ifdef DEBUG_PACKET
 507     dprintf("ret=%d\n", ret);
 508 #endif
 509     if (ret >= 0) {
 510         if (dir == OHCI_TD_DIR_IN) {
 511             ohci_copy_td(&td, buf, ret, 1);
 512 #ifdef DEBUG_PACKET
 513             dprintf("  data:");
 514             for (i = 0; i < ret; i++)
 515                 printf(" %.2x", buf[i]);
 516             dprintf("\n");
 517 #endif
 518         } else {
 519             ret = len;
 520         }
 521     }
 522
 523     /* Writeback */
 524     if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
 525         /* Transmission succeeded.  */
 526         if (ret == len) {
 527             td.cbp = 0;
 528         } else {
 529             td.cbp += ret;
 530             if ((td.cbp & 0xfff) + ret > 0xfff) {
 531                 td.cbp &= 0xfff;
 532                 td.cbp |= td.be & ~0xfff;
 533             }
 534         }
 535         td.flags |= OHCI_TD_T1;
 536         td.flags ^= OHCI_TD_T0;
 537         OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
 538         OHCI_SET_BM(td.flags, TD_EC, 0);
 539
 540         ed->head &= ~OHCI_ED_C;
 541         if (td.flags & OHCI_TD_T0)
 542             ed->head |= OHCI_ED_C;
 543     } else {
 544         if (ret >= 0) {
 545             dprintf("usb-ohci: Underrun\n");
 546             OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
 547         } else {
 548             switch (ret) {
 549             case USB_RET_NODEV:
 550                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
 551             case USB_RET_NAK:
 552                 dprintf("usb-ohci: got NAK\n");
 553                 return 1;
 554             case USB_RET_STALL:
 555                 dprintf("usb-ohci: got STALL\n");
 556                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
 557                 break;
 558             case USB_RET_BABBLE:
 559                 dprintf("usb-ohci: got BABBLE\n");
 560                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
 561                 break;
 562             default:
 563                 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
 564                 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
 565                 OHCI_SET_BM(td.flags, TD_EC, 3);
 566                 break;
 567             }
 568         }
 569         ed->head |= OHCI_ED_H;
 570     }
 571
 572     /* Retire this TD */
 573     ed->head &= ~OHCI_DPTR_MASK;
 574     ed->head |= td.next & OHCI_DPTR_MASK;
 575     td.next = ohci->done;
 576     ohci->done = addr;
 577     i = OHCI_BM(td.flags, TD_DI);
 578     if (i < ohci->done_count)
 579         ohci->done_count = i;
 580     ohci_put_td(addr, &td);
 581     return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
 582 }
 583
 584 /* Service an endpoint list.  Returns nonzero if active TD were found.  */
 585 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
 586 {
 587     struct ohci_ed ed;
 588     uint32_t next_ed;
 589     uint32_t cur;
 590     int active;
 591
 592     active = 0;
 593
 594     if (head == 0)
 595         return 0;
 596
 597     for (cur = head; cur; cur = next_ed) {
 598         if (!ohci_read_ed(cur, &ed)) {
 599             fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
 600             return 0;
 601         }
 602
 603         next_ed = ed.next & OHCI_DPTR_MASK;
 604
 605         if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K))
 606             continue;
 607
 608         /* Skip isochronous endpoints.  */
 609         if (ed.flags & OHCI_ED_F)
 610           continue;
 611
 612         while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
 613 #ifdef DEBUG_PACKET
 614             dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
 615                     "h=%u c=%u\n  head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
 616                     OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
 617                     OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
 618                     (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
 619                     OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
 620                     (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
 621                     ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
 622 #endif
 623             active = 1;
 624
 625             if (ohci_service_td(ohci, &ed))
 626                 break;
 627         }
 628
 629         ohci_put_ed(cur, &ed);
 630     }
 631
 632     return active;
 633 }
 634
 635 /* Generate a SOF event, and set a timer for EOF */
 636 static void ohci_sof(OHCIState *ohci)
 637 {
 638     ohci->sof_time = qemu_get_clock(vm_clock);
 639     qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
 640     ohci_set_interrupt(ohci, OHCI_INTR_SF);
 641 }
 642
 643 /* Do frame processing on frame boundary */
 644 static void ohci_frame_boundary(void *opaque)
 645 {
 646     OHCIState *ohci = opaque;
 647     struct ohci_hcca hcca;
 648
 649     cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 0);
 650
 651     /* Process all the lists at the end of the frame */
 652     if (ohci->ctl & OHCI_CTL_PLE) {
 653         int n;
 654
 655         n = ohci->frame_number & 0x1f;
 656         ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]));
 657     }
 658     if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
 659         if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head)
 660           dprintf("usb-ohci: head %x, cur %x\n", ohci->ctrl_head, ohci->ctrl_cur);
 661         if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
 662             ohci->ctrl_cur = 0;
 663             ohci->status &= ~OHCI_STATUS_CLF;
 664         }
 665     }
 666
 667     if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
 668         if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
 669             ohci->bulk_cur = 0;
 670             ohci->status &= ~OHCI_STATUS_BLF;
 671         }
 672     }
 673
 674     /* Frame boundary, so do EOF stuf here */
 675     ohci->frt = ohci->fit;
 676
 677     /* XXX: endianness */
 678     ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
 679     hcca.frame = cpu_to_le32(ohci->frame_number);
 680
 681     if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
 682         if (!ohci->done)
 683             abort();
 684         if (ohci->intr & ohci->intr_status)
 685             ohci->done |= 1;
 686         hcca.done = cpu_to_le32(ohci->done);
 687         ohci->done = 0;
 688         ohci->done_count = 7;
 689         ohci_set_interrupt(ohci, OHCI_INTR_WD);
 690     }
 691
 692     if (ohci->done_count != 7 && ohci->done_count != 0)
 693         ohci->done_count--;
 694
 695     /* Do SOF stuff here */
 696     ohci_sof(ohci);
 697
 698     /* Writeback HCCA */
 699     cpu_physical_memory_rw(ohci->hcca, (uint8_t *)&hcca, sizeof(hcca), 1);
 700 }
 701
 702 /* Start sending SOF tokens across the USB bus, lists are processed in
 703  * next frame
 704  */
 705 static int ohci_bus_start(OHCIState *ohci)
 706 {
 707     ohci->eof_timer = qemu_new_timer(vm_clock,
 708                     ohci_frame_boundary,
 709                     ohci);
 710
 711     if (ohci->eof_timer == NULL) {
 712         fprintf(stderr, "usb-ohci: %s: qemu_new_timer failed\n",
 713             ohci->pci_dev.name);
 714         /* TODO: Signal unrecoverable error */
 715         return 0;
 716     }
 717
 718     dprintf("usb-ohci: %s: USB Operational\n", ohci->pci_dev.name);
 719
 720     ohci_sof(ohci);
 721
 722     return 1;
 723 }
 724
 725 /* Stop sending SOF tokens on the bus */
 726 static void ohci_bus_stop(OHCIState *ohci)
 727 {
 728     if (ohci->eof_timer)
 729         qemu_del_timer(ohci->eof_timer);
 730 }
 731
 732 /* Sets a flag in a port status register but only set it if the port is
 733  * connected, if not set ConnectStatusChange flag. If flag is enabled
 734  * return 1.
 735  */
 736 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
 737 {
 738     int ret = 1;
 739
 740     /* writing a 0 has no effect */
 741     if (val == 0)
 742         return 0;
 743
 744     /* If CurrentConnectStatus is cleared we set
 745      * ConnectStatusChange
 746      */
 747     if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
 748         ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
 749         if (ohci->rhstatus & OHCI_RHS_DRWE) {
 750             /* TODO: CSC is a wakeup event */
 751         }
 752         return 0;
 753     }
 754
 755     if (ohci->rhport[i].ctrl & val)
 756         ret = 0;
 757
 758     /* set the bit */
 759     ohci->rhport[i].ctrl |= val;
 760
 761     return ret;
 762 }
 763
 764 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
 765 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
 766 {
 767     val &= OHCI_FMI_FI;
 768
 769     if (val != ohci->fi) {
 770         dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
 771             ohci->pci_dev.name, ohci->fi, ohci->fi);
 772     }
 773
 774     ohci->fi = val;
 775 }
 776
 777 static void ohci_port_power(OHCIState *ohci, int i, int p)
 778 {
 779     if (p) {
 780         ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
 781     } else {
 782         ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
 783                     OHCI_PORT_CCS|
 784                     OHCI_PORT_PSS|
 785                     OHCI_PORT_PRS);
 786     }
 787 }
 788
 789 /* Set HcControlRegister */
 790 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
 791 {
 792     uint32_t old_state;
 793     uint32_t new_state;
 794
 795     old_state = ohci->ctl & OHCI_CTL_HCFS;
 796     ohci->ctl = val;
 797     new_state = ohci->ctl & OHCI_CTL_HCFS;
 798
 799     /* no state change */
 800     if (old_state == new_state)
 801         return;
 802
 803     switch (new_state) {
 804     case OHCI_USB_OPERATIONAL:
 805         ohci_bus_start(ohci);
 806         break;
 807     case OHCI_USB_SUSPEND:
 808         ohci_bus_stop(ohci);
 809         dprintf("usb-ohci: %s: USB Suspended\n", ohci->pci_dev.name);
 810         break;
 811     case OHCI_USB_RESUME:
 812         dprintf("usb-ohci: %s: USB Resume\n", ohci->pci_dev.name);
 813         break;
 814     case OHCI_USB_RESET:
 815         dprintf("usb-ohci: %s: USB Reset\n", ohci->pci_dev.name);
 816         break;
 817     }
 818 }
 819
 820 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
 821 {
 822     uint16_t fr;
 823     int64_t tks;
 824
 825     if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
 826         return (ohci->frt << 31);
 827
 828     /* Being in USB operational state guarnatees sof_time was
 829      * set already.
 830      */
 831     tks = qemu_get_clock(vm_clock) - ohci->sof_time;
 832
 833     /* avoid muldiv if possible */
 834     if (tks >= usb_frame_time)
 835         return (ohci->frt << 31);
 836
 837     tks = muldiv64(1, tks, usb_bit_time);
 838     fr = (uint16_t)(ohci->fi - tks);
 839
 840     return (ohci->frt << 31) | fr;
 841 }
 842
 843
 844 /* Set root hub status */
 845 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
 846 {
 847     uint32_t old_state;
 848
 849     old_state = ohci->rhstatus;
 850
 851     /* write 1 to clear OCIC */
 852     if (val & OHCI_RHS_OCIC)
 853         ohci->rhstatus &= ~OHCI_RHS_OCIC;
 854
 855     if (val & OHCI_RHS_LPS) {
 856         int i;
 857
 858         for (i = 0; i < ohci->num_ports; i++)
 859             ohci_port_power(ohci, i, 0);
 860         dprintf("usb-ohci: powered down all ports\n");
 861     }
 862
 863     if (val & OHCI_RHS_LPSC) {
 864         int i;
 865
 866         for (i = 0; i < ohci->num_ports; i++)
 867             ohci_port_power(ohci, i, 1);
 868         dprintf("usb-ohci: powered up all ports\n");
 869     }
 870
 871     if (val & OHCI_RHS_DRWE)
 872         ohci->rhstatus |= OHCI_RHS_DRWE;
 873
 874     if (val & OHCI_RHS_CRWE)
 875         ohci->rhstatus &= ~OHCI_RHS_DRWE;
 876
 877     if (old_state != ohci->rhstatus)
 878         ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
 879 }
 880
 881 /* Set root hub port status */
 882 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
 883 {
 884     uint32_t old_state;
 885     OHCIPort *port;
 886
 887     port = &ohci->rhport[portnum];
 888     old_state = port->ctrl;
 889
 890     /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
 891     if (val & OHCI_PORT_WTC)
 892         port->ctrl &= ~(val & OHCI_PORT_WTC);
 893
 894     if (val & OHCI_PORT_CCS)
 895         port->ctrl &= ~OHCI_PORT_PES;
 896
 897     ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
 898
 899     if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS))
 900         dprintf("usb-ohci: port %d: SUSPEND\n", portnum);
 901
 902     if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
 903         dprintf("usb-ohci: port %d: RESET\n", portnum);
 904         port->port.dev->handle_packet(port->port.dev, USB_MSG_RESET,
 905                                       0, 0, NULL, 0);
 906         port->ctrl &= ~OHCI_PORT_PRS;
 907         /* ??? Should this also set OHCI_PORT_PESC.  */
 908         port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
 909     }
 910
 911     /* Invert order here to ensure in ambiguous case, device is
 912      * powered up...
 913      */
 914     if (val & OHCI_PORT_LSDA)
 915         ohci_port_power(ohci, portnum, 0);
 916     if (val & OHCI_PORT_PPS)
 917         ohci_port_power(ohci, portnum, 1);
 918
 919     if (old_state != port->ctrl)
 920         ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
 921
 922     return;
 923 }
 924
 925 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
 926 {
 927     OHCIState *ohci = ptr;
 928
 929     addr -= ohci->mem_base;
 930
 931     /* Only aligned reads are allowed on OHCI */
 932     if (addr & 3) {
 933         fprintf(stderr, "usb-ohci: Mis-aligned read\n");
 934         return 0xffffffff;
 935     }
 936
 937     if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
 938         /* HcRhPortStatus */
 939         return ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
 940     }
 941
 942     switch (addr >> 2) {
 943     case 0: /* HcRevision */
 944         return 0x10;
 945
 946     case 1: /* HcControl */
 947         return ohci->ctl;
 948
 949     case 2: /* HcCommandStatus */
 950         return ohci->status;
 951
 952     case 3: /* HcInterruptStatus */
 953         return ohci->intr_status;
 954
 955     case 4: /* HcInterruptEnable */
 956     case 5: /* HcInterruptDisable */
 957         return ohci->intr;
 958
 959     case 6: /* HcHCCA */
 960         return ohci->hcca;
 961
 962     case 7: /* HcPeriodCurrentED */
 963         return ohci->per_cur;
 964
 965     case 8: /* HcControlHeadED */
 966         return ohci->ctrl_head;
 967
 968     case 9: /* HcControlCurrentED */
 969         return ohci->ctrl_cur;
 970
 971     case 10: /* HcBulkHeadED */
 972         return ohci->bulk_head;
 973
 974     case 11: /* HcBulkCurrentED */
 975         return ohci->bulk_cur;
 976
 977     case 12: /* HcDoneHead */
 978         return ohci->done;
 979
 980     case 13: /* HcFmInterval */
 981         return (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
 982
 983     case 14: /* HcFmRemaining */
 984         return ohci_get_frame_remaining(ohci);
 985
 986     case 15: /* HcFmNumber */
 987         return ohci->frame_number;
 988
 989     case 16: /* HcPeriodicStart */
 990         return ohci->pstart;
 991
 992     case 17: /* HcLSThreshold */
 993         return ohci->lst;
 994
 995     case 18: /* HcRhDescriptorA */
 996         return ohci->rhdesc_a;
 997
 998     case 19: /* HcRhDescriptorB */
 999         return ohci->rhdesc_b;
1000
1001     case 20: /* HcRhStatus */
1002         return ohci->rhstatus;
1003
1004     default:
1005         fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1006         return 0xffffffff;
1007     }
1008 }
1009
1010 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1011 {
1012     OHCIState *ohci = ptr;
1013
1014     addr -= ohci->mem_base;
1015
1016     /* Only aligned reads are allowed on OHCI */
1017     if (addr & 3) {
1018         fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1019         return;
1020     }
1021
1022     if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1023         /* HcRhPortStatus */
1024         ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1025         return;
1026     }
1027
1028     switch (addr >> 2) {
1029     case 1: /* HcControl */
1030         ohci_set_ctl(ohci, val);
1031         break;
1032
1033     case 2: /* HcCommandStatus */
1034         /* SOC is read-only */
1035         val = (val & ~OHCI_STATUS_SOC);
1036
1037         /* Bits written as '0' remain unchanged in the register */
1038         ohci->status |= val;
1039
1040         if (ohci->status & OHCI_STATUS_HCR)
1041             ohci_reset(ohci);
1042         break;
1043
1044     case 3: /* HcInterruptStatus */
1045         ohci->intr_status &= ~val;
1046         ohci_intr_update(ohci);
1047         break;
1048
1049     case 4: /* HcInterruptEnable */
1050         ohci->intr |= val;
1051         ohci_intr_update(ohci);
1052         break;
1053
1054     case 5: /* HcInterruptDisable */
1055         ohci->intr &= ~val;
1056         ohci_intr_update(ohci);
1057         break;
1058
1059     case 6: /* HcHCCA */
1060         ohci->hcca = val & OHCI_HCCA_MASK;
1061         break;
1062
1063     case 8: /* HcControlHeadED */
1064         ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1065         break;
1066
1067     case 9: /* HcControlCurrentED */
1068         ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1069         break;
1070
1071     case 10: /* HcBulkHeadED */
1072         ohci->bulk_head = val & OHCI_EDPTR_MASK;
1073         break;
1074
1075     case 11: /* HcBulkCurrentED */
1076         ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1077         break;
1078
1079     case 13: /* HcFmInterval */
1080         ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1081         ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1082         ohci_set_frame_interval(ohci, val);
1083         break;
1084
1085     case 16: /* HcPeriodicStart */
1086         ohci->pstart = val & 0xffff;
1087         break;
1088
1089     case 17: /* HcLSThreshold */
1090         ohci->lst = val & 0xffff;
1091         break;
1092
1093     case 18: /* HcRhDescriptorA */
1094         ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1095         ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1096         break;
1097
1098     case 19: /* HcRhDescriptorB */
1099         break;
1100
1101     case 20: /* HcRhStatus */
1102         ohci_set_hub_status(ohci, val);
1103         break;
1104
1105     default:
1106         fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1107         break;
1108     }
1109 }
1110
1111 /* Only dword reads are defined on OHCI register space */
1112 static CPUReadMemoryFunc *ohci_readfn[3]={
1113     ohci_mem_read,
1114     ohci_mem_read,
1115     ohci_mem_read
1116 };
1117
1118 /* Only dword writes are defined on OHCI register space */
1119 static CPUWriteMemoryFunc *ohci_writefn[3]={
1120     ohci_mem_write,
1121     ohci_mem_write,
1122     ohci_mem_write
1123 };
1124
1125 static void ohci_mapfunc(PCIDevice *pci_dev, int i,
1126             uint32_t addr, uint32_t size, int type)
1127 {
1128     OHCIState *ohci = (OHCIState *)pci_dev;
1129     ohci->mem_base = addr;
1130     cpu_register_physical_memory(addr, size, ohci->mem);
1131 }
1132
1133 void usb_ohci_init(struct PCIBus *bus, int num_ports, int devfn)
1134 {
1135     OHCIState *ohci;
1136     int vid = 0x106b;
1137     int did = 0x003f;
1138     int i;
1139
1140
1141     if (usb_frame_time == 0) {
1142 #if OHCI_TIME_WARP
1143         usb_frame_time = ticks_per_sec;
1144         usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ/1000);
1145 #else
1146         usb_frame_time = muldiv64(1, ticks_per_sec, 1000);
1147         if (ticks_per_sec >= USB_HZ) {
1148             usb_bit_time = muldiv64(1, ticks_per_sec, USB_HZ);
1149         } else {
1150             usb_bit_time = 1;
1151         }
1152 #endif
1153         dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1154                 usb_frame_time, usb_bit_time);
1155     }
1156
1157     ohci = (OHCIState *)pci_register_device(bus, "OHCI USB", sizeof(*ohci),
1158                                             devfn, NULL, NULL);
1159     if (ohci == NULL) {
1160         fprintf(stderr, "usb-ohci: Failed to register PCI device\n");
1161         return;
1162     }
1163
1164     ohci->pci_dev.config[0x00] = vid & 0xff;
1165     ohci->pci_dev.config[0x01] = (vid >> 8) & 0xff;
1166     ohci->pci_dev.config[0x02] = did & 0xff;
1167     ohci->pci_dev.config[0x03] = (did >> 8) & 0xff;
1168     ohci->pci_dev.config[0x09] = 0x10; /* OHCI */
1169     ohci->pci_dev.config[0x0a] = 0x3;
1170     ohci->pci_dev.config[0x0b] = 0xc;
1171     ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1172
1173     ohci->mem = cpu_register_io_memory(0, ohci_readfn, ohci_writefn, ohci);
1174
1175     pci_register_io_region((struct PCIDevice *)ohci, 0, 256,
1176                            PCI_ADDRESS_SPACE_MEM, ohci_mapfunc);
1177
1178     ohci->num_ports = num_ports;
1179     for (i = 0; i < num_ports; i++) {
1180         qemu_register_usb_port(&ohci->rhport[i].port, ohci, i, ohci_attach);
1181     }
1182
1183     ohci_reset(ohci);
1184 }