hw/vexpress.c

   1 /*
   2  * ARM Versatile Express emulation.
   3  *
   4  * Copyright (c) 2010 - 2011 B Labs Ltd.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Bahadir Balban, Amit Mahajan, Peter Maydell
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License version 2 as
  10  *  published by the Free Software Foundation.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  *  Contributions after 2012-01-13 are licensed under the terms of the
  21  *  GNU GPL, version 2 or (at your option) any later version.
  22  */
  23
  24 #include "sysbus.h"
  25 #include "arm-misc.h"
  26 #include "primecell.h"
  27 #include "devices.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "exec-memory.h"
  32
  33 #define SMP_BOOT_ADDR 0xe0000000
  34
  35 #define VEXPRESS_BOARD_ID 0x8e0
  36
  37 static struct arm_boot_info vexpress_binfo = {
  38     .smp_loader_start = SMP_BOOT_ADDR,
  39 };
  40
  41 static void vexpress_a9_init(ram_addr_t ram_size,
  42                      const char *boot_device,
  43                      const char *kernel_filename, const char *kernel_cmdline,
  44                      const char *initrd_filename, const char *cpu_model)
  45 {
  46     CPUState *env = NULL;
  47     MemoryRegion *sysmem = get_system_memory();
  48     MemoryRegion *ram = g_new(MemoryRegion, 1);
  49     MemoryRegion *lowram = g_new(MemoryRegion, 1);
  50     MemoryRegion *vram = g_new(MemoryRegion, 1);
  51     MemoryRegion *sram = g_new(MemoryRegion, 1);
  52     MemoryRegion *hackram = g_new(MemoryRegion, 1);
  53     DeviceState *dev, *sysctl, *pl041;
  54     SysBusDevice *busdev;
  55     qemu_irq *irqp;
  56     qemu_irq pic[64];
  57     int n;
  58     qemu_irq cpu_irq[4];
  59     uint32_t proc_id;
  60     uint32_t sys_id;
  61     ram_addr_t low_ram_size, vram_size, sram_size;
  62
  63     if (!cpu_model) {
  64         cpu_model = "cortex-a9";
  65     }
  66
  67     for (n = 0; n < smp_cpus; n++) {
  68         env = cpu_init(cpu_model);
  69         if (!env) {
  70             fprintf(stderr, "Unable to find CPU definition\n");
  71             exit(1);
  72         }
  73         irqp = arm_pic_init_cpu(env);
  74         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
  75     }
  76
  77     if (ram_size > 0x40000000) {
  78         /* 1GB is the maximum the address space permits */
  79         fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n");
  80         exit(1);
  81     }
  82
  83     memory_region_init_ram(ram, "vexpress.highmem", ram_size);
  84     vmstate_register_ram_global(ram);
  85     low_ram_size = ram_size;
  86     if (low_ram_size > 0x4000000) {
  87         low_ram_size = 0x4000000;
  88     }
  89     /* RAM is from 0x60000000 upwards. The bottom 64MB of the
  90      * address space should in theory be remappable to various
  91      * things including ROM or RAM; we always map the RAM there.
  92      */
  93     memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size);
  94     memory_region_add_subregion(sysmem, 0x0, lowram);
  95     memory_region_add_subregion(sysmem, 0x60000000, ram);
  96
  97     /* 0x1e000000 A9MPCore (SCU) private memory region */
  98     dev = qdev_create(NULL, "a9mpcore_priv");
  99     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 100     qdev_init_nofail(dev);
 101     busdev = sysbus_from_qdev(dev);
 102     vexpress_binfo.smp_priv_base = 0x1e000000;
 103     sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base);
 104     for (n = 0; n < smp_cpus; n++) {
 105         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 106     }
 107     /* Interrupts [42:0] are from the motherboard;
 108      * [47:43] are reserved; [63:48] are daughterboard
 109      * peripherals. Note that some documentation numbers
 110      * external interrupts starting from 32 (because the
 111      * A9MP has internal interrupts 0..31).
 112      */
 113     for (n = 0; n < 64; n++) {
 114         pic[n] = qdev_get_gpio_in(dev, n);
 115     }
 116
 117     /* Motherboard peripherals CS7 : 0x10000000 .. 0x10020000 */
 118     sys_id = 0x1190f500;
 119     proc_id = 0x0c000191;
 120
 121     /* 0x10000000 System registers */
 122     sysctl = qdev_create(NULL, "realview_sysctl");
 123     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 124     qdev_init_nofail(sysctl);
 125     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 126     sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
 127
 128     /* 0x10001000 SP810 system control */
 129     /* 0x10002000 serial bus PCI */
 130     /* 0x10004000 PL041 audio */
 131     pl041 = qdev_create(NULL, "pl041");
 132     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 133     qdev_init_nofail(pl041);
 134     sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
 135     sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]);
 136
 137     dev = sysbus_create_varargs("pl181", 0x10005000, pic[9], pic[10], NULL);
 138     /* Wire up MMC card detect and read-only signals */
 139     qdev_connect_gpio_out(dev, 0,
 140                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT));
 141     qdev_connect_gpio_out(dev, 1,
 142                           qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN));
 143
 144     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[12]);
 145     sysbus_create_simple("pl050_mouse", 0x10007000, pic[13]);
 146
 147     sysbus_create_simple("pl011", 0x10009000, pic[5]);
 148     sysbus_create_simple("pl011", 0x1000a000, pic[6]);
 149     sysbus_create_simple("pl011", 0x1000b000, pic[7]);
 150     sysbus_create_simple("pl011", 0x1000c000, pic[8]);
 151
 152     /* 0x1000f000 SP805 WDT */
 153
 154     sysbus_create_simple("sp804", 0x10011000, pic[2]);
 155     sysbus_create_simple("sp804", 0x10012000, pic[3]);
 156
 157     /* 0x10016000 Serial Bus DVI */
 158
 159     sysbus_create_simple("pl031", 0x10017000, pic[4]); /* RTC */
 160
 161     /* 0x1001a000 Compact Flash */
 162
 163     /* 0x1001f000 PL111 CLCD (motherboard) */
 164
 165     /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */
 166
 167     /* 0x10020000 PL111 CLCD (daughterboard) */
 168     sysbus_create_simple("pl111", 0x10020000, pic[44]);
 169
 170     /* 0x10060000 AXI RAM */
 171     /* 0x100e0000 PL341 Dynamic Memory Controller */
 172     /* 0x100e1000 PL354 Static Memory Controller */
 173     /* 0x100e2000 System Configuration Controller */
 174
 175     sysbus_create_simple("sp804", 0x100e4000, pic[48]);
 176     /* 0x100e5000 SP805 Watchdog module */
 177     /* 0x100e6000 BP147 TrustZone Protection Controller */
 178     /* 0x100e9000 PL301 'Fast' AXI matrix */
 179     /* 0x100ea000 PL301 'Slow' AXI matrix */
 180     /* 0x100ec000 TrustZone Address Space Controller */
 181     /* 0x10200000 CoreSight debug APB */
 182     /* 0x1e00a000 PL310 L2 Cache Controller */
 183
 184     /* CS0: NOR0 flash          : 0x40000000 .. 0x44000000 */
 185     /* CS4: NOR1 flash          : 0x44000000 .. 0x48000000 */
 186     /* CS2: SRAM                : 0x48000000 .. 0x4a000000 */
 187     sram_size = 0x2000000;
 188     memory_region_init_ram(sram, "vexpress.sram", sram_size);
 189     vmstate_register_ram_global(sram);
 190     memory_region_add_subregion(sysmem, 0x48000000, sram);
 191
 192     /* CS3: USB, ethernet, VRAM : 0x4c000000 .. 0x50000000 */
 193
 194     /* 0x4c000000 Video RAM */
 195     vram_size = 0x800000;
 196     memory_region_init_ram(vram, "vexpress.vram", vram_size);
 197     vmstate_register_ram_global(vram);
 198     memory_region_add_subregion(sysmem, 0x4c000000, vram);
 199
 200     /* 0x4e000000 LAN9118 Ethernet */
 201     if (nd_table[0].vlan) {
 202         lan9118_init(&nd_table[0], 0x4e000000, pic[15]);
 203     }
 204
 205     /* 0x4f000000 ISP1761 USB */
 206
 207     /* ??? Hack to map an additional page of ram for the secondary CPU
 208        startup code.  I guess this works on real hardware because the
 209        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 210        until after Linux boots the secondary CPUs.  */
 211     memory_region_init_ram(hackram, "vexpress.hack", 0x1000);
 212     vmstate_register_ram_global(hackram);
 213     memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, hackram);
 214
 215     vexpress_binfo.ram_size = ram_size;
 216     vexpress_binfo.kernel_filename = kernel_filename;
 217     vexpress_binfo.kernel_cmdline = kernel_cmdline;
 218     vexpress_binfo.initrd_filename = initrd_filename;
 219     vexpress_binfo.nb_cpus = smp_cpus;
 220     vexpress_binfo.board_id = VEXPRESS_BOARD_ID;
 221     vexpress_binfo.loader_start = 0x60000000;
 222     arm_load_kernel(first_cpu, &vexpress_binfo);
 223 }
 224
 225
 226 static QEMUMachine vexpress_a9_machine = {
 227     .name = "vexpress-a9",
 228     .desc = "ARM Versatile Express for Cortex-A9",
 229     .init = vexpress_a9_init,
 230     .use_scsi = 1,
 231     .max_cpus = 4,
 232 };
 233
 234 static void vexpress_machine_init(void)
 235 {
 236     qemu_register_machine(&vexpress_a9_machine);
 237 }
 238
 239 machine_init(vexpress_machine_init);