hw/vga-pci.c

   1 /*
   2  * QEMU PCI VGA Emulator.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pci.h"
  27 #include "vga_int.h"
  28 #include "pixel_ops.h"
  29 #include "qemu-timer.h"
  30 #include "loader.h"
  31
  32 #define PCI_VGA_IOPORT_OFFSET 0x400
  33 #define PCI_VGA_IOPORT_SIZE   (0x3e0 - 0x3c0)
  34 #define PCI_VGA_BOCHS_OFFSET  0x500
  35 #define PCI_VGA_BOCHS_SIZE    (0x0b * 2)
  36 #define PCI_VGA_MMIO_SIZE     0x1000
  37
  38 enum vga_pci_flags {
  39     PCI_VGA_FLAG_ENABLE_MMIO = 1,
  40 };
  41
  42 typedef struct PCIVGAState {
  43     PCIDevice dev;
  44     VGACommonState vga;
  45     uint32_t flags;
  46     MemoryRegion mmio;
  47     MemoryRegion ioport;
  48     MemoryRegion bochs;
  49 } PCIVGAState;
  50
  51 static const VMStateDescription vmstate_vga_pci = {
  52     .name = "vga",
  53     .version_id = 2,
  54     .minimum_version_id = 2,
  55     .minimum_version_id_old = 2,
  56     .fields      = (VMStateField []) {
  57         VMSTATE_PCI_DEVICE(dev, PCIVGAState),
  58         VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
  59         VMSTATE_END_OF_LIST()
  60     }
  61 };
  62
  63 static uint64_t pci_vga_ioport_read(void *ptr, target_phys_addr_t addr,
  64                                     unsigned size)
  65 {
  66     PCIVGAState *d = ptr;
  67     uint64_t ret = 0;
  68
  69     switch (size) {
  70     case 1:
  71         ret = vga_ioport_read(&d->vga, addr);
  72         break;
  73     case 2:
  74         ret  = vga_ioport_read(&d->vga, addr);
  75         ret |= vga_ioport_read(&d->vga, addr+1) << 8;
  76         break;
  77     }
  78     return ret;
  79 }
  80
  81 static void pci_vga_ioport_write(void *ptr, target_phys_addr_t addr,
  82                                  uint64_t val, unsigned size)
  83 {
  84     PCIVGAState *d = ptr;
  85     switch (size) {
  86     case 1:
  87         vga_ioport_write(&d->vga, addr, val);
  88         break;
  89     case 2:
  90         /*
  91          * Update bytes in little endian order.  Allows to update
  92          * indexed registers with a single word write because the
  93          * index byte is updated first.
  94          */
  95         vga_ioport_write(&d->vga, addr, val & 0xff);
  96         vga_ioport_write(&d->vga, addr+1, (val >> 8) & 0xff);
  97         break;
  98     }
  99 }
 100
 101 static const MemoryRegionOps pci_vga_ioport_ops = {
 102     .read = pci_vga_ioport_read,
 103     .write = pci_vga_ioport_write,
 104     .valid.min_access_size = 1,
 105     .valid.max_access_size = 4,
 106     .impl.min_access_size = 1,
 107     .impl.max_access_size = 2,
 108     .endianness = DEVICE_LITTLE_ENDIAN,
 109 };
 110
 111 static uint64_t pci_vga_bochs_read(void *ptr, target_phys_addr_t addr,
 112                                    unsigned size)
 113 {
 114     PCIVGAState *d = ptr;
 115     int index = addr >> 1;
 116
 117     vbe_ioport_write_index(&d->vga, 0, index);
 118     return vbe_ioport_read_data(&d->vga, 0);
 119 }
 120
 121 static void pci_vga_bochs_write(void *ptr, target_phys_addr_t addr,
 122                                 uint64_t val, unsigned size)
 123 {
 124     PCIVGAState *d = ptr;
 125     int index = addr >> 1;
 126
 127     vbe_ioport_write_index(&d->vga, 0, index);
 128     vbe_ioport_write_data(&d->vga, 0, val);
 129 }
 130
 131 static const MemoryRegionOps pci_vga_bochs_ops = {
 132     .read = pci_vga_bochs_read,
 133     .write = pci_vga_bochs_write,
 134     .valid.min_access_size = 1,
 135     .valid.max_access_size = 4,
 136     .impl.min_access_size = 2,
 137     .impl.max_access_size = 2,
 138     .endianness = DEVICE_LITTLE_ENDIAN,
 139 };
 140
 141 static int pci_std_vga_initfn(PCIDevice *dev)
 142 {
 143     PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
 144     VGACommonState *s = &d->vga;
 145
 146     /* vga + console init */
 147     vga_common_init(s);
 148     vga_init(s, pci_address_space(dev), pci_address_space_io(dev), true);
 149
 150     s->ds = graphic_console_init(s->update, s->invalidate,
 151                                  s->screen_dump, s->text_update, s);
 152
 153     /* XXX: VGA_RAM_SIZE must be a power of two */
 154     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 155
 156     /* mmio bar for vga register access */
 157     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
 158         memory_region_init(&d->mmio, "vga.mmio", 4096);
 159         memory_region_init_io(&d->ioport, &pci_vga_ioport_ops, d,
 160                               "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
 161         memory_region_init_io(&d->bochs, &pci_vga_bochs_ops, d,
 162                               "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
 163
 164         memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
 165                                     &d->ioport);
 166         memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
 167                                     &d->bochs);
 168         pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 169     }
 170
 171     if (!dev->rom_bar) {
 172         /* compatibility with pc-0.13 and older */
 173         vga_init_vbe(s, pci_address_space(dev));
 174     }
 175
 176     return 0;
 177 }
 178
 179 static Property vga_pci_properties[] = {
 180     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 181     DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
 182     DEFINE_PROP_END_OF_LIST(),
 183 };
 184
 185 static void vga_class_init(ObjectClass *klass, void *data)
 186 {
 187     DeviceClass *dc = DEVICE_CLASS(klass);
 188     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 189
 190     k->no_hotplug = 1;
 191     k->init = pci_std_vga_initfn;
 192     k->romfile = "vgabios-stdvga.bin";
 193     k->vendor_id = PCI_VENDOR_ID_QEMU;
 194     k->device_id = PCI_DEVICE_ID_QEMU_VGA;
 195     k->class_id = PCI_CLASS_DISPLAY_VGA;
 196     dc->vmsd = &vmstate_vga_pci;
 197     dc->props = vga_pci_properties;
 198 }
 199
 200 static TypeInfo vga_info = {
 201     .name          = "VGA",
 202     .parent        = TYPE_PCI_DEVICE,
 203     .instance_size = sizeof(PCIVGAState),
 204     .class_init    = vga_class_init,
 205 };
 206
 207 static void vga_register_types(void)
 208 {
 209     type_register_static(&vga_info);
 210 }
 211
 212 type_init(vga_register_types)