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vga: add some optional CGA compatibility hacks
[qemu.git] / hw / vga.c
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "vga.h"
26 #include "console.h"
27 #include "pc.h"
28 #include "pci.h"
29 #include "vga_int.h"
30 #include "pixel_ops.h"
31 #include "qemu-timer.h"
32 #include "xen.h"
33 #include "trace.h"
34
35 //#define DEBUG_VGA
36 //#define DEBUG_VGA_MEM
37 //#define DEBUG_VGA_REG
38
39 //#define DEBUG_BOCHS_VBE
40
41 /* 16 state changes per vertical frame @60 Hz */
42 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
43
44 /*
45 * Video Graphics Array (VGA)
46 *
47 * Chipset docs for original IBM VGA:
48 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
49 *
50 * FreeVGA site:
51 * http://www.osdever.net/FreeVGA/home.htm
52 *
53 * Standard VGA features and Bochs VBE extensions are implemented.
54 */
55
56 /* force some bits to zero */
57 const uint8_t sr_mask[8] = {
58 0x03,
59 0x3d,
60 0x0f,
61 0x3f,
62 0x0e,
63 0x00,
64 0x00,
65 0xff,
66 };
67
68 const uint8_t gr_mask[16] = {
69 0x0f, /* 0x00 */
70 0x0f, /* 0x01 */
71 0x0f, /* 0x02 */
72 0x1f, /* 0x03 */
73 0x03, /* 0x04 */
74 0x7b, /* 0x05 */
75 0x0f, /* 0x06 */
76 0x0f, /* 0x07 */
77 0xff, /* 0x08 */
78 0x00, /* 0x09 */
79 0x00, /* 0x0a */
80 0x00, /* 0x0b */
81 0x00, /* 0x0c */
82 0x00, /* 0x0d */
83 0x00, /* 0x0e */
84 0x00, /* 0x0f */
85 };
86
87 #define cbswap_32(__x) \
88 ((uint32_t)( \
89 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
90 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
91 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
92 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
93
94 #ifdef HOST_WORDS_BIGENDIAN
95 #define PAT(x) cbswap_32(x)
96 #else
97 #define PAT(x) (x)
98 #endif
99
100 #ifdef HOST_WORDS_BIGENDIAN
101 #define BIG 1
102 #else
103 #define BIG 0
104 #endif
105
106 #ifdef HOST_WORDS_BIGENDIAN
107 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
108 #else
109 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
110 #endif
111
112 static const uint32_t mask16[16] = {
113 PAT(0x00000000),
114 PAT(0x000000ff),
115 PAT(0x0000ff00),
116 PAT(0x0000ffff),
117 PAT(0x00ff0000),
118 PAT(0x00ff00ff),
119 PAT(0x00ffff00),
120 PAT(0x00ffffff),
121 PAT(0xff000000),
122 PAT(0xff0000ff),
123 PAT(0xff00ff00),
124 PAT(0xff00ffff),
125 PAT(0xffff0000),
126 PAT(0xffff00ff),
127 PAT(0xffffff00),
128 PAT(0xffffffff),
129 };
130
131 #undef PAT
132
133 #ifdef HOST_WORDS_BIGENDIAN
134 #define PAT(x) (x)
135 #else
136 #define PAT(x) cbswap_32(x)
137 #endif
138
139 static const uint32_t dmask16[16] = {
140 PAT(0x00000000),
141 PAT(0x000000ff),
142 PAT(0x0000ff00),
143 PAT(0x0000ffff),
144 PAT(0x00ff0000),
145 PAT(0x00ff00ff),
146 PAT(0x00ffff00),
147 PAT(0x00ffffff),
148 PAT(0xff000000),
149 PAT(0xff0000ff),
150 PAT(0xff00ff00),
151 PAT(0xff00ffff),
152 PAT(0xffff0000),
153 PAT(0xffff00ff),
154 PAT(0xffffff00),
155 PAT(0xffffffff),
156 };
157
158 static const uint32_t dmask4[4] = {
159 PAT(0x00000000),
160 PAT(0x0000ffff),
161 PAT(0xffff0000),
162 PAT(0xffffffff),
163 };
164
165 static uint32_t expand4[256];
166 static uint16_t expand2[256];
167 static uint8_t expand4to8[16];
168
169 static void vga_screen_dump(void *opaque, const char *filename, bool cswitch);
170
171 static void vga_update_memory_access(VGACommonState *s)
172 {
173 MemoryRegion *region, *old_region = s->chain4_alias;
174 target_phys_addr_t base, offset, size;
175
176 s->chain4_alias = NULL;
177
178 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
179 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
180 offset = 0;
181 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
182 case 0:
183 base = 0xa0000;
184 size = 0x20000;
185 break;
186 case 1:
187 base = 0xa0000;
188 size = 0x10000;
189 offset = s->bank_offset;
190 break;
191 case 2:
192 base = 0xb0000;
193 size = 0x8000;
194 break;
195 case 3:
196 default:
197 base = 0xb8000;
198 size = 0x8000;
199 break;
200 }
201 base += isa_mem_base;
202 region = g_malloc(sizeof(*region));
203 memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
204 memory_region_add_subregion_overlap(s->legacy_address_space, base,
205 region, 2);
206 s->chain4_alias = region;
207 }
208 if (old_region) {
209 memory_region_del_subregion(s->legacy_address_space, old_region);
210 memory_region_destroy(old_region);
211 g_free(old_region);
212 s->plane_updated = 0xf;
213 }
214 }
215
216 static void vga_dumb_update_retrace_info(VGACommonState *s)
217 {
218 (void) s;
219 }
220
221 static void vga_precise_update_retrace_info(VGACommonState *s)
222 {
223 int htotal_chars;
224 int hretr_start_char;
225 int hretr_skew_chars;
226 int hretr_end_char;
227
228 int vtotal_lines;
229 int vretr_start_line;
230 int vretr_end_line;
231
232 int dots;
233 #if 0
234 int div2, sldiv2;
235 #endif
236 int clocking_mode;
237 int clock_sel;
238 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
239 int64_t chars_per_sec;
240 struct vga_precise_retrace *r = &s->retrace_info.precise;
241
242 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
243 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
244 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
245 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
246
247 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
248 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
249 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
250 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
251 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
252 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
253 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
254
255 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
256 clock_sel = (s->msr >> 2) & 3;
257 dots = (s->msr & 1) ? 8 : 9;
258
259 chars_per_sec = clk_hz[clock_sel] / dots;
260
261 htotal_chars <<= clocking_mode;
262
263 r->total_chars = vtotal_lines * htotal_chars;
264 if (r->freq) {
265 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
266 } else {
267 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
268 }
269
270 r->vstart = vretr_start_line;
271 r->vend = r->vstart + vretr_end_line + 1;
272
273 r->hstart = hretr_start_char + hretr_skew_chars;
274 r->hend = r->hstart + hretr_end_char + 1;
275 r->htotal = htotal_chars;
276
277 #if 0
278 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
279 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
280 printf (
281 "hz=%f\n"
282 "htotal = %d\n"
283 "hretr_start = %d\n"
284 "hretr_skew = %d\n"
285 "hretr_end = %d\n"
286 "vtotal = %d\n"
287 "vretr_start = %d\n"
288 "vretr_end = %d\n"
289 "div2 = %d sldiv2 = %d\n"
290 "clocking_mode = %d\n"
291 "clock_sel = %d %d\n"
292 "dots = %d\n"
293 "ticks/char = %" PRId64 "\n"
294 "\n",
295 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
296 htotal_chars,
297 hretr_start_char,
298 hretr_skew_chars,
299 hretr_end_char,
300 vtotal_lines,
301 vretr_start_line,
302 vretr_end_line,
303 div2, sldiv2,
304 clocking_mode,
305 clock_sel,
306 clk_hz[clock_sel],
307 dots,
308 r->ticks_per_char
309 );
310 #endif
311 }
312
313 static uint8_t vga_precise_retrace(VGACommonState *s)
314 {
315 struct vga_precise_retrace *r = &s->retrace_info.precise;
316 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
317
318 if (r->total_chars) {
319 int cur_line, cur_line_char, cur_char;
320 int64_t cur_tick;
321
322 cur_tick = qemu_get_clock_ns(vm_clock);
323
324 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
325 cur_line = cur_char / r->htotal;
326
327 if (cur_line >= r->vstart && cur_line <= r->vend) {
328 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
329 } else {
330 cur_line_char = cur_char % r->htotal;
331 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
332 val |= ST01_DISP_ENABLE;
333 }
334 }
335
336 return val;
337 } else {
338 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
339 }
340 }
341
342 static uint8_t vga_dumb_retrace(VGACommonState *s)
343 {
344 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
345 }
346
347 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
348 {
349 if (s->msr & VGA_MIS_COLOR) {
350 /* Color */
351 return (addr >= 0x3b0 && addr <= 0x3bf);
352 } else {
353 /* Monochrome */
354 return (addr >= 0x3d0 && addr <= 0x3df);
355 }
356 }
357
358 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
359 {
360 VGACommonState *s = opaque;
361 int val, index;
362
363 if (vga_ioport_invalid(s, addr)) {
364 val = 0xff;
365 } else {
366 switch(addr) {
367 case VGA_ATT_W:
368 if (s->ar_flip_flop == 0) {
369 val = s->ar_index;
370 } else {
371 val = 0;
372 }
373 break;
374 case VGA_ATT_R:
375 index = s->ar_index & 0x1f;
376 if (index < VGA_ATT_C) {
377 val = s->ar[index];
378 } else {
379 val = 0;
380 }
381 break;
382 case VGA_MIS_W:
383 val = s->st00;
384 break;
385 case VGA_SEQ_I:
386 val = s->sr_index;
387 break;
388 case VGA_SEQ_D:
389 val = s->sr[s->sr_index];
390 #ifdef DEBUG_VGA_REG
391 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
392 #endif
393 break;
394 case VGA_PEL_IR:
395 val = s->dac_state;
396 break;
397 case VGA_PEL_IW:
398 val = s->dac_write_index;
399 break;
400 case VGA_PEL_D:
401 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
402 if (++s->dac_sub_index == 3) {
403 s->dac_sub_index = 0;
404 s->dac_read_index++;
405 }
406 break;
407 case VGA_FTC_R:
408 val = s->fcr;
409 break;
410 case VGA_MIS_R:
411 val = s->msr;
412 break;
413 case VGA_GFX_I:
414 val = s->gr_index;
415 break;
416 case VGA_GFX_D:
417 val = s->gr[s->gr_index];
418 #ifdef DEBUG_VGA_REG
419 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
420 #endif
421 break;
422 case VGA_CRT_IM:
423 case VGA_CRT_IC:
424 val = s->cr_index;
425 break;
426 case VGA_CRT_DM:
427 case VGA_CRT_DC:
428 val = s->cr[s->cr_index];
429 #ifdef DEBUG_VGA_REG
430 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
431 #endif
432 break;
433 case VGA_IS1_RM:
434 case VGA_IS1_RC:
435 /* just toggle to fool polling */
436 val = s->st01 = s->retrace(s);
437 s->ar_flip_flop = 0;
438 break;
439 default:
440 val = 0x00;
441 break;
442 }
443 }
444 #if defined(DEBUG_VGA)
445 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
446 #endif
447 return val;
448 }
449
450 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
451 {
452 VGACommonState *s = opaque;
453 int index;
454
455 /* check port range access depending on color/monochrome mode */
456 if (vga_ioport_invalid(s, addr)) {
457 return;
458 }
459 #ifdef DEBUG_VGA
460 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
461 #endif
462
463 switch(addr) {
464 case VGA_ATT_W:
465 if (s->ar_flip_flop == 0) {
466 val &= 0x3f;
467 s->ar_index = val;
468 } else {
469 index = s->ar_index & 0x1f;
470 switch(index) {
471 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
472 s->ar[index] = val & 0x3f;
473 break;
474 case VGA_ATC_MODE:
475 s->ar[index] = val & ~0x10;
476 break;
477 case VGA_ATC_OVERSCAN:
478 s->ar[index] = val;
479 break;
480 case VGA_ATC_PLANE_ENABLE:
481 s->ar[index] = val & ~0xc0;
482 break;
483 case VGA_ATC_PEL:
484 s->ar[index] = val & ~0xf0;
485 break;
486 case VGA_ATC_COLOR_PAGE:
487 s->ar[index] = val & ~0xf0;
488 break;
489 default:
490 break;
491 }
492 }
493 s->ar_flip_flop ^= 1;
494 break;
495 case VGA_MIS_W:
496 s->msr = val & ~0x10;
497 s->update_retrace_info(s);
498 break;
499 case VGA_SEQ_I:
500 s->sr_index = val & 7;
501 break;
502 case VGA_SEQ_D:
503 #ifdef DEBUG_VGA_REG
504 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
505 #endif
506 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
507 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
508 s->update_retrace_info(s);
509 }
510 vga_update_memory_access(s);
511 break;
512 case VGA_PEL_IR:
513 s->dac_read_index = val;
514 s->dac_sub_index = 0;
515 s->dac_state = 3;
516 break;
517 case VGA_PEL_IW:
518 s->dac_write_index = val;
519 s->dac_sub_index = 0;
520 s->dac_state = 0;
521 break;
522 case VGA_PEL_D:
523 s->dac_cache[s->dac_sub_index] = val;
524 if (++s->dac_sub_index == 3) {
525 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
526 s->dac_sub_index = 0;
527 s->dac_write_index++;
528 }
529 break;
530 case VGA_GFX_I:
531 s->gr_index = val & 0x0f;
532 break;
533 case VGA_GFX_D:
534 #ifdef DEBUG_VGA_REG
535 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
536 #endif
537 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
538 vga_update_memory_access(s);
539 break;
540 case VGA_CRT_IM:
541 case VGA_CRT_IC:
542 s->cr_index = val;
543 break;
544 case VGA_CRT_DM:
545 case VGA_CRT_DC:
546 #ifdef DEBUG_VGA_REG
547 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
548 #endif
549 /* handle CR0-7 protection */
550 if (s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) {
551 if (s->cr_index <= VGA_CRTC_OVERFLOW) {
552 /* can always write bit 4 of CR7 */
553 if (s->cr_index == VGA_CRTC_OVERFLOW) {
554 s->cr[VGA_CRTC_OVERFLOW] =
555 (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) | (val & 0x10);
556 }
557 return;
558 } else if ((vga_cga_hacks & VGA_CGA_HACK_FONT_HEIGHT) &&
559 !(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
560 /* extra CGA compatibility hacks (not in standard VGA) */
561 if (s->cr_index == VGA_CRTC_MAX_SCAN &&
562 val == 7 &&
563 (s->cr[VGA_CRTC_MAX_SCAN] & 0xf) == 0xf) {
564 return;
565 } else if (s->cr_index == VGA_CRTC_CURSOR_START &&
566 val == 6 &&
567 (s->cr[VGA_CRTC_MAX_SCAN] & 0xf) == 0xf) {
568 val = 0xd;
569 } else if (s->cr_index == VGA_CRTC_CURSOR_END &&
570 val == 7 &&
571 (s->cr[VGA_CRTC_MAX_SCAN] & 0xf) == 0xf) {
572 val = 0xe;
573 }
574 }
575 }
576 s->cr[s->cr_index] = val;
577
578 switch(s->cr_index) {
579 case VGA_CRTC_H_TOTAL:
580 case VGA_CRTC_H_SYNC_START:
581 case VGA_CRTC_H_SYNC_END:
582 case VGA_CRTC_V_TOTAL:
583 case VGA_CRTC_OVERFLOW:
584 case VGA_CRTC_V_SYNC_END:
585 case VGA_CRTC_MODE:
586 s->update_retrace_info(s);
587 break;
588 }
589 break;
590 case VGA_IS1_RM:
591 case VGA_IS1_RC:
592 s->fcr = val & 0x10;
593 break;
594 }
595 }
596
597 #ifdef CONFIG_BOCHS_VBE
598 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
599 {
600 VGACommonState *s = opaque;
601 uint32_t val;
602 val = s->vbe_index;
603 return val;
604 }
605
606 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
607 {
608 VGACommonState *s = opaque;
609 uint32_t val;
610
611 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
612 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
613 switch(s->vbe_index) {
614 /* XXX: do not hardcode ? */
615 case VBE_DISPI_INDEX_XRES:
616 val = VBE_DISPI_MAX_XRES;
617 break;
618 case VBE_DISPI_INDEX_YRES:
619 val = VBE_DISPI_MAX_YRES;
620 break;
621 case VBE_DISPI_INDEX_BPP:
622 val = VBE_DISPI_MAX_BPP;
623 break;
624 default:
625 val = s->vbe_regs[s->vbe_index];
626 break;
627 }
628 } else {
629 val = s->vbe_regs[s->vbe_index];
630 }
631 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
632 val = s->vram_size / (64 * 1024);
633 } else {
634 val = 0;
635 }
636 #ifdef DEBUG_BOCHS_VBE
637 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
638 #endif
639 return val;
640 }
641
642 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
643 {
644 VGACommonState *s = opaque;
645 s->vbe_index = val;
646 }
647
648 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
649 {
650 VGACommonState *s = opaque;
651
652 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
653 #ifdef DEBUG_BOCHS_VBE
654 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
655 #endif
656 switch(s->vbe_index) {
657 case VBE_DISPI_INDEX_ID:
658 if (val == VBE_DISPI_ID0 ||
659 val == VBE_DISPI_ID1 ||
660 val == VBE_DISPI_ID2 ||
661 val == VBE_DISPI_ID3 ||
662 val == VBE_DISPI_ID4) {
663 s->vbe_regs[s->vbe_index] = val;
664 }
665 break;
666 case VBE_DISPI_INDEX_XRES:
667 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
668 s->vbe_regs[s->vbe_index] = val;
669 }
670 break;
671 case VBE_DISPI_INDEX_YRES:
672 if (val <= VBE_DISPI_MAX_YRES) {
673 s->vbe_regs[s->vbe_index] = val;
674 }
675 break;
676 case VBE_DISPI_INDEX_BPP:
677 if (val == 0)
678 val = 8;
679 if (val == 4 || val == 8 || val == 15 ||
680 val == 16 || val == 24 || val == 32) {
681 s->vbe_regs[s->vbe_index] = val;
682 }
683 break;
684 case VBE_DISPI_INDEX_BANK:
685 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
686 val &= (s->vbe_bank_mask >> 2);
687 } else {
688 val &= s->vbe_bank_mask;
689 }
690 s->vbe_regs[s->vbe_index] = val;
691 s->bank_offset = (val << 16);
692 vga_update_memory_access(s);
693 break;
694 case VBE_DISPI_INDEX_ENABLE:
695 if ((val & VBE_DISPI_ENABLED) &&
696 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
697 int h, shift_control;
698
699 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
700 s->vbe_regs[VBE_DISPI_INDEX_XRES];
701 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
702 s->vbe_regs[VBE_DISPI_INDEX_YRES];
703 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
704 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
705
706 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
707 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
708 else
709 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
710 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
711 s->vbe_start_addr = 0;
712
713 /* clear the screen (should be done in BIOS) */
714 if (!(val & VBE_DISPI_NOCLEARMEM)) {
715 memset(s->vram_ptr, 0,
716 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
717 }
718
719 /* we initialize the VGA graphic mode (should be done
720 in BIOS) */
721 /* graphic mode + memory map 1 */
722 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
723 VGA_GR06_GRAPHICS_MODE;
724 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
725 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
726 /* width */
727 s->cr[VGA_CRTC_H_DISP] =
728 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
729 /* height (only meaningful if < 1024) */
730 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
731 s->cr[VGA_CRTC_V_DISP_END] = h;
732 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
733 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
734 /* line compare to 1023 */
735 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
736 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
737 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
738
739 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
740 shift_control = 0;
741 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
742 } else {
743 shift_control = 2;
744 /* set chain 4 mode */
745 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
746 /* activate all planes */
747 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
748 }
749 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
750 (shift_control << 5);
751 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
752 } else {
753 /* XXX: the bios should do that */
754 s->bank_offset = 0;
755 }
756 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
757 s->vbe_regs[s->vbe_index] = val;
758 vga_update_memory_access(s);
759 break;
760 case VBE_DISPI_INDEX_VIRT_WIDTH:
761 {
762 int w, h, line_offset;
763
764 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
765 return;
766 w = val;
767 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
768 line_offset = w >> 1;
769 else
770 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
771 h = s->vram_size / line_offset;
772 /* XXX: support weird bochs semantics ? */
773 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
774 return;
775 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
776 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
777 s->vbe_line_offset = line_offset;
778 }
779 break;
780 case VBE_DISPI_INDEX_X_OFFSET:
781 case VBE_DISPI_INDEX_Y_OFFSET:
782 {
783 int x;
784 s->vbe_regs[s->vbe_index] = val;
785 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
786 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
787 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
788 s->vbe_start_addr += x >> 1;
789 else
790 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
791 s->vbe_start_addr >>= 2;
792 }
793 break;
794 default:
795 break;
796 }
797 }
798 }
799 #endif
800
801 /* called for accesses between 0xa0000 and 0xc0000 */
802 uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
803 {
804 int memory_map_mode, plane;
805 uint32_t ret;
806
807 /* convert to VGA memory offset */
808 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
809 addr &= 0x1ffff;
810 switch(memory_map_mode) {
811 case 0:
812 break;
813 case 1:
814 if (addr >= 0x10000)
815 return 0xff;
816 addr += s->bank_offset;
817 break;
818 case 2:
819 addr -= 0x10000;
820 if (addr >= 0x8000)
821 return 0xff;
822 break;
823 default:
824 case 3:
825 addr -= 0x18000;
826 if (addr >= 0x8000)
827 return 0xff;
828 break;
829 }
830
831 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
832 /* chain 4 mode : simplest access */
833 ret = s->vram_ptr[addr];
834 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
835 /* odd/even mode (aka text mode mapping) */
836 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
837 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
838 } else {
839 /* standard VGA latched access */
840 s->latch = ((uint32_t *)s->vram_ptr)[addr];
841
842 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
843 /* read mode 0 */
844 plane = s->gr[VGA_GFX_PLANE_READ];
845 ret = GET_PLANE(s->latch, plane);
846 } else {
847 /* read mode 1 */
848 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
849 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
850 ret |= ret >> 16;
851 ret |= ret >> 8;
852 ret = (~ret) & 0xff;
853 }
854 }
855 return ret;
856 }
857
858 /* called for accesses between 0xa0000 and 0xc0000 */
859 void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
860 {
861 int memory_map_mode, plane, write_mode, b, func_select, mask;
862 uint32_t write_mask, bit_mask, set_mask;
863
864 #ifdef DEBUG_VGA_MEM
865 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
866 #endif
867 /* convert to VGA memory offset */
868 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
869 addr &= 0x1ffff;
870 switch(memory_map_mode) {
871 case 0:
872 break;
873 case 1:
874 if (addr >= 0x10000)
875 return;
876 addr += s->bank_offset;
877 break;
878 case 2:
879 addr -= 0x10000;
880 if (addr >= 0x8000)
881 return;
882 break;
883 default:
884 case 3:
885 addr -= 0x18000;
886 if (addr >= 0x8000)
887 return;
888 break;
889 }
890
891 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
892 /* chain 4 mode : simplest access */
893 plane = addr & 3;
894 mask = (1 << plane);
895 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
896 s->vram_ptr[addr] = val;
897 #ifdef DEBUG_VGA_MEM
898 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
899 #endif
900 s->plane_updated |= mask; /* only used to detect font change */
901 memory_region_set_dirty(&s->vram, addr, 1);
902 }
903 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
904 /* odd/even mode (aka text mode mapping) */
905 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
906 mask = (1 << plane);
907 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
908 addr = ((addr & ~1) << 1) | plane;
909 s->vram_ptr[addr] = val;
910 #ifdef DEBUG_VGA_MEM
911 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
912 #endif
913 s->plane_updated |= mask; /* only used to detect font change */
914 memory_region_set_dirty(&s->vram, addr, 1);
915 }
916 } else {
917 /* standard VGA latched access */
918 write_mode = s->gr[VGA_GFX_MODE] & 3;
919 switch(write_mode) {
920 default:
921 case 0:
922 /* rotate */
923 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
924 val = ((val >> b) | (val << (8 - b))) & 0xff;
925 val |= val << 8;
926 val |= val << 16;
927
928 /* apply set/reset mask */
929 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
930 val = (val & ~set_mask) |
931 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
932 bit_mask = s->gr[VGA_GFX_BIT_MASK];
933 break;
934 case 1:
935 val = s->latch;
936 goto do_write;
937 case 2:
938 val = mask16[val & 0x0f];
939 bit_mask = s->gr[VGA_GFX_BIT_MASK];
940 break;
941 case 3:
942 /* rotate */
943 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
944 val = (val >> b) | (val << (8 - b));
945
946 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
947 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
948 break;
949 }
950
951 /* apply logical operation */
952 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
953 switch(func_select) {
954 case 0:
955 default:
956 /* nothing to do */
957 break;
958 case 1:
959 /* and */
960 val &= s->latch;
961 break;
962 case 2:
963 /* or */
964 val |= s->latch;
965 break;
966 case 3:
967 /* xor */
968 val ^= s->latch;
969 break;
970 }
971
972 /* apply bit mask */
973 bit_mask |= bit_mask << 8;
974 bit_mask |= bit_mask << 16;
975 val = (val & bit_mask) | (s->latch & ~bit_mask);
976
977 do_write:
978 /* mask data according to sr[2] */
979 mask = s->sr[VGA_SEQ_PLANE_WRITE];
980 s->plane_updated |= mask; /* only used to detect font change */
981 write_mask = mask16[mask];
982 ((uint32_t *)s->vram_ptr)[addr] =
983 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
984 (val & write_mask);
985 #ifdef DEBUG_VGA_MEM
986 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
987 addr * 4, write_mask, val);
988 #endif
989 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
990 }
991 }
992
993 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
994 const uint8_t *font_ptr, int h,
995 uint32_t fgcol, uint32_t bgcol);
996 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
997 const uint8_t *font_ptr, int h,
998 uint32_t fgcol, uint32_t bgcol, int dup9);
999 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
1000 const uint8_t *s, int width);
1001
1002 #define DEPTH 8
1003 #include "vga_template.h"
1004
1005 #define DEPTH 15
1006 #include "vga_template.h"
1007
1008 #define BGR_FORMAT
1009 #define DEPTH 15
1010 #include "vga_template.h"
1011
1012 #define DEPTH 16
1013 #include "vga_template.h"
1014
1015 #define BGR_FORMAT
1016 #define DEPTH 16
1017 #include "vga_template.h"
1018
1019 #define DEPTH 32
1020 #include "vga_template.h"
1021
1022 #define BGR_FORMAT
1023 #define DEPTH 32
1024 #include "vga_template.h"
1025
1026 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1027 {
1028 unsigned int col;
1029 col = rgb_to_pixel8(r, g, b);
1030 col |= col << 8;
1031 col |= col << 16;
1032 return col;
1033 }
1034
1035 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1036 {
1037 unsigned int col;
1038 col = rgb_to_pixel15(r, g, b);
1039 col |= col << 16;
1040 return col;
1041 }
1042
1043 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1044 unsigned int b)
1045 {
1046 unsigned int col;
1047 col = rgb_to_pixel15bgr(r, g, b);
1048 col |= col << 16;
1049 return col;
1050 }
1051
1052 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1053 {
1054 unsigned int col;
1055 col = rgb_to_pixel16(r, g, b);
1056 col |= col << 16;
1057 return col;
1058 }
1059
1060 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1061 unsigned int b)
1062 {
1063 unsigned int col;
1064 col = rgb_to_pixel16bgr(r, g, b);
1065 col |= col << 16;
1066 return col;
1067 }
1068
1069 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1070 {
1071 unsigned int col;
1072 col = rgb_to_pixel32(r, g, b);
1073 return col;
1074 }
1075
1076 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1077 {
1078 unsigned int col;
1079 col = rgb_to_pixel32bgr(r, g, b);
1080 return col;
1081 }
1082
1083 /* return true if the palette was modified */
1084 static int update_palette16(VGACommonState *s)
1085 {
1086 int full_update, i;
1087 uint32_t v, col, *palette;
1088
1089 full_update = 0;
1090 palette = s->last_palette;
1091 for(i = 0; i < 16; i++) {
1092 v = s->ar[i];
1093 if (s->ar[VGA_ATC_MODE] & 0x80) {
1094 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1095 } else {
1096 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1097 }
1098 v = v * 3;
1099 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1100 c6_to_8(s->palette[v + 1]),
1101 c6_to_8(s->palette[v + 2]));
1102 if (col != palette[i]) {
1103 full_update = 1;
1104 palette[i] = col;
1105 }
1106 }
1107 return full_update;
1108 }
1109
1110 /* return true if the palette was modified */
1111 static int update_palette256(VGACommonState *s)
1112 {
1113 int full_update, i;
1114 uint32_t v, col, *palette;
1115
1116 full_update = 0;
1117 palette = s->last_palette;
1118 v = 0;
1119 for(i = 0; i < 256; i++) {
1120 if (s->dac_8bit) {
1121 col = s->rgb_to_pixel(s->palette[v],
1122 s->palette[v + 1],
1123 s->palette[v + 2]);
1124 } else {
1125 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1126 c6_to_8(s->palette[v + 1]),
1127 c6_to_8(s->palette[v + 2]));
1128 }
1129 if (col != palette[i]) {
1130 full_update = 1;
1131 palette[i] = col;
1132 }
1133 v += 3;
1134 }
1135 return full_update;
1136 }
1137
1138 static void vga_get_offsets(VGACommonState *s,
1139 uint32_t *pline_offset,
1140 uint32_t *pstart_addr,
1141 uint32_t *pline_compare)
1142 {
1143 uint32_t start_addr, line_offset, line_compare;
1144 #ifdef CONFIG_BOCHS_VBE
1145 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1146 line_offset = s->vbe_line_offset;
1147 start_addr = s->vbe_start_addr;
1148 line_compare = 65535;
1149 } else
1150 #endif
1151 {
1152 /* compute line_offset in bytes */
1153 line_offset = s->cr[VGA_CRTC_OFFSET];
1154 line_offset <<= 3;
1155
1156 /* starting address */
1157 start_addr = s->cr[VGA_CRTC_START_LO] |
1158 (s->cr[VGA_CRTC_START_HI] << 8);
1159
1160 /* line compare */
1161 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1162 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1163 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1164 }
1165 *pline_offset = line_offset;
1166 *pstart_addr = start_addr;
1167 *pline_compare = line_compare;
1168 }
1169
1170 /* update start_addr and line_offset. Return TRUE if modified */
1171 static int update_basic_params(VGACommonState *s)
1172 {
1173 int full_update;
1174 uint32_t start_addr, line_offset, line_compare;
1175
1176 full_update = 0;
1177
1178 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1179
1180 if (line_offset != s->line_offset ||
1181 start_addr != s->start_addr ||
1182 line_compare != s->line_compare) {
1183 s->line_offset = line_offset;
1184 s->start_addr = start_addr;
1185 s->line_compare = line_compare;
1186 full_update = 1;
1187 }
1188 return full_update;
1189 }
1190
1191 #define NB_DEPTHS 7
1192
1193 static inline int get_depth_index(DisplayState *s)
1194 {
1195 switch(ds_get_bits_per_pixel(s)) {
1196 default:
1197 case 8:
1198 return 0;
1199 case 15:
1200 return 1;
1201 case 16:
1202 return 2;
1203 case 32:
1204 if (is_surface_bgr(s->surface))
1205 return 4;
1206 else
1207 return 3;
1208 }
1209 }
1210
1211 static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
1212 vga_draw_glyph8_8,
1213 vga_draw_glyph8_16,
1214 vga_draw_glyph8_16,
1215 vga_draw_glyph8_32,
1216 vga_draw_glyph8_32,
1217 vga_draw_glyph8_16,
1218 vga_draw_glyph8_16,
1219 };
1220
1221 static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
1222 vga_draw_glyph16_8,
1223 vga_draw_glyph16_16,
1224 vga_draw_glyph16_16,
1225 vga_draw_glyph16_32,
1226 vga_draw_glyph16_32,
1227 vga_draw_glyph16_16,
1228 vga_draw_glyph16_16,
1229 };
1230
1231 static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
1232 vga_draw_glyph9_8,
1233 vga_draw_glyph9_16,
1234 vga_draw_glyph9_16,
1235 vga_draw_glyph9_32,
1236 vga_draw_glyph9_32,
1237 vga_draw_glyph9_16,
1238 vga_draw_glyph9_16,
1239 };
1240
1241 static const uint8_t cursor_glyph[32 * 4] = {
1242 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1243 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1244 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1245 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1246 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1247 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1248 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1249 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1250 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1251 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1252 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1253 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1254 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1255 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1256 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1257 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1258 };
1259
1260 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1261 int *pcwidth, int *pcheight)
1262 {
1263 int width, cwidth, height, cheight;
1264
1265 /* total width & height */
1266 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1267 cwidth = 8;
1268 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1269 cwidth = 9;
1270 }
1271 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1272 cwidth = 16; /* NOTE: no 18 pixel wide */
1273 }
1274 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1275 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1276 /* ugly hack for CGA 160x100x16 - explain me the logic */
1277 height = 100;
1278 } else {
1279 height = s->cr[VGA_CRTC_V_DISP_END] |
1280 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1281 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1282 height = (height + 1) / cheight;
1283 }
1284
1285 *pwidth = width;
1286 *pheight = height;
1287 *pcwidth = cwidth;
1288 *pcheight = cheight;
1289 }
1290
1291 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1292
1293 static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
1294 rgb_to_pixel8_dup,
1295 rgb_to_pixel15_dup,
1296 rgb_to_pixel16_dup,
1297 rgb_to_pixel32_dup,
1298 rgb_to_pixel32bgr_dup,
1299 rgb_to_pixel15bgr_dup,
1300 rgb_to_pixel16bgr_dup,
1301 };
1302
1303 /*
1304 * Text mode update
1305 * Missing:
1306 * - double scan
1307 * - double width
1308 * - underline
1309 * - flashing
1310 */
1311 static void vga_draw_text(VGACommonState *s, int full_update)
1312 {
1313 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1314 int cx_min, cx_max, linesize, x_incr, line, line1;
1315 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1316 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1317 const uint8_t *font_ptr, *font_base[2];
1318 int dup9, line_offset, depth_index;
1319 uint32_t *palette;
1320 uint32_t *ch_attr_ptr;
1321 vga_draw_glyph8_func *vga_draw_glyph8;
1322 vga_draw_glyph9_func *vga_draw_glyph9;
1323 int64_t now = qemu_get_clock_ms(vm_clock);
1324
1325 /* compute font data address (in plane 2) */
1326 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1327 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1328 if (offset != s->font_offsets[0]) {
1329 s->font_offsets[0] = offset;
1330 full_update = 1;
1331 }
1332 font_base[0] = s->vram_ptr + offset;
1333
1334 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1335 font_base[1] = s->vram_ptr + offset;
1336 if (offset != s->font_offsets[1]) {
1337 s->font_offsets[1] = offset;
1338 full_update = 1;
1339 }
1340 if (s->plane_updated & (1 << 2) || s->chain4_alias) {
1341 /* if the plane 2 was modified since the last display, it
1342 indicates the font may have been modified */
1343 s->plane_updated = 0;
1344 full_update = 1;
1345 }
1346 full_update |= update_basic_params(s);
1347
1348 line_offset = s->line_offset;
1349
1350 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1351 if ((height * width) <= 1) {
1352 /* better than nothing: exit if transient size is too small */
1353 return;
1354 }
1355 if ((height * width) > CH_ATTR_SIZE) {
1356 /* better than nothing: exit if transient size is too big */
1357 return;
1358 }
1359
1360 if (width != s->last_width || height != s->last_height ||
1361 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1362 s->last_scr_width = width * cw;
1363 s->last_scr_height = height * cheight;
1364 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1365 s->last_depth = 0;
1366 s->last_width = width;
1367 s->last_height = height;
1368 s->last_ch = cheight;
1369 s->last_cw = cw;
1370 full_update = 1;
1371 }
1372 s->rgb_to_pixel =
1373 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1374 full_update |= update_palette16(s);
1375 palette = s->last_palette;
1376 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1377
1378 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1379 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1380 if (cursor_offset != s->cursor_offset ||
1381 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1382 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1383 /* if the cursor position changed, we update the old and new
1384 chars */
1385 if (s->cursor_offset < CH_ATTR_SIZE)
1386 s->last_ch_attr[s->cursor_offset] = -1;
1387 if (cursor_offset < CH_ATTR_SIZE)
1388 s->last_ch_attr[cursor_offset] = -1;
1389 s->cursor_offset = cursor_offset;
1390 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1391 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1392 }
1393 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1394 if (now >= s->cursor_blink_time) {
1395 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1396 s->cursor_visible_phase = !s->cursor_visible_phase;
1397 }
1398
1399 depth_index = get_depth_index(s->ds);
1400 if (cw == 16)
1401 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1402 else
1403 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1404 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1405
1406 dest = ds_get_data(s->ds);
1407 linesize = ds_get_linesize(s->ds);
1408 ch_attr_ptr = s->last_ch_attr;
1409 line = 0;
1410 offset = s->start_addr * 4;
1411 for(cy = 0; cy < height; cy++) {
1412 d1 = dest;
1413 src = s->vram_ptr + offset;
1414 cx_min = width;
1415 cx_max = -1;
1416 for(cx = 0; cx < width; cx++) {
1417 ch_attr = *(uint16_t *)src;
1418 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
1419 if (cx < cx_min)
1420 cx_min = cx;
1421 if (cx > cx_max)
1422 cx_max = cx;
1423 *ch_attr_ptr = ch_attr;
1424 #ifdef HOST_WORDS_BIGENDIAN
1425 ch = ch_attr >> 8;
1426 cattr = ch_attr & 0xff;
1427 #else
1428 ch = ch_attr & 0xff;
1429 cattr = ch_attr >> 8;
1430 #endif
1431 font_ptr = font_base[(cattr >> 3) & 1];
1432 font_ptr += 32 * 4 * ch;
1433 bgcol = palette[cattr >> 4];
1434 fgcol = palette[cattr & 0x0f];
1435 if (cw != 9) {
1436 vga_draw_glyph8(d1, linesize,
1437 font_ptr, cheight, fgcol, bgcol);
1438 } else {
1439 dup9 = 0;
1440 if (ch >= 0xb0 && ch <= 0xdf &&
1441 (s->ar[VGA_ATC_MODE] & 0x04)) {
1442 dup9 = 1;
1443 }
1444 vga_draw_glyph9(d1, linesize,
1445 font_ptr, cheight, fgcol, bgcol, dup9);
1446 }
1447 if (src == cursor_ptr &&
1448 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1449 s->cursor_visible_phase) {
1450 int line_start, line_last, h;
1451 /* draw the cursor */
1452 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1453 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1454 /* XXX: check that */
1455 if (line_last > cheight - 1)
1456 line_last = cheight - 1;
1457 if (line_last >= line_start && line_start < cheight) {
1458 h = line_last - line_start + 1;
1459 d = d1 + linesize * line_start;
1460 if (cw != 9) {
1461 vga_draw_glyph8(d, linesize,
1462 cursor_glyph, h, fgcol, bgcol);
1463 } else {
1464 vga_draw_glyph9(d, linesize,
1465 cursor_glyph, h, fgcol, bgcol, 1);
1466 }
1467 }
1468 }
1469 }
1470 d1 += x_incr;
1471 src += 4;
1472 ch_attr_ptr++;
1473 }
1474 if (cx_max != -1) {
1475 dpy_update(s->ds, cx_min * cw, cy * cheight,
1476 (cx_max - cx_min + 1) * cw, cheight);
1477 }
1478 dest += linesize * cheight;
1479 line1 = line + cheight;
1480 offset += line_offset;
1481 if (line < s->line_compare && line1 >= s->line_compare) {
1482 offset = 0;
1483 }
1484 line = line1;
1485 }
1486 }
1487
1488 enum {
1489 VGA_DRAW_LINE2,
1490 VGA_DRAW_LINE2D2,
1491 VGA_DRAW_LINE4,
1492 VGA_DRAW_LINE4D2,
1493 VGA_DRAW_LINE8D2,
1494 VGA_DRAW_LINE8,
1495 VGA_DRAW_LINE15,
1496 VGA_DRAW_LINE16,
1497 VGA_DRAW_LINE24,
1498 VGA_DRAW_LINE32,
1499 VGA_DRAW_LINE_NB,
1500 };
1501
1502 static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1503 vga_draw_line2_8,
1504 vga_draw_line2_16,
1505 vga_draw_line2_16,
1506 vga_draw_line2_32,
1507 vga_draw_line2_32,
1508 vga_draw_line2_16,
1509 vga_draw_line2_16,
1510
1511 vga_draw_line2d2_8,
1512 vga_draw_line2d2_16,
1513 vga_draw_line2d2_16,
1514 vga_draw_line2d2_32,
1515 vga_draw_line2d2_32,
1516 vga_draw_line2d2_16,
1517 vga_draw_line2d2_16,
1518
1519 vga_draw_line4_8,
1520 vga_draw_line4_16,
1521 vga_draw_line4_16,
1522 vga_draw_line4_32,
1523 vga_draw_line4_32,
1524 vga_draw_line4_16,
1525 vga_draw_line4_16,
1526
1527 vga_draw_line4d2_8,
1528 vga_draw_line4d2_16,
1529 vga_draw_line4d2_16,
1530 vga_draw_line4d2_32,
1531 vga_draw_line4d2_32,
1532 vga_draw_line4d2_16,
1533 vga_draw_line4d2_16,
1534
1535 vga_draw_line8d2_8,
1536 vga_draw_line8d2_16,
1537 vga_draw_line8d2_16,
1538 vga_draw_line8d2_32,
1539 vga_draw_line8d2_32,
1540 vga_draw_line8d2_16,
1541 vga_draw_line8d2_16,
1542
1543 vga_draw_line8_8,
1544 vga_draw_line8_16,
1545 vga_draw_line8_16,
1546 vga_draw_line8_32,
1547 vga_draw_line8_32,
1548 vga_draw_line8_16,
1549 vga_draw_line8_16,
1550
1551 vga_draw_line15_8,
1552 vga_draw_line15_15,
1553 vga_draw_line15_16,
1554 vga_draw_line15_32,
1555 vga_draw_line15_32bgr,
1556 vga_draw_line15_15bgr,
1557 vga_draw_line15_16bgr,
1558
1559 vga_draw_line16_8,
1560 vga_draw_line16_15,
1561 vga_draw_line16_16,
1562 vga_draw_line16_32,
1563 vga_draw_line16_32bgr,
1564 vga_draw_line16_15bgr,
1565 vga_draw_line16_16bgr,
1566
1567 vga_draw_line24_8,
1568 vga_draw_line24_15,
1569 vga_draw_line24_16,
1570 vga_draw_line24_32,
1571 vga_draw_line24_32bgr,
1572 vga_draw_line24_15bgr,
1573 vga_draw_line24_16bgr,
1574
1575 vga_draw_line32_8,
1576 vga_draw_line32_15,
1577 vga_draw_line32_16,
1578 vga_draw_line32_32,
1579 vga_draw_line32_32bgr,
1580 vga_draw_line32_15bgr,
1581 vga_draw_line32_16bgr,
1582 };
1583
1584 static int vga_get_bpp(VGACommonState *s)
1585 {
1586 int ret;
1587 #ifdef CONFIG_BOCHS_VBE
1588 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1589 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1590 } else
1591 #endif
1592 {
1593 ret = 0;
1594 }
1595 return ret;
1596 }
1597
1598 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1599 {
1600 int width, height;
1601
1602 #ifdef CONFIG_BOCHS_VBE
1603 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1604 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1605 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1606 } else
1607 #endif
1608 {
1609 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1610 height = s->cr[VGA_CRTC_V_DISP_END] |
1611 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1612 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1613 height = (height + 1);
1614 }
1615 *pwidth = width;
1616 *pheight = height;
1617 }
1618
1619 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1620 {
1621 int y;
1622 if (y1 >= VGA_MAX_HEIGHT)
1623 return;
1624 if (y2 >= VGA_MAX_HEIGHT)
1625 y2 = VGA_MAX_HEIGHT;
1626 for(y = y1; y < y2; y++) {
1627 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1628 }
1629 }
1630
1631 static void vga_sync_dirty_bitmap(VGACommonState *s)
1632 {
1633 memory_region_sync_dirty_bitmap(&s->vram);
1634 }
1635
1636 void vga_dirty_log_start(VGACommonState *s)
1637 {
1638 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1639 }
1640
1641 void vga_dirty_log_stop(VGACommonState *s)
1642 {
1643 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1644 }
1645
1646 /*
1647 * graphic modes
1648 */
1649 static void vga_draw_graphic(VGACommonState *s, int full_update)
1650 {
1651 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1652 int width, height, shift_control, line_offset, bwidth, bits;
1653 ram_addr_t page0, page1, page_min, page_max;
1654 int disp_width, multi_scan, multi_run;
1655 uint8_t *d;
1656 uint32_t v, addr1, addr;
1657 vga_draw_line_func *vga_draw_line;
1658
1659 full_update |= update_basic_params(s);
1660
1661 if (!full_update)
1662 vga_sync_dirty_bitmap(s);
1663
1664 s->get_resolution(s, &width, &height);
1665 disp_width = width;
1666
1667 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1668 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1669 if (shift_control != 1) {
1670 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1671 - 1;
1672 } else {
1673 /* in CGA modes, multi_scan is ignored */
1674 /* XXX: is it correct ? */
1675 multi_scan = double_scan;
1676 }
1677 multi_run = multi_scan;
1678 if (shift_control != s->shift_control ||
1679 double_scan != s->double_scan) {
1680 full_update = 1;
1681 s->shift_control = shift_control;
1682 s->double_scan = double_scan;
1683 }
1684
1685 if (shift_control == 0) {
1686 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1687 disp_width <<= 1;
1688 }
1689 } else if (shift_control == 1) {
1690 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1691 disp_width <<= 1;
1692 }
1693 }
1694
1695 depth = s->get_bpp(s);
1696 if (s->line_offset != s->last_line_offset ||
1697 disp_width != s->last_width ||
1698 height != s->last_height ||
1699 s->last_depth != depth) {
1700 #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1701 if (depth == 16 || depth == 32) {
1702 #else
1703 if (depth == 32) {
1704 #endif
1705 qemu_free_displaysurface(s->ds);
1706 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1707 s->line_offset,
1708 s->vram_ptr + (s->start_addr * 4));
1709 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1710 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1711 #endif
1712 dpy_resize(s->ds);
1713 } else {
1714 qemu_console_resize(s->ds, disp_width, height);
1715 }
1716 s->last_scr_width = disp_width;
1717 s->last_scr_height = height;
1718 s->last_width = disp_width;
1719 s->last_height = height;
1720 s->last_line_offset = s->line_offset;
1721 s->last_depth = depth;
1722 full_update = 1;
1723 } else if (is_buffer_shared(s->ds->surface) &&
1724 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1725 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1726 dpy_setdata(s->ds);
1727 }
1728
1729 s->rgb_to_pixel =
1730 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1731
1732 if (shift_control == 0) {
1733 full_update |= update_palette16(s);
1734 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1735 v = VGA_DRAW_LINE4D2;
1736 } else {
1737 v = VGA_DRAW_LINE4;
1738 }
1739 bits = 4;
1740 } else if (shift_control == 1) {
1741 full_update |= update_palette16(s);
1742 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1743 v = VGA_DRAW_LINE2D2;
1744 } else {
1745 v = VGA_DRAW_LINE2;
1746 }
1747 bits = 4;
1748 } else {
1749 switch(s->get_bpp(s)) {
1750 default:
1751 case 0:
1752 full_update |= update_palette256(s);
1753 v = VGA_DRAW_LINE8D2;
1754 bits = 4;
1755 break;
1756 case 8:
1757 full_update |= update_palette256(s);
1758 v = VGA_DRAW_LINE8;
1759 bits = 8;
1760 break;
1761 case 15:
1762 v = VGA_DRAW_LINE15;
1763 bits = 16;
1764 break;
1765 case 16:
1766 v = VGA_DRAW_LINE16;
1767 bits = 16;
1768 break;
1769 case 24:
1770 v = VGA_DRAW_LINE24;
1771 bits = 24;
1772 break;
1773 case 32:
1774 v = VGA_DRAW_LINE32;
1775 bits = 32;
1776 break;
1777 }
1778 }
1779 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1780
1781 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1782 s->cursor_invalidate(s);
1783
1784 line_offset = s->line_offset;
1785 #if 0
1786 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1787 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1788 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
1789 #endif
1790 addr1 = (s->start_addr * 4);
1791 bwidth = (width * bits + 7) / 8;
1792 y_start = -1;
1793 page_min = -1;
1794 page_max = 0;
1795 d = ds_get_data(s->ds);
1796 linesize = ds_get_linesize(s->ds);
1797 y1 = 0;
1798 for(y = 0; y < height; y++) {
1799 addr = addr1;
1800 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1801 int shift;
1802 /* CGA compatibility handling */
1803 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1804 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1805 }
1806 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1807 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1808 }
1809 update = full_update;
1810 page0 = addr;
1811 page1 = addr + bwidth - 1;
1812 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1813 DIRTY_MEMORY_VGA);
1814 /* explicit invalidation for the hardware cursor */
1815 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1816 if (update) {
1817 if (y_start < 0)
1818 y_start = y;
1819 if (page0 < page_min)
1820 page_min = page0;
1821 if (page1 > page_max)
1822 page_max = page1;
1823 if (!(is_buffer_shared(s->ds->surface))) {
1824 vga_draw_line(s, d, s->vram_ptr + addr, width);
1825 if (s->cursor_draw_line)
1826 s->cursor_draw_line(s, d, y);
1827 }
1828 } else {
1829 if (y_start >= 0) {
1830 /* flush to display */
1831 dpy_update(s->ds, 0, y_start,
1832 disp_width, y - y_start);
1833 y_start = -1;
1834 }
1835 }
1836 if (!multi_run) {
1837 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1838 if ((y1 & mask) == mask)
1839 addr1 += line_offset;
1840 y1++;
1841 multi_run = multi_scan;
1842 } else {
1843 multi_run--;
1844 }
1845 /* line compare acts on the displayed lines */
1846 if (y == s->line_compare)
1847 addr1 = 0;
1848 d += linesize;
1849 }
1850 if (y_start >= 0) {
1851 /* flush to display */
1852 dpy_update(s->ds, 0, y_start,
1853 disp_width, y - y_start);
1854 }
1855 /* reset modified pages */
1856 if (page_max >= page_min) {
1857 memory_region_reset_dirty(&s->vram,
1858 page_min,
1859 page_max - page_min,
1860 DIRTY_MEMORY_VGA);
1861 }
1862 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1863 }
1864
1865 static void vga_draw_blank(VGACommonState *s, int full_update)
1866 {
1867 int i, w, val;
1868 uint8_t *d;
1869
1870 if (!full_update)
1871 return;
1872 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1873 return;
1874
1875 s->rgb_to_pixel =
1876 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1877 if (ds_get_bits_per_pixel(s->ds) == 8)
1878 val = s->rgb_to_pixel(0, 0, 0);
1879 else
1880 val = 0;
1881 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1882 d = ds_get_data(s->ds);
1883 for(i = 0; i < s->last_scr_height; i++) {
1884 memset(d, val, w);
1885 d += ds_get_linesize(s->ds);
1886 }
1887 dpy_update(s->ds, 0, 0,
1888 s->last_scr_width, s->last_scr_height);
1889 }
1890
1891 #define GMODE_TEXT 0
1892 #define GMODE_GRAPH 1
1893 #define GMODE_BLANK 2
1894
1895 static void vga_update_display(void *opaque)
1896 {
1897 VGACommonState *s = opaque;
1898 int full_update, graphic_mode;
1899
1900 qemu_flush_coalesced_mmio_buffer();
1901
1902 if (ds_get_bits_per_pixel(s->ds) == 0) {
1903 /* nothing to do */
1904 } else {
1905 full_update = 0;
1906 if (!(s->ar_index & 0x20) &&
1907 /* extra CGA compatibility hacks (not in standard VGA */
1908 (!(vga_cga_hacks & VGA_CGA_HACK_PALETTE_BLANKING) ||
1909 (s->ar_index != 0 && s->ar_flip_flop))) {
1910 graphic_mode = GMODE_BLANK;
1911 } else {
1912 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1913 }
1914 if (graphic_mode != s->graphic_mode) {
1915 s->graphic_mode = graphic_mode;
1916 s->cursor_blink_time = qemu_get_clock_ms(vm_clock);
1917 full_update = 1;
1918 }
1919 switch(graphic_mode) {
1920 case GMODE_TEXT:
1921 vga_draw_text(s, full_update);
1922 break;
1923 case GMODE_GRAPH:
1924 vga_draw_graphic(s, full_update);
1925 break;
1926 case GMODE_BLANK:
1927 default:
1928 vga_draw_blank(s, full_update);
1929 break;
1930 }
1931 }
1932 }
1933
1934 /* force a full display refresh */
1935 static void vga_invalidate_display(void *opaque)
1936 {
1937 VGACommonState *s = opaque;
1938
1939 s->last_width = -1;
1940 s->last_height = -1;
1941 }
1942
1943 void vga_common_reset(VGACommonState *s)
1944 {
1945 s->sr_index = 0;
1946 memset(s->sr, '\0', sizeof(s->sr));
1947 s->gr_index = 0;
1948 memset(s->gr, '\0', sizeof(s->gr));
1949 s->ar_index = 0;
1950 memset(s->ar, '\0', sizeof(s->ar));
1951 s->ar_flip_flop = 0;
1952 s->cr_index = 0;
1953 memset(s->cr, '\0', sizeof(s->cr));
1954 s->msr = 0;
1955 s->fcr = 0;
1956 s->st00 = 0;
1957 s->st01 = 0;
1958 s->dac_state = 0;
1959 s->dac_sub_index = 0;
1960 s->dac_read_index = 0;
1961 s->dac_write_index = 0;
1962 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1963 s->dac_8bit = 0;
1964 memset(s->palette, '\0', sizeof(s->palette));
1965 s->bank_offset = 0;
1966 #ifdef CONFIG_BOCHS_VBE
1967 s->vbe_index = 0;
1968 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1969 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1970 s->vbe_start_addr = 0;
1971 s->vbe_line_offset = 0;
1972 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1973 #endif
1974 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1975 s->graphic_mode = -1; /* force full update */
1976 s->shift_control = 0;
1977 s->double_scan = 0;
1978 s->line_offset = 0;
1979 s->line_compare = 0;
1980 s->start_addr = 0;
1981 s->plane_updated = 0;
1982 s->last_cw = 0;
1983 s->last_ch = 0;
1984 s->last_width = 0;
1985 s->last_height = 0;
1986 s->last_scr_width = 0;
1987 s->last_scr_height = 0;
1988 s->cursor_start = 0;
1989 s->cursor_end = 0;
1990 s->cursor_offset = 0;
1991 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1992 memset(s->last_palette, '\0', sizeof(s->last_palette));
1993 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1994 switch (vga_retrace_method) {
1995 case VGA_RETRACE_DUMB:
1996 break;
1997 case VGA_RETRACE_PRECISE:
1998 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1999 break;
2000 }
2001 vga_update_memory_access(s);
2002 }
2003
2004 static void vga_reset(void *opaque)
2005 {
2006 VGACommonState *s = opaque;
2007 vga_common_reset(s);
2008 }
2009
2010 #define TEXTMODE_X(x) ((x) % width)
2011 #define TEXTMODE_Y(x) ((x) / width)
2012 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
2013 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
2014 /* relay text rendering to the display driver
2015 * instead of doing a full vga_update_display() */
2016 static void vga_update_text(void *opaque, console_ch_t *chardata)
2017 {
2018 VGACommonState *s = opaque;
2019 int graphic_mode, i, cursor_offset, cursor_visible;
2020 int cw, cheight, width, height, size, c_min, c_max;
2021 uint32_t *src;
2022 console_ch_t *dst, val;
2023 char msg_buffer[80];
2024 int full_update = 0;
2025
2026 qemu_flush_coalesced_mmio_buffer();
2027
2028 if (!(s->ar_index & 0x20)) {
2029 graphic_mode = GMODE_BLANK;
2030 } else {
2031 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
2032 }
2033 if (graphic_mode != s->graphic_mode) {
2034 s->graphic_mode = graphic_mode;
2035 full_update = 1;
2036 }
2037 if (s->last_width == -1) {
2038 s->last_width = 0;
2039 full_update = 1;
2040 }
2041
2042 switch (graphic_mode) {
2043 case GMODE_TEXT:
2044 /* TODO: update palette */
2045 full_update |= update_basic_params(s);
2046
2047 /* total width & height */
2048 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
2049 cw = 8;
2050 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
2051 cw = 9;
2052 }
2053 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
2054 cw = 16; /* NOTE: no 18 pixel wide */
2055 }
2056 width = (s->cr[VGA_CRTC_H_DISP] + 1);
2057 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
2058 /* ugly hack for CGA 160x100x16 - explain me the logic */
2059 height = 100;
2060 } else {
2061 height = s->cr[VGA_CRTC_V_DISP_END] |
2062 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2063 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
2064 height = (height + 1) / cheight;
2065 }
2066
2067 size = (height * width);
2068 if (size > CH_ATTR_SIZE) {
2069 if (!full_update)
2070 return;
2071
2072 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2073 width, height);
2074 break;
2075 }
2076
2077 if (width != s->last_width || height != s->last_height ||
2078 cw != s->last_cw || cheight != s->last_ch) {
2079 s->last_scr_width = width * cw;
2080 s->last_scr_height = height * cheight;
2081 s->ds->surface->width = width;
2082 s->ds->surface->height = height;
2083 dpy_resize(s->ds);
2084 s->last_width = width;
2085 s->last_height = height;
2086 s->last_ch = cheight;
2087 s->last_cw = cw;
2088 full_update = 1;
2089 }
2090
2091 /* Update "hardware" cursor */
2092 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2093 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
2094 if (cursor_offset != s->cursor_offset ||
2095 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2096 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2097 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
2098 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2099 dpy_cursor(s->ds,
2100 TEXTMODE_X(cursor_offset),
2101 TEXTMODE_Y(cursor_offset));
2102 else
2103 dpy_cursor(s->ds, -1, -1);
2104 s->cursor_offset = cursor_offset;
2105 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2106 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
2107 }
2108
2109 src = (uint32_t *) s->vram_ptr + s->start_addr;
2110 dst = chardata;
2111
2112 if (full_update) {
2113 for (i = 0; i < size; src ++, dst ++, i ++)
2114 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
2115
2116 dpy_update(s->ds, 0, 0, width, height);
2117 } else {
2118 c_max = 0;
2119
2120 for (i = 0; i < size; src ++, dst ++, i ++) {
2121 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2122 if (*dst != val) {
2123 *dst = val;
2124 c_max = i;
2125 break;
2126 }
2127 }
2128 c_min = i;
2129 for (; i < size; src ++, dst ++, i ++) {
2130 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
2131 if (*dst != val) {
2132 *dst = val;
2133 c_max = i;
2134 }
2135 }
2136
2137 if (c_min <= c_max) {
2138 i = TEXTMODE_Y(c_min);
2139 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2140 }
2141 }
2142
2143 return;
2144 case GMODE_GRAPH:
2145 if (!full_update)
2146 return;
2147
2148 s->get_resolution(s, &width, &height);
2149 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2150 width, height);
2151 break;
2152 case GMODE_BLANK:
2153 default:
2154 if (!full_update)
2155 return;
2156
2157 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2158 break;
2159 }
2160
2161 /* Display a message */
2162 s->last_width = 60;
2163 s->last_height = height = 3;
2164 dpy_cursor(s->ds, -1, -1);
2165 s->ds->surface->width = s->last_width;
2166 s->ds->surface->height = height;
2167 dpy_resize(s->ds);
2168
2169 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2170 console_write_ch(dst ++, ' ');
2171
2172 size = strlen(msg_buffer);
2173 width = (s->last_width - size) / 2;
2174 dst = chardata + s->last_width + width;
2175 for (i = 0; i < size; i ++)
2176 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2177
2178 dpy_update(s->ds, 0, 0, s->last_width, height);
2179 }
2180
2181 static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
2182 unsigned size)
2183 {
2184 VGACommonState *s = opaque;
2185
2186 return vga_mem_readb(s, addr);
2187 }
2188
2189 static void vga_mem_write(void *opaque, target_phys_addr_t addr,
2190 uint64_t data, unsigned size)
2191 {
2192 VGACommonState *s = opaque;
2193
2194 return vga_mem_writeb(s, addr, data);
2195 }
2196
2197 const MemoryRegionOps vga_mem_ops = {
2198 .read = vga_mem_read,
2199 .write = vga_mem_write,
2200 .endianness = DEVICE_LITTLE_ENDIAN,
2201 .impl = {
2202 .min_access_size = 1,
2203 .max_access_size = 1,
2204 },
2205 };
2206
2207 static int vga_common_post_load(void *opaque, int version_id)
2208 {
2209 VGACommonState *s = opaque;
2210
2211 /* force refresh */
2212 s->graphic_mode = -1;
2213 return 0;
2214 }
2215
2216 const VMStateDescription vmstate_vga_common = {
2217 .name = "vga",
2218 .version_id = 2,
2219 .minimum_version_id = 2,
2220 .minimum_version_id_old = 2,
2221 .post_load = vga_common_post_load,
2222 .fields = (VMStateField []) {
2223 VMSTATE_UINT32(latch, VGACommonState),
2224 VMSTATE_UINT8(sr_index, VGACommonState),
2225 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2226 VMSTATE_UINT8(gr_index, VGACommonState),
2227 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2228 VMSTATE_UINT8(ar_index, VGACommonState),
2229 VMSTATE_BUFFER(ar, VGACommonState),
2230 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2231 VMSTATE_UINT8(cr_index, VGACommonState),
2232 VMSTATE_BUFFER(cr, VGACommonState),
2233 VMSTATE_UINT8(msr, VGACommonState),
2234 VMSTATE_UINT8(fcr, VGACommonState),
2235 VMSTATE_UINT8(st00, VGACommonState),
2236 VMSTATE_UINT8(st01, VGACommonState),
2237
2238 VMSTATE_UINT8(dac_state, VGACommonState),
2239 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2240 VMSTATE_UINT8(dac_read_index, VGACommonState),
2241 VMSTATE_UINT8(dac_write_index, VGACommonState),
2242 VMSTATE_BUFFER(dac_cache, VGACommonState),
2243 VMSTATE_BUFFER(palette, VGACommonState),
2244
2245 VMSTATE_INT32(bank_offset, VGACommonState),
2246 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2247 #ifdef CONFIG_BOCHS_VBE
2248 VMSTATE_UINT16(vbe_index, VGACommonState),
2249 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2250 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2251 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2252 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2253 #endif
2254 VMSTATE_END_OF_LIST()
2255 }
2256 };
2257
2258 void vga_common_init(VGACommonState *s)
2259 {
2260 int i, j, v, b;
2261
2262 for(i = 0;i < 256; i++) {
2263 v = 0;
2264 for(j = 0; j < 8; j++) {
2265 v |= ((i >> j) & 1) << (j * 4);
2266 }
2267 expand4[i] = v;
2268
2269 v = 0;
2270 for(j = 0; j < 4; j++) {
2271 v |= ((i >> (2 * j)) & 3) << (j * 4);
2272 }
2273 expand2[i] = v;
2274 }
2275 for(i = 0; i < 16; i++) {
2276 v = 0;
2277 for(j = 0; j < 4; j++) {
2278 b = ((i >> j) & 1);
2279 v |= b << (2 * j);
2280 v |= b << (2 * j + 1);
2281 }
2282 expand4to8[i] = v;
2283 }
2284
2285 /* valid range: 1 MB -> 256 MB */
2286 s->vram_size = 1024 * 1024;
2287 while (s->vram_size < (s->vram_size_mb << 20) &&
2288 s->vram_size < (256 << 20)) {
2289 s->vram_size <<= 1;
2290 }
2291 s->vram_size_mb = s->vram_size >> 20;
2292
2293 #ifdef CONFIG_BOCHS_VBE
2294 s->is_vbe_vmstate = 1;
2295 #else
2296 s->is_vbe_vmstate = 0;
2297 #endif
2298 memory_region_init_ram(&s->vram, "vga.vram", s->vram_size);
2299 vmstate_register_ram_global(&s->vram);
2300 xen_register_framebuffer(&s->vram);
2301 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2302 s->get_bpp = vga_get_bpp;
2303 s->get_offsets = vga_get_offsets;
2304 s->get_resolution = vga_get_resolution;
2305 s->update = vga_update_display;
2306 s->invalidate = vga_invalidate_display;
2307 s->screen_dump = vga_screen_dump;
2308 s->text_update = vga_update_text;
2309 switch (vga_retrace_method) {
2310 case VGA_RETRACE_DUMB:
2311 s->retrace = vga_dumb_retrace;
2312 s->update_retrace_info = vga_dumb_update_retrace_info;
2313 break;
2314
2315 case VGA_RETRACE_PRECISE:
2316 s->retrace = vga_precise_retrace;
2317 s->update_retrace_info = vga_precise_update_retrace_info;
2318 break;
2319 }
2320 vga_dirty_log_start(s);
2321 }
2322
2323 static const MemoryRegionPortio vga_portio_list[] = {
2324 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2325 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2326 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2327 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2328 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2329 PORTIO_END_OF_LIST(),
2330 };
2331
2332 #ifdef CONFIG_BOCHS_VBE
2333 static const MemoryRegionPortio vbe_portio_list[] = {
2334 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2335 # ifdef TARGET_I386
2336 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2337 # else
2338 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2339 # endif
2340 PORTIO_END_OF_LIST(),
2341 };
2342 #endif /* CONFIG_BOCHS_VBE */
2343
2344 /* Used by both ISA and PCI */
2345 MemoryRegion *vga_init_io(VGACommonState *s,
2346 const MemoryRegionPortio **vga_ports,
2347 const MemoryRegionPortio **vbe_ports)
2348 {
2349 MemoryRegion *vga_mem;
2350
2351 *vga_ports = vga_portio_list;
2352 *vbe_ports = NULL;
2353 #ifdef CONFIG_BOCHS_VBE
2354 *vbe_ports = vbe_portio_list;
2355 #endif
2356
2357 vga_mem = g_malloc(sizeof(*vga_mem));
2358 memory_region_init_io(vga_mem, &vga_mem_ops, s,
2359 "vga-lowmem", 0x20000);
2360
2361 return vga_mem;
2362 }
2363
2364 void vga_init(VGACommonState *s, MemoryRegion *address_space,
2365 MemoryRegion *address_space_io, bool init_vga_ports)
2366 {
2367 MemoryRegion *vga_io_memory;
2368 const MemoryRegionPortio *vga_ports, *vbe_ports;
2369 PortioList *vga_port_list = g_new(PortioList, 1);
2370 PortioList *vbe_port_list = g_new(PortioList, 1);
2371
2372 qemu_register_reset(vga_reset, s);
2373
2374 s->bank_offset = 0;
2375
2376 s->legacy_address_space = address_space;
2377
2378 vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
2379 memory_region_add_subregion_overlap(address_space,
2380 isa_mem_base + 0x000a0000,
2381 vga_io_memory,
2382 1);
2383 memory_region_set_coalescing(vga_io_memory);
2384 if (init_vga_ports) {
2385 portio_list_init(vga_port_list, vga_ports, s, "vga");
2386 portio_list_add(vga_port_list, address_space_io, 0x3b0);
2387 }
2388 if (vbe_ports) {
2389 portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2390 portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2391 }
2392 }
2393
2394 void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
2395 {
2396 #ifdef CONFIG_BOCHS_VBE
2397 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2398 * so use an alias to avoid double-mapping the same region.
2399 */
2400 memory_region_init_alias(&s->vram_vbe, "vram.vbe",
2401 &s->vram, 0, memory_region_size(&s->vram));
2402 /* XXX: use optimized standard vga accesses */
2403 memory_region_add_subregion(system_memory,
2404 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2405 &s->vram_vbe);
2406 s->vbe_mapped = 1;
2407 #endif
2408 }
2409 /********************************************************/
2410 /* vga screen dump */
2411
2412 int ppm_save(const char *filename, struct DisplaySurface *ds)
2413 {
2414 FILE *f;
2415 uint8_t *d, *d1;
2416 uint32_t v;
2417 int y, x;
2418 uint8_t r, g, b;
2419 int ret;
2420 char *linebuf, *pbuf;
2421
2422 trace_ppm_save(filename, ds);
2423 f = fopen(filename, "wb");
2424 if (!f)
2425 return -1;
2426 fprintf(f, "P6\n%d %d\n%d\n",
2427 ds->width, ds->height, 255);
2428 linebuf = g_malloc(ds->width * 3);
2429 d1 = ds->data;
2430 for(y = 0; y < ds->height; y++) {
2431 d = d1;
2432 pbuf = linebuf;
2433 for(x = 0; x < ds->width; x++) {
2434 if (ds->pf.bits_per_pixel == 32)
2435 v = *(uint32_t *)d;
2436 else
2437 v = (uint32_t) (*(uint16_t *)d);
2438 /* Limited to 8 or fewer bits per channel: */
2439 r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits);
2440 g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits);
2441 b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits);
2442 *pbuf++ = r;
2443 *pbuf++ = g;
2444 *pbuf++ = b;
2445 d += ds->pf.bytes_per_pixel;
2446 }
2447 d1 += ds->linesize;
2448 ret = fwrite(linebuf, 1, pbuf - linebuf, f);
2449 (void)ret;
2450 }
2451 g_free(linebuf);
2452 fclose(f);
2453 return 0;
2454 }
2455
2456 /* save the vga display in a PPM image even if no display is
2457 available */
2458 static void vga_screen_dump(void *opaque, const char *filename, bool cswitch)
2459 {
2460 VGACommonState *s = opaque;
2461
2462 if (cswitch) {
2463 vga_invalidate_display(s);
2464 }
2465 vga_hw_update();
2466 ppm_save(filename, s->ds->surface);
2467 }
Qemu copy for testing