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console: move set_mouse + cursor_define callbacks
[qemu.git] / hw / vmware_vga.c
1 /*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "loader.h"
26 #include "console.h"
27 #include "pci.h"
28
29 #undef VERBOSE
30 #define HW_RECT_ACCEL
31 #define HW_FILL_ACCEL
32 #define HW_MOUSE_ACCEL
33
34 # include "vga_int.h"
35
36 struct vmsvga_state_s {
37 VGACommonState vga;
38
39 int width;
40 int height;
41 int invalidated;
42 int depth;
43 int bypp;
44 int enable;
45 int config;
46 struct {
47 int id;
48 int x;
49 int y;
50 int on;
51 } cursor;
52
53 int index;
54 int scratch_size;
55 uint32_t *scratch;
56 int new_width;
57 int new_height;
58 uint32_t guest;
59 uint32_t svgaid;
60 uint32_t wred;
61 uint32_t wgreen;
62 uint32_t wblue;
63 int syncing;
64 int fb_size;
65
66 MemoryRegion fifo_ram;
67 uint8_t *fifo_ptr;
68 unsigned int fifo_size;
69
70 union {
71 uint32_t *fifo;
72 struct QEMU_PACKED {
73 uint32_t min;
74 uint32_t max;
75 uint32_t next_cmd;
76 uint32_t stop;
77 /* Add registers here when adding capabilities. */
78 uint32_t fifo[0];
79 } *cmd;
80 };
81
82 #define REDRAW_FIFO_LEN 512
83 struct vmsvga_rect_s {
84 int x, y, w, h;
85 } redraw_fifo[REDRAW_FIFO_LEN];
86 int redraw_fifo_first, redraw_fifo_last;
87 };
88
89 struct pci_vmsvga_state_s {
90 PCIDevice card;
91 struct vmsvga_state_s chip;
92 MemoryRegion io_bar;
93 };
94
95 #define SVGA_MAGIC 0x900000UL
96 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
97 #define SVGA_ID_0 SVGA_MAKE_ID(0)
98 #define SVGA_ID_1 SVGA_MAKE_ID(1)
99 #define SVGA_ID_2 SVGA_MAKE_ID(2)
100
101 #define SVGA_LEGACY_BASE_PORT 0x4560
102 #define SVGA_INDEX_PORT 0x0
103 #define SVGA_VALUE_PORT 0x1
104 #define SVGA_BIOS_PORT 0x2
105
106 #define SVGA_VERSION_2
107
108 #ifdef SVGA_VERSION_2
109 # define SVGA_ID SVGA_ID_2
110 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
111 # define SVGA_IO_MUL 1
112 # define SVGA_FIFO_SIZE 0x10000
113 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
114 #else
115 # define SVGA_ID SVGA_ID_1
116 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
117 # define SVGA_IO_MUL 4
118 # define SVGA_FIFO_SIZE 0x10000
119 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
120 #endif
121
122 enum {
123 /* ID 0, 1 and 2 registers */
124 SVGA_REG_ID = 0,
125 SVGA_REG_ENABLE = 1,
126 SVGA_REG_WIDTH = 2,
127 SVGA_REG_HEIGHT = 3,
128 SVGA_REG_MAX_WIDTH = 4,
129 SVGA_REG_MAX_HEIGHT = 5,
130 SVGA_REG_DEPTH = 6,
131 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
132 SVGA_REG_PSEUDOCOLOR = 8,
133 SVGA_REG_RED_MASK = 9,
134 SVGA_REG_GREEN_MASK = 10,
135 SVGA_REG_BLUE_MASK = 11,
136 SVGA_REG_BYTES_PER_LINE = 12,
137 SVGA_REG_FB_START = 13,
138 SVGA_REG_FB_OFFSET = 14,
139 SVGA_REG_VRAM_SIZE = 15,
140 SVGA_REG_FB_SIZE = 16,
141
142 /* ID 1 and 2 registers */
143 SVGA_REG_CAPABILITIES = 17,
144 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
145 SVGA_REG_MEM_SIZE = 19,
146 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
147 SVGA_REG_SYNC = 21, /* Write to force synchronization */
148 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
149 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
150 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
151 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
152 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
153 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
154 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
155 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
156 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
157 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
158 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
159
160 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
161 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
162 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
163 };
164
165 #define SVGA_CAP_NONE 0
166 #define SVGA_CAP_RECT_FILL (1 << 0)
167 #define SVGA_CAP_RECT_COPY (1 << 1)
168 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
169 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
170 #define SVGA_CAP_RASTER_OP (1 << 4)
171 #define SVGA_CAP_CURSOR (1 << 5)
172 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
173 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
174 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
175 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
176 #define SVGA_CAP_GLYPH (1 << 10)
177 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
178 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
179 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
180 #define SVGA_CAP_3D (1 << 14)
181 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
182 #define SVGA_CAP_MULTIMON (1 << 16)
183 #define SVGA_CAP_PITCHLOCK (1 << 17)
184
185 /*
186 * FIFO offsets (seen as an array of 32-bit words)
187 */
188 enum {
189 /*
190 * The original defined FIFO offsets
191 */
192 SVGA_FIFO_MIN = 0,
193 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
194 SVGA_FIFO_NEXT_CMD,
195 SVGA_FIFO_STOP,
196
197 /*
198 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
199 */
200 SVGA_FIFO_CAPABILITIES = 4,
201 SVGA_FIFO_FLAGS,
202 SVGA_FIFO_FENCE,
203 SVGA_FIFO_3D_HWVERSION,
204 SVGA_FIFO_PITCHLOCK,
205 };
206
207 #define SVGA_FIFO_CAP_NONE 0
208 #define SVGA_FIFO_CAP_FENCE (1 << 0)
209 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
210 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
211
212 #define SVGA_FIFO_FLAG_NONE 0
213 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
214
215 /* These values can probably be changed arbitrarily. */
216 #define SVGA_SCRATCH_SIZE 0x8000
217 #define SVGA_MAX_WIDTH 2360
218 #define SVGA_MAX_HEIGHT 1770
219
220 #ifdef VERBOSE
221 # define GUEST_OS_BASE 0x5001
222 static const char *vmsvga_guest_id[] = {
223 [0x00] = "Dos",
224 [0x01] = "Windows 3.1",
225 [0x02] = "Windows 95",
226 [0x03] = "Windows 98",
227 [0x04] = "Windows ME",
228 [0x05] = "Windows NT",
229 [0x06] = "Windows 2000",
230 [0x07] = "Linux",
231 [0x08] = "OS/2",
232 [0x09] = "an unknown OS",
233 [0x0a] = "BSD",
234 [0x0b] = "Whistler",
235 [0x0c] = "an unknown OS",
236 [0x0d] = "an unknown OS",
237 [0x0e] = "an unknown OS",
238 [0x0f] = "an unknown OS",
239 [0x10] = "an unknown OS",
240 [0x11] = "an unknown OS",
241 [0x12] = "an unknown OS",
242 [0x13] = "an unknown OS",
243 [0x14] = "an unknown OS",
244 [0x15] = "Windows 2003",
245 };
246 #endif
247
248 enum {
249 SVGA_CMD_INVALID_CMD = 0,
250 SVGA_CMD_UPDATE = 1,
251 SVGA_CMD_RECT_FILL = 2,
252 SVGA_CMD_RECT_COPY = 3,
253 SVGA_CMD_DEFINE_BITMAP = 4,
254 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
255 SVGA_CMD_DEFINE_PIXMAP = 6,
256 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
257 SVGA_CMD_RECT_BITMAP_FILL = 8,
258 SVGA_CMD_RECT_PIXMAP_FILL = 9,
259 SVGA_CMD_RECT_BITMAP_COPY = 10,
260 SVGA_CMD_RECT_PIXMAP_COPY = 11,
261 SVGA_CMD_FREE_OBJECT = 12,
262 SVGA_CMD_RECT_ROP_FILL = 13,
263 SVGA_CMD_RECT_ROP_COPY = 14,
264 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
265 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
266 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
267 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
268 SVGA_CMD_DEFINE_CURSOR = 19,
269 SVGA_CMD_DISPLAY_CURSOR = 20,
270 SVGA_CMD_MOVE_CURSOR = 21,
271 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
272 SVGA_CMD_DRAW_GLYPH = 23,
273 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
274 SVGA_CMD_UPDATE_VERBOSE = 25,
275 SVGA_CMD_SURFACE_FILL = 26,
276 SVGA_CMD_SURFACE_COPY = 27,
277 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
278 SVGA_CMD_FRONT_ROP_FILL = 29,
279 SVGA_CMD_FENCE = 30,
280 };
281
282 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
283 enum {
284 SVGA_CURSOR_ON_HIDE = 0,
285 SVGA_CURSOR_ON_SHOW = 1,
286 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
287 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
288 };
289
290 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
291 int x, int y, int w, int h)
292 {
293 int line;
294 int bypl;
295 int width;
296 int start;
297 uint8_t *src;
298 uint8_t *dst;
299
300 if (x + w > s->width) {
301 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
302 __FUNCTION__, x, w);
303 x = MIN(x, s->width);
304 w = s->width - x;
305 }
306
307 if (y + h > s->height) {
308 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
309 __FUNCTION__, y, h);
310 y = MIN(y, s->height);
311 h = s->height - y;
312 }
313
314 line = h;
315 bypl = s->bypp * s->width;
316 width = s->bypp * w;
317 start = s->bypp * x + bypl * y;
318 src = s->vga.vram_ptr + start;
319 dst = ds_get_data(s->vga.ds) + start;
320
321 for (; line > 0; line --, src += bypl, dst += bypl)
322 memcpy(dst, src, width);
323
324 dpy_update(s->vga.ds, x, y, w, h);
325 }
326
327 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
328 {
329 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
330 s->bypp * s->width * s->height);
331 dpy_update(s->vga.ds, 0, 0, s->width, s->height);
332 }
333
334 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
335 int x, int y, int w, int h)
336 {
337 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
338 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
339 rect->x = x;
340 rect->y = y;
341 rect->w = w;
342 rect->h = h;
343 }
344
345 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
346 {
347 struct vmsvga_rect_s *rect;
348 if (s->invalidated) {
349 s->redraw_fifo_first = s->redraw_fifo_last;
350 return;
351 }
352 /* Overlapping region updates can be optimised out here - if someone
353 * knows a smart algorithm to do that, please share. */
354 while (s->redraw_fifo_first != s->redraw_fifo_last) {
355 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
356 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
357 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
358 }
359 }
360
361 #ifdef HW_RECT_ACCEL
362 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
363 int x0, int y0, int x1, int y1, int w, int h)
364 {
365 uint8_t *vram = s->vga.vram_ptr;
366 int bypl = s->bypp * s->width;
367 int width = s->bypp * w;
368 int line = h;
369 uint8_t *ptr[2];
370
371 if (y1 > y0) {
372 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
373 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
374 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
375 memmove(ptr[1], ptr[0], width);
376 }
377 } else {
378 ptr[0] = vram + s->bypp * x0 + bypl * y0;
379 ptr[1] = vram + s->bypp * x1 + bypl * y1;
380 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
381 memmove(ptr[1], ptr[0], width);
382 }
383 }
384
385 vmsvga_update_rect_delayed(s, x1, y1, w, h);
386 }
387 #endif
388
389 #ifdef HW_FILL_ACCEL
390 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
391 uint32_t c, int x, int y, int w, int h)
392 {
393 uint8_t *vram = s->vga.vram_ptr;
394 int bypp = s->bypp;
395 int bypl = bypp * s->width;
396 int width = bypp * w;
397 int line = h;
398 int column;
399 uint8_t *fst = vram + bypp * x + bypl * y;
400 uint8_t *dst;
401 uint8_t *src;
402 uint8_t col[4];
403
404 col[0] = c;
405 col[1] = c >> 8;
406 col[2] = c >> 16;
407 col[3] = c >> 24;
408
409 if (line--) {
410 dst = fst;
411 src = col;
412 for (column = width; column > 0; column--) {
413 *(dst++) = *(src++);
414 if (src - col == bypp) {
415 src = col;
416 }
417 }
418 dst = fst;
419 for (; line > 0; line--) {
420 dst += bypl;
421 memcpy(dst, fst, width);
422 }
423 }
424
425 vmsvga_update_rect_delayed(s, x, y, w, h);
426 }
427 #endif
428
429 struct vmsvga_cursor_definition_s {
430 int width;
431 int height;
432 int id;
433 int bpp;
434 int hot_x;
435 int hot_y;
436 uint32_t mask[1024];
437 uint32_t image[4096];
438 };
439
440 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
441 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
442
443 #ifdef HW_MOUSE_ACCEL
444 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
445 struct vmsvga_cursor_definition_s *c)
446 {
447 QEMUCursor *qc;
448 int i, pixels;
449
450 qc = cursor_alloc(c->width, c->height);
451 qc->hot_x = c->hot_x;
452 qc->hot_y = c->hot_y;
453 switch (c->bpp) {
454 case 1:
455 cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image,
456 1, (void*)c->mask);
457 #ifdef DEBUG
458 cursor_print_ascii_art(qc, "vmware/mono");
459 #endif
460 break;
461 case 32:
462 /* fill alpha channel from mask, set color to zero */
463 cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask,
464 1, (void*)c->mask);
465 /* add in rgb values */
466 pixels = c->width * c->height;
467 for (i = 0; i < pixels; i++) {
468 qc->data[i] |= c->image[i] & 0xffffff;
469 }
470 #ifdef DEBUG
471 cursor_print_ascii_art(qc, "vmware/32bit");
472 #endif
473 break;
474 default:
475 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
476 __FUNCTION__, c->bpp);
477 cursor_put(qc);
478 qc = cursor_builtin_left_ptr();
479 }
480
481 dpy_cursor_define(s->vga.ds, qc);
482 cursor_put(qc);
483 }
484 #endif
485
486 #define CMD(f) le32_to_cpu(s->cmd->f)
487
488 static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
489 {
490 int num;
491 if (!s->config || !s->enable)
492 return 0;
493 num = CMD(next_cmd) - CMD(stop);
494 if (num < 0)
495 num += CMD(max) - CMD(min);
496 return num >> 2;
497 }
498
499 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
500 {
501 uint32_t cmd = s->fifo[CMD(stop) >> 2];
502 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
503 if (CMD(stop) >= CMD(max))
504 s->cmd->stop = s->cmd->min;
505 return cmd;
506 }
507
508 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
509 {
510 return le32_to_cpu(vmsvga_fifo_read_raw(s));
511 }
512
513 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
514 {
515 uint32_t cmd, colour;
516 int args, len;
517 int x, y, dx, dy, width, height;
518 struct vmsvga_cursor_definition_s cursor;
519 uint32_t cmd_start;
520
521 len = vmsvga_fifo_length(s);
522 while (len > 0) {
523 /* May need to go back to the start of the command if incomplete */
524 cmd_start = s->cmd->stop;
525
526 switch (cmd = vmsvga_fifo_read(s)) {
527 case SVGA_CMD_UPDATE:
528 case SVGA_CMD_UPDATE_VERBOSE:
529 len -= 5;
530 if (len < 0)
531 goto rewind;
532
533 x = vmsvga_fifo_read(s);
534 y = vmsvga_fifo_read(s);
535 width = vmsvga_fifo_read(s);
536 height = vmsvga_fifo_read(s);
537 vmsvga_update_rect_delayed(s, x, y, width, height);
538 break;
539
540 case SVGA_CMD_RECT_FILL:
541 len -= 6;
542 if (len < 0)
543 goto rewind;
544
545 colour = vmsvga_fifo_read(s);
546 x = vmsvga_fifo_read(s);
547 y = vmsvga_fifo_read(s);
548 width = vmsvga_fifo_read(s);
549 height = vmsvga_fifo_read(s);
550 #ifdef HW_FILL_ACCEL
551 vmsvga_fill_rect(s, colour, x, y, width, height);
552 break;
553 #else
554 args = 0;
555 goto badcmd;
556 #endif
557
558 case SVGA_CMD_RECT_COPY:
559 len -= 7;
560 if (len < 0)
561 goto rewind;
562
563 x = vmsvga_fifo_read(s);
564 y = vmsvga_fifo_read(s);
565 dx = vmsvga_fifo_read(s);
566 dy = vmsvga_fifo_read(s);
567 width = vmsvga_fifo_read(s);
568 height = vmsvga_fifo_read(s);
569 #ifdef HW_RECT_ACCEL
570 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
571 break;
572 #else
573 args = 0;
574 goto badcmd;
575 #endif
576
577 case SVGA_CMD_DEFINE_CURSOR:
578 len -= 8;
579 if (len < 0)
580 goto rewind;
581
582 cursor.id = vmsvga_fifo_read(s);
583 cursor.hot_x = vmsvga_fifo_read(s);
584 cursor.hot_y = vmsvga_fifo_read(s);
585 cursor.width = x = vmsvga_fifo_read(s);
586 cursor.height = y = vmsvga_fifo_read(s);
587 vmsvga_fifo_read(s);
588 cursor.bpp = vmsvga_fifo_read(s);
589
590 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
591 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
592 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image)
593 goto badcmd;
594
595 len -= args;
596 if (len < 0)
597 goto rewind;
598
599 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
600 cursor.mask[args] = vmsvga_fifo_read_raw(s);
601 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
602 cursor.image[args] = vmsvga_fifo_read_raw(s);
603 #ifdef HW_MOUSE_ACCEL
604 vmsvga_cursor_define(s, &cursor);
605 break;
606 #else
607 args = 0;
608 goto badcmd;
609 #endif
610
611 /*
612 * Other commands that we at least know the number of arguments
613 * for so we can avoid FIFO desync if driver uses them illegally.
614 */
615 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
616 len -= 6;
617 if (len < 0)
618 goto rewind;
619
620 vmsvga_fifo_read(s);
621 vmsvga_fifo_read(s);
622 vmsvga_fifo_read(s);
623 x = vmsvga_fifo_read(s);
624 y = vmsvga_fifo_read(s);
625 args = x * y;
626 goto badcmd;
627 case SVGA_CMD_RECT_ROP_FILL:
628 args = 6;
629 goto badcmd;
630 case SVGA_CMD_RECT_ROP_COPY:
631 args = 7;
632 goto badcmd;
633 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
634 len -= 4;
635 if (len < 0)
636 goto rewind;
637
638 vmsvga_fifo_read(s);
639 vmsvga_fifo_read(s);
640 args = 7 + (vmsvga_fifo_read(s) >> 2);
641 goto badcmd;
642 case SVGA_CMD_SURFACE_ALPHA_BLEND:
643 args = 12;
644 goto badcmd;
645
646 /*
647 * Other commands that are not listed as depending on any
648 * CAPABILITIES bits, but are not described in the README either.
649 */
650 case SVGA_CMD_SURFACE_FILL:
651 case SVGA_CMD_SURFACE_COPY:
652 case SVGA_CMD_FRONT_ROP_FILL:
653 case SVGA_CMD_FENCE:
654 case SVGA_CMD_INVALID_CMD:
655 break; /* Nop */
656
657 default:
658 args = 0;
659 badcmd:
660 len -= args;
661 if (len < 0)
662 goto rewind;
663 while (args --)
664 vmsvga_fifo_read(s);
665 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
666 __FUNCTION__, cmd);
667 break;
668
669 rewind:
670 s->cmd->stop = cmd_start;
671 break;
672 }
673 }
674
675 s->syncing = 0;
676 }
677
678 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
679 {
680 struct vmsvga_state_s *s = opaque;
681 return s->index;
682 }
683
684 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
685 {
686 struct vmsvga_state_s *s = opaque;
687 s->index = index;
688 }
689
690 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
691 {
692 uint32_t caps;
693 struct vmsvga_state_s *s = opaque;
694 switch (s->index) {
695 case SVGA_REG_ID:
696 return s->svgaid;
697
698 case SVGA_REG_ENABLE:
699 return s->enable;
700
701 case SVGA_REG_WIDTH:
702 return s->width;
703
704 case SVGA_REG_HEIGHT:
705 return s->height;
706
707 case SVGA_REG_MAX_WIDTH:
708 return SVGA_MAX_WIDTH;
709
710 case SVGA_REG_MAX_HEIGHT:
711 return SVGA_MAX_HEIGHT;
712
713 case SVGA_REG_DEPTH:
714 return s->depth;
715
716 case SVGA_REG_BITS_PER_PIXEL:
717 return (s->depth + 7) & ~7;
718
719 case SVGA_REG_PSEUDOCOLOR:
720 return 0x0;
721
722 case SVGA_REG_RED_MASK:
723 return s->wred;
724 case SVGA_REG_GREEN_MASK:
725 return s->wgreen;
726 case SVGA_REG_BLUE_MASK:
727 return s->wblue;
728
729 case SVGA_REG_BYTES_PER_LINE:
730 return ((s->depth + 7) >> 3) * s->new_width;
731
732 case SVGA_REG_FB_START: {
733 struct pci_vmsvga_state_s *pci_vmsvga
734 = container_of(s, struct pci_vmsvga_state_s, chip);
735 return pci_get_bar_addr(&pci_vmsvga->card, 1);
736 }
737
738 case SVGA_REG_FB_OFFSET:
739 return 0x0;
740
741 case SVGA_REG_VRAM_SIZE:
742 return s->vga.vram_size;
743
744 case SVGA_REG_FB_SIZE:
745 return s->fb_size;
746
747 case SVGA_REG_CAPABILITIES:
748 caps = SVGA_CAP_NONE;
749 #ifdef HW_RECT_ACCEL
750 caps |= SVGA_CAP_RECT_COPY;
751 #endif
752 #ifdef HW_FILL_ACCEL
753 caps |= SVGA_CAP_RECT_FILL;
754 #endif
755 #ifdef HW_MOUSE_ACCEL
756 if (dpy_cursor_define_supported(s->vga.ds)) {
757 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
758 SVGA_CAP_CURSOR_BYPASS;
759 }
760 #endif
761 return caps;
762
763 case SVGA_REG_MEM_START: {
764 struct pci_vmsvga_state_s *pci_vmsvga
765 = container_of(s, struct pci_vmsvga_state_s, chip);
766 return pci_get_bar_addr(&pci_vmsvga->card, 2);
767 }
768
769 case SVGA_REG_MEM_SIZE:
770 return s->fifo_size;
771
772 case SVGA_REG_CONFIG_DONE:
773 return s->config;
774
775 case SVGA_REG_SYNC:
776 case SVGA_REG_BUSY:
777 return s->syncing;
778
779 case SVGA_REG_GUEST_ID:
780 return s->guest;
781
782 case SVGA_REG_CURSOR_ID:
783 return s->cursor.id;
784
785 case SVGA_REG_CURSOR_X:
786 return s->cursor.x;
787
788 case SVGA_REG_CURSOR_Y:
789 return s->cursor.x;
790
791 case SVGA_REG_CURSOR_ON:
792 return s->cursor.on;
793
794 case SVGA_REG_HOST_BITS_PER_PIXEL:
795 return (s->depth + 7) & ~7;
796
797 case SVGA_REG_SCRATCH_SIZE:
798 return s->scratch_size;
799
800 case SVGA_REG_MEM_REGS:
801 case SVGA_REG_NUM_DISPLAYS:
802 case SVGA_REG_PITCHLOCK:
803 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
804 return 0;
805
806 default:
807 if (s->index >= SVGA_SCRATCH_BASE &&
808 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
809 return s->scratch[s->index - SVGA_SCRATCH_BASE];
810 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
811 }
812
813 return 0;
814 }
815
816 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
817 {
818 struct vmsvga_state_s *s = opaque;
819 switch (s->index) {
820 case SVGA_REG_ID:
821 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
822 s->svgaid = value;
823 break;
824
825 case SVGA_REG_ENABLE:
826 s->enable = value;
827 s->config &= !!value;
828 s->width = -1;
829 s->height = -1;
830 s->invalidated = 1;
831 s->vga.invalidate(&s->vga);
832 if (s->enable) {
833 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
834 vga_dirty_log_stop(&s->vga);
835 } else {
836 vga_dirty_log_start(&s->vga);
837 }
838 break;
839
840 case SVGA_REG_WIDTH:
841 s->new_width = value;
842 s->invalidated = 1;
843 break;
844
845 case SVGA_REG_HEIGHT:
846 s->new_height = value;
847 s->invalidated = 1;
848 break;
849
850 case SVGA_REG_DEPTH:
851 case SVGA_REG_BITS_PER_PIXEL:
852 if (value != s->depth) {
853 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
854 s->config = 0;
855 }
856 break;
857
858 case SVGA_REG_CONFIG_DONE:
859 if (value) {
860 s->fifo = (uint32_t *) s->fifo_ptr;
861 /* Check range and alignment. */
862 if ((CMD(min) | CMD(max) |
863 CMD(next_cmd) | CMD(stop)) & 3)
864 break;
865 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
866 break;
867 if (CMD(max) > SVGA_FIFO_SIZE)
868 break;
869 if (CMD(max) < CMD(min) + 10 * 1024)
870 break;
871 }
872 s->config = !!value;
873 break;
874
875 case SVGA_REG_SYNC:
876 s->syncing = 1;
877 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
878 break;
879
880 case SVGA_REG_GUEST_ID:
881 s->guest = value;
882 #ifdef VERBOSE
883 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
884 ARRAY_SIZE(vmsvga_guest_id))
885 printf("%s: guest runs %s.\n", __FUNCTION__,
886 vmsvga_guest_id[value - GUEST_OS_BASE]);
887 #endif
888 break;
889
890 case SVGA_REG_CURSOR_ID:
891 s->cursor.id = value;
892 break;
893
894 case SVGA_REG_CURSOR_X:
895 s->cursor.x = value;
896 break;
897
898 case SVGA_REG_CURSOR_Y:
899 s->cursor.y = value;
900 break;
901
902 case SVGA_REG_CURSOR_ON:
903 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
904 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
905 #ifdef HW_MOUSE_ACCEL
906 if (value <= SVGA_CURSOR_ON_SHOW) {
907 dpy_mouse_set(s->vga.ds, s->cursor.x, s->cursor.y, s->cursor.on);
908 }
909 #endif
910 break;
911
912 case SVGA_REG_MEM_REGS:
913 case SVGA_REG_NUM_DISPLAYS:
914 case SVGA_REG_PITCHLOCK:
915 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
916 break;
917
918 default:
919 if (s->index >= SVGA_SCRATCH_BASE &&
920 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
921 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
922 break;
923 }
924 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
925 }
926 }
927
928 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
929 {
930 printf("%s: what are we supposed to return?\n", __FUNCTION__);
931 return 0xcafe;
932 }
933
934 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
935 {
936 printf("%s: what are we supposed to do with (%08x)?\n",
937 __FUNCTION__, data);
938 }
939
940 static inline void vmsvga_size(struct vmsvga_state_s *s)
941 {
942 if (s->new_width != s->width || s->new_height != s->height) {
943 s->width = s->new_width;
944 s->height = s->new_height;
945 qemu_console_resize(s->vga.ds, s->width, s->height);
946 s->invalidated = 1;
947 }
948 }
949
950 static void vmsvga_update_display(void *opaque)
951 {
952 struct vmsvga_state_s *s = opaque;
953 if (!s->enable) {
954 s->vga.update(&s->vga);
955 return;
956 }
957
958 vmsvga_size(s);
959
960 vmsvga_fifo_run(s);
961 vmsvga_update_rect_flush(s);
962
963 /*
964 * Is it more efficient to look at vram VGA-dirty bits or wait
965 * for the driver to issue SVGA_CMD_UPDATE?
966 */
967 if (s->invalidated) {
968 s->invalidated = 0;
969 vmsvga_update_screen(s);
970 }
971 }
972
973 static void vmsvga_reset(DeviceState *dev)
974 {
975 struct pci_vmsvga_state_s *pci =
976 DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
977 struct vmsvga_state_s *s = &pci->chip;
978
979 s->index = 0;
980 s->enable = 0;
981 s->config = 0;
982 s->width = -1;
983 s->height = -1;
984 s->svgaid = SVGA_ID;
985 s->cursor.on = 0;
986 s->redraw_fifo_first = 0;
987 s->redraw_fifo_last = 0;
988 s->syncing = 0;
989
990 vga_dirty_log_start(&s->vga);
991 }
992
993 static void vmsvga_invalidate_display(void *opaque)
994 {
995 struct vmsvga_state_s *s = opaque;
996 if (!s->enable) {
997 s->vga.invalidate(&s->vga);
998 return;
999 }
1000
1001 s->invalidated = 1;
1002 }
1003
1004 /* save the vga display in a PPM image even if no display is
1005 available */
1006 static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch,
1007 Error **errp)
1008 {
1009 struct vmsvga_state_s *s = opaque;
1010 if (!s->enable) {
1011 s->vga.screen_dump(&s->vga, filename, cswitch, errp);
1012 return;
1013 }
1014
1015 if (s->depth == 32) {
1016 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
1017 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
1018 ppm_save(filename, ds, errp);
1019 g_free(ds);
1020 }
1021 }
1022
1023 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
1024 {
1025 struct vmsvga_state_s *s = opaque;
1026
1027 if (s->vga.text_update)
1028 s->vga.text_update(&s->vga, chardata);
1029 }
1030
1031 static int vmsvga_post_load(void *opaque, int version_id)
1032 {
1033 struct vmsvga_state_s *s = opaque;
1034
1035 s->invalidated = 1;
1036 if (s->config)
1037 s->fifo = (uint32_t *) s->fifo_ptr;
1038
1039 return 0;
1040 }
1041
1042 static const VMStateDescription vmstate_vmware_vga_internal = {
1043 .name = "vmware_vga_internal",
1044 .version_id = 0,
1045 .minimum_version_id = 0,
1046 .minimum_version_id_old = 0,
1047 .post_load = vmsvga_post_load,
1048 .fields = (VMStateField []) {
1049 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1050 VMSTATE_INT32(enable, struct vmsvga_state_s),
1051 VMSTATE_INT32(config, struct vmsvga_state_s),
1052 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1053 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1054 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1055 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1056 VMSTATE_INT32(index, struct vmsvga_state_s),
1057 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1058 scratch_size, 0, vmstate_info_uint32, uint32_t),
1059 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1060 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1061 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1062 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1063 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1064 VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1065 VMSTATE_END_OF_LIST()
1066 }
1067 };
1068
1069 static const VMStateDescription vmstate_vmware_vga = {
1070 .name = "vmware_vga",
1071 .version_id = 0,
1072 .minimum_version_id = 0,
1073 .minimum_version_id_old = 0,
1074 .fields = (VMStateField []) {
1075 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1076 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1077 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1078 VMSTATE_END_OF_LIST()
1079 }
1080 };
1081
1082 static void vmsvga_init(struct vmsvga_state_s *s,
1083 MemoryRegion *address_space, MemoryRegion *io)
1084 {
1085 s->scratch_size = SVGA_SCRATCH_SIZE;
1086 s->scratch = g_malloc(s->scratch_size * 4);
1087
1088 s->vga.ds = graphic_console_init(vmsvga_update_display,
1089 vmsvga_invalidate_display,
1090 vmsvga_screen_dump,
1091 vmsvga_text_update, s);
1092
1093
1094 s->fifo_size = SVGA_FIFO_SIZE;
1095 memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
1096 vmstate_register_ram_global(&s->fifo_ram);
1097 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
1098
1099 vga_common_init(&s->vga);
1100 vga_init(&s->vga, address_space, io, true);
1101 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
1102
1103 s->depth = ds_get_bits_per_pixel(s->vga.ds);
1104 s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
1105 switch (s->depth) {
1106 case 8:
1107 s->wred = 0x00000007;
1108 s->wgreen = 0x00000038;
1109 s->wblue = 0x000000c0;
1110 break;
1111 case 15:
1112 s->wred = 0x0000001f;
1113 s->wgreen = 0x000003e0;
1114 s->wblue = 0x00007c00;
1115 break;
1116 case 16:
1117 s->wred = 0x0000001f;
1118 s->wgreen = 0x000007e0;
1119 s->wblue = 0x0000f800;
1120 break;
1121 case 24:
1122 s->wred = 0x00ff0000;
1123 s->wgreen = 0x0000ff00;
1124 s->wblue = 0x000000ff;
1125 break;
1126 case 32:
1127 s->wred = 0x00ff0000;
1128 s->wgreen = 0x0000ff00;
1129 s->wblue = 0x000000ff;
1130 break;
1131 }
1132 }
1133
1134 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr,
1135 unsigned size)
1136 {
1137 struct vmsvga_state_s *s = opaque;
1138
1139 switch (addr) {
1140 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1141 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1142 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1143 default: return -1u;
1144 }
1145 }
1146
1147 static void vmsvga_io_write(void *opaque, hwaddr addr,
1148 uint64_t data, unsigned size)
1149 {
1150 struct vmsvga_state_s *s = opaque;
1151
1152 switch (addr) {
1153 case SVGA_IO_MUL * SVGA_INDEX_PORT:
1154 vmsvga_index_write(s, addr, data);
1155 break;
1156 case SVGA_IO_MUL * SVGA_VALUE_PORT:
1157 vmsvga_value_write(s, addr, data);
1158 break;
1159 case SVGA_IO_MUL * SVGA_BIOS_PORT:
1160 vmsvga_bios_write(s, addr, data);
1161 break;
1162 }
1163 }
1164
1165 static const MemoryRegionOps vmsvga_io_ops = {
1166 .read = vmsvga_io_read,
1167 .write = vmsvga_io_write,
1168 .endianness = DEVICE_LITTLE_ENDIAN,
1169 .valid = {
1170 .min_access_size = 4,
1171 .max_access_size = 4,
1172 },
1173 };
1174
1175 static int pci_vmsvga_initfn(PCIDevice *dev)
1176 {
1177 struct pci_vmsvga_state_s *s =
1178 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1179 MemoryRegion *iomem;
1180
1181 iomem = &s->chip.vga.vram;
1182
1183 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
1184 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
1185 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
1186
1187 memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
1188 "vmsvga-io", 0x10);
1189 memory_region_set_flush_coalesced(&s->io_bar);
1190 pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1191
1192 vmsvga_init(&s->chip, pci_address_space(dev),
1193 pci_address_space_io(dev));
1194
1195 pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
1196 pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1197 &s->chip.fifo_ram);
1198
1199 if (!dev->rom_bar) {
1200 /* compatibility with pc-0.13 and older */
1201 vga_init_vbe(&s->chip.vga, pci_address_space(dev));
1202 }
1203
1204 return 0;
1205 }
1206
1207 static Property vga_vmware_properties[] = {
1208 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
1209 chip.vga.vram_size_mb, 16),
1210 DEFINE_PROP_END_OF_LIST(),
1211 };
1212
1213 static void vmsvga_class_init(ObjectClass *klass, void *data)
1214 {
1215 DeviceClass *dc = DEVICE_CLASS(klass);
1216 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1217
1218 k->no_hotplug = 1;
1219 k->init = pci_vmsvga_initfn;
1220 k->romfile = "vgabios-vmware.bin";
1221 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1222 k->device_id = SVGA_PCI_DEVICE_ID;
1223 k->class_id = PCI_CLASS_DISPLAY_VGA;
1224 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1225 k->subsystem_id = SVGA_PCI_DEVICE_ID;
1226 dc->reset = vmsvga_reset;
1227 dc->vmsd = &vmstate_vmware_vga;
1228 dc->props = vga_vmware_properties;
1229 }
1230
1231 static TypeInfo vmsvga_info = {
1232 .name = "vmware-svga",
1233 .parent = TYPE_PCI_DEVICE,
1234 .instance_size = sizeof(struct pci_vmsvga_state_s),
1235 .class_init = vmsvga_class_init,
1236 };
1237
1238 static void vmsvga_register_types(void)
1239 {
1240 type_register_static(&vmsvga_info);
1241 }
1242
1243 type_init(vmsvga_register_types)
Qemu copy for testing