hw/vt82c686.c

   1 /*
   2  * VT82C686B south bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
   6  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   7  * This code is licensed under the GNU GPL v2.
   8  */
   9
  10 #include "hw.h"
  11 #include "pc.h"
  12 #include "vt82c686.h"
  13 #include "i2c.h"
  14 #include "smbus.h"
  15 #include "pci.h"
  16 #include "isa.h"
  17 #include "sysbus.h"
  18 #include "mips.h"
  19 #include "apm.h"
  20 #include "acpi.h"
  21 #include "pm_smbus.h"
  22 #include "sysemu.h"
  23 #include "qemu-timer.h"
  24
  25 typedef uint32_t pci_addr_t;
  26 #include "pci_host.h"
  27 //#define DEBUG_VT82C686B
  28
  29 #ifdef DEBUG_VT82C686B
  30 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  31 #else
  32 #define DPRINTF(fmt, ...)
  33 #endif
  34
  35 typedef struct SuperIOConfig
  36 {
  37     uint8_t config[0xff];
  38     uint8_t index;
  39     uint8_t data;
  40 } SuperIOConfig;
  41
  42 typedef struct VT82C686BState {
  43     PCIDevice dev;
  44     SuperIOConfig superio_conf;
  45 } VT82C686BState;
  46
  47 static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data)
  48 {
  49     int can_write;
  50     SuperIOConfig *superio_conf = opaque;
  51
  52     DPRINTF("superio_ioport_writeb  address 0x%x  val 0x%x  \n", addr, data);
  53     if (addr == 0x3f0) {
  54         superio_conf->index = data & 0xff;
  55     } else {
  56         /* 0x3f1 */
  57         switch (superio_conf->index) {
  58         case 0x00 ... 0xdf:
  59         case 0xe4:
  60         case 0xe5:
  61         case 0xe9 ... 0xed:
  62         case 0xf3:
  63         case 0xf5:
  64         case 0xf7:
  65         case 0xf9 ... 0xfb:
  66         case 0xfd ... 0xff:
  67             can_write = 0;
  68             break;
  69         default:
  70             can_write = 1;
  71
  72             if (can_write) {
  73                 switch (superio_conf->index) {
  74                 case 0xe7:
  75                     if ((data & 0xff) != 0xfe) {
  76                         DPRINTF("chage uart 1 base. unsupported yet \n");
  77                     }
  78                     break;
  79                 case 0xe8:
  80                     if ((data & 0xff) != 0xbe) {
  81                         DPRINTF("chage uart 2 base. unsupported yet \n");
  82                     }
  83                     break;
  84
  85                 default:
  86                     superio_conf->config[superio_conf->index] = data & 0xff;
  87                 }
  88             }
  89         }
  90         superio_conf->config[superio_conf->index] = data & 0xff;
  91     }
  92 }
  93
  94 static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
  95 {
  96     SuperIOConfig *superio_conf = opaque;
  97
  98     DPRINTF("superio_ioport_readb  address 0x%x   \n", addr);
  99     return (superio_conf->config[superio_conf->index]);
 100 }
 101
 102 static void vt82c686b_reset(void * opaque)
 103 {
 104     PCIDevice *d = opaque;
 105     uint8_t *pci_conf = d->config;
 106     VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
 107
 108     pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
 109     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 110                  PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
 111     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 112
 113     pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
 114     pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
 115     pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
 116     pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
 117     pci_conf[0x59] = 0x04;
 118     pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
 119     pci_conf[0x5f] = 0x04;
 120     pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
 121
 122     vt82c->superio_conf.config[0xe0] = 0x3c;
 123     vt82c->superio_conf.config[0xe2] = 0x03;
 124     vt82c->superio_conf.config[0xe3] = 0xfc;
 125     vt82c->superio_conf.config[0xe6] = 0xde;
 126     vt82c->superio_conf.config[0xe7] = 0xfe;
 127     vt82c->superio_conf.config[0xe8] = 0xbe;
 128 }
 129
 130 /* write config pci function0 registers. PCI-ISA bridge */
 131 static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
 132                                    uint32_t val, int len)
 133 {
 134     VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
 135
 136     DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x \n",
 137            address, val, len);
 138
 139     pci_default_write_config(d, address, val, len);
 140     if (address == 0x85) {  /* enable or disable super IO configure */
 141         if (val & 0x2) {
 142             /* floppy also uses 0x3f0 and 0x3f1.
 143              * But we do not emulate flopy,so just set it here. */
 144             isa_unassign_ioport(0x3f0, 2);
 145             register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
 146                                  &vt686->superio_conf);
 147             register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
 148                                   &vt686->superio_conf);
 149         } else {
 150             isa_unassign_ioport(0x3f0, 2);
 151         }
 152     }
 153 }
 154
 155 #define ACPI_DBG_IO_ADDR  0xb044
 156
 157 typedef struct VT686PMState {
 158     PCIDevice dev;
 159     uint16_t pmsts;
 160     uint16_t pmen;
 161     uint16_t pmcntrl;
 162     APMState apm;
 163     ACPIPMTimer tmr;
 164     PMSMBus smb;
 165     uint32_t smb_io_base;
 166 } VT686PMState;
 167
 168 typedef struct VT686AC97State {
 169     PCIDevice dev;
 170 } VT686AC97State;
 171
 172 typedef struct VT686MC97State {
 173     PCIDevice dev;
 174 } VT686MC97State;
 175
 176 #define RTC_EN    (1 << 10)
 177 #define PWRBTN_EN (1 << 8)
 178 #define GBL_EN    (1 << 5)
 179 #define TMROF_EN  (1 << 0)
 180 #define SUS_EN    (1 << 13)
 181
 182 #define ACPI_ENABLE  0xf1
 183 #define ACPI_DISABLE 0xf0
 184
 185 static int get_pmsts(VT686PMState *s)
 186 {
 187     int64_t d = acpi_pm_tmr_get_clock();
 188     if (d >= s->tmr.overflow_time) {
 189         s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
 190     }
 191     return s->pmsts;
 192 }
 193
 194 static void pm_update_sci(VT686PMState *s)
 195 {
 196     int sci_level, pmsts;
 197
 198     pmsts = get_pmsts(s);
 199     sci_level = (((pmsts & s->pmen) &
 200                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 201     qemu_set_irq(s->dev.irq[0], sci_level);
 202     /* schedule a timer interruption if needed */
 203     acpi_pm_tmr_update(&s->tmr, (s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
 204                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 205 }
 206
 207 static void pm_tmr_timer(ACPIPMTimer *tmr)
 208 {
 209     VT686PMState *s = container_of(tmr, VT686PMState, tmr);
 210     pm_update_sci(s);
 211 }
 212
 213 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 214 {
 215     VT686PMState *s = opaque;
 216
 217     addr &= 0x0f;
 218     switch (addr) {
 219     case 0x00:
 220         {
 221             int pmsts;
 222             pmsts = get_pmsts(s);
 223             if (pmsts & val & TMROF_EN) {
 224                 /* if TMRSTS is reset, then compute the new overflow time */
 225                 acpi_pm_tmr_calc_overflow_time(&s->tmr);
 226             }
 227             s->pmsts &= ~val;
 228             pm_update_sci(s);
 229         }
 230         break;
 231     case 0x02:
 232         s->pmen = val;
 233         pm_update_sci(s);
 234         break;
 235     case 0x04:
 236         {
 237             int sus_typ;
 238             s->pmcntrl = val & ~(SUS_EN);
 239             if (val & SUS_EN) {
 240                 /* change suspend type */
 241                 sus_typ = (val >> 10) & 3;
 242                 switch (sus_typ) {
 243                 case 0: /* soft power off */
 244                     qemu_system_shutdown_request();
 245                     break;
 246                 default:
 247                     break;
 248                 }
 249             }
 250         }
 251         break;
 252     default:
 253         break;
 254     }
 255     DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val);
 256 }
 257
 258 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 259 {
 260     VT686PMState *s = opaque;
 261     uint32_t val;
 262
 263     addr &= 0x0f;
 264     switch (addr) {
 265     case 0x00:
 266         val = get_pmsts(s);
 267         break;
 268     case 0x02:
 269         val = s->pmen;
 270         break;
 271     case 0x04:
 272         val = s->pmcntrl;
 273         break;
 274     default:
 275         val = 0;
 276         break;
 277     }
 278     DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val);
 279     return val;
 280 }
 281
 282 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 283 {
 284     addr &= 0x0f;
 285     DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val);
 286 }
 287
 288 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 289 {
 290     VT686PMState *s = opaque;
 291     uint32_t val;
 292
 293     addr &= 0x0f;
 294     switch (addr) {
 295     case 0x08:
 296         val = acpi_pm_tmr_get(&s->tmr);
 297         break;
 298     default:
 299         val = 0;
 300         break;
 301     }
 302     DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val);
 303     return val;
 304 }
 305
 306 static void pm_io_space_update(VT686PMState *s)
 307 {
 308     uint32_t pm_io_base;
 309
 310     if (s->dev.config[0x80] & 1) {
 311         pm_io_base = pci_get_long(s->dev.config + 0x40);
 312         pm_io_base &= 0xffc0;
 313
 314         /* XXX: need to improve memory and ioport allocation */
 315         DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 316         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 317         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 318         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 319         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 320     }
 321 }
 322
 323 static void pm_write_config(PCIDevice *d,
 324                             uint32_t address, uint32_t val, int len)
 325 {
 326     DPRINTF("pm_write_config  address 0x%x  val 0x%x len 0x%x \n",
 327            address, val, len);
 328     pci_default_write_config(d, address, val, len);
 329 }
 330
 331 static int vmstate_acpi_post_load(void *opaque, int version_id)
 332 {
 333     VT686PMState *s = opaque;
 334
 335     pm_io_space_update(s);
 336     return 0;
 337 }
 338
 339 static const VMStateDescription vmstate_acpi = {
 340     .name = "vt82c686b_pm",
 341     .version_id = 1,
 342     .minimum_version_id = 1,
 343     .minimum_version_id_old = 1,
 344     .post_load = vmstate_acpi_post_load,
 345     .fields      = (VMStateField []) {
 346         VMSTATE_PCI_DEVICE(dev, VT686PMState),
 347         VMSTATE_UINT16(pmsts, VT686PMState),
 348         VMSTATE_UINT16(pmen, VT686PMState),
 349         VMSTATE_UINT16(pmcntrl, VT686PMState),
 350         VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
 351         VMSTATE_TIMER(tmr.timer, VT686PMState),
 352         VMSTATE_INT64(tmr.overflow_time, VT686PMState),
 353         VMSTATE_END_OF_LIST()
 354     }
 355 };
 356
 357 /*
 358  * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
 359  * just register a PCI device now, functionalities will be implemented later.
 360  */
 361
 362 static int vt82c686b_ac97_initfn(PCIDevice *dev)
 363 {
 364     VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
 365     uint8_t *pci_conf = s->dev.config;
 366
 367     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 368     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97);
 369     pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO);
 370     pci_config_set_revision(pci_conf, 0x50);
 371
 372     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 373                  PCI_COMMAND_PARITY);
 374     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
 375                  PCI_STATUS_DEVSEL_MEDIUM);
 376     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 377
 378     return 0;
 379 }
 380
 381 void vt82c686b_ac97_init(PCIBus *bus, int devfn)
 382 {
 383     PCIDevice *dev;
 384
 385     dev = pci_create(bus, devfn, "VT82C686B_AC97");
 386     qdev_init_nofail(&dev->qdev);
 387 }
 388
 389 static PCIDeviceInfo via_ac97_info = {
 390     .qdev.name          = "VT82C686B_AC97",
 391     .qdev.desc          = "AC97",
 392     .qdev.size          = sizeof(VT686AC97State),
 393     .init               = vt82c686b_ac97_initfn,
 394 };
 395
 396 static void vt82c686b_ac97_register(void)
 397 {
 398     pci_qdev_register(&via_ac97_info);
 399 }
 400
 401 device_init(vt82c686b_ac97_register);
 402
 403 static int vt82c686b_mc97_initfn(PCIDevice *dev)
 404 {
 405     VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
 406     uint8_t *pci_conf = s->dev.config;
 407
 408     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 409     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97);
 410     pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER);
 411     pci_config_set_revision(pci_conf, 0x30);
 412
 413     pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
 414                  PCI_COMMAND_VGA_PALETTE);
 415     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
 416     pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
 417
 418     return 0;
 419 }
 420
 421 void vt82c686b_mc97_init(PCIBus *bus, int devfn)
 422 {
 423     PCIDevice *dev;
 424
 425     dev = pci_create(bus, devfn, "VT82C686B_MC97");
 426     qdev_init_nofail(&dev->qdev);
 427 }
 428
 429 static PCIDeviceInfo via_mc97_info = {
 430     .qdev.name          = "VT82C686B_MC97",
 431     .qdev.desc          = "MC97",
 432     .qdev.size          = sizeof(VT686MC97State),
 433     .init               = vt82c686b_mc97_initfn,
 434 };
 435
 436 static void vt82c686b_mc97_register(void)
 437 {
 438     pci_qdev_register(&via_mc97_info);
 439 }
 440
 441 device_init(vt82c686b_mc97_register);
 442
 443 /* vt82c686 pm init */
 444 static int vt82c686b_pm_initfn(PCIDevice *dev)
 445 {
 446     VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
 447     uint8_t *pci_conf;
 448
 449     pci_conf = s->dev.config;
 450     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 451     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI);
 452     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 453     pci_config_set_revision(pci_conf, 0x40);
 454
 455     pci_set_word(pci_conf + PCI_COMMAND, 0);
 456     pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
 457                  PCI_STATUS_DEVSEL_MEDIUM);
 458
 459     /* 0x48-0x4B is Power Management I/O Base */
 460     pci_set_long(pci_conf + 0x48, 0x00000001);
 461
 462     /* SMB ports:0xeee0~0xeeef */
 463     s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
 464     pci_conf[0x90] = s->smb_io_base | 1;
 465     pci_conf[0x91] = s->smb_io_base >> 8;
 466     pci_conf[0xd2] = 0x90;
 467     register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
 468     register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
 469
 470     apm_init(&s->apm, NULL, s);
 471
 472     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 473
 474     pm_smbus_init(&s->dev.qdev, &s->smb);
 475
 476     return 0;
 477 }
 478
 479 i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 480                        qemu_irq sci_irq)
 481 {
 482     PCIDevice *dev;
 483     VT686PMState *s;
 484
 485     dev = pci_create(bus, devfn, "VT82C686B_PM");
 486     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 487
 488     s = DO_UPCAST(VT686PMState, dev, dev);
 489
 490     qdev_init_nofail(&dev->qdev);
 491
 492     return s->smb.smbus;
 493 }
 494
 495 static PCIDeviceInfo via_pm_info = {
 496     .qdev.name          = "VT82C686B_PM",
 497     .qdev.desc          = "PM",
 498     .qdev.size          = sizeof(VT686PMState),
 499     .qdev.vmsd          = &vmstate_acpi,
 500     .init               = vt82c686b_pm_initfn,
 501     .config_write       = pm_write_config,
 502     .qdev.props         = (Property[]) {
 503         DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
 504         DEFINE_PROP_END_OF_LIST(),
 505     }
 506 };
 507
 508 static void vt82c686b_pm_register(void)
 509 {
 510     pci_qdev_register(&via_pm_info);
 511 }
 512
 513 device_init(vt82c686b_pm_register);
 514
 515 static const VMStateDescription vmstate_via = {
 516     .name = "vt82c686b",
 517     .version_id = 1,
 518     .minimum_version_id = 1,
 519     .minimum_version_id_old = 1,
 520     .fields      = (VMStateField []) {
 521         VMSTATE_PCI_DEVICE(dev, VT82C686BState),
 522         VMSTATE_END_OF_LIST()
 523     }
 524 };
 525
 526 /* init the PCI-to-ISA bridge */
 527 static int vt82c686b_initfn(PCIDevice *d)
 528 {
 529     uint8_t *pci_conf;
 530     uint8_t *wmask;
 531     int i;
 532
 533     isa_bus_new(&d->qdev);
 534
 535     pci_conf = d->config;
 536     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA);
 537     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE);
 538     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 539     pci_config_set_prog_interface(pci_conf, 0x0);
 540     pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */
 541
 542     wmask = d->wmask;
 543     for (i = 0x00; i < 0xff; i++) {
 544        if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
 545            wmask[i] = 0x00;
 546        }
 547     }
 548
 549     qemu_register_reset(vt82c686b_reset, d);
 550
 551     return 0;
 552 }
 553
 554 int vt82c686b_init(PCIBus *bus, int devfn)
 555 {
 556     PCIDevice *d;
 557
 558     d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
 559
 560     return d->devfn;
 561 }
 562
 563 static PCIDeviceInfo via_info = {
 564     .qdev.name    = "VT82C686B",
 565     .qdev.desc    = "ISA bridge",
 566     .qdev.size    = sizeof(VT82C686BState),
 567     .qdev.vmsd    = &vmstate_via,
 568     .qdev.no_user = 1,
 569     .init         = vt82c686b_initfn,
 570     .config_write = vt82c686b_write_config,
 571 };
 572
 573 static void vt82c686b_register(void)
 574 {
 575     pci_qdev_register(&via_info);
 576 }
 577 device_init(vt82c686b_register);