hw/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "sysemu.h"
  27 #include "ptimer.h"
  28 #include "qemu-log.h"
  29 #include "fifo.h"
  30 #include "ssi.h"
  31 #include "bitops.h"
  32
  33 #ifdef XILINX_SPIPS_ERR_DEBUG
  34 #define DB_PRINT(...) do { \
  35     fprintf(stderr,  ": %s: ", __func__); \
  36     fprintf(stderr, ## __VA_ARGS__); \
  37     } while (0);
  38 #else
  39     #define DB_PRINT(...)
  40 #endif
  41
  42 /* config register */
  43 #define R_CONFIG            (0x00 / 4)
  44 #define IFMODE              (1 << 31)
  45 #define ENDIAN              (1 << 26)
  46 #define MODEFAIL_GEN_EN     (1 << 17)
  47 #define MAN_START_COM       (1 << 16)
  48 #define MAN_START_EN        (1 << 15)
  49 #define MANUAL_CS           (1 << 14)
  50 #define CS                  (0xF << 10)
  51 #define CS_SHIFT            (10)
  52 #define PERI_SEL            (1 << 9)
  53 #define REF_CLK             (1 << 8)
  54 #define FIFO_WIDTH          (3 << 6)
  55 #define BAUD_RATE_DIV       (7 << 3)
  56 #define CLK_PH              (1 << 2)
  57 #define CLK_POL             (1 << 1)
  58 #define MODE_SEL            (1 << 0)
  59
  60 /* interrupt mechanism */
  61 #define R_INTR_STATUS       (0x04 / 4)
  62 #define R_INTR_EN           (0x08 / 4)
  63 #define R_INTR_DIS          (0x0C / 4)
  64 #define R_INTR_MASK         (0x10 / 4)
  65 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  66 #define IXR_RX_FIFO_FULL        (1 << 5)
  67 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  68 #define IXR_TX_FIFO_FULL        (1 << 3)
  69 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  70 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  71 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  72 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  73
  74 #define R_EN                (0x14 / 4)
  75 #define R_DELAY             (0x18 / 4)
  76 #define R_TX_DATA           (0x1C / 4)
  77 #define R_RX_DATA           (0x20 / 4)
  78 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  79 #define R_TX_THRES          (0x28 / 4)
  80 #define R_RX_THRES          (0x2C / 4)
  81 #define R_TXD1              (0x80 / 4)
  82 #define R_TXD2              (0x84 / 4)
  83 #define R_TXD3              (0x88 / 4)
  84
  85 #define R_LQSPI_CFG         (0xa0 / 4)
  86 #define R_LQSPI_CFG_RESET       0x03A002EB
  87 #define LQSPI_CFG_LQ_MODE       (1 << 31)
  88 #define LQSPI_CFG_TWO_MEM       (1 << 30)
  89 #define LQSPI_CFG_SEP_BUS       (1 << 30)
  90 #define LQSPI_CFG_U_PAGE        (1 << 28)
  91 #define LQSPI_CFG_MODE_EN       (1 << 25)
  92 #define LQSPI_CFG_MODE_WIDTH    8
  93 #define LQSPI_CFG_MODE_SHIFT    16
  94 #define LQSPI_CFG_DUMMY_WIDTH   3
  95 #define LQSPI_CFG_DUMMY_SHIFT   8
  96 #define LQSPI_CFG_INST_CODE     0xFF
  97
  98 #define R_LQSPI_STS         (0xA4 / 4)
  99 #define LQSPI_STS_WR_RECVD      (1 << 1)
 100
 101 #define R_MOD_ID            (0xFC / 4)
 102
 103 #define R_MAX (R_MOD_ID+1)
 104
 105 /* size of TXRX FIFOs */
 106 #define RXFF_A          32
 107 #define TXFF_A          32
 108
 109 /* 16MB per linear region */
 110 #define LQSPI_ADDRESS_BITS 24
 111 /* Bite off 4k chunks at a time */
 112 #define LQSPI_CACHE_SIZE 1024
 113
 114 #define SNOOP_CHECKING 0xFF
 115 #define SNOOP_NONE 0xFE
 116 #define SNOOP_STRIPING 0
 117
 118 typedef struct {
 119     SysBusDevice busdev;
 120     MemoryRegion iomem;
 121     MemoryRegion mmlqspi;
 122
 123     qemu_irq irq;
 124     int irqline;
 125
 126     uint8_t num_cs;
 127     uint8_t num_busses;
 128
 129     uint8_t snoop_state;
 130     qemu_irq *cs_lines;
 131     SSIBus **spi;
 132
 133     Fifo8 rx_fifo;
 134     Fifo8 tx_fifo;
 135
 136     uint8_t num_txrx_bytes;
 137
 138     uint32_t regs[R_MAX];
 139
 140     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
 141     hwaddr lqspi_cached_addr;
 142 } XilinxSPIPS;
 143
 144 static inline int num_effective_busses(XilinxSPIPS *s)
 145 {
 146     return (s->regs[R_LQSPI_STS] & LQSPI_CFG_SEP_BUS &&
 147             s->regs[R_LQSPI_STS] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 148 }
 149
 150 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 151 {
 152     int i, j;
 153     bool found = false;
 154     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 155
 156     for (i = 0; i < s->num_cs; i++) {
 157         for (j = 0; j < num_effective_busses(s); j++) {
 158             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
 159             int cs_to_set = (j * s->num_cs + i + upage) %
 160                                 (s->num_cs * s->num_busses);
 161
 162             if (~field & (1 << i) && !found) {
 163                 DB_PRINT("selecting slave %d\n", i);
 164                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
 165             } else {
 166                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
 167             }
 168         }
 169         if (~field & (1 << i)) {
 170             found = true;
 171         }
 172     }
 173     if (!found) {
 174         s->snoop_state = SNOOP_CHECKING;
 175     }
 176 }
 177
 178 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 179 {
 180     /* These are set/cleared as they occur */
 181     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 182                                 IXR_TX_FIFO_MODE_FAIL);
 183     /* these are pure functions of fifo state, set them here */
 184     s->regs[R_INTR_STATUS] |=
 185         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 186         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 187         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 188         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 189     /* drive external interrupt pin */
 190     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 191                                                                 IXR_ALL);
 192     if (new_irqline != s->irqline) {
 193         s->irqline = new_irqline;
 194         qemu_set_irq(s->irq, s->irqline);
 195     }
 196 }
 197
 198 static void xilinx_spips_reset(DeviceState *d)
 199 {
 200     XilinxSPIPS *s = DO_UPCAST(XilinxSPIPS, busdev.qdev, d);
 201
 202     int i;
 203     for (i = 0; i < R_MAX; i++) {
 204         s->regs[i] = 0;
 205     }
 206
 207     fifo8_reset(&s->rx_fifo);
 208     fifo8_reset(&s->rx_fifo);
 209     /* non zero resets */
 210     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 211     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 212     s->regs[R_TX_THRES] = 1;
 213     s->regs[R_RX_THRES] = 1;
 214     /* FIXME: move magic number definition somewhere sensible */
 215     s->regs[R_MOD_ID] = 0x01090106;
 216     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 217     s->snoop_state = SNOOP_CHECKING;
 218     xilinx_spips_update_ixr(s);
 219     xilinx_spips_update_cs_lines(s);
 220 }
 221
 222 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 223 {
 224     for (;;) {
 225         int i;
 226         uint8_t rx;
 227         uint8_t tx = 0;
 228
 229         for (i = 0; i < num_effective_busses(s); ++i) {
 230             if (!i || s->snoop_state == SNOOP_STRIPING) {
 231                 if (fifo8_is_empty(&s->tx_fifo)) {
 232                     s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 233                     xilinx_spips_update_ixr(s);
 234                     return;
 235                 } else {
 236                     tx = fifo8_pop(&s->tx_fifo);
 237                 }
 238             }
 239             rx = ssi_transfer(s->spi[i], (uint32_t)tx);
 240             DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
 241             if (!i || s->snoop_state == SNOOP_STRIPING) {
 242                 if (fifo8_is_full(&s->rx_fifo)) {
 243                     s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 244                     DB_PRINT("rx FIFO overflow");
 245                 } else {
 246                     fifo8_push(&s->rx_fifo, (uint8_t)rx);
 247                 }
 248             }
 249         }
 250
 251         switch (s->snoop_state) {
 252         case (SNOOP_CHECKING):
 253             switch (tx) { /* new instruction code */
 254             case 0x0b: /* dual/quad output read DOR/QOR */
 255             case 0x6b:
 256                 s->snoop_state = 4;
 257                 break;
 258             /* FIXME: these vary between vendor - set to spansion */
 259             case 0xbb: /* high performance dual read DIOR */
 260                 s->snoop_state = 4;
 261                 break;
 262             case 0xeb: /* high performance quad read QIOR */
 263                 s->snoop_state = 6;
 264                 break;
 265             default:
 266                 s->snoop_state = SNOOP_NONE;
 267             }
 268             break;
 269         case (SNOOP_STRIPING):
 270         case (SNOOP_NONE):
 271             break;
 272         default:
 273             s->snoop_state--;
 274         }
 275     }
 276 }
 277
 278 static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
 279 {
 280     int i;
 281
 282     *value = 0;
 283     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
 284         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
 285         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
 286     }
 287 }
 288
 289 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 290                                                         unsigned size)
 291 {
 292     XilinxSPIPS *s = opaque;
 293     uint32_t mask = ~0;
 294     uint32_t ret;
 295
 296     addr >>= 2;
 297     switch (addr) {
 298     case R_CONFIG:
 299         mask = 0x0002FFFF;
 300         break;
 301     case R_INTR_STATUS:
 302     case R_INTR_MASK:
 303         mask = IXR_ALL;
 304         break;
 305     case  R_EN:
 306         mask = 0x1;
 307         break;
 308     case R_SLAVE_IDLE_COUNT:
 309         mask = 0xFF;
 310         break;
 311     case R_MOD_ID:
 312         mask = 0x01FFFFFF;
 313         break;
 314     case R_INTR_EN:
 315     case R_INTR_DIS:
 316     case R_TX_DATA:
 317         mask = 0;
 318         break;
 319     case R_RX_DATA:
 320         rx_data_bytes(s, &ret, s->num_txrx_bytes);
 321         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 322         xilinx_spips_update_ixr(s);
 323         return ret;
 324     }
 325     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 326     return s->regs[addr] & mask;
 327
 328 }
 329
 330 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 331 {
 332     int i;
 333     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
 334         if (s->regs[R_CONFIG] & ENDIAN) {
 335             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
 336             value <<= 8;
 337         } else {
 338             fifo8_push(&s->tx_fifo, (uint8_t)value);
 339             value >>= 8;
 340         }
 341     }
 342 }
 343
 344 static void xilinx_spips_write(void *opaque, hwaddr addr,
 345                                         uint64_t value, unsigned size)
 346 {
 347     int mask = ~0;
 348     int man_start_com = 0;
 349     XilinxSPIPS *s = opaque;
 350
 351     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 352     addr >>= 2;
 353     switch (addr) {
 354     case R_CONFIG:
 355         mask = 0x0002FFFF;
 356         if (value & MAN_START_COM) {
 357             man_start_com = 1;
 358         }
 359         break;
 360     case R_INTR_STATUS:
 361         mask = IXR_ALL;
 362         s->regs[R_INTR_STATUS] &= ~(mask & value);
 363         goto no_reg_update;
 364     case R_INTR_DIS:
 365         mask = IXR_ALL;
 366         s->regs[R_INTR_MASK] &= ~(mask & value);
 367         goto no_reg_update;
 368     case R_INTR_EN:
 369         mask = IXR_ALL;
 370         s->regs[R_INTR_MASK] |= mask & value;
 371         goto no_reg_update;
 372     case R_EN:
 373         mask = 0x1;
 374         break;
 375     case R_SLAVE_IDLE_COUNT:
 376         mask = 0xFF;
 377         break;
 378     case R_RX_DATA:
 379     case R_INTR_MASK:
 380     case R_MOD_ID:
 381         mask = 0;
 382         break;
 383     case R_TX_DATA:
 384         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
 385         goto no_reg_update;
 386     case R_TXD1:
 387         tx_data_bytes(s, (uint32_t)value, 1);
 388         goto no_reg_update;
 389     case R_TXD2:
 390         tx_data_bytes(s, (uint32_t)value, 2);
 391         goto no_reg_update;
 392     case R_TXD3:
 393         tx_data_bytes(s, (uint32_t)value, 3);
 394         goto no_reg_update;
 395     }
 396     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 397 no_reg_update:
 398     if (man_start_com) {
 399         xilinx_spips_flush_txfifo(s);
 400     }
 401     xilinx_spips_update_ixr(s);
 402     xilinx_spips_update_cs_lines(s);
 403 }
 404
 405 static const MemoryRegionOps spips_ops = {
 406     .read = xilinx_spips_read,
 407     .write = xilinx_spips_write,
 408     .endianness = DEVICE_LITTLE_ENDIAN,
 409 };
 410
 411 #define LQSPI_CACHE_SIZE 1024
 412
 413 static uint64_t
 414 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 415 {
 416     int i;
 417     XilinxSPIPS *s = opaque;
 418
 419     if (addr >= s->lqspi_cached_addr &&
 420             addr <= s->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
 421         return s->lqspi_buf[(addr - s->lqspi_cached_addr) >> 2];
 422     } else {
 423         int flash_addr = (addr / num_effective_busses(s));
 424         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
 425         int cache_entry = 0;
 426
 427         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 428
 429         fifo8_reset(&s->tx_fifo);
 430         fifo8_reset(&s->rx_fifo);
 431
 432         s->regs[R_CONFIG] &= ~CS;
 433         s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS;
 434         xilinx_spips_update_cs_lines(s);
 435
 436         /* instruction */
 437         DB_PRINT("pushing read instruction: %02x\n",
 438                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
 439         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
 440         /* read address */
 441         DB_PRINT("pushing read address %06x\n", flash_addr);
 442         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
 443         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
 444         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
 445         /* mode bits */
 446         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
 447             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
 448                                               LQSPI_CFG_MODE_SHIFT,
 449                                               LQSPI_CFG_MODE_WIDTH));
 450         }
 451         /* dummy bytes */
 452         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
 453                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
 454             DB_PRINT("pushing dummy byte\n");
 455             fifo8_push(&s->tx_fifo, 0);
 456         }
 457         xilinx_spips_flush_txfifo(s);
 458         fifo8_reset(&s->rx_fifo);
 459
 460         DB_PRINT("starting QSPI data read\n");
 461
 462         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
 463             tx_data_bytes(s, 0, 4);
 464             xilinx_spips_flush_txfifo(s);
 465             rx_data_bytes(s, &s->lqspi_buf[cache_entry], 4);
 466             cache_entry++;
 467         }
 468
 469         s->regs[R_CONFIG] |= CS;
 470         xilinx_spips_update_cs_lines(s);
 471
 472         s->lqspi_cached_addr = addr;
 473         return lqspi_read(opaque, addr, size);
 474     }
 475 }
 476
 477 static const MemoryRegionOps lqspi_ops = {
 478     .read = lqspi_read,
 479     .endianness = DEVICE_NATIVE_ENDIAN,
 480     .valid = {
 481         .min_access_size = 4,
 482         .max_access_size = 4
 483     }
 484 };
 485
 486 static int xilinx_spips_init(SysBusDevice *dev)
 487 {
 488     XilinxSPIPS *s = FROM_SYSBUS(typeof(*s), dev);
 489     int i;
 490
 491     DB_PRINT("inited device model\n");
 492
 493     s->spi = g_new(SSIBus *, s->num_busses);
 494     for (i = 0; i < s->num_busses; ++i) {
 495         char bus_name[16];
 496         snprintf(bus_name, 16, "spi%d", i);
 497         s->spi[i] = ssi_create_bus(&dev->qdev, bus_name);
 498     }
 499
 500     s->cs_lines = g_new(qemu_irq, s->num_cs * s->num_busses);
 501     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
 502     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
 503     sysbus_init_irq(dev, &s->irq);
 504     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
 505         sysbus_init_irq(dev, &s->cs_lines[i]);
 506     }
 507
 508     memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
 509     sysbus_init_mmio(dev, &s->iomem);
 510
 511     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
 512                           (1 << LQSPI_ADDRESS_BITS) * 2);
 513     sysbus_init_mmio(dev, &s->mmlqspi);
 514
 515     s->irqline = -1;
 516     s->lqspi_cached_addr = ~0ULL;
 517
 518     fifo8_create(&s->rx_fifo, RXFF_A);
 519     fifo8_create(&s->tx_fifo, TXFF_A);
 520
 521     return 0;
 522 }
 523
 524 static int xilinx_spips_post_load(void *opaque, int version_id)
 525 {
 526     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 527     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 528     return 0;
 529 }
 530
 531 static const VMStateDescription vmstate_xilinx_spips = {
 532     .name = "xilinx_spips",
 533     .version_id = 2,
 534     .minimum_version_id = 2,
 535     .minimum_version_id_old = 2,
 536     .post_load = xilinx_spips_post_load,
 537     .fields = (VMStateField[]) {
 538         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 539         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 540         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 541         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
 542         VMSTATE_END_OF_LIST()
 543     }
 544 };
 545
 546 static Property xilinx_spips_properties[] = {
 547     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
 548     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
 549     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
 550     DEFINE_PROP_END_OF_LIST(),
 551 };
 552 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 553 {
 554     DeviceClass *dc = DEVICE_CLASS(klass);
 555     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 556
 557     sdc->init = xilinx_spips_init;
 558     dc->reset = xilinx_spips_reset;
 559     dc->props = xilinx_spips_properties;
 560     dc->vmsd = &vmstate_xilinx_spips;
 561 }
 562
 563 static const TypeInfo xilinx_spips_info = {
 564     .name  = "xilinx,spips",
 565     .parent = TYPE_SYS_BUS_DEVICE,
 566     .instance_size  = sizeof(XilinxSPIPS),
 567     .class_init = xilinx_spips_class_init,
 568 };
 569
 570 static void xilinx_spips_register_types(void)
 571 {
 572     type_register_static(&xilinx_spips_info);
 573 }
 574
 575 type_init(xilinx_spips_register_types)