include/exec/cpu-defs.h

   1 /*
   2  * common defines for all CPUs
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_DEFS_H
  20 #define CPU_DEFS_H
  21
  22 #ifndef NEED_CPU_H
  23 #error cpu.h included from common code
  24 #endif
  25
  26 #include "config.h"
  27 #include <setjmp.h>
  28 #include <inttypes.h>
  29 #include "qemu/osdep.h"
  30 #include "qemu/queue.h"
  31 #include "exec/hwaddr.h"
  32
  33 #ifndef TARGET_LONG_BITS
  34 #error TARGET_LONG_BITS must be defined before including this header
  35 #endif
  36
  37 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
  38
  39 typedef int32_t target_int __attribute__((aligned(TARGET_INT_ALIGNMENT)));
  40 typedef uint32_t target_uint __attribute__((aligned(TARGET_INT_ALIGNMENT)));
  41 typedef int64_t target_llong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
  42 typedef uint64_t target_ullong __attribute__((aligned(TARGET_LLONG_ALIGNMENT)));
  43 /* target_ulong is the type of a virtual address */
  44 #if TARGET_LONG_SIZE == 4
  45 typedef int32_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  46 typedef uint32_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  47 #define TARGET_FMT_lx "%08x"
  48 #define TARGET_FMT_ld "%d"
  49 #define TARGET_FMT_lu "%u"
  50 #elif TARGET_LONG_SIZE == 8
  51 typedef int64_t target_long __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  52 typedef uint64_t target_ulong __attribute__((aligned(TARGET_LONG_ALIGNMENT)));
  53 #define TARGET_FMT_lx "%016" PRIx64
  54 #define TARGET_FMT_ld "%" PRId64
  55 #define TARGET_FMT_lu "%" PRIu64
  56 #else
  57 #error TARGET_LONG_SIZE undefined
  58 #endif
  59
  60 #define EXCP_INTERRUPT  0x10000 /* async interruption */
  61 #define EXCP_HLT        0x10001 /* hlt instruction reached */
  62 #define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
  63 #define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
  64
  65 #define TB_JMP_CACHE_BITS 12
  66 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
  67
  68 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
  69    addresses on the same page.  The top bits are the same.  This allows
  70    TLB invalidation to quickly clear a subset of the hash table.  */
  71 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
  72 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
  73 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
  74 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
  75
  76 #if !defined(CONFIG_USER_ONLY)
  77 #define CPU_TLB_BITS 8
  78 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
  79
  80 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
  81 #define CPU_TLB_ENTRY_BITS 4
  82 #else
  83 #define CPU_TLB_ENTRY_BITS 5
  84 #endif
  85
  86 typedef struct CPUTLBEntry {
  87     /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
  88        bit TARGET_PAGE_BITS-1..4  : Nonzero for accesses that should not
  89                                     go directly to ram.
  90        bit 3                      : indicates that the entry is invalid
  91        bit 2..0                   : zero
  92     */
  93     target_ulong addr_read;
  94     target_ulong addr_write;
  95     target_ulong addr_code;
  96     /* Addend to virtual address to get host address.  IO accesses
  97        use the corresponding iotlb value.  */
  98     uintptr_t addend;
  99     /* padding to get a power of two size */
 100     uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
 101                   (sizeof(target_ulong) * 3 +
 102                    ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
 103                    sizeof(uintptr_t))];
 104 } CPUTLBEntry;
 105
 106 extern int CPUTLBEntry_wrong_size[sizeof(CPUTLBEntry) == (1 << CPU_TLB_ENTRY_BITS) ? 1 : -1];
 107
 108 #define CPU_COMMON_TLB \
 109     /* The meaning of the MMU modes is defined in the target code. */   \
 110     CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
 111     hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE];               \
 112     target_ulong tlb_flush_addr;                                        \
 113     target_ulong tlb_flush_mask;
 114
 115 #else
 116
 117 #define CPU_COMMON_TLB
 118
 119 #endif
 120
 121
 122 #ifdef HOST_WORDS_BIGENDIAN
 123 typedef struct icount_decr_u16 {
 124     uint16_t high;
 125     uint16_t low;
 126 } icount_decr_u16;
 127 #else
 128 typedef struct icount_decr_u16 {
 129     uint16_t low;
 130     uint16_t high;
 131 } icount_decr_u16;
 132 #endif
 133
 134 typedef struct CPUBreakpoint {
 135     target_ulong pc;
 136     int flags; /* BP_* */
 137     QTAILQ_ENTRY(CPUBreakpoint) entry;
 138 } CPUBreakpoint;
 139
 140 typedef struct CPUWatchpoint {
 141     target_ulong vaddr;
 142     target_ulong len_mask;
 143     int flags; /* BP_* */
 144     QTAILQ_ENTRY(CPUWatchpoint) entry;
 145 } CPUWatchpoint;
 146
 147 #define CPU_TEMP_BUF_NLONGS 128
 148 #define CPU_COMMON                                                      \
 149     /* soft mmu support */                                              \
 150     /* in order to avoid passing too many arguments to the MMIO         \
 151        helpers, we store some rarely used information in the CPU        \
 152        context) */                                                      \
 153     uintptr_t mem_io_pc; /* host pc at which the memory was             \
 154                             accessed */                                 \
 155     target_ulong mem_io_vaddr; /* target virtual addr at which the      \
 156                                      memory was accessed */             \
 157     CPU_COMMON_TLB                                                      \
 158     struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
 159     /* buffer for temporaries in the code generator */                  \
 160     long temp_buf[CPU_TEMP_BUF_NLONGS];                                 \
 161                                                                         \
 162     int64_t icount_extra; /* Instructions until next timer event.  */   \
 163     /* Number of cycles left, with interrupt flag in high bit.          \
 164        This allows a single read-compare-cbranch-write sequence to test \
 165        for both decrementer underflow and exceptions.  */               \
 166     union {                                                             \
 167         uint32_t u32;                                                   \
 168         icount_decr_u16 u16;                                            \
 169     } icount_decr;                                                      \
 170     uint32_t can_do_io; /* nonzero if memory mapped IO is safe.  */     \
 171                                                                         \
 172     /* from this point: preserved by CPU reset */                       \
 173     /* ice debug support */                                             \
 174     QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;            \
 175     int singlestep_enabled;                                             \
 176                                                                         \
 177     QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;            \
 178     CPUWatchpoint *watchpoint_hit;                                      \
 179                                                                         \
 180     struct GDBRegisterState *gdb_regs;                                  \
 181                                                                         \
 182     /* Core interrupt code */                                           \
 183     sigjmp_buf jmp_env;                                                 \
 184     int exception_index;                                                \
 185                                                                         \
 186     CPUArchState *next_cpu; /* next CPU sharing TB cache */                 \
 187     /* user data */                                                     \
 188     void *opaque;                                                       \
 189                                                                         \
 190     const char *cpu_model_str;
 191
 192 #endif