include/hw/arm/aspeed_soc.h

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #ifndef ASPEED_SOC_H
  13 #define ASPEED_SOC_H
  14
  15 #include "hw/cpu/a15mpcore.h"
  16 #include "hw/arm/armv7m.h"
  17 #include "hw/intc/aspeed_vic.h"
  18 #include "hw/misc/aspeed_scu.h"
  19 #include "hw/adc/aspeed_adc.h"
  20 #include "hw/misc/aspeed_sdmc.h"
  21 #include "hw/misc/aspeed_xdma.h"
  22 #include "hw/timer/aspeed_timer.h"
  23 #include "hw/rtc/aspeed_rtc.h"
  24 #include "hw/i2c/aspeed_i2c.h"
  25 #include "hw/misc/aspeed_i3c.h"
  26 #include "hw/ssi/aspeed_smc.h"
  27 #include "hw/misc/aspeed_hace.h"
  28 #include "hw/misc/aspeed_sbc.h"
  29 #include "hw/watchdog/wdt_aspeed.h"
  30 #include "hw/net/ftgmac100.h"
  31 #include "target/arm/cpu.h"
  32 #include "hw/gpio/aspeed_gpio.h"
  33 #include "hw/sd/aspeed_sdhci.h"
  34 #include "hw/usb/hcd-ehci.h"
  35 #include "qom/object.h"
  36 #include "hw/misc/aspeed_lpc.h"
  37 #include "hw/misc/unimp.h"
  38 #include "hw/misc/aspeed_peci.h"
  39
  40 #define ASPEED_SPIS_NUM  2
  41 #define ASPEED_EHCIS_NUM 2
  42 #define ASPEED_WDTS_NUM  4
  43 #define ASPEED_CPUS_NUM  2
  44 #define ASPEED_MACS_NUM  4
  45
  46 struct AspeedSoCState {
  47     /*< private >*/
  48     DeviceState parent;
  49
  50     /*< public >*/
  51     ARMCPU cpu[ASPEED_CPUS_NUM];
  52     A15MPPrivState     a7mpcore;
  53     ARMv7MState        armv7m;
  54     MemoryRegion *memory;
  55     MemoryRegion *dram_mr;
  56     MemoryRegion dram_container;
  57     MemoryRegion sram;
  58     AspeedVICState vic;
  59     AspeedRtcState rtc;
  60     AspeedTimerCtrlState timerctrl;
  61     AspeedI2CState i2c;
  62     AspeedI3CState i3c;
  63     AspeedSCUState scu;
  64     AspeedHACEState hace;
  65     AspeedXDMAState xdma;
  66     AspeedADCState adc;
  67     AspeedSMCState fmc;
  68     AspeedSMCState spi[ASPEED_SPIS_NUM];
  69     EHCISysBusState ehci[ASPEED_EHCIS_NUM];
  70     AspeedSBCState sbc;
  71     UnimplementedDeviceState sbc_unimplemented;
  72     AspeedSDMCState sdmc;
  73     AspeedWDTState wdt[ASPEED_WDTS_NUM];
  74     FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
  75     AspeedMiiState mii[ASPEED_MACS_NUM];
  76     AspeedGPIOState gpio;
  77     AspeedGPIOState gpio_1_8v;
  78     AspeedSDHCIState sdhci;
  79     AspeedSDHCIState emmc;
  80     AspeedLPCState lpc;
  81     AspeedPECIState peci;
  82     uint32_t uart_default;
  83     Clock *sysclk;
  84     UnimplementedDeviceState iomem;
  85     UnimplementedDeviceState video;
  86     UnimplementedDeviceState emmc_boot_controller;
  87     UnimplementedDeviceState dpmcu;
  88 };
  89
  90 #define TYPE_ASPEED_SOC "aspeed-soc"
  91 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
  92
  93 struct AspeedSoCClass {
  94     DeviceClass parent_class;
  95
  96     const char *name;
  97     const char *cpu_type;
  98     uint32_t silicon_rev;
  99     uint64_t sram_size;
 100     int spis_num;
 101     int ehcis_num;
 102     int wdts_num;
 103     int macs_num;
 104     int uarts_num;
 105     const int *irqmap;
 106     const hwaddr *memmap;
 107     uint32_t num_cpus;
 108     qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
 109 };
 110
 111
 112 enum {
 113     ASPEED_DEV_IOMEM,
 114     ASPEED_DEV_UART1,
 115     ASPEED_DEV_UART2,
 116     ASPEED_DEV_UART3,
 117     ASPEED_DEV_UART4,
 118     ASPEED_DEV_UART5,
 119     ASPEED_DEV_UART6,
 120     ASPEED_DEV_UART7,
 121     ASPEED_DEV_UART8,
 122     ASPEED_DEV_UART9,
 123     ASPEED_DEV_UART10,
 124     ASPEED_DEV_UART11,
 125     ASPEED_DEV_UART12,
 126     ASPEED_DEV_UART13,
 127     ASPEED_DEV_VUART,
 128     ASPEED_DEV_FMC,
 129     ASPEED_DEV_SPI1,
 130     ASPEED_DEV_SPI2,
 131     ASPEED_DEV_EHCI1,
 132     ASPEED_DEV_EHCI2,
 133     ASPEED_DEV_VIC,
 134     ASPEED_DEV_SDMC,
 135     ASPEED_DEV_SCU,
 136     ASPEED_DEV_ADC,
 137     ASPEED_DEV_SBC,
 138     ASPEED_DEV_EMMC_BC,
 139     ASPEED_DEV_VIDEO,
 140     ASPEED_DEV_SRAM,
 141     ASPEED_DEV_SDHCI,
 142     ASPEED_DEV_GPIO,
 143     ASPEED_DEV_GPIO_1_8V,
 144     ASPEED_DEV_RTC,
 145     ASPEED_DEV_TIMER1,
 146     ASPEED_DEV_TIMER2,
 147     ASPEED_DEV_TIMER3,
 148     ASPEED_DEV_TIMER4,
 149     ASPEED_DEV_TIMER5,
 150     ASPEED_DEV_TIMER6,
 151     ASPEED_DEV_TIMER7,
 152     ASPEED_DEV_TIMER8,
 153     ASPEED_DEV_WDT,
 154     ASPEED_DEV_PWM,
 155     ASPEED_DEV_LPC,
 156     ASPEED_DEV_IBT,
 157     ASPEED_DEV_I2C,
 158     ASPEED_DEV_PECI,
 159     ASPEED_DEV_ETH1,
 160     ASPEED_DEV_ETH2,
 161     ASPEED_DEV_ETH3,
 162     ASPEED_DEV_ETH4,
 163     ASPEED_DEV_MII1,
 164     ASPEED_DEV_MII2,
 165     ASPEED_DEV_MII3,
 166     ASPEED_DEV_MII4,
 167     ASPEED_DEV_SDRAM,
 168     ASPEED_DEV_XDMA,
 169     ASPEED_DEV_EMMC,
 170     ASPEED_DEV_KCS,
 171     ASPEED_DEV_HACE,
 172     ASPEED_DEV_DPMCU,
 173     ASPEED_DEV_DP,
 174     ASPEED_DEV_I3C,
 175 };
 176
 177 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
 178 void aspeed_soc_uart_init(AspeedSoCState *s);
 179 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
 180 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
 181 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
 182                                    const char *name, hwaddr addr,
 183                                    uint64_t size);
 184
 185 #endif /* ASPEED_SOC_H */