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git.proxmox.com Git - qemu.git/blob - include/qemu/atomic.h
1 #ifndef __QEMU_BARRIER_H
2 #define __QEMU_BARRIER_H 1
5 #define barrier() asm volatile("" ::: "memory")
9 #include "qemu/compiler.h" /* QEMU_GNUC_PREREQ */
12 * Because of the strongly ordered x86 storage model, wmb() and rmb() are nops
13 * on x86(well, a compiler barrier only). Well, at least as long as
14 * qemu doesn't do accesses to write-combining memory or non-temporal
15 * load/stores from C code.
17 #define smp_wmb() barrier()
18 #define smp_rmb() barrier()
21 * We use GCC builtin if it's available, as that can use
22 * mfence on 32 bit as well, e.g. if built with -march=pentium-m.
23 * However, on i386, there seem to be known bugs as recently as 4.3.
25 #if QEMU_GNUC_PREREQ(4, 4)
26 #define smp_mb() __sync_synchronize()
28 #define smp_mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
31 #elif defined(__x86_64__)
33 #define smp_wmb() barrier()
34 #define smp_rmb() barrier()
35 #define smp_mb() asm volatile("mfence" ::: "memory")
37 #elif defined(_ARCH_PPC)
40 * We use an eieio() for wmb() on powerpc. This assumes we don't
41 * need to order cacheable and non-cacheable stores with respect to
44 #define smp_wmb() asm volatile("eieio" ::: "memory")
46 #if defined(__powerpc64__)
47 #define smp_rmb() asm volatile("lwsync" ::: "memory")
49 #define smp_rmb() asm volatile("sync" ::: "memory")
52 #define smp_mb() asm volatile("sync" ::: "memory")
57 * For (host) platforms we don't have explicit barrier definitions
58 * for, we use the gcc __sync_synchronize() primitive to generate a
59 * full barrier. This should be safe on all platforms, though it may
60 * be overkill for wmb() and rmb().
62 #define smp_wmb() __sync_synchronize()
63 #define smp_mb() __sync_synchronize()
64 #define smp_rmb() __sync_synchronize()