]> git.proxmox.com Git - qemu.git/blob - linux-user/main.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
target-alpha: Reduce internal processor registers for user-mode.
[qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27
28 #include "qemu.h"
29 #include "qemu-common.h"
30 #include "cache-utils.h"
31 /* For tb_lock */
32 #include "exec-all.h"
33
34
35 #include "envlist.h"
36
37 #define DEBUG_LOGFILE "/tmp/qemu.log"
38
39 char *exec_path;
40
41 int singlestep;
42 #if defined(CONFIG_USE_GUEST_BASE)
43 unsigned long mmap_min_addr;
44 unsigned long guest_base;
45 int have_guest_base;
46 #endif
47
48 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
49 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
50
51 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
52 we allocate a bigger stack. Need a better solution, for example
53 by remapping the process stack directly at the right place */
54 unsigned long x86_stack_size = 512 * 1024;
55
56 void gemu_log(const char *fmt, ...)
57 {
58 va_list ap;
59
60 va_start(ap, fmt);
61 vfprintf(stderr, fmt, ap);
62 va_end(ap);
63 }
64
65 #if defined(TARGET_I386)
66 int cpu_get_pic_interrupt(CPUState *env)
67 {
68 return -1;
69 }
70 #endif
71
72 /* timers for rdtsc */
73
74 #if 0
75
76 static uint64_t emu_time;
77
78 int64_t cpu_get_real_ticks(void)
79 {
80 return emu_time++;
81 }
82
83 #endif
84
85 #if defined(CONFIG_USE_NPTL)
86 /***********************************************************/
87 /* Helper routines for implementing atomic operations. */
88
89 /* To implement exclusive operations we force all cpus to syncronise.
90 We don't require a full sync, only that no cpus are executing guest code.
91 The alternative is to map target atomic ops onto host equivalents,
92 which requires quite a lot of per host/target work. */
93 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
94 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
95 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
96 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
97 static int pending_cpus;
98
99 /* Make sure everything is in a consistent state for calling fork(). */
100 void fork_start(void)
101 {
102 pthread_mutex_lock(&tb_lock);
103 pthread_mutex_lock(&exclusive_lock);
104 mmap_fork_start();
105 }
106
107 void fork_end(int child)
108 {
109 mmap_fork_end(child);
110 if (child) {
111 /* Child processes created by fork() only have a single thread.
112 Discard information about the parent threads. */
113 first_cpu = thread_env;
114 thread_env->next_cpu = NULL;
115 pending_cpus = 0;
116 pthread_mutex_init(&exclusive_lock, NULL);
117 pthread_mutex_init(&cpu_list_mutex, NULL);
118 pthread_cond_init(&exclusive_cond, NULL);
119 pthread_cond_init(&exclusive_resume, NULL);
120 pthread_mutex_init(&tb_lock, NULL);
121 gdbserver_fork(thread_env);
122 } else {
123 pthread_mutex_unlock(&exclusive_lock);
124 pthread_mutex_unlock(&tb_lock);
125 }
126 }
127
128 /* Wait for pending exclusive operations to complete. The exclusive lock
129 must be held. */
130 static inline void exclusive_idle(void)
131 {
132 while (pending_cpus) {
133 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
134 }
135 }
136
137 /* Start an exclusive operation.
138 Must only be called from outside cpu_arm_exec. */
139 static inline void start_exclusive(void)
140 {
141 CPUState *other;
142 pthread_mutex_lock(&exclusive_lock);
143 exclusive_idle();
144
145 pending_cpus = 1;
146 /* Make all other cpus stop executing. */
147 for (other = first_cpu; other; other = other->next_cpu) {
148 if (other->running) {
149 pending_cpus++;
150 cpu_exit(other);
151 }
152 }
153 if (pending_cpus > 1) {
154 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
155 }
156 }
157
158 /* Finish an exclusive operation. */
159 static inline void end_exclusive(void)
160 {
161 pending_cpus = 0;
162 pthread_cond_broadcast(&exclusive_resume);
163 pthread_mutex_unlock(&exclusive_lock);
164 }
165
166 /* Wait for exclusive ops to finish, and begin cpu execution. */
167 static inline void cpu_exec_start(CPUState *env)
168 {
169 pthread_mutex_lock(&exclusive_lock);
170 exclusive_idle();
171 env->running = 1;
172 pthread_mutex_unlock(&exclusive_lock);
173 }
174
175 /* Mark cpu as not executing, and release pending exclusive ops. */
176 static inline void cpu_exec_end(CPUState *env)
177 {
178 pthread_mutex_lock(&exclusive_lock);
179 env->running = 0;
180 if (pending_cpus > 1) {
181 pending_cpus--;
182 if (pending_cpus == 1) {
183 pthread_cond_signal(&exclusive_cond);
184 }
185 }
186 exclusive_idle();
187 pthread_mutex_unlock(&exclusive_lock);
188 }
189
190 void cpu_list_lock(void)
191 {
192 pthread_mutex_lock(&cpu_list_mutex);
193 }
194
195 void cpu_list_unlock(void)
196 {
197 pthread_mutex_unlock(&cpu_list_mutex);
198 }
199 #else /* if !CONFIG_USE_NPTL */
200 /* These are no-ops because we are not threadsafe. */
201 static inline void cpu_exec_start(CPUState *env)
202 {
203 }
204
205 static inline void cpu_exec_end(CPUState *env)
206 {
207 }
208
209 static inline void start_exclusive(void)
210 {
211 }
212
213 static inline void end_exclusive(void)
214 {
215 }
216
217 void fork_start(void)
218 {
219 }
220
221 void fork_end(int child)
222 {
223 if (child) {
224 gdbserver_fork(thread_env);
225 }
226 }
227
228 void cpu_list_lock(void)
229 {
230 }
231
232 void cpu_list_unlock(void)
233 {
234 }
235 #endif
236
237
238 #ifdef TARGET_I386
239 /***********************************************************/
240 /* CPUX86 core interface */
241
242 void cpu_smm_update(CPUState *env)
243 {
244 }
245
246 uint64_t cpu_get_tsc(CPUX86State *env)
247 {
248 return cpu_get_real_ticks();
249 }
250
251 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
252 int flags)
253 {
254 unsigned int e1, e2;
255 uint32_t *p;
256 e1 = (addr << 16) | (limit & 0xffff);
257 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
258 e2 |= flags;
259 p = ptr;
260 p[0] = tswap32(e1);
261 p[1] = tswap32(e2);
262 }
263
264 static uint64_t *idt_table;
265 #ifdef TARGET_X86_64
266 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
267 uint64_t addr, unsigned int sel)
268 {
269 uint32_t *p, e1, e2;
270 e1 = (addr & 0xffff) | (sel << 16);
271 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
272 p = ptr;
273 p[0] = tswap32(e1);
274 p[1] = tswap32(e2);
275 p[2] = tswap32(addr >> 32);
276 p[3] = 0;
277 }
278 /* only dpl matters as we do only user space emulation */
279 static void set_idt(int n, unsigned int dpl)
280 {
281 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
282 }
283 #else
284 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
285 uint32_t addr, unsigned int sel)
286 {
287 uint32_t *p, e1, e2;
288 e1 = (addr & 0xffff) | (sel << 16);
289 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
290 p = ptr;
291 p[0] = tswap32(e1);
292 p[1] = tswap32(e2);
293 }
294
295 /* only dpl matters as we do only user space emulation */
296 static void set_idt(int n, unsigned int dpl)
297 {
298 set_gate(idt_table + n, 0, dpl, 0, 0);
299 }
300 #endif
301
302 void cpu_loop(CPUX86State *env)
303 {
304 int trapnr;
305 abi_ulong pc;
306 target_siginfo_t info;
307
308 for(;;) {
309 trapnr = cpu_x86_exec(env);
310 switch(trapnr) {
311 case 0x80:
312 /* linux syscall from int $0x80 */
313 env->regs[R_EAX] = do_syscall(env,
314 env->regs[R_EAX],
315 env->regs[R_EBX],
316 env->regs[R_ECX],
317 env->regs[R_EDX],
318 env->regs[R_ESI],
319 env->regs[R_EDI],
320 env->regs[R_EBP]);
321 break;
322 #ifndef TARGET_ABI32
323 case EXCP_SYSCALL:
324 /* linux syscall from syscall intruction */
325 env->regs[R_EAX] = do_syscall(env,
326 env->regs[R_EAX],
327 env->regs[R_EDI],
328 env->regs[R_ESI],
329 env->regs[R_EDX],
330 env->regs[10],
331 env->regs[8],
332 env->regs[9]);
333 env->eip = env->exception_next_eip;
334 break;
335 #endif
336 case EXCP0B_NOSEG:
337 case EXCP0C_STACK:
338 info.si_signo = SIGBUS;
339 info.si_errno = 0;
340 info.si_code = TARGET_SI_KERNEL;
341 info._sifields._sigfault._addr = 0;
342 queue_signal(env, info.si_signo, &info);
343 break;
344 case EXCP0D_GPF:
345 /* XXX: potential problem if ABI32 */
346 #ifndef TARGET_X86_64
347 if (env->eflags & VM_MASK) {
348 handle_vm86_fault(env);
349 } else
350 #endif
351 {
352 info.si_signo = SIGSEGV;
353 info.si_errno = 0;
354 info.si_code = TARGET_SI_KERNEL;
355 info._sifields._sigfault._addr = 0;
356 queue_signal(env, info.si_signo, &info);
357 }
358 break;
359 case EXCP0E_PAGE:
360 info.si_signo = SIGSEGV;
361 info.si_errno = 0;
362 if (!(env->error_code & 1))
363 info.si_code = TARGET_SEGV_MAPERR;
364 else
365 info.si_code = TARGET_SEGV_ACCERR;
366 info._sifields._sigfault._addr = env->cr[2];
367 queue_signal(env, info.si_signo, &info);
368 break;
369 case EXCP00_DIVZ:
370 #ifndef TARGET_X86_64
371 if (env->eflags & VM_MASK) {
372 handle_vm86_trap(env, trapnr);
373 } else
374 #endif
375 {
376 /* division by zero */
377 info.si_signo = SIGFPE;
378 info.si_errno = 0;
379 info.si_code = TARGET_FPE_INTDIV;
380 info._sifields._sigfault._addr = env->eip;
381 queue_signal(env, info.si_signo, &info);
382 }
383 break;
384 case EXCP01_DB:
385 case EXCP03_INT3:
386 #ifndef TARGET_X86_64
387 if (env->eflags & VM_MASK) {
388 handle_vm86_trap(env, trapnr);
389 } else
390 #endif
391 {
392 info.si_signo = SIGTRAP;
393 info.si_errno = 0;
394 if (trapnr == EXCP01_DB) {
395 info.si_code = TARGET_TRAP_BRKPT;
396 info._sifields._sigfault._addr = env->eip;
397 } else {
398 info.si_code = TARGET_SI_KERNEL;
399 info._sifields._sigfault._addr = 0;
400 }
401 queue_signal(env, info.si_signo, &info);
402 }
403 break;
404 case EXCP04_INTO:
405 case EXCP05_BOUND:
406 #ifndef TARGET_X86_64
407 if (env->eflags & VM_MASK) {
408 handle_vm86_trap(env, trapnr);
409 } else
410 #endif
411 {
412 info.si_signo = SIGSEGV;
413 info.si_errno = 0;
414 info.si_code = TARGET_SI_KERNEL;
415 info._sifields._sigfault._addr = 0;
416 queue_signal(env, info.si_signo, &info);
417 }
418 break;
419 case EXCP06_ILLOP:
420 info.si_signo = SIGILL;
421 info.si_errno = 0;
422 info.si_code = TARGET_ILL_ILLOPN;
423 info._sifields._sigfault._addr = env->eip;
424 queue_signal(env, info.si_signo, &info);
425 break;
426 case EXCP_INTERRUPT:
427 /* just indicate that signals should be handled asap */
428 break;
429 case EXCP_DEBUG:
430 {
431 int sig;
432
433 sig = gdb_handlesig (env, TARGET_SIGTRAP);
434 if (sig)
435 {
436 info.si_signo = sig;
437 info.si_errno = 0;
438 info.si_code = TARGET_TRAP_BRKPT;
439 queue_signal(env, info.si_signo, &info);
440 }
441 }
442 break;
443 default:
444 pc = env->segs[R_CS].base + env->eip;
445 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
446 (long)pc, trapnr);
447 abort();
448 }
449 process_pending_signals(env);
450 }
451 }
452 #endif
453
454 #ifdef TARGET_ARM
455
456 static void arm_cache_flush(abi_ulong start, abi_ulong last)
457 {
458 abi_ulong addr, last1;
459
460 if (last < start)
461 return;
462 addr = start;
463 for(;;) {
464 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
465 if (last1 > last)
466 last1 = last;
467 tb_invalidate_page_range(addr, last1 + 1);
468 if (last1 == last)
469 break;
470 addr = last1 + 1;
471 }
472 }
473
474 /* Handle a jump to the kernel code page. */
475 static int
476 do_kernel_trap(CPUARMState *env)
477 {
478 uint32_t addr;
479 uint32_t cpsr;
480 uint32_t val;
481
482 switch (env->regs[15]) {
483 case 0xffff0fa0: /* __kernel_memory_barrier */
484 /* ??? No-op. Will need to do better for SMP. */
485 break;
486 case 0xffff0fc0: /* __kernel_cmpxchg */
487 /* XXX: This only works between threads, not between processes.
488 It's probably possible to implement this with native host
489 operations. However things like ldrex/strex are much harder so
490 there's not much point trying. */
491 start_exclusive();
492 cpsr = cpsr_read(env);
493 addr = env->regs[2];
494 /* FIXME: This should SEGV if the access fails. */
495 if (get_user_u32(val, addr))
496 val = ~env->regs[0];
497 if (val == env->regs[0]) {
498 val = env->regs[1];
499 /* FIXME: Check for segfaults. */
500 put_user_u32(val, addr);
501 env->regs[0] = 0;
502 cpsr |= CPSR_C;
503 } else {
504 env->regs[0] = -1;
505 cpsr &= ~CPSR_C;
506 }
507 cpsr_write(env, cpsr, CPSR_C);
508 end_exclusive();
509 break;
510 case 0xffff0fe0: /* __kernel_get_tls */
511 env->regs[0] = env->cp15.c13_tls2;
512 break;
513 default:
514 return 1;
515 }
516 /* Jump back to the caller. */
517 addr = env->regs[14];
518 if (addr & 1) {
519 env->thumb = 1;
520 addr &= ~1;
521 }
522 env->regs[15] = addr;
523
524 return 0;
525 }
526
527 static int do_strex(CPUARMState *env)
528 {
529 uint32_t val;
530 int size;
531 int rc = 1;
532 int segv = 0;
533 uint32_t addr;
534 start_exclusive();
535 addr = env->exclusive_addr;
536 if (addr != env->exclusive_test) {
537 goto fail;
538 }
539 size = env->exclusive_info & 0xf;
540 switch (size) {
541 case 0:
542 segv = get_user_u8(val, addr);
543 break;
544 case 1:
545 segv = get_user_u16(val, addr);
546 break;
547 case 2:
548 case 3:
549 segv = get_user_u32(val, addr);
550 break;
551 default:
552 abort();
553 }
554 if (segv) {
555 env->cp15.c6_data = addr;
556 goto done;
557 }
558 if (val != env->exclusive_val) {
559 goto fail;
560 }
561 if (size == 3) {
562 segv = get_user_u32(val, addr + 4);
563 if (segv) {
564 env->cp15.c6_data = addr + 4;
565 goto done;
566 }
567 if (val != env->exclusive_high) {
568 goto fail;
569 }
570 }
571 val = env->regs[(env->exclusive_info >> 8) & 0xf];
572 switch (size) {
573 case 0:
574 segv = put_user_u8(val, addr);
575 break;
576 case 1:
577 segv = put_user_u16(val, addr);
578 break;
579 case 2:
580 case 3:
581 segv = put_user_u32(val, addr);
582 break;
583 }
584 if (segv) {
585 env->cp15.c6_data = addr;
586 goto done;
587 }
588 if (size == 3) {
589 val = env->regs[(env->exclusive_info >> 12) & 0xf];
590 segv = put_user_u32(val, addr);
591 if (segv) {
592 env->cp15.c6_data = addr + 4;
593 goto done;
594 }
595 }
596 rc = 0;
597 fail:
598 env->regs[15] += 4;
599 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
600 done:
601 end_exclusive();
602 return segv;
603 }
604
605 void cpu_loop(CPUARMState *env)
606 {
607 int trapnr;
608 unsigned int n, insn;
609 target_siginfo_t info;
610 uint32_t addr;
611
612 for(;;) {
613 cpu_exec_start(env);
614 trapnr = cpu_arm_exec(env);
615 cpu_exec_end(env);
616 switch(trapnr) {
617 case EXCP_UDEF:
618 {
619 TaskState *ts = env->opaque;
620 uint32_t opcode;
621 int rc;
622
623 /* we handle the FPU emulation here, as Linux */
624 /* we get the opcode */
625 /* FIXME - what to do if get_user() fails? */
626 get_user_u32(opcode, env->regs[15]);
627
628 rc = EmulateAll(opcode, &ts->fpa, env);
629 if (rc == 0) { /* illegal instruction */
630 info.si_signo = SIGILL;
631 info.si_errno = 0;
632 info.si_code = TARGET_ILL_ILLOPN;
633 info._sifields._sigfault._addr = env->regs[15];
634 queue_signal(env, info.si_signo, &info);
635 } else if (rc < 0) { /* FP exception */
636 int arm_fpe=0;
637
638 /* translate softfloat flags to FPSR flags */
639 if (-rc & float_flag_invalid)
640 arm_fpe |= BIT_IOC;
641 if (-rc & float_flag_divbyzero)
642 arm_fpe |= BIT_DZC;
643 if (-rc & float_flag_overflow)
644 arm_fpe |= BIT_OFC;
645 if (-rc & float_flag_underflow)
646 arm_fpe |= BIT_UFC;
647 if (-rc & float_flag_inexact)
648 arm_fpe |= BIT_IXC;
649
650 FPSR fpsr = ts->fpa.fpsr;
651 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
652
653 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
654 info.si_signo = SIGFPE;
655 info.si_errno = 0;
656
657 /* ordered by priority, least first */
658 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
659 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
660 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
661 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
662 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
663
664 info._sifields._sigfault._addr = env->regs[15];
665 queue_signal(env, info.si_signo, &info);
666 } else {
667 env->regs[15] += 4;
668 }
669
670 /* accumulate unenabled exceptions */
671 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
672 fpsr |= BIT_IXC;
673 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
674 fpsr |= BIT_UFC;
675 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
676 fpsr |= BIT_OFC;
677 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
678 fpsr |= BIT_DZC;
679 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
680 fpsr |= BIT_IOC;
681 ts->fpa.fpsr=fpsr;
682 } else { /* everything OK */
683 /* increment PC */
684 env->regs[15] += 4;
685 }
686 }
687 break;
688 case EXCP_SWI:
689 case EXCP_BKPT:
690 {
691 env->eabi = 1;
692 /* system call */
693 if (trapnr == EXCP_BKPT) {
694 if (env->thumb) {
695 /* FIXME - what to do if get_user() fails? */
696 get_user_u16(insn, env->regs[15]);
697 n = insn & 0xff;
698 env->regs[15] += 2;
699 } else {
700 /* FIXME - what to do if get_user() fails? */
701 get_user_u32(insn, env->regs[15]);
702 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
703 env->regs[15] += 4;
704 }
705 } else {
706 if (env->thumb) {
707 /* FIXME - what to do if get_user() fails? */
708 get_user_u16(insn, env->regs[15] - 2);
709 n = insn & 0xff;
710 } else {
711 /* FIXME - what to do if get_user() fails? */
712 get_user_u32(insn, env->regs[15] - 4);
713 n = insn & 0xffffff;
714 }
715 }
716
717 if (n == ARM_NR_cacheflush) {
718 arm_cache_flush(env->regs[0], env->regs[1]);
719 } else if (n == ARM_NR_semihosting
720 || n == ARM_NR_thumb_semihosting) {
721 env->regs[0] = do_arm_semihosting (env);
722 } else if (n == 0 || n >= ARM_SYSCALL_BASE
723 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
724 /* linux syscall */
725 if (env->thumb || n == 0) {
726 n = env->regs[7];
727 } else {
728 n -= ARM_SYSCALL_BASE;
729 env->eabi = 0;
730 }
731 if ( n > ARM_NR_BASE) {
732 switch (n) {
733 case ARM_NR_cacheflush:
734 arm_cache_flush(env->regs[0], env->regs[1]);
735 break;
736 case ARM_NR_set_tls:
737 cpu_set_tls(env, env->regs[0]);
738 env->regs[0] = 0;
739 break;
740 default:
741 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
742 n);
743 env->regs[0] = -TARGET_ENOSYS;
744 break;
745 }
746 } else {
747 env->regs[0] = do_syscall(env,
748 n,
749 env->regs[0],
750 env->regs[1],
751 env->regs[2],
752 env->regs[3],
753 env->regs[4],
754 env->regs[5]);
755 }
756 } else {
757 goto error;
758 }
759 }
760 break;
761 case EXCP_INTERRUPT:
762 /* just indicate that signals should be handled asap */
763 break;
764 case EXCP_PREFETCH_ABORT:
765 addr = env->cp15.c6_insn;
766 goto do_segv;
767 case EXCP_DATA_ABORT:
768 addr = env->cp15.c6_data;
769 goto do_segv;
770 do_segv:
771 {
772 info.si_signo = SIGSEGV;
773 info.si_errno = 0;
774 /* XXX: check env->error_code */
775 info.si_code = TARGET_SEGV_MAPERR;
776 info._sifields._sigfault._addr = addr;
777 queue_signal(env, info.si_signo, &info);
778 }
779 break;
780 case EXCP_DEBUG:
781 {
782 int sig;
783
784 sig = gdb_handlesig (env, TARGET_SIGTRAP);
785 if (sig)
786 {
787 info.si_signo = sig;
788 info.si_errno = 0;
789 info.si_code = TARGET_TRAP_BRKPT;
790 queue_signal(env, info.si_signo, &info);
791 }
792 }
793 break;
794 case EXCP_KERNEL_TRAP:
795 if (do_kernel_trap(env))
796 goto error;
797 break;
798 case EXCP_STREX:
799 if (do_strex(env)) {
800 addr = env->cp15.c6_data;
801 goto do_segv;
802 }
803 break;
804 default:
805 error:
806 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
807 trapnr);
808 cpu_dump_state(env, stderr, fprintf, 0);
809 abort();
810 }
811 process_pending_signals(env);
812 }
813 }
814
815 #endif
816
817 #ifdef TARGET_SPARC
818 #define SPARC64_STACK_BIAS 2047
819
820 //#define DEBUG_WIN
821
822 /* WARNING: dealing with register windows _is_ complicated. More info
823 can be found at http://www.sics.se/~psm/sparcstack.html */
824 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
825 {
826 index = (index + cwp * 16) % (16 * env->nwindows);
827 /* wrap handling : if cwp is on the last window, then we use the
828 registers 'after' the end */
829 if (index < 8 && env->cwp == env->nwindows - 1)
830 index += 16 * env->nwindows;
831 return index;
832 }
833
834 /* save the register window 'cwp1' */
835 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
836 {
837 unsigned int i;
838 abi_ulong sp_ptr;
839
840 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
841 #ifdef TARGET_SPARC64
842 if (sp_ptr & 3)
843 sp_ptr += SPARC64_STACK_BIAS;
844 #endif
845 #if defined(DEBUG_WIN)
846 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
847 sp_ptr, cwp1);
848 #endif
849 for(i = 0; i < 16; i++) {
850 /* FIXME - what to do if put_user() fails? */
851 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
852 sp_ptr += sizeof(abi_ulong);
853 }
854 }
855
856 static void save_window(CPUSPARCState *env)
857 {
858 #ifndef TARGET_SPARC64
859 unsigned int new_wim;
860 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
861 ((1LL << env->nwindows) - 1);
862 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
863 env->wim = new_wim;
864 #else
865 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
866 env->cansave++;
867 env->canrestore--;
868 #endif
869 }
870
871 static void restore_window(CPUSPARCState *env)
872 {
873 #ifndef TARGET_SPARC64
874 unsigned int new_wim;
875 #endif
876 unsigned int i, cwp1;
877 abi_ulong sp_ptr;
878
879 #ifndef TARGET_SPARC64
880 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
881 ((1LL << env->nwindows) - 1);
882 #endif
883
884 /* restore the invalid window */
885 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
886 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
887 #ifdef TARGET_SPARC64
888 if (sp_ptr & 3)
889 sp_ptr += SPARC64_STACK_BIAS;
890 #endif
891 #if defined(DEBUG_WIN)
892 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
893 sp_ptr, cwp1);
894 #endif
895 for(i = 0; i < 16; i++) {
896 /* FIXME - what to do if get_user() fails? */
897 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
898 sp_ptr += sizeof(abi_ulong);
899 }
900 #ifdef TARGET_SPARC64
901 env->canrestore++;
902 if (env->cleanwin < env->nwindows - 1)
903 env->cleanwin++;
904 env->cansave--;
905 #else
906 env->wim = new_wim;
907 #endif
908 }
909
910 static void flush_windows(CPUSPARCState *env)
911 {
912 int offset, cwp1;
913
914 offset = 1;
915 for(;;) {
916 /* if restore would invoke restore_window(), then we can stop */
917 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
918 #ifndef TARGET_SPARC64
919 if (env->wim & (1 << cwp1))
920 break;
921 #else
922 if (env->canrestore == 0)
923 break;
924 env->cansave++;
925 env->canrestore--;
926 #endif
927 save_window_offset(env, cwp1);
928 offset++;
929 }
930 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
931 #ifndef TARGET_SPARC64
932 /* set wim so that restore will reload the registers */
933 env->wim = 1 << cwp1;
934 #endif
935 #if defined(DEBUG_WIN)
936 printf("flush_windows: nb=%d\n", offset - 1);
937 #endif
938 }
939
940 void cpu_loop (CPUSPARCState *env)
941 {
942 int trapnr, ret;
943 target_siginfo_t info;
944
945 while (1) {
946 trapnr = cpu_sparc_exec (env);
947
948 switch (trapnr) {
949 #ifndef TARGET_SPARC64
950 case 0x88:
951 case 0x90:
952 #else
953 case 0x110:
954 case 0x16d:
955 #endif
956 ret = do_syscall (env, env->gregs[1],
957 env->regwptr[0], env->regwptr[1],
958 env->regwptr[2], env->regwptr[3],
959 env->regwptr[4], env->regwptr[5]);
960 if ((unsigned int)ret >= (unsigned int)(-515)) {
961 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
962 env->xcc |= PSR_CARRY;
963 #else
964 env->psr |= PSR_CARRY;
965 #endif
966 ret = -ret;
967 } else {
968 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
969 env->xcc &= ~PSR_CARRY;
970 #else
971 env->psr &= ~PSR_CARRY;
972 #endif
973 }
974 env->regwptr[0] = ret;
975 /* next instruction */
976 env->pc = env->npc;
977 env->npc = env->npc + 4;
978 break;
979 case 0x83: /* flush windows */
980 #ifdef TARGET_ABI32
981 case 0x103:
982 #endif
983 flush_windows(env);
984 /* next instruction */
985 env->pc = env->npc;
986 env->npc = env->npc + 4;
987 break;
988 #ifndef TARGET_SPARC64
989 case TT_WIN_OVF: /* window overflow */
990 save_window(env);
991 break;
992 case TT_WIN_UNF: /* window underflow */
993 restore_window(env);
994 break;
995 case TT_TFAULT:
996 case TT_DFAULT:
997 {
998 info.si_signo = SIGSEGV;
999 info.si_errno = 0;
1000 /* XXX: check env->error_code */
1001 info.si_code = TARGET_SEGV_MAPERR;
1002 info._sifields._sigfault._addr = env->mmuregs[4];
1003 queue_signal(env, info.si_signo, &info);
1004 }
1005 break;
1006 #else
1007 case TT_SPILL: /* window overflow */
1008 save_window(env);
1009 break;
1010 case TT_FILL: /* window underflow */
1011 restore_window(env);
1012 break;
1013 case TT_TFAULT:
1014 case TT_DFAULT:
1015 {
1016 info.si_signo = SIGSEGV;
1017 info.si_errno = 0;
1018 /* XXX: check env->error_code */
1019 info.si_code = TARGET_SEGV_MAPERR;
1020 if (trapnr == TT_DFAULT)
1021 info._sifields._sigfault._addr = env->dmmuregs[4];
1022 else
1023 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1024 queue_signal(env, info.si_signo, &info);
1025 }
1026 break;
1027 #ifndef TARGET_ABI32
1028 case 0x16e:
1029 flush_windows(env);
1030 sparc64_get_context(env);
1031 break;
1032 case 0x16f:
1033 flush_windows(env);
1034 sparc64_set_context(env);
1035 break;
1036 #endif
1037 #endif
1038 case EXCP_INTERRUPT:
1039 /* just indicate that signals should be handled asap */
1040 break;
1041 case EXCP_DEBUG:
1042 {
1043 int sig;
1044
1045 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1046 if (sig)
1047 {
1048 info.si_signo = sig;
1049 info.si_errno = 0;
1050 info.si_code = TARGET_TRAP_BRKPT;
1051 queue_signal(env, info.si_signo, &info);
1052 }
1053 }
1054 break;
1055 default:
1056 printf ("Unhandled trap: 0x%x\n", trapnr);
1057 cpu_dump_state(env, stderr, fprintf, 0);
1058 exit (1);
1059 }
1060 process_pending_signals (env);
1061 }
1062 }
1063
1064 #endif
1065
1066 #ifdef TARGET_PPC
1067 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1068 {
1069 /* TO FIX */
1070 return 0;
1071 }
1072
1073 uint64_t cpu_ppc_load_tbl (CPUState *env)
1074 {
1075 return cpu_ppc_get_tb(env);
1076 }
1077
1078 uint32_t cpu_ppc_load_tbu (CPUState *env)
1079 {
1080 return cpu_ppc_get_tb(env) >> 32;
1081 }
1082
1083 uint64_t cpu_ppc_load_atbl (CPUState *env)
1084 {
1085 return cpu_ppc_get_tb(env);
1086 }
1087
1088 uint32_t cpu_ppc_load_atbu (CPUState *env)
1089 {
1090 return cpu_ppc_get_tb(env) >> 32;
1091 }
1092
1093 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1094 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1095
1096 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1097 {
1098 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1099 }
1100
1101 /* XXX: to be fixed */
1102 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1103 {
1104 return -1;
1105 }
1106
1107 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1108 {
1109 return -1;
1110 }
1111
1112 #define EXCP_DUMP(env, fmt, ...) \
1113 do { \
1114 fprintf(stderr, fmt , ## __VA_ARGS__); \
1115 cpu_dump_state(env, stderr, fprintf, 0); \
1116 qemu_log(fmt, ## __VA_ARGS__); \
1117 if (logfile) \
1118 log_cpu_state(env, 0); \
1119 } while (0)
1120
1121 static int do_store_exclusive(CPUPPCState *env)
1122 {
1123 target_ulong addr;
1124 target_ulong page_addr;
1125 target_ulong val;
1126 int flags;
1127 int segv = 0;
1128
1129 addr = env->reserve_ea;
1130 page_addr = addr & TARGET_PAGE_MASK;
1131 start_exclusive();
1132 mmap_lock();
1133 flags = page_get_flags(page_addr);
1134 if ((flags & PAGE_READ) == 0) {
1135 segv = 1;
1136 } else {
1137 int reg = env->reserve_info & 0x1f;
1138 int size = (env->reserve_info >> 5) & 0xf;
1139 int stored = 0;
1140
1141 if (addr == env->reserve_addr) {
1142 switch (size) {
1143 case 1: segv = get_user_u8(val, addr); break;
1144 case 2: segv = get_user_u16(val, addr); break;
1145 case 4: segv = get_user_u32(val, addr); break;
1146 #if defined(TARGET_PPC64)
1147 case 8: segv = get_user_u64(val, addr); break;
1148 #endif
1149 default: abort();
1150 }
1151 if (!segv && val == env->reserve_val) {
1152 val = env->gpr[reg];
1153 switch (size) {
1154 case 1: segv = put_user_u8(val, addr); break;
1155 case 2: segv = put_user_u16(val, addr); break;
1156 case 4: segv = put_user_u32(val, addr); break;
1157 #if defined(TARGET_PPC64)
1158 case 8: segv = put_user_u64(val, addr); break;
1159 #endif
1160 default: abort();
1161 }
1162 if (!segv) {
1163 stored = 1;
1164 }
1165 }
1166 }
1167 env->crf[0] = (stored << 1) | xer_so;
1168 env->reserve_addr = (target_ulong)-1;
1169 }
1170 if (!segv) {
1171 env->nip += 4;
1172 }
1173 mmap_unlock();
1174 end_exclusive();
1175 return segv;
1176 }
1177
1178 void cpu_loop(CPUPPCState *env)
1179 {
1180 target_siginfo_t info;
1181 int trapnr;
1182 uint32_t ret;
1183
1184 for(;;) {
1185 cpu_exec_start(env);
1186 trapnr = cpu_ppc_exec(env);
1187 cpu_exec_end(env);
1188 switch(trapnr) {
1189 case POWERPC_EXCP_NONE:
1190 /* Just go on */
1191 break;
1192 case POWERPC_EXCP_CRITICAL: /* Critical input */
1193 cpu_abort(env, "Critical interrupt while in user mode. "
1194 "Aborting\n");
1195 break;
1196 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1197 cpu_abort(env, "Machine check exception while in user mode. "
1198 "Aborting\n");
1199 break;
1200 case POWERPC_EXCP_DSI: /* Data storage exception */
1201 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1202 env->spr[SPR_DAR]);
1203 /* XXX: check this. Seems bugged */
1204 switch (env->error_code & 0xFF000000) {
1205 case 0x40000000:
1206 info.si_signo = TARGET_SIGSEGV;
1207 info.si_errno = 0;
1208 info.si_code = TARGET_SEGV_MAPERR;
1209 break;
1210 case 0x04000000:
1211 info.si_signo = TARGET_SIGILL;
1212 info.si_errno = 0;
1213 info.si_code = TARGET_ILL_ILLADR;
1214 break;
1215 case 0x08000000:
1216 info.si_signo = TARGET_SIGSEGV;
1217 info.si_errno = 0;
1218 info.si_code = TARGET_SEGV_ACCERR;
1219 break;
1220 default:
1221 /* Let's send a regular segfault... */
1222 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1223 env->error_code);
1224 info.si_signo = TARGET_SIGSEGV;
1225 info.si_errno = 0;
1226 info.si_code = TARGET_SEGV_MAPERR;
1227 break;
1228 }
1229 info._sifields._sigfault._addr = env->nip;
1230 queue_signal(env, info.si_signo, &info);
1231 break;
1232 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1233 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1234 "\n", env->spr[SPR_SRR0]);
1235 /* XXX: check this */
1236 switch (env->error_code & 0xFF000000) {
1237 case 0x40000000:
1238 info.si_signo = TARGET_SIGSEGV;
1239 info.si_errno = 0;
1240 info.si_code = TARGET_SEGV_MAPERR;
1241 break;
1242 case 0x10000000:
1243 case 0x08000000:
1244 info.si_signo = TARGET_SIGSEGV;
1245 info.si_errno = 0;
1246 info.si_code = TARGET_SEGV_ACCERR;
1247 break;
1248 default:
1249 /* Let's send a regular segfault... */
1250 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1251 env->error_code);
1252 info.si_signo = TARGET_SIGSEGV;
1253 info.si_errno = 0;
1254 info.si_code = TARGET_SEGV_MAPERR;
1255 break;
1256 }
1257 info._sifields._sigfault._addr = env->nip - 4;
1258 queue_signal(env, info.si_signo, &info);
1259 break;
1260 case POWERPC_EXCP_EXTERNAL: /* External input */
1261 cpu_abort(env, "External interrupt while in user mode. "
1262 "Aborting\n");
1263 break;
1264 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1265 EXCP_DUMP(env, "Unaligned memory access\n");
1266 /* XXX: check this */
1267 info.si_signo = TARGET_SIGBUS;
1268 info.si_errno = 0;
1269 info.si_code = TARGET_BUS_ADRALN;
1270 info._sifields._sigfault._addr = env->nip - 4;
1271 queue_signal(env, info.si_signo, &info);
1272 break;
1273 case POWERPC_EXCP_PROGRAM: /* Program exception */
1274 /* XXX: check this */
1275 switch (env->error_code & ~0xF) {
1276 case POWERPC_EXCP_FP:
1277 EXCP_DUMP(env, "Floating point program exception\n");
1278 info.si_signo = TARGET_SIGFPE;
1279 info.si_errno = 0;
1280 switch (env->error_code & 0xF) {
1281 case POWERPC_EXCP_FP_OX:
1282 info.si_code = TARGET_FPE_FLTOVF;
1283 break;
1284 case POWERPC_EXCP_FP_UX:
1285 info.si_code = TARGET_FPE_FLTUND;
1286 break;
1287 case POWERPC_EXCP_FP_ZX:
1288 case POWERPC_EXCP_FP_VXZDZ:
1289 info.si_code = TARGET_FPE_FLTDIV;
1290 break;
1291 case POWERPC_EXCP_FP_XX:
1292 info.si_code = TARGET_FPE_FLTRES;
1293 break;
1294 case POWERPC_EXCP_FP_VXSOFT:
1295 info.si_code = TARGET_FPE_FLTINV;
1296 break;
1297 case POWERPC_EXCP_FP_VXSNAN:
1298 case POWERPC_EXCP_FP_VXISI:
1299 case POWERPC_EXCP_FP_VXIDI:
1300 case POWERPC_EXCP_FP_VXIMZ:
1301 case POWERPC_EXCP_FP_VXVC:
1302 case POWERPC_EXCP_FP_VXSQRT:
1303 case POWERPC_EXCP_FP_VXCVI:
1304 info.si_code = TARGET_FPE_FLTSUB;
1305 break;
1306 default:
1307 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1308 env->error_code);
1309 break;
1310 }
1311 break;
1312 case POWERPC_EXCP_INVAL:
1313 EXCP_DUMP(env, "Invalid instruction\n");
1314 info.si_signo = TARGET_SIGILL;
1315 info.si_errno = 0;
1316 switch (env->error_code & 0xF) {
1317 case POWERPC_EXCP_INVAL_INVAL:
1318 info.si_code = TARGET_ILL_ILLOPC;
1319 break;
1320 case POWERPC_EXCP_INVAL_LSWX:
1321 info.si_code = TARGET_ILL_ILLOPN;
1322 break;
1323 case POWERPC_EXCP_INVAL_SPR:
1324 info.si_code = TARGET_ILL_PRVREG;
1325 break;
1326 case POWERPC_EXCP_INVAL_FP:
1327 info.si_code = TARGET_ILL_COPROC;
1328 break;
1329 default:
1330 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1331 env->error_code & 0xF);
1332 info.si_code = TARGET_ILL_ILLADR;
1333 break;
1334 }
1335 break;
1336 case POWERPC_EXCP_PRIV:
1337 EXCP_DUMP(env, "Privilege violation\n");
1338 info.si_signo = TARGET_SIGILL;
1339 info.si_errno = 0;
1340 switch (env->error_code & 0xF) {
1341 case POWERPC_EXCP_PRIV_OPC:
1342 info.si_code = TARGET_ILL_PRVOPC;
1343 break;
1344 case POWERPC_EXCP_PRIV_REG:
1345 info.si_code = TARGET_ILL_PRVREG;
1346 break;
1347 default:
1348 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1349 env->error_code & 0xF);
1350 info.si_code = TARGET_ILL_PRVOPC;
1351 break;
1352 }
1353 break;
1354 case POWERPC_EXCP_TRAP:
1355 cpu_abort(env, "Tried to call a TRAP\n");
1356 break;
1357 default:
1358 /* Should not happen ! */
1359 cpu_abort(env, "Unknown program exception (%02x)\n",
1360 env->error_code);
1361 break;
1362 }
1363 info._sifields._sigfault._addr = env->nip - 4;
1364 queue_signal(env, info.si_signo, &info);
1365 break;
1366 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1367 EXCP_DUMP(env, "No floating point allowed\n");
1368 info.si_signo = TARGET_SIGILL;
1369 info.si_errno = 0;
1370 info.si_code = TARGET_ILL_COPROC;
1371 info._sifields._sigfault._addr = env->nip - 4;
1372 queue_signal(env, info.si_signo, &info);
1373 break;
1374 case POWERPC_EXCP_SYSCALL: /* System call exception */
1375 cpu_abort(env, "Syscall exception while in user mode. "
1376 "Aborting\n");
1377 break;
1378 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1379 EXCP_DUMP(env, "No APU instruction allowed\n");
1380 info.si_signo = TARGET_SIGILL;
1381 info.si_errno = 0;
1382 info.si_code = TARGET_ILL_COPROC;
1383 info._sifields._sigfault._addr = env->nip - 4;
1384 queue_signal(env, info.si_signo, &info);
1385 break;
1386 case POWERPC_EXCP_DECR: /* Decrementer exception */
1387 cpu_abort(env, "Decrementer interrupt while in user mode. "
1388 "Aborting\n");
1389 break;
1390 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1391 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1392 "Aborting\n");
1393 break;
1394 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1395 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1396 "Aborting\n");
1397 break;
1398 case POWERPC_EXCP_DTLB: /* Data TLB error */
1399 cpu_abort(env, "Data TLB exception while in user mode. "
1400 "Aborting\n");
1401 break;
1402 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1403 cpu_abort(env, "Instruction TLB exception while in user mode. "
1404 "Aborting\n");
1405 break;
1406 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1407 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1408 info.si_signo = TARGET_SIGILL;
1409 info.si_errno = 0;
1410 info.si_code = TARGET_ILL_COPROC;
1411 info._sifields._sigfault._addr = env->nip - 4;
1412 queue_signal(env, info.si_signo, &info);
1413 break;
1414 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1415 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1416 break;
1417 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1418 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1419 break;
1420 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1421 cpu_abort(env, "Performance monitor exception not handled\n");
1422 break;
1423 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1424 cpu_abort(env, "Doorbell interrupt while in user mode. "
1425 "Aborting\n");
1426 break;
1427 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1428 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1429 "Aborting\n");
1430 break;
1431 case POWERPC_EXCP_RESET: /* System reset exception */
1432 cpu_abort(env, "Reset interrupt while in user mode. "
1433 "Aborting\n");
1434 break;
1435 case POWERPC_EXCP_DSEG: /* Data segment exception */
1436 cpu_abort(env, "Data segment exception while in user mode. "
1437 "Aborting\n");
1438 break;
1439 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1440 cpu_abort(env, "Instruction segment exception "
1441 "while in user mode. Aborting\n");
1442 break;
1443 /* PowerPC 64 with hypervisor mode support */
1444 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1445 cpu_abort(env, "Hypervisor decrementer interrupt "
1446 "while in user mode. Aborting\n");
1447 break;
1448 case POWERPC_EXCP_TRACE: /* Trace exception */
1449 /* Nothing to do:
1450 * we use this exception to emulate step-by-step execution mode.
1451 */
1452 break;
1453 /* PowerPC 64 with hypervisor mode support */
1454 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1455 cpu_abort(env, "Hypervisor data storage exception "
1456 "while in user mode. Aborting\n");
1457 break;
1458 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1459 cpu_abort(env, "Hypervisor instruction storage exception "
1460 "while in user mode. Aborting\n");
1461 break;
1462 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1463 cpu_abort(env, "Hypervisor data segment exception "
1464 "while in user mode. Aborting\n");
1465 break;
1466 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1467 cpu_abort(env, "Hypervisor instruction segment exception "
1468 "while in user mode. Aborting\n");
1469 break;
1470 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1471 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1472 info.si_signo = TARGET_SIGILL;
1473 info.si_errno = 0;
1474 info.si_code = TARGET_ILL_COPROC;
1475 info._sifields._sigfault._addr = env->nip - 4;
1476 queue_signal(env, info.si_signo, &info);
1477 break;
1478 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1479 cpu_abort(env, "Programable interval timer interrupt "
1480 "while in user mode. Aborting\n");
1481 break;
1482 case POWERPC_EXCP_IO: /* IO error exception */
1483 cpu_abort(env, "IO error exception while in user mode. "
1484 "Aborting\n");
1485 break;
1486 case POWERPC_EXCP_RUNM: /* Run mode exception */
1487 cpu_abort(env, "Run mode exception while in user mode. "
1488 "Aborting\n");
1489 break;
1490 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1491 cpu_abort(env, "Emulation trap exception not handled\n");
1492 break;
1493 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1494 cpu_abort(env, "Instruction fetch TLB exception "
1495 "while in user-mode. Aborting");
1496 break;
1497 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1498 cpu_abort(env, "Data load TLB exception while in user-mode. "
1499 "Aborting");
1500 break;
1501 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1502 cpu_abort(env, "Data store TLB exception while in user-mode. "
1503 "Aborting");
1504 break;
1505 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1506 cpu_abort(env, "Floating-point assist exception not handled\n");
1507 break;
1508 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1509 cpu_abort(env, "Instruction address breakpoint exception "
1510 "not handled\n");
1511 break;
1512 case POWERPC_EXCP_SMI: /* System management interrupt */
1513 cpu_abort(env, "System management interrupt while in user mode. "
1514 "Aborting\n");
1515 break;
1516 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1517 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1518 "Aborting\n");
1519 break;
1520 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1521 cpu_abort(env, "Performance monitor exception not handled\n");
1522 break;
1523 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1524 cpu_abort(env, "Vector assist exception not handled\n");
1525 break;
1526 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1527 cpu_abort(env, "Soft patch exception not handled\n");
1528 break;
1529 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1530 cpu_abort(env, "Maintenance exception while in user mode. "
1531 "Aborting\n");
1532 break;
1533 case POWERPC_EXCP_STOP: /* stop translation */
1534 /* We did invalidate the instruction cache. Go on */
1535 break;
1536 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1537 /* We just stopped because of a branch. Go on */
1538 break;
1539 case POWERPC_EXCP_SYSCALL_USER:
1540 /* system call in user-mode emulation */
1541 /* WARNING:
1542 * PPC ABI uses overflow flag in cr0 to signal an error
1543 * in syscalls.
1544 */
1545 #if 0
1546 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1547 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1548 #endif
1549 env->crf[0] &= ~0x1;
1550 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1551 env->gpr[5], env->gpr[6], env->gpr[7],
1552 env->gpr[8]);
1553 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) {
1554 /* Returning from a successful sigreturn syscall.
1555 Avoid corrupting register state. */
1556 break;
1557 }
1558 if (ret > (uint32_t)(-515)) {
1559 env->crf[0] |= 0x1;
1560 ret = -ret;
1561 }
1562 env->gpr[3] = ret;
1563 #if 0
1564 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1565 #endif
1566 break;
1567 case POWERPC_EXCP_STCX:
1568 if (do_store_exclusive(env)) {
1569 info.si_signo = TARGET_SIGSEGV;
1570 info.si_errno = 0;
1571 info.si_code = TARGET_SEGV_MAPERR;
1572 info._sifields._sigfault._addr = env->nip;
1573 queue_signal(env, info.si_signo, &info);
1574 }
1575 break;
1576 case EXCP_DEBUG:
1577 {
1578 int sig;
1579
1580 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1581 if (sig) {
1582 info.si_signo = sig;
1583 info.si_errno = 0;
1584 info.si_code = TARGET_TRAP_BRKPT;
1585 queue_signal(env, info.si_signo, &info);
1586 }
1587 }
1588 break;
1589 case EXCP_INTERRUPT:
1590 /* just indicate that signals should be handled asap */
1591 break;
1592 default:
1593 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1594 break;
1595 }
1596 process_pending_signals(env);
1597 }
1598 }
1599 #endif
1600
1601 #ifdef TARGET_MIPS
1602
1603 #define MIPS_SYS(name, args) args,
1604
1605 static const uint8_t mips_syscall_args[] = {
1606 MIPS_SYS(sys_syscall , 0) /* 4000 */
1607 MIPS_SYS(sys_exit , 1)
1608 MIPS_SYS(sys_fork , 0)
1609 MIPS_SYS(sys_read , 3)
1610 MIPS_SYS(sys_write , 3)
1611 MIPS_SYS(sys_open , 3) /* 4005 */
1612 MIPS_SYS(sys_close , 1)
1613 MIPS_SYS(sys_waitpid , 3)
1614 MIPS_SYS(sys_creat , 2)
1615 MIPS_SYS(sys_link , 2)
1616 MIPS_SYS(sys_unlink , 1) /* 4010 */
1617 MIPS_SYS(sys_execve , 0)
1618 MIPS_SYS(sys_chdir , 1)
1619 MIPS_SYS(sys_time , 1)
1620 MIPS_SYS(sys_mknod , 3)
1621 MIPS_SYS(sys_chmod , 2) /* 4015 */
1622 MIPS_SYS(sys_lchown , 3)
1623 MIPS_SYS(sys_ni_syscall , 0)
1624 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1625 MIPS_SYS(sys_lseek , 3)
1626 MIPS_SYS(sys_getpid , 0) /* 4020 */
1627 MIPS_SYS(sys_mount , 5)
1628 MIPS_SYS(sys_oldumount , 1)
1629 MIPS_SYS(sys_setuid , 1)
1630 MIPS_SYS(sys_getuid , 0)
1631 MIPS_SYS(sys_stime , 1) /* 4025 */
1632 MIPS_SYS(sys_ptrace , 4)
1633 MIPS_SYS(sys_alarm , 1)
1634 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1635 MIPS_SYS(sys_pause , 0)
1636 MIPS_SYS(sys_utime , 2) /* 4030 */
1637 MIPS_SYS(sys_ni_syscall , 0)
1638 MIPS_SYS(sys_ni_syscall , 0)
1639 MIPS_SYS(sys_access , 2)
1640 MIPS_SYS(sys_nice , 1)
1641 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1642 MIPS_SYS(sys_sync , 0)
1643 MIPS_SYS(sys_kill , 2)
1644 MIPS_SYS(sys_rename , 2)
1645 MIPS_SYS(sys_mkdir , 2)
1646 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1647 MIPS_SYS(sys_dup , 1)
1648 MIPS_SYS(sys_pipe , 0)
1649 MIPS_SYS(sys_times , 1)
1650 MIPS_SYS(sys_ni_syscall , 0)
1651 MIPS_SYS(sys_brk , 1) /* 4045 */
1652 MIPS_SYS(sys_setgid , 1)
1653 MIPS_SYS(sys_getgid , 0)
1654 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1655 MIPS_SYS(sys_geteuid , 0)
1656 MIPS_SYS(sys_getegid , 0) /* 4050 */
1657 MIPS_SYS(sys_acct , 0)
1658 MIPS_SYS(sys_umount , 2)
1659 MIPS_SYS(sys_ni_syscall , 0)
1660 MIPS_SYS(sys_ioctl , 3)
1661 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1662 MIPS_SYS(sys_ni_syscall , 2)
1663 MIPS_SYS(sys_setpgid , 2)
1664 MIPS_SYS(sys_ni_syscall , 0)
1665 MIPS_SYS(sys_olduname , 1)
1666 MIPS_SYS(sys_umask , 1) /* 4060 */
1667 MIPS_SYS(sys_chroot , 1)
1668 MIPS_SYS(sys_ustat , 2)
1669 MIPS_SYS(sys_dup2 , 2)
1670 MIPS_SYS(sys_getppid , 0)
1671 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1672 MIPS_SYS(sys_setsid , 0)
1673 MIPS_SYS(sys_sigaction , 3)
1674 MIPS_SYS(sys_sgetmask , 0)
1675 MIPS_SYS(sys_ssetmask , 1)
1676 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1677 MIPS_SYS(sys_setregid , 2)
1678 MIPS_SYS(sys_sigsuspend , 0)
1679 MIPS_SYS(sys_sigpending , 1)
1680 MIPS_SYS(sys_sethostname , 2)
1681 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1682 MIPS_SYS(sys_getrlimit , 2)
1683 MIPS_SYS(sys_getrusage , 2)
1684 MIPS_SYS(sys_gettimeofday, 2)
1685 MIPS_SYS(sys_settimeofday, 2)
1686 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1687 MIPS_SYS(sys_setgroups , 2)
1688 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1689 MIPS_SYS(sys_symlink , 2)
1690 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1691 MIPS_SYS(sys_readlink , 3) /* 4085 */
1692 MIPS_SYS(sys_uselib , 1)
1693 MIPS_SYS(sys_swapon , 2)
1694 MIPS_SYS(sys_reboot , 3)
1695 MIPS_SYS(old_readdir , 3)
1696 MIPS_SYS(old_mmap , 6) /* 4090 */
1697 MIPS_SYS(sys_munmap , 2)
1698 MIPS_SYS(sys_truncate , 2)
1699 MIPS_SYS(sys_ftruncate , 2)
1700 MIPS_SYS(sys_fchmod , 2)
1701 MIPS_SYS(sys_fchown , 3) /* 4095 */
1702 MIPS_SYS(sys_getpriority , 2)
1703 MIPS_SYS(sys_setpriority , 3)
1704 MIPS_SYS(sys_ni_syscall , 0)
1705 MIPS_SYS(sys_statfs , 2)
1706 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1707 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1708 MIPS_SYS(sys_socketcall , 2)
1709 MIPS_SYS(sys_syslog , 3)
1710 MIPS_SYS(sys_setitimer , 3)
1711 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1712 MIPS_SYS(sys_newstat , 2)
1713 MIPS_SYS(sys_newlstat , 2)
1714 MIPS_SYS(sys_newfstat , 2)
1715 MIPS_SYS(sys_uname , 1)
1716 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1717 MIPS_SYS(sys_vhangup , 0)
1718 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1719 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1720 MIPS_SYS(sys_wait4 , 4)
1721 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1722 MIPS_SYS(sys_sysinfo , 1)
1723 MIPS_SYS(sys_ipc , 6)
1724 MIPS_SYS(sys_fsync , 1)
1725 MIPS_SYS(sys_sigreturn , 0)
1726 MIPS_SYS(sys_clone , 6) /* 4120 */
1727 MIPS_SYS(sys_setdomainname, 2)
1728 MIPS_SYS(sys_newuname , 1)
1729 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1730 MIPS_SYS(sys_adjtimex , 1)
1731 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1732 MIPS_SYS(sys_sigprocmask , 3)
1733 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1734 MIPS_SYS(sys_init_module , 5)
1735 MIPS_SYS(sys_delete_module, 1)
1736 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1737 MIPS_SYS(sys_quotactl , 0)
1738 MIPS_SYS(sys_getpgid , 1)
1739 MIPS_SYS(sys_fchdir , 1)
1740 MIPS_SYS(sys_bdflush , 2)
1741 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1742 MIPS_SYS(sys_personality , 1)
1743 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1744 MIPS_SYS(sys_setfsuid , 1)
1745 MIPS_SYS(sys_setfsgid , 1)
1746 MIPS_SYS(sys_llseek , 5) /* 4140 */
1747 MIPS_SYS(sys_getdents , 3)
1748 MIPS_SYS(sys_select , 5)
1749 MIPS_SYS(sys_flock , 2)
1750 MIPS_SYS(sys_msync , 3)
1751 MIPS_SYS(sys_readv , 3) /* 4145 */
1752 MIPS_SYS(sys_writev , 3)
1753 MIPS_SYS(sys_cacheflush , 3)
1754 MIPS_SYS(sys_cachectl , 3)
1755 MIPS_SYS(sys_sysmips , 4)
1756 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1757 MIPS_SYS(sys_getsid , 1)
1758 MIPS_SYS(sys_fdatasync , 0)
1759 MIPS_SYS(sys_sysctl , 1)
1760 MIPS_SYS(sys_mlock , 2)
1761 MIPS_SYS(sys_munlock , 2) /* 4155 */
1762 MIPS_SYS(sys_mlockall , 1)
1763 MIPS_SYS(sys_munlockall , 0)
1764 MIPS_SYS(sys_sched_setparam, 2)
1765 MIPS_SYS(sys_sched_getparam, 2)
1766 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1767 MIPS_SYS(sys_sched_getscheduler, 1)
1768 MIPS_SYS(sys_sched_yield , 0)
1769 MIPS_SYS(sys_sched_get_priority_max, 1)
1770 MIPS_SYS(sys_sched_get_priority_min, 1)
1771 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1772 MIPS_SYS(sys_nanosleep, 2)
1773 MIPS_SYS(sys_mremap , 4)
1774 MIPS_SYS(sys_accept , 3)
1775 MIPS_SYS(sys_bind , 3)
1776 MIPS_SYS(sys_connect , 3) /* 4170 */
1777 MIPS_SYS(sys_getpeername , 3)
1778 MIPS_SYS(sys_getsockname , 3)
1779 MIPS_SYS(sys_getsockopt , 5)
1780 MIPS_SYS(sys_listen , 2)
1781 MIPS_SYS(sys_recv , 4) /* 4175 */
1782 MIPS_SYS(sys_recvfrom , 6)
1783 MIPS_SYS(sys_recvmsg , 3)
1784 MIPS_SYS(sys_send , 4)
1785 MIPS_SYS(sys_sendmsg , 3)
1786 MIPS_SYS(sys_sendto , 6) /* 4180 */
1787 MIPS_SYS(sys_setsockopt , 5)
1788 MIPS_SYS(sys_shutdown , 2)
1789 MIPS_SYS(sys_socket , 3)
1790 MIPS_SYS(sys_socketpair , 4)
1791 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1792 MIPS_SYS(sys_getresuid , 3)
1793 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1794 MIPS_SYS(sys_poll , 3)
1795 MIPS_SYS(sys_nfsservctl , 3)
1796 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1797 MIPS_SYS(sys_getresgid , 3)
1798 MIPS_SYS(sys_prctl , 5)
1799 MIPS_SYS(sys_rt_sigreturn, 0)
1800 MIPS_SYS(sys_rt_sigaction, 4)
1801 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1802 MIPS_SYS(sys_rt_sigpending, 2)
1803 MIPS_SYS(sys_rt_sigtimedwait, 4)
1804 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1805 MIPS_SYS(sys_rt_sigsuspend, 0)
1806 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1807 MIPS_SYS(sys_pwrite64 , 6)
1808 MIPS_SYS(sys_chown , 3)
1809 MIPS_SYS(sys_getcwd , 2)
1810 MIPS_SYS(sys_capget , 2)
1811 MIPS_SYS(sys_capset , 2) /* 4205 */
1812 MIPS_SYS(sys_sigaltstack , 0)
1813 MIPS_SYS(sys_sendfile , 4)
1814 MIPS_SYS(sys_ni_syscall , 0)
1815 MIPS_SYS(sys_ni_syscall , 0)
1816 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1817 MIPS_SYS(sys_truncate64 , 4)
1818 MIPS_SYS(sys_ftruncate64 , 4)
1819 MIPS_SYS(sys_stat64 , 2)
1820 MIPS_SYS(sys_lstat64 , 2)
1821 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1822 MIPS_SYS(sys_pivot_root , 2)
1823 MIPS_SYS(sys_mincore , 3)
1824 MIPS_SYS(sys_madvise , 3)
1825 MIPS_SYS(sys_getdents64 , 3)
1826 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1827 MIPS_SYS(sys_ni_syscall , 0)
1828 MIPS_SYS(sys_gettid , 0)
1829 MIPS_SYS(sys_readahead , 5)
1830 MIPS_SYS(sys_setxattr , 5)
1831 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1832 MIPS_SYS(sys_fsetxattr , 5)
1833 MIPS_SYS(sys_getxattr , 4)
1834 MIPS_SYS(sys_lgetxattr , 4)
1835 MIPS_SYS(sys_fgetxattr , 4)
1836 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1837 MIPS_SYS(sys_llistxattr , 3)
1838 MIPS_SYS(sys_flistxattr , 3)
1839 MIPS_SYS(sys_removexattr , 2)
1840 MIPS_SYS(sys_lremovexattr, 2)
1841 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1842 MIPS_SYS(sys_tkill , 2)
1843 MIPS_SYS(sys_sendfile64 , 5)
1844 MIPS_SYS(sys_futex , 2)
1845 MIPS_SYS(sys_sched_setaffinity, 3)
1846 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1847 MIPS_SYS(sys_io_setup , 2)
1848 MIPS_SYS(sys_io_destroy , 1)
1849 MIPS_SYS(sys_io_getevents, 5)
1850 MIPS_SYS(sys_io_submit , 3)
1851 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1852 MIPS_SYS(sys_exit_group , 1)
1853 MIPS_SYS(sys_lookup_dcookie, 3)
1854 MIPS_SYS(sys_epoll_create, 1)
1855 MIPS_SYS(sys_epoll_ctl , 4)
1856 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1857 MIPS_SYS(sys_remap_file_pages, 5)
1858 MIPS_SYS(sys_set_tid_address, 1)
1859 MIPS_SYS(sys_restart_syscall, 0)
1860 MIPS_SYS(sys_fadvise64_64, 7)
1861 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1862 MIPS_SYS(sys_fstatfs64 , 2)
1863 MIPS_SYS(sys_timer_create, 3)
1864 MIPS_SYS(sys_timer_settime, 4)
1865 MIPS_SYS(sys_timer_gettime, 2)
1866 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1867 MIPS_SYS(sys_timer_delete, 1)
1868 MIPS_SYS(sys_clock_settime, 2)
1869 MIPS_SYS(sys_clock_gettime, 2)
1870 MIPS_SYS(sys_clock_getres, 2)
1871 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1872 MIPS_SYS(sys_tgkill , 3)
1873 MIPS_SYS(sys_utimes , 2)
1874 MIPS_SYS(sys_mbind , 4)
1875 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1876 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1877 MIPS_SYS(sys_mq_open , 4)
1878 MIPS_SYS(sys_mq_unlink , 1)
1879 MIPS_SYS(sys_mq_timedsend, 5)
1880 MIPS_SYS(sys_mq_timedreceive, 5)
1881 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1882 MIPS_SYS(sys_mq_getsetattr, 3)
1883 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1884 MIPS_SYS(sys_waitid , 4)
1885 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1886 MIPS_SYS(sys_add_key , 5)
1887 MIPS_SYS(sys_request_key, 4)
1888 MIPS_SYS(sys_keyctl , 5)
1889 MIPS_SYS(sys_set_thread_area, 1)
1890 MIPS_SYS(sys_inotify_init, 0)
1891 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1892 MIPS_SYS(sys_inotify_rm_watch, 2)
1893 MIPS_SYS(sys_migrate_pages, 4)
1894 MIPS_SYS(sys_openat, 4)
1895 MIPS_SYS(sys_mkdirat, 3)
1896 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1897 MIPS_SYS(sys_fchownat, 5)
1898 MIPS_SYS(sys_futimesat, 3)
1899 MIPS_SYS(sys_fstatat64, 4)
1900 MIPS_SYS(sys_unlinkat, 3)
1901 MIPS_SYS(sys_renameat, 4) /* 4295 */
1902 MIPS_SYS(sys_linkat, 5)
1903 MIPS_SYS(sys_symlinkat, 3)
1904 MIPS_SYS(sys_readlinkat, 4)
1905 MIPS_SYS(sys_fchmodat, 3)
1906 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1907 MIPS_SYS(sys_pselect6, 6)
1908 MIPS_SYS(sys_ppoll, 5)
1909 MIPS_SYS(sys_unshare, 1)
1910 MIPS_SYS(sys_splice, 4)
1911 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1912 MIPS_SYS(sys_tee, 4)
1913 MIPS_SYS(sys_vmsplice, 4)
1914 MIPS_SYS(sys_move_pages, 6)
1915 MIPS_SYS(sys_set_robust_list, 2)
1916 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1917 MIPS_SYS(sys_kexec_load, 4)
1918 MIPS_SYS(sys_getcpu, 3)
1919 MIPS_SYS(sys_epoll_pwait, 6)
1920 MIPS_SYS(sys_ioprio_set, 3)
1921 MIPS_SYS(sys_ioprio_get, 2)
1922 };
1923
1924 #undef MIPS_SYS
1925
1926 static int do_store_exclusive(CPUMIPSState *env)
1927 {
1928 target_ulong addr;
1929 target_ulong page_addr;
1930 target_ulong val;
1931 int flags;
1932 int segv = 0;
1933 int reg;
1934 int d;
1935
1936 addr = env->lladdr;
1937 page_addr = addr & TARGET_PAGE_MASK;
1938 start_exclusive();
1939 mmap_lock();
1940 flags = page_get_flags(page_addr);
1941 if ((flags & PAGE_READ) == 0) {
1942 segv = 1;
1943 } else {
1944 reg = env->llreg & 0x1f;
1945 d = (env->llreg & 0x20) != 0;
1946 if (d) {
1947 segv = get_user_s64(val, addr);
1948 } else {
1949 segv = get_user_s32(val, addr);
1950 }
1951 if (!segv) {
1952 if (val != env->llval) {
1953 env->active_tc.gpr[reg] = 0;
1954 } else {
1955 if (d) {
1956 segv = put_user_u64(env->llnewval, addr);
1957 } else {
1958 segv = put_user_u32(env->llnewval, addr);
1959 }
1960 if (!segv) {
1961 env->active_tc.gpr[reg] = 1;
1962 }
1963 }
1964 }
1965 }
1966 env->lladdr = -1;
1967 if (!segv) {
1968 env->active_tc.PC += 4;
1969 }
1970 mmap_unlock();
1971 end_exclusive();
1972 return segv;
1973 }
1974
1975 void cpu_loop(CPUMIPSState *env)
1976 {
1977 target_siginfo_t info;
1978 int trapnr, ret;
1979 unsigned int syscall_num;
1980
1981 for(;;) {
1982 cpu_exec_start(env);
1983 trapnr = cpu_mips_exec(env);
1984 cpu_exec_end(env);
1985 switch(trapnr) {
1986 case EXCP_SYSCALL:
1987 syscall_num = env->active_tc.gpr[2] - 4000;
1988 env->active_tc.PC += 4;
1989 if (syscall_num >= sizeof(mips_syscall_args)) {
1990 ret = -ENOSYS;
1991 } else {
1992 int nb_args;
1993 abi_ulong sp_reg;
1994 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1995
1996 nb_args = mips_syscall_args[syscall_num];
1997 sp_reg = env->active_tc.gpr[29];
1998 switch (nb_args) {
1999 /* these arguments are taken from the stack */
2000 /* FIXME - what to do if get_user() fails? */
2001 case 8: get_user_ual(arg8, sp_reg + 28);
2002 case 7: get_user_ual(arg7, sp_reg + 24);
2003 case 6: get_user_ual(arg6, sp_reg + 20);
2004 case 5: get_user_ual(arg5, sp_reg + 16);
2005 default:
2006 break;
2007 }
2008 ret = do_syscall(env, env->active_tc.gpr[2],
2009 env->active_tc.gpr[4],
2010 env->active_tc.gpr[5],
2011 env->active_tc.gpr[6],
2012 env->active_tc.gpr[7],
2013 arg5, arg6/*, arg7, arg8*/);
2014 }
2015 if (ret == -TARGET_QEMU_ESIGRETURN) {
2016 /* Returning from a successful sigreturn syscall.
2017 Avoid clobbering register state. */
2018 break;
2019 }
2020 if ((unsigned int)ret >= (unsigned int)(-1133)) {
2021 env->active_tc.gpr[7] = 1; /* error flag */
2022 ret = -ret;
2023 } else {
2024 env->active_tc.gpr[7] = 0; /* error flag */
2025 }
2026 env->active_tc.gpr[2] = ret;
2027 break;
2028 case EXCP_TLBL:
2029 case EXCP_TLBS:
2030 info.si_signo = TARGET_SIGSEGV;
2031 info.si_errno = 0;
2032 /* XXX: check env->error_code */
2033 info.si_code = TARGET_SEGV_MAPERR;
2034 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2035 queue_signal(env, info.si_signo, &info);
2036 break;
2037 case EXCP_CpU:
2038 case EXCP_RI:
2039 info.si_signo = TARGET_SIGILL;
2040 info.si_errno = 0;
2041 info.si_code = 0;
2042 queue_signal(env, info.si_signo, &info);
2043 break;
2044 case EXCP_INTERRUPT:
2045 /* just indicate that signals should be handled asap */
2046 break;
2047 case EXCP_DEBUG:
2048 {
2049 int sig;
2050
2051 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2052 if (sig)
2053 {
2054 info.si_signo = sig;
2055 info.si_errno = 0;
2056 info.si_code = TARGET_TRAP_BRKPT;
2057 queue_signal(env, info.si_signo, &info);
2058 }
2059 }
2060 break;
2061 case EXCP_SC:
2062 if (do_store_exclusive(env)) {
2063 info.si_signo = TARGET_SIGSEGV;
2064 info.si_errno = 0;
2065 info.si_code = TARGET_SEGV_MAPERR;
2066 info._sifields._sigfault._addr = env->active_tc.PC;
2067 queue_signal(env, info.si_signo, &info);
2068 }
2069 break;
2070 default:
2071 // error:
2072 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2073 trapnr);
2074 cpu_dump_state(env, stderr, fprintf, 0);
2075 abort();
2076 }
2077 process_pending_signals(env);
2078 }
2079 }
2080 #endif
2081
2082 #ifdef TARGET_SH4
2083 void cpu_loop (CPUState *env)
2084 {
2085 int trapnr, ret;
2086 target_siginfo_t info;
2087
2088 while (1) {
2089 trapnr = cpu_sh4_exec (env);
2090
2091 switch (trapnr) {
2092 case 0x160:
2093 env->pc += 2;
2094 ret = do_syscall(env,
2095 env->gregs[3],
2096 env->gregs[4],
2097 env->gregs[5],
2098 env->gregs[6],
2099 env->gregs[7],
2100 env->gregs[0],
2101 env->gregs[1]);
2102 env->gregs[0] = ret;
2103 break;
2104 case EXCP_INTERRUPT:
2105 /* just indicate that signals should be handled asap */
2106 break;
2107 case EXCP_DEBUG:
2108 {
2109 int sig;
2110
2111 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2112 if (sig)
2113 {
2114 info.si_signo = sig;
2115 info.si_errno = 0;
2116 info.si_code = TARGET_TRAP_BRKPT;
2117 queue_signal(env, info.si_signo, &info);
2118 }
2119 }
2120 break;
2121 case 0xa0:
2122 case 0xc0:
2123 info.si_signo = SIGSEGV;
2124 info.si_errno = 0;
2125 info.si_code = TARGET_SEGV_MAPERR;
2126 info._sifields._sigfault._addr = env->tea;
2127 queue_signal(env, info.si_signo, &info);
2128 break;
2129
2130 default:
2131 printf ("Unhandled trap: 0x%x\n", trapnr);
2132 cpu_dump_state(env, stderr, fprintf, 0);
2133 exit (1);
2134 }
2135 process_pending_signals (env);
2136 }
2137 }
2138 #endif
2139
2140 #ifdef TARGET_CRIS
2141 void cpu_loop (CPUState *env)
2142 {
2143 int trapnr, ret;
2144 target_siginfo_t info;
2145
2146 while (1) {
2147 trapnr = cpu_cris_exec (env);
2148 switch (trapnr) {
2149 case 0xaa:
2150 {
2151 info.si_signo = SIGSEGV;
2152 info.si_errno = 0;
2153 /* XXX: check env->error_code */
2154 info.si_code = TARGET_SEGV_MAPERR;
2155 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2156 queue_signal(env, info.si_signo, &info);
2157 }
2158 break;
2159 case EXCP_INTERRUPT:
2160 /* just indicate that signals should be handled asap */
2161 break;
2162 case EXCP_BREAK:
2163 ret = do_syscall(env,
2164 env->regs[9],
2165 env->regs[10],
2166 env->regs[11],
2167 env->regs[12],
2168 env->regs[13],
2169 env->pregs[7],
2170 env->pregs[11]);
2171 env->regs[10] = ret;
2172 break;
2173 case EXCP_DEBUG:
2174 {
2175 int sig;
2176
2177 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2178 if (sig)
2179 {
2180 info.si_signo = sig;
2181 info.si_errno = 0;
2182 info.si_code = TARGET_TRAP_BRKPT;
2183 queue_signal(env, info.si_signo, &info);
2184 }
2185 }
2186 break;
2187 default:
2188 printf ("Unhandled trap: 0x%x\n", trapnr);
2189 cpu_dump_state(env, stderr, fprintf, 0);
2190 exit (1);
2191 }
2192 process_pending_signals (env);
2193 }
2194 }
2195 #endif
2196
2197 #ifdef TARGET_MICROBLAZE
2198 void cpu_loop (CPUState *env)
2199 {
2200 int trapnr, ret;
2201 target_siginfo_t info;
2202
2203 while (1) {
2204 trapnr = cpu_mb_exec (env);
2205 switch (trapnr) {
2206 case 0xaa:
2207 {
2208 info.si_signo = SIGSEGV;
2209 info.si_errno = 0;
2210 /* XXX: check env->error_code */
2211 info.si_code = TARGET_SEGV_MAPERR;
2212 info._sifields._sigfault._addr = 0;
2213 queue_signal(env, info.si_signo, &info);
2214 }
2215 break;
2216 case EXCP_INTERRUPT:
2217 /* just indicate that signals should be handled asap */
2218 break;
2219 case EXCP_BREAK:
2220 /* Return address is 4 bytes after the call. */
2221 env->regs[14] += 4;
2222 ret = do_syscall(env,
2223 env->regs[12],
2224 env->regs[5],
2225 env->regs[6],
2226 env->regs[7],
2227 env->regs[8],
2228 env->regs[9],
2229 env->regs[10]);
2230 env->regs[3] = ret;
2231 env->sregs[SR_PC] = env->regs[14];
2232 break;
2233 case EXCP_DEBUG:
2234 {
2235 int sig;
2236
2237 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2238 if (sig)
2239 {
2240 info.si_signo = sig;
2241 info.si_errno = 0;
2242 info.si_code = TARGET_TRAP_BRKPT;
2243 queue_signal(env, info.si_signo, &info);
2244 }
2245 }
2246 break;
2247 default:
2248 printf ("Unhandled trap: 0x%x\n", trapnr);
2249 cpu_dump_state(env, stderr, fprintf, 0);
2250 exit (1);
2251 }
2252 process_pending_signals (env);
2253 }
2254 }
2255 #endif
2256
2257 #ifdef TARGET_M68K
2258
2259 void cpu_loop(CPUM68KState *env)
2260 {
2261 int trapnr;
2262 unsigned int n;
2263 target_siginfo_t info;
2264 TaskState *ts = env->opaque;
2265
2266 for(;;) {
2267 trapnr = cpu_m68k_exec(env);
2268 switch(trapnr) {
2269 case EXCP_ILLEGAL:
2270 {
2271 if (ts->sim_syscalls) {
2272 uint16_t nr;
2273 nr = lduw(env->pc + 2);
2274 env->pc += 4;
2275 do_m68k_simcall(env, nr);
2276 } else {
2277 goto do_sigill;
2278 }
2279 }
2280 break;
2281 case EXCP_HALT_INSN:
2282 /* Semihosing syscall. */
2283 env->pc += 4;
2284 do_m68k_semihosting(env, env->dregs[0]);
2285 break;
2286 case EXCP_LINEA:
2287 case EXCP_LINEF:
2288 case EXCP_UNSUPPORTED:
2289 do_sigill:
2290 info.si_signo = SIGILL;
2291 info.si_errno = 0;
2292 info.si_code = TARGET_ILL_ILLOPN;
2293 info._sifields._sigfault._addr = env->pc;
2294 queue_signal(env, info.si_signo, &info);
2295 break;
2296 case EXCP_TRAP0:
2297 {
2298 ts->sim_syscalls = 0;
2299 n = env->dregs[0];
2300 env->pc += 2;
2301 env->dregs[0] = do_syscall(env,
2302 n,
2303 env->dregs[1],
2304 env->dregs[2],
2305 env->dregs[3],
2306 env->dregs[4],
2307 env->dregs[5],
2308 env->aregs[0]);
2309 }
2310 break;
2311 case EXCP_INTERRUPT:
2312 /* just indicate that signals should be handled asap */
2313 break;
2314 case EXCP_ACCESS:
2315 {
2316 info.si_signo = SIGSEGV;
2317 info.si_errno = 0;
2318 /* XXX: check env->error_code */
2319 info.si_code = TARGET_SEGV_MAPERR;
2320 info._sifields._sigfault._addr = env->mmu.ar;
2321 queue_signal(env, info.si_signo, &info);
2322 }
2323 break;
2324 case EXCP_DEBUG:
2325 {
2326 int sig;
2327
2328 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2329 if (sig)
2330 {
2331 info.si_signo = sig;
2332 info.si_errno = 0;
2333 info.si_code = TARGET_TRAP_BRKPT;
2334 queue_signal(env, info.si_signo, &info);
2335 }
2336 }
2337 break;
2338 default:
2339 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2340 trapnr);
2341 cpu_dump_state(env, stderr, fprintf, 0);
2342 abort();
2343 }
2344 process_pending_signals(env);
2345 }
2346 }
2347 #endif /* TARGET_M68K */
2348
2349 #ifdef TARGET_ALPHA
2350 void cpu_loop (CPUState *env)
2351 {
2352 int trapnr;
2353 target_siginfo_t info;
2354
2355 while (1) {
2356 trapnr = cpu_alpha_exec (env);
2357
2358 switch (trapnr) {
2359 case EXCP_RESET:
2360 fprintf(stderr, "Reset requested. Exit\n");
2361 exit(1);
2362 break;
2363 case EXCP_MCHK:
2364 fprintf(stderr, "Machine check exception. Exit\n");
2365 exit(1);
2366 break;
2367 case EXCP_ARITH:
2368 fprintf(stderr, "Arithmetic trap.\n");
2369 exit(1);
2370 break;
2371 case EXCP_HW_INTERRUPT:
2372 fprintf(stderr, "External interrupt. Exit\n");
2373 exit(1);
2374 break;
2375 case EXCP_DFAULT:
2376 fprintf(stderr, "MMU data fault\n");
2377 exit(1);
2378 break;
2379 case EXCP_DTB_MISS_PAL:
2380 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2381 exit(1);
2382 break;
2383 case EXCP_ITB_MISS:
2384 fprintf(stderr, "MMU instruction TLB miss\n");
2385 exit(1);
2386 break;
2387 case EXCP_ITB_ACV:
2388 fprintf(stderr, "MMU instruction access violation\n");
2389 exit(1);
2390 break;
2391 case EXCP_DTB_MISS_NATIVE:
2392 fprintf(stderr, "MMU data TLB miss\n");
2393 exit(1);
2394 break;
2395 case EXCP_UNALIGN:
2396 fprintf(stderr, "Unaligned access\n");
2397 exit(1);
2398 break;
2399 case EXCP_OPCDEC:
2400 fprintf(stderr, "Invalid instruction\n");
2401 exit(1);
2402 break;
2403 case EXCP_FEN:
2404 fprintf(stderr, "Floating-point not allowed\n");
2405 exit(1);
2406 break;
2407 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2408 call_pal(env, (trapnr >> 6) | 0x80);
2409 break;
2410 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2411 fprintf(stderr, "Privileged call to PALcode\n");
2412 exit(1);
2413 break;
2414 case EXCP_DEBUG:
2415 {
2416 int sig;
2417
2418 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2419 if (sig)
2420 {
2421 info.si_signo = sig;
2422 info.si_errno = 0;
2423 info.si_code = TARGET_TRAP_BRKPT;
2424 queue_signal(env, info.si_signo, &info);
2425 }
2426 }
2427 break;
2428 default:
2429 printf ("Unhandled trap: 0x%x\n", trapnr);
2430 cpu_dump_state(env, stderr, fprintf, 0);
2431 exit (1);
2432 }
2433 process_pending_signals (env);
2434 }
2435 }
2436 #endif /* TARGET_ALPHA */
2437
2438 static void usage(void)
2439 {
2440 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2441 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2442 "Linux CPU emulator (compiled for %s emulation)\n"
2443 "\n"
2444 "Standard options:\n"
2445 "-h print this help\n"
2446 "-g port wait gdb connection to port\n"
2447 "-L path set the elf interpreter prefix (default=%s)\n"
2448 "-s size set the stack size in bytes (default=%ld)\n"
2449 "-cpu model select CPU (-cpu ? for list)\n"
2450 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2451 "-E var=value sets/modifies targets environment variable(s)\n"
2452 "-U var unsets targets environment variable(s)\n"
2453 "-0 argv0 forces target process argv[0] to be argv0\n"
2454 #if defined(CONFIG_USE_GUEST_BASE)
2455 "-B address set guest_base address to address\n"
2456 #endif
2457 "\n"
2458 "Debug options:\n"
2459 "-d options activate log (logfile=%s)\n"
2460 "-p pagesize set the host page size to 'pagesize'\n"
2461 "-singlestep always run in singlestep mode\n"
2462 "-strace log system calls\n"
2463 "\n"
2464 "Environment variables:\n"
2465 "QEMU_STRACE Print system calls and arguments similar to the\n"
2466 " 'strace' program. Enable by setting to any value.\n"
2467 "You can use -E and -U options to set/unset environment variables\n"
2468 "for target process. It is possible to provide several variables\n"
2469 "by repeating the option. For example:\n"
2470 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2471 "Note that if you provide several changes to single variable\n"
2472 "last change will stay in effect.\n"
2473 ,
2474 TARGET_ARCH,
2475 interp_prefix,
2476 x86_stack_size,
2477 DEBUG_LOGFILE);
2478 exit(1);
2479 }
2480
2481 THREAD CPUState *thread_env;
2482
2483 void task_settid(TaskState *ts)
2484 {
2485 if (ts->ts_tid == 0) {
2486 #ifdef CONFIG_USE_NPTL
2487 ts->ts_tid = (pid_t)syscall(SYS_gettid);
2488 #else
2489 /* when no threads are used, tid becomes pid */
2490 ts->ts_tid = getpid();
2491 #endif
2492 }
2493 }
2494
2495 void stop_all_tasks(void)
2496 {
2497 /*
2498 * We trust that when using NPTL, start_exclusive()
2499 * handles thread stopping correctly.
2500 */
2501 start_exclusive();
2502 }
2503
2504 /* Assumes contents are already zeroed. */
2505 void init_task_state(TaskState *ts)
2506 {
2507 int i;
2508
2509 ts->used = 1;
2510 ts->first_free = ts->sigqueue_table;
2511 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2512 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2513 }
2514 ts->sigqueue_table[i].next = NULL;
2515 }
2516
2517 int main(int argc, char **argv, char **envp)
2518 {
2519 const char *filename;
2520 const char *cpu_model;
2521 struct target_pt_regs regs1, *regs = &regs1;
2522 struct image_info info1, *info = &info1;
2523 struct linux_binprm bprm;
2524 TaskState ts1, *ts = &ts1;
2525 CPUState *env;
2526 int optind;
2527 const char *r;
2528 int gdbstub_port = 0;
2529 char **target_environ, **wrk;
2530 char **target_argv;
2531 int target_argc;
2532 envlist_t *envlist = NULL;
2533 const char *argv0 = NULL;
2534 int i;
2535 int ret;
2536
2537 if (argc <= 1)
2538 usage();
2539
2540 qemu_cache_utils_init(envp);
2541
2542 /* init debug */
2543 cpu_set_log_filename(DEBUG_LOGFILE);
2544
2545 if ((envlist = envlist_create()) == NULL) {
2546 (void) fprintf(stderr, "Unable to allocate envlist\n");
2547 exit(1);
2548 }
2549
2550 /* add current environment into the list */
2551 for (wrk = environ; *wrk != NULL; wrk++) {
2552 (void) envlist_setenv(envlist, *wrk);
2553 }
2554
2555 cpu_model = NULL;
2556 #if defined(cpudef_setup)
2557 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
2558 #endif
2559
2560 optind = 1;
2561 for(;;) {
2562 if (optind >= argc)
2563 break;
2564 r = argv[optind];
2565 if (r[0] != '-')
2566 break;
2567 optind++;
2568 r++;
2569 if (!strcmp(r, "-")) {
2570 break;
2571 } else if (!strcmp(r, "d")) {
2572 int mask;
2573 const CPULogItem *item;
2574
2575 if (optind >= argc)
2576 break;
2577
2578 r = argv[optind++];
2579 mask = cpu_str_to_log_mask(r);
2580 if (!mask) {
2581 printf("Log items (comma separated):\n");
2582 for(item = cpu_log_items; item->mask != 0; item++) {
2583 printf("%-10s %s\n", item->name, item->help);
2584 }
2585 exit(1);
2586 }
2587 cpu_set_log(mask);
2588 } else if (!strcmp(r, "E")) {
2589 r = argv[optind++];
2590 if (envlist_setenv(envlist, r) != 0)
2591 usage();
2592 } else if (!strcmp(r, "U")) {
2593 r = argv[optind++];
2594 if (envlist_unsetenv(envlist, r) != 0)
2595 usage();
2596 } else if (!strcmp(r, "0")) {
2597 r = argv[optind++];
2598 argv0 = r;
2599 } else if (!strcmp(r, "s")) {
2600 if (optind >= argc)
2601 break;
2602 r = argv[optind++];
2603 x86_stack_size = strtol(r, (char **)&r, 0);
2604 if (x86_stack_size <= 0)
2605 usage();
2606 if (*r == 'M')
2607 x86_stack_size *= 1024 * 1024;
2608 else if (*r == 'k' || *r == 'K')
2609 x86_stack_size *= 1024;
2610 } else if (!strcmp(r, "L")) {
2611 interp_prefix = argv[optind++];
2612 } else if (!strcmp(r, "p")) {
2613 if (optind >= argc)
2614 break;
2615 qemu_host_page_size = atoi(argv[optind++]);
2616 if (qemu_host_page_size == 0 ||
2617 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2618 fprintf(stderr, "page size must be a power of two\n");
2619 exit(1);
2620 }
2621 } else if (!strcmp(r, "g")) {
2622 if (optind >= argc)
2623 break;
2624 gdbstub_port = atoi(argv[optind++]);
2625 } else if (!strcmp(r, "r")) {
2626 qemu_uname_release = argv[optind++];
2627 } else if (!strcmp(r, "cpu")) {
2628 cpu_model = argv[optind++];
2629 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
2630 /* XXX: implement xxx_cpu_list for targets that still miss it */
2631 #if defined(cpu_list_id)
2632 cpu_list_id(stdout, &fprintf, "");
2633 #endif
2634 exit(1);
2635 }
2636 #if defined(CONFIG_USE_GUEST_BASE)
2637 } else if (!strcmp(r, "B")) {
2638 guest_base = strtol(argv[optind++], NULL, 0);
2639 have_guest_base = 1;
2640 #endif
2641 } else if (!strcmp(r, "drop-ld-preload")) {
2642 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
2643 } else if (!strcmp(r, "singlestep")) {
2644 singlestep = 1;
2645 } else if (!strcmp(r, "strace")) {
2646 do_strace = 1;
2647 } else
2648 {
2649 usage();
2650 }
2651 }
2652 if (optind >= argc)
2653 usage();
2654 filename = argv[optind];
2655 exec_path = argv[optind];
2656
2657 /* Zero out regs */
2658 memset(regs, 0, sizeof(struct target_pt_regs));
2659
2660 /* Zero out image_info */
2661 memset(info, 0, sizeof(struct image_info));
2662
2663 memset(&bprm, 0, sizeof (bprm));
2664
2665 /* Scan interp_prefix dir for replacement files. */
2666 init_paths(interp_prefix);
2667
2668 if (cpu_model == NULL) {
2669 #if defined(TARGET_I386)
2670 #ifdef TARGET_X86_64
2671 cpu_model = "qemu64";
2672 #else
2673 cpu_model = "qemu32";
2674 #endif
2675 #elif defined(TARGET_ARM)
2676 cpu_model = "any";
2677 #elif defined(TARGET_M68K)
2678 cpu_model = "any";
2679 #elif defined(TARGET_SPARC)
2680 #ifdef TARGET_SPARC64
2681 cpu_model = "TI UltraSparc II";
2682 #else
2683 cpu_model = "Fujitsu MB86904";
2684 #endif
2685 #elif defined(TARGET_MIPS)
2686 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2687 cpu_model = "20Kc";
2688 #else
2689 cpu_model = "24Kf";
2690 #endif
2691 #elif defined(TARGET_PPC)
2692 #ifdef TARGET_PPC64
2693 cpu_model = "970";
2694 #else
2695 cpu_model = "750";
2696 #endif
2697 #else
2698 cpu_model = "any";
2699 #endif
2700 }
2701 cpu_exec_init_all(0);
2702 /* NOTE: we need to init the CPU at this stage to get
2703 qemu_host_page_size */
2704 env = cpu_init(cpu_model);
2705 if (!env) {
2706 fprintf(stderr, "Unable to find CPU definition\n");
2707 exit(1);
2708 }
2709 #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
2710 cpu_reset(env);
2711 #endif
2712
2713 thread_env = env;
2714
2715 if (getenv("QEMU_STRACE")) {
2716 do_strace = 1;
2717 }
2718
2719 target_environ = envlist_to_environ(envlist, NULL);
2720 envlist_free(envlist);
2721
2722 #if defined(CONFIG_USE_GUEST_BASE)
2723 /*
2724 * Now that page sizes are configured in cpu_init() we can do
2725 * proper page alignment for guest_base.
2726 */
2727 guest_base = HOST_PAGE_ALIGN(guest_base);
2728
2729 /*
2730 * Read in mmap_min_addr kernel parameter. This value is used
2731 * When loading the ELF image to determine whether guest_base
2732 * is needed.
2733 *
2734 * When user has explicitly set the quest base, we skip this
2735 * test.
2736 */
2737 if (!have_guest_base) {
2738 FILE *fp;
2739
2740 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
2741 unsigned long tmp;
2742 if (fscanf(fp, "%lu", &tmp) == 1) {
2743 mmap_min_addr = tmp;
2744 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
2745 }
2746 fclose(fp);
2747 }
2748 }
2749 #endif /* CONFIG_USE_GUEST_BASE */
2750
2751 /*
2752 * Prepare copy of argv vector for target.
2753 */
2754 target_argc = argc - optind;
2755 target_argv = calloc(target_argc + 1, sizeof (char *));
2756 if (target_argv == NULL) {
2757 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
2758 exit(1);
2759 }
2760
2761 /*
2762 * If argv0 is specified (using '-0' switch) we replace
2763 * argv[0] pointer with the given one.
2764 */
2765 i = 0;
2766 if (argv0 != NULL) {
2767 target_argv[i++] = strdup(argv0);
2768 }
2769 for (; i < target_argc; i++) {
2770 target_argv[i] = strdup(argv[optind + i]);
2771 }
2772 target_argv[target_argc] = NULL;
2773
2774 memset(ts, 0, sizeof(TaskState));
2775 init_task_state(ts);
2776 /* build Task State */
2777 ts->info = info;
2778 ts->bprm = &bprm;
2779 env->opaque = ts;
2780 task_settid(ts);
2781
2782 ret = loader_exec(filename, target_argv, target_environ, regs,
2783 info, &bprm);
2784 if (ret != 0) {
2785 printf("Error %d while loading %s\n", ret, filename);
2786 _exit(1);
2787 }
2788
2789 for (i = 0; i < target_argc; i++) {
2790 free(target_argv[i]);
2791 }
2792 free(target_argv);
2793
2794 for (wrk = target_environ; *wrk; wrk++) {
2795 free(*wrk);
2796 }
2797
2798 free(target_environ);
2799
2800 if (qemu_log_enabled()) {
2801 #if defined(CONFIG_USE_GUEST_BASE)
2802 qemu_log("guest_base 0x%lx\n", guest_base);
2803 #endif
2804 log_page_dump();
2805
2806 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2807 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2808 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
2809 info->start_code);
2810 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
2811 info->start_data);
2812 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2813 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
2814 info->start_stack);
2815 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2816 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2817 }
2818
2819 target_set_brk(info->brk);
2820 syscall_init();
2821 signal_init();
2822
2823 #if defined(TARGET_I386)
2824 cpu_x86_set_cpl(env, 3);
2825
2826 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2827 env->hflags |= HF_PE_MASK;
2828 if (env->cpuid_features & CPUID_SSE) {
2829 env->cr[4] |= CR4_OSFXSR_MASK;
2830 env->hflags |= HF_OSFXSR_MASK;
2831 }
2832 #ifndef TARGET_ABI32
2833 /* enable 64 bit mode if possible */
2834 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2835 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2836 exit(1);
2837 }
2838 env->cr[4] |= CR4_PAE_MASK;
2839 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2840 env->hflags |= HF_LMA_MASK;
2841 #endif
2842
2843 /* flags setup : we activate the IRQs by default as in user mode */
2844 env->eflags |= IF_MASK;
2845
2846 /* linux register setup */
2847 #ifndef TARGET_ABI32
2848 env->regs[R_EAX] = regs->rax;
2849 env->regs[R_EBX] = regs->rbx;
2850 env->regs[R_ECX] = regs->rcx;
2851 env->regs[R_EDX] = regs->rdx;
2852 env->regs[R_ESI] = regs->rsi;
2853 env->regs[R_EDI] = regs->rdi;
2854 env->regs[R_EBP] = regs->rbp;
2855 env->regs[R_ESP] = regs->rsp;
2856 env->eip = regs->rip;
2857 #else
2858 env->regs[R_EAX] = regs->eax;
2859 env->regs[R_EBX] = regs->ebx;
2860 env->regs[R_ECX] = regs->ecx;
2861 env->regs[R_EDX] = regs->edx;
2862 env->regs[R_ESI] = regs->esi;
2863 env->regs[R_EDI] = regs->edi;
2864 env->regs[R_EBP] = regs->ebp;
2865 env->regs[R_ESP] = regs->esp;
2866 env->eip = regs->eip;
2867 #endif
2868
2869 /* linux interrupt setup */
2870 #ifndef TARGET_ABI32
2871 env->idt.limit = 511;
2872 #else
2873 env->idt.limit = 255;
2874 #endif
2875 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
2876 PROT_READ|PROT_WRITE,
2877 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2878 idt_table = g2h(env->idt.base);
2879 set_idt(0, 0);
2880 set_idt(1, 0);
2881 set_idt(2, 0);
2882 set_idt(3, 3);
2883 set_idt(4, 3);
2884 set_idt(5, 0);
2885 set_idt(6, 0);
2886 set_idt(7, 0);
2887 set_idt(8, 0);
2888 set_idt(9, 0);
2889 set_idt(10, 0);
2890 set_idt(11, 0);
2891 set_idt(12, 0);
2892 set_idt(13, 0);
2893 set_idt(14, 0);
2894 set_idt(15, 0);
2895 set_idt(16, 0);
2896 set_idt(17, 0);
2897 set_idt(18, 0);
2898 set_idt(19, 0);
2899 set_idt(0x80, 3);
2900
2901 /* linux segment setup */
2902 {
2903 uint64_t *gdt_table;
2904 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
2905 PROT_READ|PROT_WRITE,
2906 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2907 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
2908 gdt_table = g2h(env->gdt.base);
2909 #ifdef TARGET_ABI32
2910 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2911 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2912 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2913 #else
2914 /* 64 bit code segment */
2915 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2916 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2917 DESC_L_MASK |
2918 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2919 #endif
2920 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
2921 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2922 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
2923 }
2924 cpu_x86_load_seg(env, R_CS, __USER_CS);
2925 cpu_x86_load_seg(env, R_SS, __USER_DS);
2926 #ifdef TARGET_ABI32
2927 cpu_x86_load_seg(env, R_DS, __USER_DS);
2928 cpu_x86_load_seg(env, R_ES, __USER_DS);
2929 cpu_x86_load_seg(env, R_FS, __USER_DS);
2930 cpu_x86_load_seg(env, R_GS, __USER_DS);
2931 /* This hack makes Wine work... */
2932 env->segs[R_FS].selector = 0;
2933 #else
2934 cpu_x86_load_seg(env, R_DS, 0);
2935 cpu_x86_load_seg(env, R_ES, 0);
2936 cpu_x86_load_seg(env, R_FS, 0);
2937 cpu_x86_load_seg(env, R_GS, 0);
2938 #endif
2939 #elif defined(TARGET_ARM)
2940 {
2941 int i;
2942 cpsr_write(env, regs->uregs[16], 0xffffffff);
2943 for(i = 0; i < 16; i++) {
2944 env->regs[i] = regs->uregs[i];
2945 }
2946 }
2947 #elif defined(TARGET_SPARC)
2948 {
2949 int i;
2950 env->pc = regs->pc;
2951 env->npc = regs->npc;
2952 env->y = regs->y;
2953 for(i = 0; i < 8; i++)
2954 env->gregs[i] = regs->u_regs[i];
2955 for(i = 0; i < 8; i++)
2956 env->regwptr[i] = regs->u_regs[i + 8];
2957 }
2958 #elif defined(TARGET_PPC)
2959 {
2960 int i;
2961
2962 #if defined(TARGET_PPC64)
2963 #if defined(TARGET_ABI32)
2964 env->msr &= ~((target_ulong)1 << MSR_SF);
2965 #else
2966 env->msr |= (target_ulong)1 << MSR_SF;
2967 #endif
2968 #endif
2969 env->nip = regs->nip;
2970 for(i = 0; i < 32; i++) {
2971 env->gpr[i] = regs->gpr[i];
2972 }
2973 }
2974 #elif defined(TARGET_M68K)
2975 {
2976 env->pc = regs->pc;
2977 env->dregs[0] = regs->d0;
2978 env->dregs[1] = regs->d1;
2979 env->dregs[2] = regs->d2;
2980 env->dregs[3] = regs->d3;
2981 env->dregs[4] = regs->d4;
2982 env->dregs[5] = regs->d5;
2983 env->dregs[6] = regs->d6;
2984 env->dregs[7] = regs->d7;
2985 env->aregs[0] = regs->a0;
2986 env->aregs[1] = regs->a1;
2987 env->aregs[2] = regs->a2;
2988 env->aregs[3] = regs->a3;
2989 env->aregs[4] = regs->a4;
2990 env->aregs[5] = regs->a5;
2991 env->aregs[6] = regs->a6;
2992 env->aregs[7] = regs->usp;
2993 env->sr = regs->sr;
2994 ts->sim_syscalls = 1;
2995 }
2996 #elif defined(TARGET_MICROBLAZE)
2997 {
2998 env->regs[0] = regs->r0;
2999 env->regs[1] = regs->r1;
3000 env->regs[2] = regs->r2;
3001 env->regs[3] = regs->r3;
3002 env->regs[4] = regs->r4;
3003 env->regs[5] = regs->r5;
3004 env->regs[6] = regs->r6;
3005 env->regs[7] = regs->r7;
3006 env->regs[8] = regs->r8;
3007 env->regs[9] = regs->r9;
3008 env->regs[10] = regs->r10;
3009 env->regs[11] = regs->r11;
3010 env->regs[12] = regs->r12;
3011 env->regs[13] = regs->r13;
3012 env->regs[14] = regs->r14;
3013 env->regs[15] = regs->r15;
3014 env->regs[16] = regs->r16;
3015 env->regs[17] = regs->r17;
3016 env->regs[18] = regs->r18;
3017 env->regs[19] = regs->r19;
3018 env->regs[20] = regs->r20;
3019 env->regs[21] = regs->r21;
3020 env->regs[22] = regs->r22;
3021 env->regs[23] = regs->r23;
3022 env->regs[24] = regs->r24;
3023 env->regs[25] = regs->r25;
3024 env->regs[26] = regs->r26;
3025 env->regs[27] = regs->r27;
3026 env->regs[28] = regs->r28;
3027 env->regs[29] = regs->r29;
3028 env->regs[30] = regs->r30;
3029 env->regs[31] = regs->r31;
3030 env->sregs[SR_PC] = regs->pc;
3031 }
3032 #elif defined(TARGET_MIPS)
3033 {
3034 int i;
3035
3036 for(i = 0; i < 32; i++) {
3037 env->active_tc.gpr[i] = regs->regs[i];
3038 }
3039 env->active_tc.PC = regs->cp0_epc;
3040 }
3041 #elif defined(TARGET_SH4)
3042 {
3043 int i;
3044
3045 for(i = 0; i < 16; i++) {
3046 env->gregs[i] = regs->regs[i];
3047 }
3048 env->pc = regs->pc;
3049 }
3050 #elif defined(TARGET_ALPHA)
3051 {
3052 int i;
3053
3054 for(i = 0; i < 28; i++) {
3055 env->ir[i] = ((abi_ulong *)regs)[i];
3056 }
3057 env->ir[IR_SP] = regs->usp;
3058 env->pc = regs->pc;
3059 }
3060 #elif defined(TARGET_CRIS)
3061 {
3062 env->regs[0] = regs->r0;
3063 env->regs[1] = regs->r1;
3064 env->regs[2] = regs->r2;
3065 env->regs[3] = regs->r3;
3066 env->regs[4] = regs->r4;
3067 env->regs[5] = regs->r5;
3068 env->regs[6] = regs->r6;
3069 env->regs[7] = regs->r7;
3070 env->regs[8] = regs->r8;
3071 env->regs[9] = regs->r9;
3072 env->regs[10] = regs->r10;
3073 env->regs[11] = regs->r11;
3074 env->regs[12] = regs->r12;
3075 env->regs[13] = regs->r13;
3076 env->regs[14] = info->start_stack;
3077 env->regs[15] = regs->acr;
3078 env->pc = regs->erp;
3079 }
3080 #else
3081 #error unsupported target CPU
3082 #endif
3083
3084 #if defined(TARGET_ARM) || defined(TARGET_M68K)
3085 ts->stack_base = info->start_stack;
3086 ts->heap_base = info->brk;
3087 /* This will be filled in on the first SYS_HEAPINFO call. */
3088 ts->heap_limit = 0;
3089 #endif
3090
3091 if (gdbstub_port) {
3092 gdbserver_start (gdbstub_port);
3093 gdb_handlesig(env, 0);
3094 }
3095 cpu_loop(env);
3096 /* never exits */
3097 return 0;
3098 }
Qemu copy for testing