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[qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "qemu/cache-utils.h"
32 #include "cpu.h"
33 #include "tcg.h"
34 #include "qemu/timer.h"
35 #include "qemu/envlist.h"
36 #include "elf.h"
37
38 char *exec_path;
39
40 int singlestep;
41 const char *filename;
42 const char *argv0;
43 int gdbstub_port;
44 envlist_t *envlist;
45 const char *cpu_model;
46 unsigned long mmap_min_addr;
47 #if defined(CONFIG_USE_GUEST_BASE)
48 unsigned long guest_base;
49 int have_guest_base;
50 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51 /*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
58 # ifdef TARGET_MIPS
59 /* MIPS only supports 31 bits of virtual address space for user space */
60 unsigned long reserved_va = 0x77000000;
61 # else
62 unsigned long reserved_va = 0xf7000000;
63 # endif
64 #else
65 unsigned long reserved_va;
66 #endif
67 #endif
68
69 static void usage(void);
70
71 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
72 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
73
74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
77 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
78
79 void gemu_log(const char *fmt, ...)
80 {
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86 }
87
88 #if defined(TARGET_I386)
89 int cpu_get_pic_interrupt(CPUX86State *env)
90 {
91 return -1;
92 }
93 #endif
94
95 #if defined(CONFIG_USE_NPTL)
96 /***********************************************************/
97 /* Helper routines for implementing atomic operations. */
98
99 /* To implement exclusive operations we force all cpus to syncronise.
100 We don't require a full sync, only that no cpus are executing guest code.
101 The alternative is to map target atomic ops onto host equivalents,
102 which requires quite a lot of per host/target work. */
103 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
104 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
105 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
106 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
107 static int pending_cpus;
108
109 /* Make sure everything is in a consistent state for calling fork(). */
110 void fork_start(void)
111 {
112 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
113 pthread_mutex_lock(&exclusive_lock);
114 mmap_fork_start();
115 }
116
117 void fork_end(int child)
118 {
119 mmap_fork_end(child);
120 if (child) {
121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
123 first_cpu = ENV_GET_CPU(thread_env);
124 first_cpu->next_cpu = NULL;
125 pending_cpus = 0;
126 pthread_mutex_init(&exclusive_lock, NULL);
127 pthread_mutex_init(&cpu_list_mutex, NULL);
128 pthread_cond_init(&exclusive_cond, NULL);
129 pthread_cond_init(&exclusive_resume, NULL);
130 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
131 gdbserver_fork(thread_env);
132 } else {
133 pthread_mutex_unlock(&exclusive_lock);
134 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
135 }
136 }
137
138 /* Wait for pending exclusive operations to complete. The exclusive lock
139 must be held. */
140 static inline void exclusive_idle(void)
141 {
142 while (pending_cpus) {
143 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
144 }
145 }
146
147 /* Start an exclusive operation.
148 Must only be called from outside cpu_arm_exec. */
149 static inline void start_exclusive(void)
150 {
151 CPUState *other_cpu;
152
153 pthread_mutex_lock(&exclusive_lock);
154 exclusive_idle();
155
156 pending_cpus = 1;
157 /* Make all other cpus stop executing. */
158 for (other_cpu = first_cpu; other_cpu; other_cpu = other_cpu->next_cpu) {
159 if (other_cpu->running) {
160 pending_cpus++;
161 cpu_exit(other_cpu);
162 }
163 }
164 if (pending_cpus > 1) {
165 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
166 }
167 }
168
169 /* Finish an exclusive operation. */
170 static inline void end_exclusive(void)
171 {
172 pending_cpus = 0;
173 pthread_cond_broadcast(&exclusive_resume);
174 pthread_mutex_unlock(&exclusive_lock);
175 }
176
177 /* Wait for exclusive ops to finish, and begin cpu execution. */
178 static inline void cpu_exec_start(CPUState *cpu)
179 {
180 pthread_mutex_lock(&exclusive_lock);
181 exclusive_idle();
182 cpu->running = true;
183 pthread_mutex_unlock(&exclusive_lock);
184 }
185
186 /* Mark cpu as not executing, and release pending exclusive ops. */
187 static inline void cpu_exec_end(CPUState *cpu)
188 {
189 pthread_mutex_lock(&exclusive_lock);
190 cpu->running = false;
191 if (pending_cpus > 1) {
192 pending_cpus--;
193 if (pending_cpus == 1) {
194 pthread_cond_signal(&exclusive_cond);
195 }
196 }
197 exclusive_idle();
198 pthread_mutex_unlock(&exclusive_lock);
199 }
200
201 void cpu_list_lock(void)
202 {
203 pthread_mutex_lock(&cpu_list_mutex);
204 }
205
206 void cpu_list_unlock(void)
207 {
208 pthread_mutex_unlock(&cpu_list_mutex);
209 }
210 #else /* if !CONFIG_USE_NPTL */
211 /* These are no-ops because we are not threadsafe. */
212 static inline void cpu_exec_start(CPUState *cpu)
213 {
214 }
215
216 static inline void cpu_exec_end(CPUState *cpu)
217 {
218 }
219
220 static inline void start_exclusive(void)
221 {
222 }
223
224 static inline void end_exclusive(void)
225 {
226 }
227
228 void fork_start(void)
229 {
230 }
231
232 void fork_end(int child)
233 {
234 if (child) {
235 gdbserver_fork(thread_env);
236 }
237 }
238
239 void cpu_list_lock(void)
240 {
241 }
242
243 void cpu_list_unlock(void)
244 {
245 }
246 #endif
247
248
249 #ifdef TARGET_I386
250 /***********************************************************/
251 /* CPUX86 core interface */
252
253 void cpu_smm_update(CPUX86State *env)
254 {
255 }
256
257 uint64_t cpu_get_tsc(CPUX86State *env)
258 {
259 return cpu_get_real_ticks();
260 }
261
262 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
263 int flags)
264 {
265 unsigned int e1, e2;
266 uint32_t *p;
267 e1 = (addr << 16) | (limit & 0xffff);
268 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
269 e2 |= flags;
270 p = ptr;
271 p[0] = tswap32(e1);
272 p[1] = tswap32(e2);
273 }
274
275 static uint64_t *idt_table;
276 #ifdef TARGET_X86_64
277 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
278 uint64_t addr, unsigned int sel)
279 {
280 uint32_t *p, e1, e2;
281 e1 = (addr & 0xffff) | (sel << 16);
282 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
283 p = ptr;
284 p[0] = tswap32(e1);
285 p[1] = tswap32(e2);
286 p[2] = tswap32(addr >> 32);
287 p[3] = 0;
288 }
289 /* only dpl matters as we do only user space emulation */
290 static void set_idt(int n, unsigned int dpl)
291 {
292 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
293 }
294 #else
295 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
296 uint32_t addr, unsigned int sel)
297 {
298 uint32_t *p, e1, e2;
299 e1 = (addr & 0xffff) | (sel << 16);
300 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
301 p = ptr;
302 p[0] = tswap32(e1);
303 p[1] = tswap32(e2);
304 }
305
306 /* only dpl matters as we do only user space emulation */
307 static void set_idt(int n, unsigned int dpl)
308 {
309 set_gate(idt_table + n, 0, dpl, 0, 0);
310 }
311 #endif
312
313 void cpu_loop(CPUX86State *env)
314 {
315 int trapnr;
316 abi_ulong pc;
317 target_siginfo_t info;
318
319 for(;;) {
320 trapnr = cpu_x86_exec(env);
321 switch(trapnr) {
322 case 0x80:
323 /* linux syscall from int $0x80 */
324 env->regs[R_EAX] = do_syscall(env,
325 env->regs[R_EAX],
326 env->regs[R_EBX],
327 env->regs[R_ECX],
328 env->regs[R_EDX],
329 env->regs[R_ESI],
330 env->regs[R_EDI],
331 env->regs[R_EBP],
332 0, 0);
333 break;
334 #ifndef TARGET_ABI32
335 case EXCP_SYSCALL:
336 /* linux syscall from syscall instruction */
337 env->regs[R_EAX] = do_syscall(env,
338 env->regs[R_EAX],
339 env->regs[R_EDI],
340 env->regs[R_ESI],
341 env->regs[R_EDX],
342 env->regs[10],
343 env->regs[8],
344 env->regs[9],
345 0, 0);
346 env->eip = env->exception_next_eip;
347 break;
348 #endif
349 case EXCP0B_NOSEG:
350 case EXCP0C_STACK:
351 info.si_signo = SIGBUS;
352 info.si_errno = 0;
353 info.si_code = TARGET_SI_KERNEL;
354 info._sifields._sigfault._addr = 0;
355 queue_signal(env, info.si_signo, &info);
356 break;
357 case EXCP0D_GPF:
358 /* XXX: potential problem if ABI32 */
359 #ifndef TARGET_X86_64
360 if (env->eflags & VM_MASK) {
361 handle_vm86_fault(env);
362 } else
363 #endif
364 {
365 info.si_signo = SIGSEGV;
366 info.si_errno = 0;
367 info.si_code = TARGET_SI_KERNEL;
368 info._sifields._sigfault._addr = 0;
369 queue_signal(env, info.si_signo, &info);
370 }
371 break;
372 case EXCP0E_PAGE:
373 info.si_signo = SIGSEGV;
374 info.si_errno = 0;
375 if (!(env->error_code & 1))
376 info.si_code = TARGET_SEGV_MAPERR;
377 else
378 info.si_code = TARGET_SEGV_ACCERR;
379 info._sifields._sigfault._addr = env->cr[2];
380 queue_signal(env, info.si_signo, &info);
381 break;
382 case EXCP00_DIVZ:
383 #ifndef TARGET_X86_64
384 if (env->eflags & VM_MASK) {
385 handle_vm86_trap(env, trapnr);
386 } else
387 #endif
388 {
389 /* division by zero */
390 info.si_signo = SIGFPE;
391 info.si_errno = 0;
392 info.si_code = TARGET_FPE_INTDIV;
393 info._sifields._sigfault._addr = env->eip;
394 queue_signal(env, info.si_signo, &info);
395 }
396 break;
397 case EXCP01_DB:
398 case EXCP03_INT3:
399 #ifndef TARGET_X86_64
400 if (env->eflags & VM_MASK) {
401 handle_vm86_trap(env, trapnr);
402 } else
403 #endif
404 {
405 info.si_signo = SIGTRAP;
406 info.si_errno = 0;
407 if (trapnr == EXCP01_DB) {
408 info.si_code = TARGET_TRAP_BRKPT;
409 info._sifields._sigfault._addr = env->eip;
410 } else {
411 info.si_code = TARGET_SI_KERNEL;
412 info._sifields._sigfault._addr = 0;
413 }
414 queue_signal(env, info.si_signo, &info);
415 }
416 break;
417 case EXCP04_INTO:
418 case EXCP05_BOUND:
419 #ifndef TARGET_X86_64
420 if (env->eflags & VM_MASK) {
421 handle_vm86_trap(env, trapnr);
422 } else
423 #endif
424 {
425 info.si_signo = SIGSEGV;
426 info.si_errno = 0;
427 info.si_code = TARGET_SI_KERNEL;
428 info._sifields._sigfault._addr = 0;
429 queue_signal(env, info.si_signo, &info);
430 }
431 break;
432 case EXCP06_ILLOP:
433 info.si_signo = SIGILL;
434 info.si_errno = 0;
435 info.si_code = TARGET_ILL_ILLOPN;
436 info._sifields._sigfault._addr = env->eip;
437 queue_signal(env, info.si_signo, &info);
438 break;
439 case EXCP_INTERRUPT:
440 /* just indicate that signals should be handled asap */
441 break;
442 case EXCP_DEBUG:
443 {
444 int sig;
445
446 sig = gdb_handlesig (env, TARGET_SIGTRAP);
447 if (sig)
448 {
449 info.si_signo = sig;
450 info.si_errno = 0;
451 info.si_code = TARGET_TRAP_BRKPT;
452 queue_signal(env, info.si_signo, &info);
453 }
454 }
455 break;
456 default:
457 pc = env->segs[R_CS].base + env->eip;
458 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
459 (long)pc, trapnr);
460 abort();
461 }
462 process_pending_signals(env);
463 }
464 }
465 #endif
466
467 #ifdef TARGET_ARM
468
469 #define get_user_code_u32(x, gaddr, doswap) \
470 ({ abi_long __r = get_user_u32((x), (gaddr)); \
471 if (!__r && (doswap)) { \
472 (x) = bswap32(x); \
473 } \
474 __r; \
475 })
476
477 #define get_user_code_u16(x, gaddr, doswap) \
478 ({ abi_long __r = get_user_u16((x), (gaddr)); \
479 if (!__r && (doswap)) { \
480 (x) = bswap16(x); \
481 } \
482 __r; \
483 })
484
485 /*
486 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
487 * Input:
488 * r0 = pointer to oldval
489 * r1 = pointer to newval
490 * r2 = pointer to target value
491 *
492 * Output:
493 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
494 * C set if *ptr was changed, clear if no exchange happened
495 *
496 * Note segv's in kernel helpers are a bit tricky, we can set the
497 * data address sensibly but the PC address is just the entry point.
498 */
499 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
500 {
501 uint64_t oldval, newval, val;
502 uint32_t addr, cpsr;
503 target_siginfo_t info;
504
505 /* Based on the 32 bit code in do_kernel_trap */
506
507 /* XXX: This only works between threads, not between processes.
508 It's probably possible to implement this with native host
509 operations. However things like ldrex/strex are much harder so
510 there's not much point trying. */
511 start_exclusive();
512 cpsr = cpsr_read(env);
513 addr = env->regs[2];
514
515 if (get_user_u64(oldval, env->regs[0])) {
516 env->cp15.c6_data = env->regs[0];
517 goto segv;
518 };
519
520 if (get_user_u64(newval, env->regs[1])) {
521 env->cp15.c6_data = env->regs[1];
522 goto segv;
523 };
524
525 if (get_user_u64(val, addr)) {
526 env->cp15.c6_data = addr;
527 goto segv;
528 }
529
530 if (val == oldval) {
531 val = newval;
532
533 if (put_user_u64(val, addr)) {
534 env->cp15.c6_data = addr;
535 goto segv;
536 };
537
538 env->regs[0] = 0;
539 cpsr |= CPSR_C;
540 } else {
541 env->regs[0] = -1;
542 cpsr &= ~CPSR_C;
543 }
544 cpsr_write(env, cpsr, CPSR_C);
545 end_exclusive();
546 return;
547
548 segv:
549 end_exclusive();
550 /* We get the PC of the entry address - which is as good as anything,
551 on a real kernel what you get depends on which mode it uses. */
552 info.si_signo = SIGSEGV;
553 info.si_errno = 0;
554 /* XXX: check env->error_code */
555 info.si_code = TARGET_SEGV_MAPERR;
556 info._sifields._sigfault._addr = env->cp15.c6_data;
557 queue_signal(env, info.si_signo, &info);
558
559 end_exclusive();
560 }
561
562 /* Handle a jump to the kernel code page. */
563 static int
564 do_kernel_trap(CPUARMState *env)
565 {
566 uint32_t addr;
567 uint32_t cpsr;
568 uint32_t val;
569
570 switch (env->regs[15]) {
571 case 0xffff0fa0: /* __kernel_memory_barrier */
572 /* ??? No-op. Will need to do better for SMP. */
573 break;
574 case 0xffff0fc0: /* __kernel_cmpxchg */
575 /* XXX: This only works between threads, not between processes.
576 It's probably possible to implement this with native host
577 operations. However things like ldrex/strex are much harder so
578 there's not much point trying. */
579 start_exclusive();
580 cpsr = cpsr_read(env);
581 addr = env->regs[2];
582 /* FIXME: This should SEGV if the access fails. */
583 if (get_user_u32(val, addr))
584 val = ~env->regs[0];
585 if (val == env->regs[0]) {
586 val = env->regs[1];
587 /* FIXME: Check for segfaults. */
588 put_user_u32(val, addr);
589 env->regs[0] = 0;
590 cpsr |= CPSR_C;
591 } else {
592 env->regs[0] = -1;
593 cpsr &= ~CPSR_C;
594 }
595 cpsr_write(env, cpsr, CPSR_C);
596 end_exclusive();
597 break;
598 case 0xffff0fe0: /* __kernel_get_tls */
599 env->regs[0] = env->cp15.c13_tls2;
600 break;
601 case 0xffff0f60: /* __kernel_cmpxchg64 */
602 arm_kernel_cmpxchg64_helper(env);
603 break;
604
605 default:
606 return 1;
607 }
608 /* Jump back to the caller. */
609 addr = env->regs[14];
610 if (addr & 1) {
611 env->thumb = 1;
612 addr &= ~1;
613 }
614 env->regs[15] = addr;
615
616 return 0;
617 }
618
619 static int do_strex(CPUARMState *env)
620 {
621 uint32_t val;
622 int size;
623 int rc = 1;
624 int segv = 0;
625 uint32_t addr;
626 start_exclusive();
627 addr = env->exclusive_addr;
628 if (addr != env->exclusive_test) {
629 goto fail;
630 }
631 size = env->exclusive_info & 0xf;
632 switch (size) {
633 case 0:
634 segv = get_user_u8(val, addr);
635 break;
636 case 1:
637 segv = get_user_u16(val, addr);
638 break;
639 case 2:
640 case 3:
641 segv = get_user_u32(val, addr);
642 break;
643 default:
644 abort();
645 }
646 if (segv) {
647 env->cp15.c6_data = addr;
648 goto done;
649 }
650 if (val != env->exclusive_val) {
651 goto fail;
652 }
653 if (size == 3) {
654 segv = get_user_u32(val, addr + 4);
655 if (segv) {
656 env->cp15.c6_data = addr + 4;
657 goto done;
658 }
659 if (val != env->exclusive_high) {
660 goto fail;
661 }
662 }
663 val = env->regs[(env->exclusive_info >> 8) & 0xf];
664 switch (size) {
665 case 0:
666 segv = put_user_u8(val, addr);
667 break;
668 case 1:
669 segv = put_user_u16(val, addr);
670 break;
671 case 2:
672 case 3:
673 segv = put_user_u32(val, addr);
674 break;
675 }
676 if (segv) {
677 env->cp15.c6_data = addr;
678 goto done;
679 }
680 if (size == 3) {
681 val = env->regs[(env->exclusive_info >> 12) & 0xf];
682 segv = put_user_u32(val, addr + 4);
683 if (segv) {
684 env->cp15.c6_data = addr + 4;
685 goto done;
686 }
687 }
688 rc = 0;
689 fail:
690 env->regs[15] += 4;
691 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
692 done:
693 end_exclusive();
694 return segv;
695 }
696
697 void cpu_loop(CPUARMState *env)
698 {
699 CPUState *cs = CPU(arm_env_get_cpu(env));
700 int trapnr;
701 unsigned int n, insn;
702 target_siginfo_t info;
703 uint32_t addr;
704
705 for(;;) {
706 cpu_exec_start(cs);
707 trapnr = cpu_arm_exec(env);
708 cpu_exec_end(cs);
709 switch(trapnr) {
710 case EXCP_UDEF:
711 {
712 TaskState *ts = env->opaque;
713 uint32_t opcode;
714 int rc;
715
716 /* we handle the FPU emulation here, as Linux */
717 /* we get the opcode */
718 /* FIXME - what to do if get_user() fails? */
719 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
720
721 rc = EmulateAll(opcode, &ts->fpa, env);
722 if (rc == 0) { /* illegal instruction */
723 info.si_signo = SIGILL;
724 info.si_errno = 0;
725 info.si_code = TARGET_ILL_ILLOPN;
726 info._sifields._sigfault._addr = env->regs[15];
727 queue_signal(env, info.si_signo, &info);
728 } else if (rc < 0) { /* FP exception */
729 int arm_fpe=0;
730
731 /* translate softfloat flags to FPSR flags */
732 if (-rc & float_flag_invalid)
733 arm_fpe |= BIT_IOC;
734 if (-rc & float_flag_divbyzero)
735 arm_fpe |= BIT_DZC;
736 if (-rc & float_flag_overflow)
737 arm_fpe |= BIT_OFC;
738 if (-rc & float_flag_underflow)
739 arm_fpe |= BIT_UFC;
740 if (-rc & float_flag_inexact)
741 arm_fpe |= BIT_IXC;
742
743 FPSR fpsr = ts->fpa.fpsr;
744 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
745
746 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
747 info.si_signo = SIGFPE;
748 info.si_errno = 0;
749
750 /* ordered by priority, least first */
751 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
752 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
753 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
754 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
755 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
756
757 info._sifields._sigfault._addr = env->regs[15];
758 queue_signal(env, info.si_signo, &info);
759 } else {
760 env->regs[15] += 4;
761 }
762
763 /* accumulate unenabled exceptions */
764 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
765 fpsr |= BIT_IXC;
766 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
767 fpsr |= BIT_UFC;
768 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
769 fpsr |= BIT_OFC;
770 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
771 fpsr |= BIT_DZC;
772 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
773 fpsr |= BIT_IOC;
774 ts->fpa.fpsr=fpsr;
775 } else { /* everything OK */
776 /* increment PC */
777 env->regs[15] += 4;
778 }
779 }
780 break;
781 case EXCP_SWI:
782 case EXCP_BKPT:
783 {
784 env->eabi = 1;
785 /* system call */
786 if (trapnr == EXCP_BKPT) {
787 if (env->thumb) {
788 /* FIXME - what to do if get_user() fails? */
789 get_user_code_u16(insn, env->regs[15], env->bswap_code);
790 n = insn & 0xff;
791 env->regs[15] += 2;
792 } else {
793 /* FIXME - what to do if get_user() fails? */
794 get_user_code_u32(insn, env->regs[15], env->bswap_code);
795 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
796 env->regs[15] += 4;
797 }
798 } else {
799 if (env->thumb) {
800 /* FIXME - what to do if get_user() fails? */
801 get_user_code_u16(insn, env->regs[15] - 2,
802 env->bswap_code);
803 n = insn & 0xff;
804 } else {
805 /* FIXME - what to do if get_user() fails? */
806 get_user_code_u32(insn, env->regs[15] - 4,
807 env->bswap_code);
808 n = insn & 0xffffff;
809 }
810 }
811
812 if (n == ARM_NR_cacheflush) {
813 /* nop */
814 } else if (n == ARM_NR_semihosting
815 || n == ARM_NR_thumb_semihosting) {
816 env->regs[0] = do_arm_semihosting (env);
817 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
818 /* linux syscall */
819 if (env->thumb || n == 0) {
820 n = env->regs[7];
821 } else {
822 n -= ARM_SYSCALL_BASE;
823 env->eabi = 0;
824 }
825 if ( n > ARM_NR_BASE) {
826 switch (n) {
827 case ARM_NR_cacheflush:
828 /* nop */
829 break;
830 case ARM_NR_set_tls:
831 cpu_set_tls(env, env->regs[0]);
832 env->regs[0] = 0;
833 break;
834 default:
835 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
836 n);
837 env->regs[0] = -TARGET_ENOSYS;
838 break;
839 }
840 } else {
841 env->regs[0] = do_syscall(env,
842 n,
843 env->regs[0],
844 env->regs[1],
845 env->regs[2],
846 env->regs[3],
847 env->regs[4],
848 env->regs[5],
849 0, 0);
850 }
851 } else {
852 goto error;
853 }
854 }
855 break;
856 case EXCP_INTERRUPT:
857 /* just indicate that signals should be handled asap */
858 break;
859 case EXCP_PREFETCH_ABORT:
860 addr = env->cp15.c6_insn;
861 goto do_segv;
862 case EXCP_DATA_ABORT:
863 addr = env->cp15.c6_data;
864 do_segv:
865 {
866 info.si_signo = SIGSEGV;
867 info.si_errno = 0;
868 /* XXX: check env->error_code */
869 info.si_code = TARGET_SEGV_MAPERR;
870 info._sifields._sigfault._addr = addr;
871 queue_signal(env, info.si_signo, &info);
872 }
873 break;
874 case EXCP_DEBUG:
875 {
876 int sig;
877
878 sig = gdb_handlesig (env, TARGET_SIGTRAP);
879 if (sig)
880 {
881 info.si_signo = sig;
882 info.si_errno = 0;
883 info.si_code = TARGET_TRAP_BRKPT;
884 queue_signal(env, info.si_signo, &info);
885 }
886 }
887 break;
888 case EXCP_KERNEL_TRAP:
889 if (do_kernel_trap(env))
890 goto error;
891 break;
892 case EXCP_STREX:
893 if (do_strex(env)) {
894 addr = env->cp15.c6_data;
895 goto do_segv;
896 }
897 break;
898 default:
899 error:
900 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
901 trapnr);
902 cpu_dump_state(cs, stderr, fprintf, 0);
903 abort();
904 }
905 process_pending_signals(env);
906 }
907 }
908
909 #endif
910
911 #ifdef TARGET_UNICORE32
912
913 void cpu_loop(CPUUniCore32State *env)
914 {
915 CPUState *cs = CPU(uc32_env_get_cpu(env));
916 int trapnr;
917 unsigned int n, insn;
918 target_siginfo_t info;
919
920 for (;;) {
921 cpu_exec_start(cs);
922 trapnr = uc32_cpu_exec(env);
923 cpu_exec_end(cs);
924 switch (trapnr) {
925 case UC32_EXCP_PRIV:
926 {
927 /* system call */
928 get_user_u32(insn, env->regs[31] - 4);
929 n = insn & 0xffffff;
930
931 if (n >= UC32_SYSCALL_BASE) {
932 /* linux syscall */
933 n -= UC32_SYSCALL_BASE;
934 if (n == UC32_SYSCALL_NR_set_tls) {
935 cpu_set_tls(env, env->regs[0]);
936 env->regs[0] = 0;
937 } else {
938 env->regs[0] = do_syscall(env,
939 n,
940 env->regs[0],
941 env->regs[1],
942 env->regs[2],
943 env->regs[3],
944 env->regs[4],
945 env->regs[5],
946 0, 0);
947 }
948 } else {
949 goto error;
950 }
951 }
952 break;
953 case UC32_EXCP_DTRAP:
954 case UC32_EXCP_ITRAP:
955 info.si_signo = SIGSEGV;
956 info.si_errno = 0;
957 /* XXX: check env->error_code */
958 info.si_code = TARGET_SEGV_MAPERR;
959 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
960 queue_signal(env, info.si_signo, &info);
961 break;
962 case EXCP_INTERRUPT:
963 /* just indicate that signals should be handled asap */
964 break;
965 case EXCP_DEBUG:
966 {
967 int sig;
968
969 sig = gdb_handlesig(env, TARGET_SIGTRAP);
970 if (sig) {
971 info.si_signo = sig;
972 info.si_errno = 0;
973 info.si_code = TARGET_TRAP_BRKPT;
974 queue_signal(env, info.si_signo, &info);
975 }
976 }
977 break;
978 default:
979 goto error;
980 }
981 process_pending_signals(env);
982 }
983
984 error:
985 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
986 cpu_dump_state(cs, stderr, fprintf, 0);
987 abort();
988 }
989 #endif
990
991 #ifdef TARGET_SPARC
992 #define SPARC64_STACK_BIAS 2047
993
994 //#define DEBUG_WIN
995
996 /* WARNING: dealing with register windows _is_ complicated. More info
997 can be found at http://www.sics.se/~psm/sparcstack.html */
998 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
999 {
1000 index = (index + cwp * 16) % (16 * env->nwindows);
1001 /* wrap handling : if cwp is on the last window, then we use the
1002 registers 'after' the end */
1003 if (index < 8 && env->cwp == env->nwindows - 1)
1004 index += 16 * env->nwindows;
1005 return index;
1006 }
1007
1008 /* save the register window 'cwp1' */
1009 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1010 {
1011 unsigned int i;
1012 abi_ulong sp_ptr;
1013
1014 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1015 #ifdef TARGET_SPARC64
1016 if (sp_ptr & 3)
1017 sp_ptr += SPARC64_STACK_BIAS;
1018 #endif
1019 #if defined(DEBUG_WIN)
1020 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1021 sp_ptr, cwp1);
1022 #endif
1023 for(i = 0; i < 16; i++) {
1024 /* FIXME - what to do if put_user() fails? */
1025 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1026 sp_ptr += sizeof(abi_ulong);
1027 }
1028 }
1029
1030 static void save_window(CPUSPARCState *env)
1031 {
1032 #ifndef TARGET_SPARC64
1033 unsigned int new_wim;
1034 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1035 ((1LL << env->nwindows) - 1);
1036 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1037 env->wim = new_wim;
1038 #else
1039 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1040 env->cansave++;
1041 env->canrestore--;
1042 #endif
1043 }
1044
1045 static void restore_window(CPUSPARCState *env)
1046 {
1047 #ifndef TARGET_SPARC64
1048 unsigned int new_wim;
1049 #endif
1050 unsigned int i, cwp1;
1051 abi_ulong sp_ptr;
1052
1053 #ifndef TARGET_SPARC64
1054 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1055 ((1LL << env->nwindows) - 1);
1056 #endif
1057
1058 /* restore the invalid window */
1059 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1060 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1061 #ifdef TARGET_SPARC64
1062 if (sp_ptr & 3)
1063 sp_ptr += SPARC64_STACK_BIAS;
1064 #endif
1065 #if defined(DEBUG_WIN)
1066 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1067 sp_ptr, cwp1);
1068 #endif
1069 for(i = 0; i < 16; i++) {
1070 /* FIXME - what to do if get_user() fails? */
1071 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1072 sp_ptr += sizeof(abi_ulong);
1073 }
1074 #ifdef TARGET_SPARC64
1075 env->canrestore++;
1076 if (env->cleanwin < env->nwindows - 1)
1077 env->cleanwin++;
1078 env->cansave--;
1079 #else
1080 env->wim = new_wim;
1081 #endif
1082 }
1083
1084 static void flush_windows(CPUSPARCState *env)
1085 {
1086 int offset, cwp1;
1087
1088 offset = 1;
1089 for(;;) {
1090 /* if restore would invoke restore_window(), then we can stop */
1091 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1092 #ifndef TARGET_SPARC64
1093 if (env->wim & (1 << cwp1))
1094 break;
1095 #else
1096 if (env->canrestore == 0)
1097 break;
1098 env->cansave++;
1099 env->canrestore--;
1100 #endif
1101 save_window_offset(env, cwp1);
1102 offset++;
1103 }
1104 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1105 #ifndef TARGET_SPARC64
1106 /* set wim so that restore will reload the registers */
1107 env->wim = 1 << cwp1;
1108 #endif
1109 #if defined(DEBUG_WIN)
1110 printf("flush_windows: nb=%d\n", offset - 1);
1111 #endif
1112 }
1113
1114 void cpu_loop (CPUSPARCState *env)
1115 {
1116 CPUState *cs = CPU(sparc_env_get_cpu(env));
1117 int trapnr;
1118 abi_long ret;
1119 target_siginfo_t info;
1120
1121 while (1) {
1122 trapnr = cpu_sparc_exec (env);
1123
1124 /* Compute PSR before exposing state. */
1125 if (env->cc_op != CC_OP_FLAGS) {
1126 cpu_get_psr(env);
1127 }
1128
1129 switch (trapnr) {
1130 #ifndef TARGET_SPARC64
1131 case 0x88:
1132 case 0x90:
1133 #else
1134 case 0x110:
1135 case 0x16d:
1136 #endif
1137 ret = do_syscall (env, env->gregs[1],
1138 env->regwptr[0], env->regwptr[1],
1139 env->regwptr[2], env->regwptr[3],
1140 env->regwptr[4], env->regwptr[5],
1141 0, 0);
1142 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1143 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1144 env->xcc |= PSR_CARRY;
1145 #else
1146 env->psr |= PSR_CARRY;
1147 #endif
1148 ret = -ret;
1149 } else {
1150 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1151 env->xcc &= ~PSR_CARRY;
1152 #else
1153 env->psr &= ~PSR_CARRY;
1154 #endif
1155 }
1156 env->regwptr[0] = ret;
1157 /* next instruction */
1158 env->pc = env->npc;
1159 env->npc = env->npc + 4;
1160 break;
1161 case 0x83: /* flush windows */
1162 #ifdef TARGET_ABI32
1163 case 0x103:
1164 #endif
1165 flush_windows(env);
1166 /* next instruction */
1167 env->pc = env->npc;
1168 env->npc = env->npc + 4;
1169 break;
1170 #ifndef TARGET_SPARC64
1171 case TT_WIN_OVF: /* window overflow */
1172 save_window(env);
1173 break;
1174 case TT_WIN_UNF: /* window underflow */
1175 restore_window(env);
1176 break;
1177 case TT_TFAULT:
1178 case TT_DFAULT:
1179 {
1180 info.si_signo = TARGET_SIGSEGV;
1181 info.si_errno = 0;
1182 /* XXX: check env->error_code */
1183 info.si_code = TARGET_SEGV_MAPERR;
1184 info._sifields._sigfault._addr = env->mmuregs[4];
1185 queue_signal(env, info.si_signo, &info);
1186 }
1187 break;
1188 #else
1189 case TT_SPILL: /* window overflow */
1190 save_window(env);
1191 break;
1192 case TT_FILL: /* window underflow */
1193 restore_window(env);
1194 break;
1195 case TT_TFAULT:
1196 case TT_DFAULT:
1197 {
1198 info.si_signo = TARGET_SIGSEGV;
1199 info.si_errno = 0;
1200 /* XXX: check env->error_code */
1201 info.si_code = TARGET_SEGV_MAPERR;
1202 if (trapnr == TT_DFAULT)
1203 info._sifields._sigfault._addr = env->dmmuregs[4];
1204 else
1205 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1206 queue_signal(env, info.si_signo, &info);
1207 }
1208 break;
1209 #ifndef TARGET_ABI32
1210 case 0x16e:
1211 flush_windows(env);
1212 sparc64_get_context(env);
1213 break;
1214 case 0x16f:
1215 flush_windows(env);
1216 sparc64_set_context(env);
1217 break;
1218 #endif
1219 #endif
1220 case EXCP_INTERRUPT:
1221 /* just indicate that signals should be handled asap */
1222 break;
1223 case TT_ILL_INSN:
1224 {
1225 info.si_signo = TARGET_SIGILL;
1226 info.si_errno = 0;
1227 info.si_code = TARGET_ILL_ILLOPC;
1228 info._sifields._sigfault._addr = env->pc;
1229 queue_signal(env, info.si_signo, &info);
1230 }
1231 break;
1232 case EXCP_DEBUG:
1233 {
1234 int sig;
1235
1236 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1237 if (sig)
1238 {
1239 info.si_signo = sig;
1240 info.si_errno = 0;
1241 info.si_code = TARGET_TRAP_BRKPT;
1242 queue_signal(env, info.si_signo, &info);
1243 }
1244 }
1245 break;
1246 default:
1247 printf ("Unhandled trap: 0x%x\n", trapnr);
1248 cpu_dump_state(cs, stderr, fprintf, 0);
1249 exit (1);
1250 }
1251 process_pending_signals (env);
1252 }
1253 }
1254
1255 #endif
1256
1257 #ifdef TARGET_PPC
1258 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1259 {
1260 /* TO FIX */
1261 return 0;
1262 }
1263
1264 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1265 {
1266 return cpu_ppc_get_tb(env);
1267 }
1268
1269 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1270 {
1271 return cpu_ppc_get_tb(env) >> 32;
1272 }
1273
1274 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1275 {
1276 return cpu_ppc_get_tb(env);
1277 }
1278
1279 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1280 {
1281 return cpu_ppc_get_tb(env) >> 32;
1282 }
1283
1284 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1285 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1286
1287 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1288 {
1289 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1290 }
1291
1292 /* XXX: to be fixed */
1293 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1294 {
1295 return -1;
1296 }
1297
1298 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1299 {
1300 return -1;
1301 }
1302
1303 #define EXCP_DUMP(env, fmt, ...) \
1304 do { \
1305 fprintf(stderr, fmt , ## __VA_ARGS__); \
1306 cpu_dump_state(ENV_GET_CPU(env), stderr, fprintf, 0); \
1307 qemu_log(fmt, ## __VA_ARGS__); \
1308 if (qemu_log_enabled()) { \
1309 log_cpu_state(env, 0); \
1310 } \
1311 } while (0)
1312
1313 static int do_store_exclusive(CPUPPCState *env)
1314 {
1315 target_ulong addr;
1316 target_ulong page_addr;
1317 target_ulong val;
1318 int flags;
1319 int segv = 0;
1320
1321 addr = env->reserve_ea;
1322 page_addr = addr & TARGET_PAGE_MASK;
1323 start_exclusive();
1324 mmap_lock();
1325 flags = page_get_flags(page_addr);
1326 if ((flags & PAGE_READ) == 0) {
1327 segv = 1;
1328 } else {
1329 int reg = env->reserve_info & 0x1f;
1330 int size = (env->reserve_info >> 5) & 0xf;
1331 int stored = 0;
1332
1333 if (addr == env->reserve_addr) {
1334 switch (size) {
1335 case 1: segv = get_user_u8(val, addr); break;
1336 case 2: segv = get_user_u16(val, addr); break;
1337 case 4: segv = get_user_u32(val, addr); break;
1338 #if defined(TARGET_PPC64)
1339 case 8: segv = get_user_u64(val, addr); break;
1340 #endif
1341 default: abort();
1342 }
1343 if (!segv && val == env->reserve_val) {
1344 val = env->gpr[reg];
1345 switch (size) {
1346 case 1: segv = put_user_u8(val, addr); break;
1347 case 2: segv = put_user_u16(val, addr); break;
1348 case 4: segv = put_user_u32(val, addr); break;
1349 #if defined(TARGET_PPC64)
1350 case 8: segv = put_user_u64(val, addr); break;
1351 #endif
1352 default: abort();
1353 }
1354 if (!segv) {
1355 stored = 1;
1356 }
1357 }
1358 }
1359 env->crf[0] = (stored << 1) | xer_so;
1360 env->reserve_addr = (target_ulong)-1;
1361 }
1362 if (!segv) {
1363 env->nip += 4;
1364 }
1365 mmap_unlock();
1366 end_exclusive();
1367 return segv;
1368 }
1369
1370 void cpu_loop(CPUPPCState *env)
1371 {
1372 CPUState *cs = CPU(ppc_env_get_cpu(env));
1373 target_siginfo_t info;
1374 int trapnr;
1375 target_ulong ret;
1376
1377 for(;;) {
1378 cpu_exec_start(cs);
1379 trapnr = cpu_ppc_exec(env);
1380 cpu_exec_end(cs);
1381 switch(trapnr) {
1382 case POWERPC_EXCP_NONE:
1383 /* Just go on */
1384 break;
1385 case POWERPC_EXCP_CRITICAL: /* Critical input */
1386 cpu_abort(env, "Critical interrupt while in user mode. "
1387 "Aborting\n");
1388 break;
1389 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1390 cpu_abort(env, "Machine check exception while in user mode. "
1391 "Aborting\n");
1392 break;
1393 case POWERPC_EXCP_DSI: /* Data storage exception */
1394 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1395 env->spr[SPR_DAR]);
1396 /* XXX: check this. Seems bugged */
1397 switch (env->error_code & 0xFF000000) {
1398 case 0x40000000:
1399 info.si_signo = TARGET_SIGSEGV;
1400 info.si_errno = 0;
1401 info.si_code = TARGET_SEGV_MAPERR;
1402 break;
1403 case 0x04000000:
1404 info.si_signo = TARGET_SIGILL;
1405 info.si_errno = 0;
1406 info.si_code = TARGET_ILL_ILLADR;
1407 break;
1408 case 0x08000000:
1409 info.si_signo = TARGET_SIGSEGV;
1410 info.si_errno = 0;
1411 info.si_code = TARGET_SEGV_ACCERR;
1412 break;
1413 default:
1414 /* Let's send a regular segfault... */
1415 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1416 env->error_code);
1417 info.si_signo = TARGET_SIGSEGV;
1418 info.si_errno = 0;
1419 info.si_code = TARGET_SEGV_MAPERR;
1420 break;
1421 }
1422 info._sifields._sigfault._addr = env->nip;
1423 queue_signal(env, info.si_signo, &info);
1424 break;
1425 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1426 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1427 "\n", env->spr[SPR_SRR0]);
1428 /* XXX: check this */
1429 switch (env->error_code & 0xFF000000) {
1430 case 0x40000000:
1431 info.si_signo = TARGET_SIGSEGV;
1432 info.si_errno = 0;
1433 info.si_code = TARGET_SEGV_MAPERR;
1434 break;
1435 case 0x10000000:
1436 case 0x08000000:
1437 info.si_signo = TARGET_SIGSEGV;
1438 info.si_errno = 0;
1439 info.si_code = TARGET_SEGV_ACCERR;
1440 break;
1441 default:
1442 /* Let's send a regular segfault... */
1443 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1444 env->error_code);
1445 info.si_signo = TARGET_SIGSEGV;
1446 info.si_errno = 0;
1447 info.si_code = TARGET_SEGV_MAPERR;
1448 break;
1449 }
1450 info._sifields._sigfault._addr = env->nip - 4;
1451 queue_signal(env, info.si_signo, &info);
1452 break;
1453 case POWERPC_EXCP_EXTERNAL: /* External input */
1454 cpu_abort(env, "External interrupt while in user mode. "
1455 "Aborting\n");
1456 break;
1457 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1458 EXCP_DUMP(env, "Unaligned memory access\n");
1459 /* XXX: check this */
1460 info.si_signo = TARGET_SIGBUS;
1461 info.si_errno = 0;
1462 info.si_code = TARGET_BUS_ADRALN;
1463 info._sifields._sigfault._addr = env->nip - 4;
1464 queue_signal(env, info.si_signo, &info);
1465 break;
1466 case POWERPC_EXCP_PROGRAM: /* Program exception */
1467 /* XXX: check this */
1468 switch (env->error_code & ~0xF) {
1469 case POWERPC_EXCP_FP:
1470 EXCP_DUMP(env, "Floating point program exception\n");
1471 info.si_signo = TARGET_SIGFPE;
1472 info.si_errno = 0;
1473 switch (env->error_code & 0xF) {
1474 case POWERPC_EXCP_FP_OX:
1475 info.si_code = TARGET_FPE_FLTOVF;
1476 break;
1477 case POWERPC_EXCP_FP_UX:
1478 info.si_code = TARGET_FPE_FLTUND;
1479 break;
1480 case POWERPC_EXCP_FP_ZX:
1481 case POWERPC_EXCP_FP_VXZDZ:
1482 info.si_code = TARGET_FPE_FLTDIV;
1483 break;
1484 case POWERPC_EXCP_FP_XX:
1485 info.si_code = TARGET_FPE_FLTRES;
1486 break;
1487 case POWERPC_EXCP_FP_VXSOFT:
1488 info.si_code = TARGET_FPE_FLTINV;
1489 break;
1490 case POWERPC_EXCP_FP_VXSNAN:
1491 case POWERPC_EXCP_FP_VXISI:
1492 case POWERPC_EXCP_FP_VXIDI:
1493 case POWERPC_EXCP_FP_VXIMZ:
1494 case POWERPC_EXCP_FP_VXVC:
1495 case POWERPC_EXCP_FP_VXSQRT:
1496 case POWERPC_EXCP_FP_VXCVI:
1497 info.si_code = TARGET_FPE_FLTSUB;
1498 break;
1499 default:
1500 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1501 env->error_code);
1502 break;
1503 }
1504 break;
1505 case POWERPC_EXCP_INVAL:
1506 EXCP_DUMP(env, "Invalid instruction\n");
1507 info.si_signo = TARGET_SIGILL;
1508 info.si_errno = 0;
1509 switch (env->error_code & 0xF) {
1510 case POWERPC_EXCP_INVAL_INVAL:
1511 info.si_code = TARGET_ILL_ILLOPC;
1512 break;
1513 case POWERPC_EXCP_INVAL_LSWX:
1514 info.si_code = TARGET_ILL_ILLOPN;
1515 break;
1516 case POWERPC_EXCP_INVAL_SPR:
1517 info.si_code = TARGET_ILL_PRVREG;
1518 break;
1519 case POWERPC_EXCP_INVAL_FP:
1520 info.si_code = TARGET_ILL_COPROC;
1521 break;
1522 default:
1523 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1524 env->error_code & 0xF);
1525 info.si_code = TARGET_ILL_ILLADR;
1526 break;
1527 }
1528 break;
1529 case POWERPC_EXCP_PRIV:
1530 EXCP_DUMP(env, "Privilege violation\n");
1531 info.si_signo = TARGET_SIGILL;
1532 info.si_errno = 0;
1533 switch (env->error_code & 0xF) {
1534 case POWERPC_EXCP_PRIV_OPC:
1535 info.si_code = TARGET_ILL_PRVOPC;
1536 break;
1537 case POWERPC_EXCP_PRIV_REG:
1538 info.si_code = TARGET_ILL_PRVREG;
1539 break;
1540 default:
1541 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1542 env->error_code & 0xF);
1543 info.si_code = TARGET_ILL_PRVOPC;
1544 break;
1545 }
1546 break;
1547 case POWERPC_EXCP_TRAP:
1548 cpu_abort(env, "Tried to call a TRAP\n");
1549 break;
1550 default:
1551 /* Should not happen ! */
1552 cpu_abort(env, "Unknown program exception (%02x)\n",
1553 env->error_code);
1554 break;
1555 }
1556 info._sifields._sigfault._addr = env->nip - 4;
1557 queue_signal(env, info.si_signo, &info);
1558 break;
1559 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1560 EXCP_DUMP(env, "No floating point allowed\n");
1561 info.si_signo = TARGET_SIGILL;
1562 info.si_errno = 0;
1563 info.si_code = TARGET_ILL_COPROC;
1564 info._sifields._sigfault._addr = env->nip - 4;
1565 queue_signal(env, info.si_signo, &info);
1566 break;
1567 case POWERPC_EXCP_SYSCALL: /* System call exception */
1568 cpu_abort(env, "Syscall exception while in user mode. "
1569 "Aborting\n");
1570 break;
1571 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1572 EXCP_DUMP(env, "No APU instruction allowed\n");
1573 info.si_signo = TARGET_SIGILL;
1574 info.si_errno = 0;
1575 info.si_code = TARGET_ILL_COPROC;
1576 info._sifields._sigfault._addr = env->nip - 4;
1577 queue_signal(env, info.si_signo, &info);
1578 break;
1579 case POWERPC_EXCP_DECR: /* Decrementer exception */
1580 cpu_abort(env, "Decrementer interrupt while in user mode. "
1581 "Aborting\n");
1582 break;
1583 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1584 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1585 "Aborting\n");
1586 break;
1587 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1588 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1589 "Aborting\n");
1590 break;
1591 case POWERPC_EXCP_DTLB: /* Data TLB error */
1592 cpu_abort(env, "Data TLB exception while in user mode. "
1593 "Aborting\n");
1594 break;
1595 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1596 cpu_abort(env, "Instruction TLB exception while in user mode. "
1597 "Aborting\n");
1598 break;
1599 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1600 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1601 info.si_signo = TARGET_SIGILL;
1602 info.si_errno = 0;
1603 info.si_code = TARGET_ILL_COPROC;
1604 info._sifields._sigfault._addr = env->nip - 4;
1605 queue_signal(env, info.si_signo, &info);
1606 break;
1607 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1608 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1609 break;
1610 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1611 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1612 break;
1613 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1614 cpu_abort(env, "Performance monitor exception not handled\n");
1615 break;
1616 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1617 cpu_abort(env, "Doorbell interrupt while in user mode. "
1618 "Aborting\n");
1619 break;
1620 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1621 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1622 "Aborting\n");
1623 break;
1624 case POWERPC_EXCP_RESET: /* System reset exception */
1625 cpu_abort(env, "Reset interrupt while in user mode. "
1626 "Aborting\n");
1627 break;
1628 case POWERPC_EXCP_DSEG: /* Data segment exception */
1629 cpu_abort(env, "Data segment exception while in user mode. "
1630 "Aborting\n");
1631 break;
1632 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1633 cpu_abort(env, "Instruction segment exception "
1634 "while in user mode. Aborting\n");
1635 break;
1636 /* PowerPC 64 with hypervisor mode support */
1637 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1638 cpu_abort(env, "Hypervisor decrementer interrupt "
1639 "while in user mode. Aborting\n");
1640 break;
1641 case POWERPC_EXCP_TRACE: /* Trace exception */
1642 /* Nothing to do:
1643 * we use this exception to emulate step-by-step execution mode.
1644 */
1645 break;
1646 /* PowerPC 64 with hypervisor mode support */
1647 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1648 cpu_abort(env, "Hypervisor data storage exception "
1649 "while in user mode. Aborting\n");
1650 break;
1651 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1652 cpu_abort(env, "Hypervisor instruction storage exception "
1653 "while in user mode. Aborting\n");
1654 break;
1655 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1656 cpu_abort(env, "Hypervisor data segment exception "
1657 "while in user mode. Aborting\n");
1658 break;
1659 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1660 cpu_abort(env, "Hypervisor instruction segment exception "
1661 "while in user mode. Aborting\n");
1662 break;
1663 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1664 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1665 info.si_signo = TARGET_SIGILL;
1666 info.si_errno = 0;
1667 info.si_code = TARGET_ILL_COPROC;
1668 info._sifields._sigfault._addr = env->nip - 4;
1669 queue_signal(env, info.si_signo, &info);
1670 break;
1671 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1672 cpu_abort(env, "Programmable interval timer interrupt "
1673 "while in user mode. Aborting\n");
1674 break;
1675 case POWERPC_EXCP_IO: /* IO error exception */
1676 cpu_abort(env, "IO error exception while in user mode. "
1677 "Aborting\n");
1678 break;
1679 case POWERPC_EXCP_RUNM: /* Run mode exception */
1680 cpu_abort(env, "Run mode exception while in user mode. "
1681 "Aborting\n");
1682 break;
1683 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1684 cpu_abort(env, "Emulation trap exception not handled\n");
1685 break;
1686 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1687 cpu_abort(env, "Instruction fetch TLB exception "
1688 "while in user-mode. Aborting");
1689 break;
1690 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1691 cpu_abort(env, "Data load TLB exception while in user-mode. "
1692 "Aborting");
1693 break;
1694 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1695 cpu_abort(env, "Data store TLB exception while in user-mode. "
1696 "Aborting");
1697 break;
1698 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1699 cpu_abort(env, "Floating-point assist exception not handled\n");
1700 break;
1701 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1702 cpu_abort(env, "Instruction address breakpoint exception "
1703 "not handled\n");
1704 break;
1705 case POWERPC_EXCP_SMI: /* System management interrupt */
1706 cpu_abort(env, "System management interrupt while in user mode. "
1707 "Aborting\n");
1708 break;
1709 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1710 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1711 "Aborting\n");
1712 break;
1713 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1714 cpu_abort(env, "Performance monitor exception not handled\n");
1715 break;
1716 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1717 cpu_abort(env, "Vector assist exception not handled\n");
1718 break;
1719 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1720 cpu_abort(env, "Soft patch exception not handled\n");
1721 break;
1722 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1723 cpu_abort(env, "Maintenance exception while in user mode. "
1724 "Aborting\n");
1725 break;
1726 case POWERPC_EXCP_STOP: /* stop translation */
1727 /* We did invalidate the instruction cache. Go on */
1728 break;
1729 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1730 /* We just stopped because of a branch. Go on */
1731 break;
1732 case POWERPC_EXCP_SYSCALL_USER:
1733 /* system call in user-mode emulation */
1734 /* WARNING:
1735 * PPC ABI uses overflow flag in cr0 to signal an error
1736 * in syscalls.
1737 */
1738 env->crf[0] &= ~0x1;
1739 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1740 env->gpr[5], env->gpr[6], env->gpr[7],
1741 env->gpr[8], 0, 0);
1742 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1743 /* Returning from a successful sigreturn syscall.
1744 Avoid corrupting register state. */
1745 break;
1746 }
1747 if (ret > (target_ulong)(-515)) {
1748 env->crf[0] |= 0x1;
1749 ret = -ret;
1750 }
1751 env->gpr[3] = ret;
1752 break;
1753 case POWERPC_EXCP_STCX:
1754 if (do_store_exclusive(env)) {
1755 info.si_signo = TARGET_SIGSEGV;
1756 info.si_errno = 0;
1757 info.si_code = TARGET_SEGV_MAPERR;
1758 info._sifields._sigfault._addr = env->nip;
1759 queue_signal(env, info.si_signo, &info);
1760 }
1761 break;
1762 case EXCP_DEBUG:
1763 {
1764 int sig;
1765
1766 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1767 if (sig) {
1768 info.si_signo = sig;
1769 info.si_errno = 0;
1770 info.si_code = TARGET_TRAP_BRKPT;
1771 queue_signal(env, info.si_signo, &info);
1772 }
1773 }
1774 break;
1775 case EXCP_INTERRUPT:
1776 /* just indicate that signals should be handled asap */
1777 break;
1778 default:
1779 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1780 break;
1781 }
1782 process_pending_signals(env);
1783 }
1784 }
1785 #endif
1786
1787 #ifdef TARGET_MIPS
1788
1789 # ifdef TARGET_ABI_MIPSO32
1790 # define MIPS_SYS(name, args) args,
1791 static const uint8_t mips_syscall_args[] = {
1792 MIPS_SYS(sys_syscall , 8) /* 4000 */
1793 MIPS_SYS(sys_exit , 1)
1794 MIPS_SYS(sys_fork , 0)
1795 MIPS_SYS(sys_read , 3)
1796 MIPS_SYS(sys_write , 3)
1797 MIPS_SYS(sys_open , 3) /* 4005 */
1798 MIPS_SYS(sys_close , 1)
1799 MIPS_SYS(sys_waitpid , 3)
1800 MIPS_SYS(sys_creat , 2)
1801 MIPS_SYS(sys_link , 2)
1802 MIPS_SYS(sys_unlink , 1) /* 4010 */
1803 MIPS_SYS(sys_execve , 0)
1804 MIPS_SYS(sys_chdir , 1)
1805 MIPS_SYS(sys_time , 1)
1806 MIPS_SYS(sys_mknod , 3)
1807 MIPS_SYS(sys_chmod , 2) /* 4015 */
1808 MIPS_SYS(sys_lchown , 3)
1809 MIPS_SYS(sys_ni_syscall , 0)
1810 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1811 MIPS_SYS(sys_lseek , 3)
1812 MIPS_SYS(sys_getpid , 0) /* 4020 */
1813 MIPS_SYS(sys_mount , 5)
1814 MIPS_SYS(sys_oldumount , 1)
1815 MIPS_SYS(sys_setuid , 1)
1816 MIPS_SYS(sys_getuid , 0)
1817 MIPS_SYS(sys_stime , 1) /* 4025 */
1818 MIPS_SYS(sys_ptrace , 4)
1819 MIPS_SYS(sys_alarm , 1)
1820 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1821 MIPS_SYS(sys_pause , 0)
1822 MIPS_SYS(sys_utime , 2) /* 4030 */
1823 MIPS_SYS(sys_ni_syscall , 0)
1824 MIPS_SYS(sys_ni_syscall , 0)
1825 MIPS_SYS(sys_access , 2)
1826 MIPS_SYS(sys_nice , 1)
1827 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1828 MIPS_SYS(sys_sync , 0)
1829 MIPS_SYS(sys_kill , 2)
1830 MIPS_SYS(sys_rename , 2)
1831 MIPS_SYS(sys_mkdir , 2)
1832 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1833 MIPS_SYS(sys_dup , 1)
1834 MIPS_SYS(sys_pipe , 0)
1835 MIPS_SYS(sys_times , 1)
1836 MIPS_SYS(sys_ni_syscall , 0)
1837 MIPS_SYS(sys_brk , 1) /* 4045 */
1838 MIPS_SYS(sys_setgid , 1)
1839 MIPS_SYS(sys_getgid , 0)
1840 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1841 MIPS_SYS(sys_geteuid , 0)
1842 MIPS_SYS(sys_getegid , 0) /* 4050 */
1843 MIPS_SYS(sys_acct , 0)
1844 MIPS_SYS(sys_umount , 2)
1845 MIPS_SYS(sys_ni_syscall , 0)
1846 MIPS_SYS(sys_ioctl , 3)
1847 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1848 MIPS_SYS(sys_ni_syscall , 2)
1849 MIPS_SYS(sys_setpgid , 2)
1850 MIPS_SYS(sys_ni_syscall , 0)
1851 MIPS_SYS(sys_olduname , 1)
1852 MIPS_SYS(sys_umask , 1) /* 4060 */
1853 MIPS_SYS(sys_chroot , 1)
1854 MIPS_SYS(sys_ustat , 2)
1855 MIPS_SYS(sys_dup2 , 2)
1856 MIPS_SYS(sys_getppid , 0)
1857 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1858 MIPS_SYS(sys_setsid , 0)
1859 MIPS_SYS(sys_sigaction , 3)
1860 MIPS_SYS(sys_sgetmask , 0)
1861 MIPS_SYS(sys_ssetmask , 1)
1862 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1863 MIPS_SYS(sys_setregid , 2)
1864 MIPS_SYS(sys_sigsuspend , 0)
1865 MIPS_SYS(sys_sigpending , 1)
1866 MIPS_SYS(sys_sethostname , 2)
1867 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1868 MIPS_SYS(sys_getrlimit , 2)
1869 MIPS_SYS(sys_getrusage , 2)
1870 MIPS_SYS(sys_gettimeofday, 2)
1871 MIPS_SYS(sys_settimeofday, 2)
1872 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1873 MIPS_SYS(sys_setgroups , 2)
1874 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1875 MIPS_SYS(sys_symlink , 2)
1876 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1877 MIPS_SYS(sys_readlink , 3) /* 4085 */
1878 MIPS_SYS(sys_uselib , 1)
1879 MIPS_SYS(sys_swapon , 2)
1880 MIPS_SYS(sys_reboot , 3)
1881 MIPS_SYS(old_readdir , 3)
1882 MIPS_SYS(old_mmap , 6) /* 4090 */
1883 MIPS_SYS(sys_munmap , 2)
1884 MIPS_SYS(sys_truncate , 2)
1885 MIPS_SYS(sys_ftruncate , 2)
1886 MIPS_SYS(sys_fchmod , 2)
1887 MIPS_SYS(sys_fchown , 3) /* 4095 */
1888 MIPS_SYS(sys_getpriority , 2)
1889 MIPS_SYS(sys_setpriority , 3)
1890 MIPS_SYS(sys_ni_syscall , 0)
1891 MIPS_SYS(sys_statfs , 2)
1892 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1893 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1894 MIPS_SYS(sys_socketcall , 2)
1895 MIPS_SYS(sys_syslog , 3)
1896 MIPS_SYS(sys_setitimer , 3)
1897 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1898 MIPS_SYS(sys_newstat , 2)
1899 MIPS_SYS(sys_newlstat , 2)
1900 MIPS_SYS(sys_newfstat , 2)
1901 MIPS_SYS(sys_uname , 1)
1902 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1903 MIPS_SYS(sys_vhangup , 0)
1904 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1905 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1906 MIPS_SYS(sys_wait4 , 4)
1907 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1908 MIPS_SYS(sys_sysinfo , 1)
1909 MIPS_SYS(sys_ipc , 6)
1910 MIPS_SYS(sys_fsync , 1)
1911 MIPS_SYS(sys_sigreturn , 0)
1912 MIPS_SYS(sys_clone , 6) /* 4120 */
1913 MIPS_SYS(sys_setdomainname, 2)
1914 MIPS_SYS(sys_newuname , 1)
1915 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1916 MIPS_SYS(sys_adjtimex , 1)
1917 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1918 MIPS_SYS(sys_sigprocmask , 3)
1919 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1920 MIPS_SYS(sys_init_module , 5)
1921 MIPS_SYS(sys_delete_module, 1)
1922 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1923 MIPS_SYS(sys_quotactl , 0)
1924 MIPS_SYS(sys_getpgid , 1)
1925 MIPS_SYS(sys_fchdir , 1)
1926 MIPS_SYS(sys_bdflush , 2)
1927 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1928 MIPS_SYS(sys_personality , 1)
1929 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1930 MIPS_SYS(sys_setfsuid , 1)
1931 MIPS_SYS(sys_setfsgid , 1)
1932 MIPS_SYS(sys_llseek , 5) /* 4140 */
1933 MIPS_SYS(sys_getdents , 3)
1934 MIPS_SYS(sys_select , 5)
1935 MIPS_SYS(sys_flock , 2)
1936 MIPS_SYS(sys_msync , 3)
1937 MIPS_SYS(sys_readv , 3) /* 4145 */
1938 MIPS_SYS(sys_writev , 3)
1939 MIPS_SYS(sys_cacheflush , 3)
1940 MIPS_SYS(sys_cachectl , 3)
1941 MIPS_SYS(sys_sysmips , 4)
1942 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1943 MIPS_SYS(sys_getsid , 1)
1944 MIPS_SYS(sys_fdatasync , 0)
1945 MIPS_SYS(sys_sysctl , 1)
1946 MIPS_SYS(sys_mlock , 2)
1947 MIPS_SYS(sys_munlock , 2) /* 4155 */
1948 MIPS_SYS(sys_mlockall , 1)
1949 MIPS_SYS(sys_munlockall , 0)
1950 MIPS_SYS(sys_sched_setparam, 2)
1951 MIPS_SYS(sys_sched_getparam, 2)
1952 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1953 MIPS_SYS(sys_sched_getscheduler, 1)
1954 MIPS_SYS(sys_sched_yield , 0)
1955 MIPS_SYS(sys_sched_get_priority_max, 1)
1956 MIPS_SYS(sys_sched_get_priority_min, 1)
1957 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1958 MIPS_SYS(sys_nanosleep, 2)
1959 MIPS_SYS(sys_mremap , 4)
1960 MIPS_SYS(sys_accept , 3)
1961 MIPS_SYS(sys_bind , 3)
1962 MIPS_SYS(sys_connect , 3) /* 4170 */
1963 MIPS_SYS(sys_getpeername , 3)
1964 MIPS_SYS(sys_getsockname , 3)
1965 MIPS_SYS(sys_getsockopt , 5)
1966 MIPS_SYS(sys_listen , 2)
1967 MIPS_SYS(sys_recv , 4) /* 4175 */
1968 MIPS_SYS(sys_recvfrom , 6)
1969 MIPS_SYS(sys_recvmsg , 3)
1970 MIPS_SYS(sys_send , 4)
1971 MIPS_SYS(sys_sendmsg , 3)
1972 MIPS_SYS(sys_sendto , 6) /* 4180 */
1973 MIPS_SYS(sys_setsockopt , 5)
1974 MIPS_SYS(sys_shutdown , 2)
1975 MIPS_SYS(sys_socket , 3)
1976 MIPS_SYS(sys_socketpair , 4)
1977 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1978 MIPS_SYS(sys_getresuid , 3)
1979 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1980 MIPS_SYS(sys_poll , 3)
1981 MIPS_SYS(sys_nfsservctl , 3)
1982 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1983 MIPS_SYS(sys_getresgid , 3)
1984 MIPS_SYS(sys_prctl , 5)
1985 MIPS_SYS(sys_rt_sigreturn, 0)
1986 MIPS_SYS(sys_rt_sigaction, 4)
1987 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1988 MIPS_SYS(sys_rt_sigpending, 2)
1989 MIPS_SYS(sys_rt_sigtimedwait, 4)
1990 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1991 MIPS_SYS(sys_rt_sigsuspend, 0)
1992 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1993 MIPS_SYS(sys_pwrite64 , 6)
1994 MIPS_SYS(sys_chown , 3)
1995 MIPS_SYS(sys_getcwd , 2)
1996 MIPS_SYS(sys_capget , 2)
1997 MIPS_SYS(sys_capset , 2) /* 4205 */
1998 MIPS_SYS(sys_sigaltstack , 2)
1999 MIPS_SYS(sys_sendfile , 4)
2000 MIPS_SYS(sys_ni_syscall , 0)
2001 MIPS_SYS(sys_ni_syscall , 0)
2002 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2003 MIPS_SYS(sys_truncate64 , 4)
2004 MIPS_SYS(sys_ftruncate64 , 4)
2005 MIPS_SYS(sys_stat64 , 2)
2006 MIPS_SYS(sys_lstat64 , 2)
2007 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2008 MIPS_SYS(sys_pivot_root , 2)
2009 MIPS_SYS(sys_mincore , 3)
2010 MIPS_SYS(sys_madvise , 3)
2011 MIPS_SYS(sys_getdents64 , 3)
2012 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2013 MIPS_SYS(sys_ni_syscall , 0)
2014 MIPS_SYS(sys_gettid , 0)
2015 MIPS_SYS(sys_readahead , 5)
2016 MIPS_SYS(sys_setxattr , 5)
2017 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2018 MIPS_SYS(sys_fsetxattr , 5)
2019 MIPS_SYS(sys_getxattr , 4)
2020 MIPS_SYS(sys_lgetxattr , 4)
2021 MIPS_SYS(sys_fgetxattr , 4)
2022 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2023 MIPS_SYS(sys_llistxattr , 3)
2024 MIPS_SYS(sys_flistxattr , 3)
2025 MIPS_SYS(sys_removexattr , 2)
2026 MIPS_SYS(sys_lremovexattr, 2)
2027 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2028 MIPS_SYS(sys_tkill , 2)
2029 MIPS_SYS(sys_sendfile64 , 5)
2030 MIPS_SYS(sys_futex , 2)
2031 MIPS_SYS(sys_sched_setaffinity, 3)
2032 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2033 MIPS_SYS(sys_io_setup , 2)
2034 MIPS_SYS(sys_io_destroy , 1)
2035 MIPS_SYS(sys_io_getevents, 5)
2036 MIPS_SYS(sys_io_submit , 3)
2037 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2038 MIPS_SYS(sys_exit_group , 1)
2039 MIPS_SYS(sys_lookup_dcookie, 3)
2040 MIPS_SYS(sys_epoll_create, 1)
2041 MIPS_SYS(sys_epoll_ctl , 4)
2042 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2043 MIPS_SYS(sys_remap_file_pages, 5)
2044 MIPS_SYS(sys_set_tid_address, 1)
2045 MIPS_SYS(sys_restart_syscall, 0)
2046 MIPS_SYS(sys_fadvise64_64, 7)
2047 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2048 MIPS_SYS(sys_fstatfs64 , 2)
2049 MIPS_SYS(sys_timer_create, 3)
2050 MIPS_SYS(sys_timer_settime, 4)
2051 MIPS_SYS(sys_timer_gettime, 2)
2052 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2053 MIPS_SYS(sys_timer_delete, 1)
2054 MIPS_SYS(sys_clock_settime, 2)
2055 MIPS_SYS(sys_clock_gettime, 2)
2056 MIPS_SYS(sys_clock_getres, 2)
2057 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2058 MIPS_SYS(sys_tgkill , 3)
2059 MIPS_SYS(sys_utimes , 2)
2060 MIPS_SYS(sys_mbind , 4)
2061 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2062 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2063 MIPS_SYS(sys_mq_open , 4)
2064 MIPS_SYS(sys_mq_unlink , 1)
2065 MIPS_SYS(sys_mq_timedsend, 5)
2066 MIPS_SYS(sys_mq_timedreceive, 5)
2067 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2068 MIPS_SYS(sys_mq_getsetattr, 3)
2069 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2070 MIPS_SYS(sys_waitid , 4)
2071 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2072 MIPS_SYS(sys_add_key , 5)
2073 MIPS_SYS(sys_request_key, 4)
2074 MIPS_SYS(sys_keyctl , 5)
2075 MIPS_SYS(sys_set_thread_area, 1)
2076 MIPS_SYS(sys_inotify_init, 0)
2077 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2078 MIPS_SYS(sys_inotify_rm_watch, 2)
2079 MIPS_SYS(sys_migrate_pages, 4)
2080 MIPS_SYS(sys_openat, 4)
2081 MIPS_SYS(sys_mkdirat, 3)
2082 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2083 MIPS_SYS(sys_fchownat, 5)
2084 MIPS_SYS(sys_futimesat, 3)
2085 MIPS_SYS(sys_fstatat64, 4)
2086 MIPS_SYS(sys_unlinkat, 3)
2087 MIPS_SYS(sys_renameat, 4) /* 4295 */
2088 MIPS_SYS(sys_linkat, 5)
2089 MIPS_SYS(sys_symlinkat, 3)
2090 MIPS_SYS(sys_readlinkat, 4)
2091 MIPS_SYS(sys_fchmodat, 3)
2092 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2093 MIPS_SYS(sys_pselect6, 6)
2094 MIPS_SYS(sys_ppoll, 5)
2095 MIPS_SYS(sys_unshare, 1)
2096 MIPS_SYS(sys_splice, 4)
2097 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2098 MIPS_SYS(sys_tee, 4)
2099 MIPS_SYS(sys_vmsplice, 4)
2100 MIPS_SYS(sys_move_pages, 6)
2101 MIPS_SYS(sys_set_robust_list, 2)
2102 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2103 MIPS_SYS(sys_kexec_load, 4)
2104 MIPS_SYS(sys_getcpu, 3)
2105 MIPS_SYS(sys_epoll_pwait, 6)
2106 MIPS_SYS(sys_ioprio_set, 3)
2107 MIPS_SYS(sys_ioprio_get, 2)
2108 MIPS_SYS(sys_utimensat, 4)
2109 MIPS_SYS(sys_signalfd, 3)
2110 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2111 MIPS_SYS(sys_eventfd, 1)
2112 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2113 MIPS_SYS(sys_timerfd_create, 2)
2114 MIPS_SYS(sys_timerfd_gettime, 2)
2115 MIPS_SYS(sys_timerfd_settime, 4)
2116 MIPS_SYS(sys_signalfd4, 4)
2117 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2118 MIPS_SYS(sys_epoll_create1, 1)
2119 MIPS_SYS(sys_dup3, 3)
2120 MIPS_SYS(sys_pipe2, 2)
2121 MIPS_SYS(sys_inotify_init1, 1)
2122 MIPS_SYS(sys_preadv, 6) /* 4330 */
2123 MIPS_SYS(sys_pwritev, 6)
2124 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2125 MIPS_SYS(sys_perf_event_open, 5)
2126 MIPS_SYS(sys_accept4, 4)
2127 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2128 MIPS_SYS(sys_fanotify_init, 2)
2129 MIPS_SYS(sys_fanotify_mark, 6)
2130 MIPS_SYS(sys_prlimit64, 4)
2131 MIPS_SYS(sys_name_to_handle_at, 5)
2132 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2133 MIPS_SYS(sys_clock_adjtime, 2)
2134 MIPS_SYS(sys_syncfs, 1)
2135 };
2136 # undef MIPS_SYS
2137 # endif /* O32 */
2138
2139 static int do_store_exclusive(CPUMIPSState *env)
2140 {
2141 target_ulong addr;
2142 target_ulong page_addr;
2143 target_ulong val;
2144 int flags;
2145 int segv = 0;
2146 int reg;
2147 int d;
2148
2149 addr = env->lladdr;
2150 page_addr = addr & TARGET_PAGE_MASK;
2151 start_exclusive();
2152 mmap_lock();
2153 flags = page_get_flags(page_addr);
2154 if ((flags & PAGE_READ) == 0) {
2155 segv = 1;
2156 } else {
2157 reg = env->llreg & 0x1f;
2158 d = (env->llreg & 0x20) != 0;
2159 if (d) {
2160 segv = get_user_s64(val, addr);
2161 } else {
2162 segv = get_user_s32(val, addr);
2163 }
2164 if (!segv) {
2165 if (val != env->llval) {
2166 env->active_tc.gpr[reg] = 0;
2167 } else {
2168 if (d) {
2169 segv = put_user_u64(env->llnewval, addr);
2170 } else {
2171 segv = put_user_u32(env->llnewval, addr);
2172 }
2173 if (!segv) {
2174 env->active_tc.gpr[reg] = 1;
2175 }
2176 }
2177 }
2178 }
2179 env->lladdr = -1;
2180 if (!segv) {
2181 env->active_tc.PC += 4;
2182 }
2183 mmap_unlock();
2184 end_exclusive();
2185 return segv;
2186 }
2187
2188 /* Break codes */
2189 enum {
2190 BRK_OVERFLOW = 6,
2191 BRK_DIVZERO = 7
2192 };
2193
2194 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2195 unsigned int code)
2196 {
2197 int ret = -1;
2198
2199 switch (code) {
2200 case BRK_OVERFLOW:
2201 case BRK_DIVZERO:
2202 info->si_signo = TARGET_SIGFPE;
2203 info->si_errno = 0;
2204 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2205 queue_signal(env, info->si_signo, &*info);
2206 ret = 0;
2207 break;
2208 default:
2209 break;
2210 }
2211
2212 return ret;
2213 }
2214
2215 void cpu_loop(CPUMIPSState *env)
2216 {
2217 CPUState *cs = CPU(mips_env_get_cpu(env));
2218 target_siginfo_t info;
2219 int trapnr;
2220 abi_long ret;
2221 # ifdef TARGET_ABI_MIPSO32
2222 unsigned int syscall_num;
2223 # endif
2224
2225 for(;;) {
2226 cpu_exec_start(cs);
2227 trapnr = cpu_mips_exec(env);
2228 cpu_exec_end(cs);
2229 switch(trapnr) {
2230 case EXCP_SYSCALL:
2231 env->active_tc.PC += 4;
2232 # ifdef TARGET_ABI_MIPSO32
2233 syscall_num = env->active_tc.gpr[2] - 4000;
2234 if (syscall_num >= sizeof(mips_syscall_args)) {
2235 ret = -TARGET_ENOSYS;
2236 } else {
2237 int nb_args;
2238 abi_ulong sp_reg;
2239 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2240
2241 nb_args = mips_syscall_args[syscall_num];
2242 sp_reg = env->active_tc.gpr[29];
2243 switch (nb_args) {
2244 /* these arguments are taken from the stack */
2245 case 8:
2246 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2247 goto done_syscall;
2248 }
2249 case 7:
2250 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2251 goto done_syscall;
2252 }
2253 case 6:
2254 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2255 goto done_syscall;
2256 }
2257 case 5:
2258 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2259 goto done_syscall;
2260 }
2261 default:
2262 break;
2263 }
2264 ret = do_syscall(env, env->active_tc.gpr[2],
2265 env->active_tc.gpr[4],
2266 env->active_tc.gpr[5],
2267 env->active_tc.gpr[6],
2268 env->active_tc.gpr[7],
2269 arg5, arg6, arg7, arg8);
2270 }
2271 done_syscall:
2272 # else
2273 ret = do_syscall(env, env->active_tc.gpr[2],
2274 env->active_tc.gpr[4], env->active_tc.gpr[5],
2275 env->active_tc.gpr[6], env->active_tc.gpr[7],
2276 env->active_tc.gpr[8], env->active_tc.gpr[9],
2277 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2278 # endif /* O32 */
2279 if (ret == -TARGET_QEMU_ESIGRETURN) {
2280 /* Returning from a successful sigreturn syscall.
2281 Avoid clobbering register state. */
2282 break;
2283 }
2284 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2285 env->active_tc.gpr[7] = 1; /* error flag */
2286 ret = -ret;
2287 } else {
2288 env->active_tc.gpr[7] = 0; /* error flag */
2289 }
2290 env->active_tc.gpr[2] = ret;
2291 break;
2292 case EXCP_TLBL:
2293 case EXCP_TLBS:
2294 case EXCP_AdEL:
2295 case EXCP_AdES:
2296 info.si_signo = TARGET_SIGSEGV;
2297 info.si_errno = 0;
2298 /* XXX: check env->error_code */
2299 info.si_code = TARGET_SEGV_MAPERR;
2300 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2301 queue_signal(env, info.si_signo, &info);
2302 break;
2303 case EXCP_CpU:
2304 case EXCP_RI:
2305 info.si_signo = TARGET_SIGILL;
2306 info.si_errno = 0;
2307 info.si_code = 0;
2308 queue_signal(env, info.si_signo, &info);
2309 break;
2310 case EXCP_INTERRUPT:
2311 /* just indicate that signals should be handled asap */
2312 break;
2313 case EXCP_DEBUG:
2314 {
2315 int sig;
2316
2317 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2318 if (sig)
2319 {
2320 info.si_signo = sig;
2321 info.si_errno = 0;
2322 info.si_code = TARGET_TRAP_BRKPT;
2323 queue_signal(env, info.si_signo, &info);
2324 }
2325 }
2326 break;
2327 case EXCP_SC:
2328 if (do_store_exclusive(env)) {
2329 info.si_signo = TARGET_SIGSEGV;
2330 info.si_errno = 0;
2331 info.si_code = TARGET_SEGV_MAPERR;
2332 info._sifields._sigfault._addr = env->active_tc.PC;
2333 queue_signal(env, info.si_signo, &info);
2334 }
2335 break;
2336 case EXCP_DSPDIS:
2337 info.si_signo = TARGET_SIGILL;
2338 info.si_errno = 0;
2339 info.si_code = TARGET_ILL_ILLOPC;
2340 queue_signal(env, info.si_signo, &info);
2341 break;
2342 /* The code below was inspired by the MIPS Linux kernel trap
2343 * handling code in arch/mips/kernel/traps.c.
2344 */
2345 case EXCP_BREAK:
2346 {
2347 abi_ulong trap_instr;
2348 unsigned int code;
2349
2350 ret = get_user_ual(trap_instr, env->active_tc.PC);
2351 if (ret != 0) {
2352 goto error;
2353 }
2354
2355 /* As described in the original Linux kernel code, the
2356 * below checks on 'code' are to work around an old
2357 * assembly bug.
2358 */
2359 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2360 if (code >= (1 << 10)) {
2361 code >>= 10;
2362 }
2363
2364 if (do_break(env, &info, code) != 0) {
2365 goto error;
2366 }
2367 }
2368 break;
2369 case EXCP_TRAP:
2370 {
2371 abi_ulong trap_instr;
2372 unsigned int code = 0;
2373
2374 ret = get_user_ual(trap_instr, env->active_tc.PC);
2375 if (ret != 0) {
2376 goto error;
2377 }
2378
2379 /* The immediate versions don't provide a code. */
2380 if (!(trap_instr & 0xFC000000)) {
2381 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2382 }
2383
2384 if (do_break(env, &info, code) != 0) {
2385 goto error;
2386 }
2387 }
2388 break;
2389 default:
2390 error:
2391 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2392 trapnr);
2393 cpu_dump_state(cs, stderr, fprintf, 0);
2394 abort();
2395 }
2396 process_pending_signals(env);
2397 }
2398 }
2399 #endif
2400
2401 #ifdef TARGET_OPENRISC
2402
2403 void cpu_loop(CPUOpenRISCState *env)
2404 {
2405 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2406 int trapnr, gdbsig;
2407
2408 for (;;) {
2409 trapnr = cpu_exec(env);
2410 gdbsig = 0;
2411
2412 switch (trapnr) {
2413 case EXCP_RESET:
2414 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2415 exit(1);
2416 break;
2417 case EXCP_BUSERR:
2418 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2419 gdbsig = SIGBUS;
2420 break;
2421 case EXCP_DPF:
2422 case EXCP_IPF:
2423 cpu_dump_state(cs, stderr, fprintf, 0);
2424 gdbsig = TARGET_SIGSEGV;
2425 break;
2426 case EXCP_TICK:
2427 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2428 break;
2429 case EXCP_ALIGN:
2430 qemu_log("\nAlignment pc is %#x\n", env->pc);
2431 gdbsig = SIGBUS;
2432 break;
2433 case EXCP_ILLEGAL:
2434 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2435 gdbsig = SIGILL;
2436 break;
2437 case EXCP_INT:
2438 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2439 break;
2440 case EXCP_DTLBMISS:
2441 case EXCP_ITLBMISS:
2442 qemu_log("\nTLB miss\n");
2443 break;
2444 case EXCP_RANGE:
2445 qemu_log("\nRange\n");
2446 gdbsig = SIGSEGV;
2447 break;
2448 case EXCP_SYSCALL:
2449 env->pc += 4; /* 0xc00; */
2450 env->gpr[11] = do_syscall(env,
2451 env->gpr[11], /* return value */
2452 env->gpr[3], /* r3 - r7 are params */
2453 env->gpr[4],
2454 env->gpr[5],
2455 env->gpr[6],
2456 env->gpr[7],
2457 env->gpr[8], 0, 0);
2458 break;
2459 case EXCP_FPE:
2460 qemu_log("\nFloating point error\n");
2461 break;
2462 case EXCP_TRAP:
2463 qemu_log("\nTrap\n");
2464 gdbsig = SIGTRAP;
2465 break;
2466 case EXCP_NR:
2467 qemu_log("\nNR\n");
2468 break;
2469 default:
2470 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2471 trapnr);
2472 cpu_dump_state(cs, stderr, fprintf, 0);
2473 gdbsig = TARGET_SIGILL;
2474 break;
2475 }
2476 if (gdbsig) {
2477 gdb_handlesig(env, gdbsig);
2478 if (gdbsig != TARGET_SIGTRAP) {
2479 exit(1);
2480 }
2481 }
2482
2483 process_pending_signals(env);
2484 }
2485 }
2486
2487 #endif /* TARGET_OPENRISC */
2488
2489 #ifdef TARGET_SH4
2490 void cpu_loop(CPUSH4State *env)
2491 {
2492 CPUState *cs = CPU(sh_env_get_cpu(env));
2493 int trapnr, ret;
2494 target_siginfo_t info;
2495
2496 while (1) {
2497 trapnr = cpu_sh4_exec (env);
2498
2499 switch (trapnr) {
2500 case 0x160:
2501 env->pc += 2;
2502 ret = do_syscall(env,
2503 env->gregs[3],
2504 env->gregs[4],
2505 env->gregs[5],
2506 env->gregs[6],
2507 env->gregs[7],
2508 env->gregs[0],
2509 env->gregs[1],
2510 0, 0);
2511 env->gregs[0] = ret;
2512 break;
2513 case EXCP_INTERRUPT:
2514 /* just indicate that signals should be handled asap */
2515 break;
2516 case EXCP_DEBUG:
2517 {
2518 int sig;
2519
2520 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2521 if (sig)
2522 {
2523 info.si_signo = sig;
2524 info.si_errno = 0;
2525 info.si_code = TARGET_TRAP_BRKPT;
2526 queue_signal(env, info.si_signo, &info);
2527 }
2528 }
2529 break;
2530 case 0xa0:
2531 case 0xc0:
2532 info.si_signo = SIGSEGV;
2533 info.si_errno = 0;
2534 info.si_code = TARGET_SEGV_MAPERR;
2535 info._sifields._sigfault._addr = env->tea;
2536 queue_signal(env, info.si_signo, &info);
2537 break;
2538
2539 default:
2540 printf ("Unhandled trap: 0x%x\n", trapnr);
2541 cpu_dump_state(cs, stderr, fprintf, 0);
2542 exit (1);
2543 }
2544 process_pending_signals (env);
2545 }
2546 }
2547 #endif
2548
2549 #ifdef TARGET_CRIS
2550 void cpu_loop(CPUCRISState *env)
2551 {
2552 CPUState *cs = CPU(cris_env_get_cpu(env));
2553 int trapnr, ret;
2554 target_siginfo_t info;
2555
2556 while (1) {
2557 trapnr = cpu_cris_exec (env);
2558 switch (trapnr) {
2559 case 0xaa:
2560 {
2561 info.si_signo = SIGSEGV;
2562 info.si_errno = 0;
2563 /* XXX: check env->error_code */
2564 info.si_code = TARGET_SEGV_MAPERR;
2565 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2566 queue_signal(env, info.si_signo, &info);
2567 }
2568 break;
2569 case EXCP_INTERRUPT:
2570 /* just indicate that signals should be handled asap */
2571 break;
2572 case EXCP_BREAK:
2573 ret = do_syscall(env,
2574 env->regs[9],
2575 env->regs[10],
2576 env->regs[11],
2577 env->regs[12],
2578 env->regs[13],
2579 env->pregs[7],
2580 env->pregs[11],
2581 0, 0);
2582 env->regs[10] = ret;
2583 break;
2584 case EXCP_DEBUG:
2585 {
2586 int sig;
2587
2588 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2589 if (sig)
2590 {
2591 info.si_signo = sig;
2592 info.si_errno = 0;
2593 info.si_code = TARGET_TRAP_BRKPT;
2594 queue_signal(env, info.si_signo, &info);
2595 }
2596 }
2597 break;
2598 default:
2599 printf ("Unhandled trap: 0x%x\n", trapnr);
2600 cpu_dump_state(cs, stderr, fprintf, 0);
2601 exit (1);
2602 }
2603 process_pending_signals (env);
2604 }
2605 }
2606 #endif
2607
2608 #ifdef TARGET_MICROBLAZE
2609 void cpu_loop(CPUMBState *env)
2610 {
2611 CPUState *cs = CPU(mb_env_get_cpu(env));
2612 int trapnr, ret;
2613 target_siginfo_t info;
2614
2615 while (1) {
2616 trapnr = cpu_mb_exec (env);
2617 switch (trapnr) {
2618 case 0xaa:
2619 {
2620 info.si_signo = SIGSEGV;
2621 info.si_errno = 0;
2622 /* XXX: check env->error_code */
2623 info.si_code = TARGET_SEGV_MAPERR;
2624 info._sifields._sigfault._addr = 0;
2625 queue_signal(env, info.si_signo, &info);
2626 }
2627 break;
2628 case EXCP_INTERRUPT:
2629 /* just indicate that signals should be handled asap */
2630 break;
2631 case EXCP_BREAK:
2632 /* Return address is 4 bytes after the call. */
2633 env->regs[14] += 4;
2634 env->sregs[SR_PC] = env->regs[14];
2635 ret = do_syscall(env,
2636 env->regs[12],
2637 env->regs[5],
2638 env->regs[6],
2639 env->regs[7],
2640 env->regs[8],
2641 env->regs[9],
2642 env->regs[10],
2643 0, 0);
2644 env->regs[3] = ret;
2645 break;
2646 case EXCP_HW_EXCP:
2647 env->regs[17] = env->sregs[SR_PC] + 4;
2648 if (env->iflags & D_FLAG) {
2649 env->sregs[SR_ESR] |= 1 << 12;
2650 env->sregs[SR_PC] -= 4;
2651 /* FIXME: if branch was immed, replay the imm as well. */
2652 }
2653
2654 env->iflags &= ~(IMM_FLAG | D_FLAG);
2655
2656 switch (env->sregs[SR_ESR] & 31) {
2657 case ESR_EC_DIVZERO:
2658 info.si_signo = SIGFPE;
2659 info.si_errno = 0;
2660 info.si_code = TARGET_FPE_FLTDIV;
2661 info._sifields._sigfault._addr = 0;
2662 queue_signal(env, info.si_signo, &info);
2663 break;
2664 case ESR_EC_FPU:
2665 info.si_signo = SIGFPE;
2666 info.si_errno = 0;
2667 if (env->sregs[SR_FSR] & FSR_IO) {
2668 info.si_code = TARGET_FPE_FLTINV;
2669 }
2670 if (env->sregs[SR_FSR] & FSR_DZ) {
2671 info.si_code = TARGET_FPE_FLTDIV;
2672 }
2673 info._sifields._sigfault._addr = 0;
2674 queue_signal(env, info.si_signo, &info);
2675 break;
2676 default:
2677 printf ("Unhandled hw-exception: 0x%x\n",
2678 env->sregs[SR_ESR] & ESR_EC_MASK);
2679 cpu_dump_state(cs, stderr, fprintf, 0);
2680 exit (1);
2681 break;
2682 }
2683 break;
2684 case EXCP_DEBUG:
2685 {
2686 int sig;
2687
2688 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2689 if (sig)
2690 {
2691 info.si_signo = sig;
2692 info.si_errno = 0;
2693 info.si_code = TARGET_TRAP_BRKPT;
2694 queue_signal(env, info.si_signo, &info);
2695 }
2696 }
2697 break;
2698 default:
2699 printf ("Unhandled trap: 0x%x\n", trapnr);
2700 cpu_dump_state(cs, stderr, fprintf, 0);
2701 exit (1);
2702 }
2703 process_pending_signals (env);
2704 }
2705 }
2706 #endif
2707
2708 #ifdef TARGET_M68K
2709
2710 void cpu_loop(CPUM68KState *env)
2711 {
2712 CPUState *cs = CPU(m68k_env_get_cpu(env));
2713 int trapnr;
2714 unsigned int n;
2715 target_siginfo_t info;
2716 TaskState *ts = env->opaque;
2717
2718 for(;;) {
2719 trapnr = cpu_m68k_exec(env);
2720 switch(trapnr) {
2721 case EXCP_ILLEGAL:
2722 {
2723 if (ts->sim_syscalls) {
2724 uint16_t nr;
2725 nr = lduw(env->pc + 2);
2726 env->pc += 4;
2727 do_m68k_simcall(env, nr);
2728 } else {
2729 goto do_sigill;
2730 }
2731 }
2732 break;
2733 case EXCP_HALT_INSN:
2734 /* Semihosing syscall. */
2735 env->pc += 4;
2736 do_m68k_semihosting(env, env->dregs[0]);
2737 break;
2738 case EXCP_LINEA:
2739 case EXCP_LINEF:
2740 case EXCP_UNSUPPORTED:
2741 do_sigill:
2742 info.si_signo = SIGILL;
2743 info.si_errno = 0;
2744 info.si_code = TARGET_ILL_ILLOPN;
2745 info._sifields._sigfault._addr = env->pc;
2746 queue_signal(env, info.si_signo, &info);
2747 break;
2748 case EXCP_TRAP0:
2749 {
2750 ts->sim_syscalls = 0;
2751 n = env->dregs[0];
2752 env->pc += 2;
2753 env->dregs[0] = do_syscall(env,
2754 n,
2755 env->dregs[1],
2756 env->dregs[2],
2757 env->dregs[3],
2758 env->dregs[4],
2759 env->dregs[5],
2760 env->aregs[0],
2761 0, 0);
2762 }
2763 break;
2764 case EXCP_INTERRUPT:
2765 /* just indicate that signals should be handled asap */
2766 break;
2767 case EXCP_ACCESS:
2768 {
2769 info.si_signo = SIGSEGV;
2770 info.si_errno = 0;
2771 /* XXX: check env->error_code */
2772 info.si_code = TARGET_SEGV_MAPERR;
2773 info._sifields._sigfault._addr = env->mmu.ar;
2774 queue_signal(env, info.si_signo, &info);
2775 }
2776 break;
2777 case EXCP_DEBUG:
2778 {
2779 int sig;
2780
2781 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2782 if (sig)
2783 {
2784 info.si_signo = sig;
2785 info.si_errno = 0;
2786 info.si_code = TARGET_TRAP_BRKPT;
2787 queue_signal(env, info.si_signo, &info);
2788 }
2789 }
2790 break;
2791 default:
2792 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2793 trapnr);
2794 cpu_dump_state(cs, stderr, fprintf, 0);
2795 abort();
2796 }
2797 process_pending_signals(env);
2798 }
2799 }
2800 #endif /* TARGET_M68K */
2801
2802 #ifdef TARGET_ALPHA
2803 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
2804 {
2805 target_ulong addr, val, tmp;
2806 target_siginfo_t info;
2807 int ret = 0;
2808
2809 addr = env->lock_addr;
2810 tmp = env->lock_st_addr;
2811 env->lock_addr = -1;
2812 env->lock_st_addr = 0;
2813
2814 start_exclusive();
2815 mmap_lock();
2816
2817 if (addr == tmp) {
2818 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
2819 goto do_sigsegv;
2820 }
2821
2822 if (val == env->lock_value) {
2823 tmp = env->ir[reg];
2824 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
2825 goto do_sigsegv;
2826 }
2827 ret = 1;
2828 }
2829 }
2830 env->ir[reg] = ret;
2831 env->pc += 4;
2832
2833 mmap_unlock();
2834 end_exclusive();
2835 return;
2836
2837 do_sigsegv:
2838 mmap_unlock();
2839 end_exclusive();
2840
2841 info.si_signo = TARGET_SIGSEGV;
2842 info.si_errno = 0;
2843 info.si_code = TARGET_SEGV_MAPERR;
2844 info._sifields._sigfault._addr = addr;
2845 queue_signal(env, TARGET_SIGSEGV, &info);
2846 }
2847
2848 void cpu_loop(CPUAlphaState *env)
2849 {
2850 CPUState *cs = CPU(alpha_env_get_cpu(env));
2851 int trapnr;
2852 target_siginfo_t info;
2853 abi_long sysret;
2854
2855 while (1) {
2856 trapnr = cpu_alpha_exec (env);
2857
2858 /* All of the traps imply a transition through PALcode, which
2859 implies an REI instruction has been executed. Which means
2860 that the intr_flag should be cleared. */
2861 env->intr_flag = 0;
2862
2863 switch (trapnr) {
2864 case EXCP_RESET:
2865 fprintf(stderr, "Reset requested. Exit\n");
2866 exit(1);
2867 break;
2868 case EXCP_MCHK:
2869 fprintf(stderr, "Machine check exception. Exit\n");
2870 exit(1);
2871 break;
2872 case EXCP_SMP_INTERRUPT:
2873 case EXCP_CLK_INTERRUPT:
2874 case EXCP_DEV_INTERRUPT:
2875 fprintf(stderr, "External interrupt. Exit\n");
2876 exit(1);
2877 break;
2878 case EXCP_MMFAULT:
2879 env->lock_addr = -1;
2880 info.si_signo = TARGET_SIGSEGV;
2881 info.si_errno = 0;
2882 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
2883 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
2884 info._sifields._sigfault._addr = env->trap_arg0;
2885 queue_signal(env, info.si_signo, &info);
2886 break;
2887 case EXCP_UNALIGN:
2888 env->lock_addr = -1;
2889 info.si_signo = TARGET_SIGBUS;
2890 info.si_errno = 0;
2891 info.si_code = TARGET_BUS_ADRALN;
2892 info._sifields._sigfault._addr = env->trap_arg0;
2893 queue_signal(env, info.si_signo, &info);
2894 break;
2895 case EXCP_OPCDEC:
2896 do_sigill:
2897 env->lock_addr = -1;
2898 info.si_signo = TARGET_SIGILL;
2899 info.si_errno = 0;
2900 info.si_code = TARGET_ILL_ILLOPC;
2901 info._sifields._sigfault._addr = env->pc;
2902 queue_signal(env, info.si_signo, &info);
2903 break;
2904 case EXCP_ARITH:
2905 env->lock_addr = -1;
2906 info.si_signo = TARGET_SIGFPE;
2907 info.si_errno = 0;
2908 info.si_code = TARGET_FPE_FLTINV;
2909 info._sifields._sigfault._addr = env->pc;
2910 queue_signal(env, info.si_signo, &info);
2911 break;
2912 case EXCP_FEN:
2913 /* No-op. Linux simply re-enables the FPU. */
2914 break;
2915 case EXCP_CALL_PAL:
2916 env->lock_addr = -1;
2917 switch (env->error_code) {
2918 case 0x80:
2919 /* BPT */
2920 info.si_signo = TARGET_SIGTRAP;
2921 info.si_errno = 0;
2922 info.si_code = TARGET_TRAP_BRKPT;
2923 info._sifields._sigfault._addr = env->pc;
2924 queue_signal(env, info.si_signo, &info);
2925 break;
2926 case 0x81:
2927 /* BUGCHK */
2928 info.si_signo = TARGET_SIGTRAP;
2929 info.si_errno = 0;
2930 info.si_code = 0;
2931 info._sifields._sigfault._addr = env->pc;
2932 queue_signal(env, info.si_signo, &info);
2933 break;
2934 case 0x83:
2935 /* CALLSYS */
2936 trapnr = env->ir[IR_V0];
2937 sysret = do_syscall(env, trapnr,
2938 env->ir[IR_A0], env->ir[IR_A1],
2939 env->ir[IR_A2], env->ir[IR_A3],
2940 env->ir[IR_A4], env->ir[IR_A5],
2941 0, 0);
2942 if (trapnr == TARGET_NR_sigreturn
2943 || trapnr == TARGET_NR_rt_sigreturn) {
2944 break;
2945 }
2946 /* Syscall writes 0 to V0 to bypass error check, similar
2947 to how this is handled internal to Linux kernel.
2948 (Ab)use trapnr temporarily as boolean indicating error. */
2949 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
2950 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
2951 env->ir[IR_A3] = trapnr;
2952 break;
2953 case 0x86:
2954 /* IMB */
2955 /* ??? We can probably elide the code using page_unprotect
2956 that is checking for self-modifying code. Instead we
2957 could simply call tb_flush here. Until we work out the
2958 changes required to turn off the extra write protection,
2959 this can be a no-op. */
2960 break;
2961 case 0x9E:
2962 /* RDUNIQUE */
2963 /* Handled in the translator for usermode. */
2964 abort();
2965 case 0x9F:
2966 /* WRUNIQUE */
2967 /* Handled in the translator for usermode. */
2968 abort();
2969 case 0xAA:
2970 /* GENTRAP */
2971 info.si_signo = TARGET_SIGFPE;
2972 switch (env->ir[IR_A0]) {
2973 case TARGET_GEN_INTOVF:
2974 info.si_code = TARGET_FPE_INTOVF;
2975 break;
2976 case TARGET_GEN_INTDIV:
2977 info.si_code = TARGET_FPE_INTDIV;
2978 break;
2979 case TARGET_GEN_FLTOVF:
2980 info.si_code = TARGET_FPE_FLTOVF;
2981 break;
2982 case TARGET_GEN_FLTUND:
2983 info.si_code = TARGET_FPE_FLTUND;
2984 break;
2985 case TARGET_GEN_FLTINV:
2986 info.si_code = TARGET_FPE_FLTINV;
2987 break;
2988 case TARGET_GEN_FLTINE:
2989 info.si_code = TARGET_FPE_FLTRES;
2990 break;
2991 case TARGET_GEN_ROPRAND:
2992 info.si_code = 0;
2993 break;
2994 default:
2995 info.si_signo = TARGET_SIGTRAP;
2996 info.si_code = 0;
2997 break;
2998 }
2999 info.si_errno = 0;
3000 info._sifields._sigfault._addr = env->pc;
3001 queue_signal(env, info.si_signo, &info);
3002 break;
3003 default:
3004 goto do_sigill;
3005 }
3006 break;
3007 case EXCP_DEBUG:
3008 info.si_signo = gdb_handlesig (env, TARGET_SIGTRAP);
3009 if (info.si_signo) {
3010 env->lock_addr = -1;
3011 info.si_errno = 0;
3012 info.si_code = TARGET_TRAP_BRKPT;
3013 queue_signal(env, info.si_signo, &info);
3014 }
3015 break;
3016 case EXCP_STL_C:
3017 case EXCP_STQ_C:
3018 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3019 break;
3020 case EXCP_INTERRUPT:
3021 /* Just indicate that signals should be handled asap. */
3022 break;
3023 default:
3024 printf ("Unhandled trap: 0x%x\n", trapnr);
3025 cpu_dump_state(cs, stderr, fprintf, 0);
3026 exit (1);
3027 }
3028 process_pending_signals (env);
3029 }
3030 }
3031 #endif /* TARGET_ALPHA */
3032
3033 #ifdef TARGET_S390X
3034 void cpu_loop(CPUS390XState *env)
3035 {
3036 CPUState *cs = CPU(s390_env_get_cpu(env));
3037 int trapnr, n, sig;
3038 target_siginfo_t info;
3039 target_ulong addr;
3040
3041 while (1) {
3042 trapnr = cpu_s390x_exec(env);
3043 switch (trapnr) {
3044 case EXCP_INTERRUPT:
3045 /* Just indicate that signals should be handled asap. */
3046 break;
3047
3048 case EXCP_SVC:
3049 n = env->int_svc_code;
3050 if (!n) {
3051 /* syscalls > 255 */
3052 n = env->regs[1];
3053 }
3054 env->psw.addr += env->int_svc_ilen;
3055 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3056 env->regs[4], env->regs[5],
3057 env->regs[6], env->regs[7], 0, 0);
3058 break;
3059
3060 case EXCP_DEBUG:
3061 sig = gdb_handlesig(env, TARGET_SIGTRAP);
3062 if (sig) {
3063 n = TARGET_TRAP_BRKPT;
3064 goto do_signal_pc;
3065 }
3066 break;
3067 case EXCP_PGM:
3068 n = env->int_pgm_code;
3069 switch (n) {
3070 case PGM_OPERATION:
3071 case PGM_PRIVILEGED:
3072 sig = SIGILL;
3073 n = TARGET_ILL_ILLOPC;
3074 goto do_signal_pc;
3075 case PGM_PROTECTION:
3076 case PGM_ADDRESSING:
3077 sig = SIGSEGV;
3078 /* XXX: check env->error_code */
3079 n = TARGET_SEGV_MAPERR;
3080 addr = env->__excp_addr;
3081 goto do_signal;
3082 case PGM_EXECUTE:
3083 case PGM_SPECIFICATION:
3084 case PGM_SPECIAL_OP:
3085 case PGM_OPERAND:
3086 do_sigill_opn:
3087 sig = SIGILL;
3088 n = TARGET_ILL_ILLOPN;
3089 goto do_signal_pc;
3090
3091 case PGM_FIXPT_OVERFLOW:
3092 sig = SIGFPE;
3093 n = TARGET_FPE_INTOVF;
3094 goto do_signal_pc;
3095 case PGM_FIXPT_DIVIDE:
3096 sig = SIGFPE;
3097 n = TARGET_FPE_INTDIV;
3098 goto do_signal_pc;
3099
3100 case PGM_DATA:
3101 n = (env->fpc >> 8) & 0xff;
3102 if (n == 0xff) {
3103 /* compare-and-trap */
3104 goto do_sigill_opn;
3105 } else {
3106 /* An IEEE exception, simulated or otherwise. */
3107 if (n & 0x80) {
3108 n = TARGET_FPE_FLTINV;
3109 } else if (n & 0x40) {
3110 n = TARGET_FPE_FLTDIV;
3111 } else if (n & 0x20) {
3112 n = TARGET_FPE_FLTOVF;
3113 } else if (n & 0x10) {
3114 n = TARGET_FPE_FLTUND;
3115 } else if (n & 0x08) {
3116 n = TARGET_FPE_FLTRES;
3117 } else {
3118 /* ??? Quantum exception; BFP, DFP error. */
3119 goto do_sigill_opn;
3120 }
3121 sig = SIGFPE;
3122 goto do_signal_pc;
3123 }
3124
3125 default:
3126 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3127 cpu_dump_state(cs, stderr, fprintf, 0);
3128 exit(1);
3129 }
3130 break;
3131
3132 do_signal_pc:
3133 addr = env->psw.addr;
3134 do_signal:
3135 info.si_signo = sig;
3136 info.si_errno = 0;
3137 info.si_code = n;
3138 info._sifields._sigfault._addr = addr;
3139 queue_signal(env, info.si_signo, &info);
3140 break;
3141
3142 default:
3143 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3144 cpu_dump_state(cs, stderr, fprintf, 0);
3145 exit(1);
3146 }
3147 process_pending_signals (env);
3148 }
3149 }
3150
3151 #endif /* TARGET_S390X */
3152
3153 THREAD CPUArchState *thread_env;
3154
3155 void task_settid(TaskState *ts)
3156 {
3157 if (ts->ts_tid == 0) {
3158 #ifdef CONFIG_USE_NPTL
3159 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3160 #else
3161 /* when no threads are used, tid becomes pid */
3162 ts->ts_tid = getpid();
3163 #endif
3164 }
3165 }
3166
3167 void stop_all_tasks(void)
3168 {
3169 /*
3170 * We trust that when using NPTL, start_exclusive()
3171 * handles thread stopping correctly.
3172 */
3173 start_exclusive();
3174 }
3175
3176 /* Assumes contents are already zeroed. */
3177 void init_task_state(TaskState *ts)
3178 {
3179 int i;
3180
3181 ts->used = 1;
3182 ts->first_free = ts->sigqueue_table;
3183 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3184 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3185 }
3186 ts->sigqueue_table[i].next = NULL;
3187 }
3188
3189 static void handle_arg_help(const char *arg)
3190 {
3191 usage();
3192 }
3193
3194 static void handle_arg_log(const char *arg)
3195 {
3196 int mask;
3197
3198 mask = qemu_str_to_log_mask(arg);
3199 if (!mask) {
3200 qemu_print_log_usage(stdout);
3201 exit(1);
3202 }
3203 qemu_set_log(mask);
3204 }
3205
3206 static void handle_arg_log_filename(const char *arg)
3207 {
3208 qemu_set_log_filename(arg);
3209 }
3210
3211 static void handle_arg_set_env(const char *arg)
3212 {
3213 char *r, *p, *token;
3214 r = p = strdup(arg);
3215 while ((token = strsep(&p, ",")) != NULL) {
3216 if (envlist_setenv(envlist, token) != 0) {
3217 usage();
3218 }
3219 }
3220 free(r);
3221 }
3222
3223 static void handle_arg_unset_env(const char *arg)
3224 {
3225 char *r, *p, *token;
3226 r = p = strdup(arg);
3227 while ((token = strsep(&p, ",")) != NULL) {
3228 if (envlist_unsetenv(envlist, token) != 0) {
3229 usage();
3230 }
3231 }
3232 free(r);
3233 }
3234
3235 static void handle_arg_argv0(const char *arg)
3236 {
3237 argv0 = strdup(arg);
3238 }
3239
3240 static void handle_arg_stack_size(const char *arg)
3241 {
3242 char *p;
3243 guest_stack_size = strtoul(arg, &p, 0);
3244 if (guest_stack_size == 0) {
3245 usage();
3246 }
3247
3248 if (*p == 'M') {
3249 guest_stack_size *= 1024 * 1024;
3250 } else if (*p == 'k' || *p == 'K') {
3251 guest_stack_size *= 1024;
3252 }
3253 }
3254
3255 static void handle_arg_ld_prefix(const char *arg)
3256 {
3257 interp_prefix = strdup(arg);
3258 }
3259
3260 static void handle_arg_pagesize(const char *arg)
3261 {
3262 qemu_host_page_size = atoi(arg);
3263 if (qemu_host_page_size == 0 ||
3264 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3265 fprintf(stderr, "page size must be a power of two\n");
3266 exit(1);
3267 }
3268 }
3269
3270 static void handle_arg_gdb(const char *arg)
3271 {
3272 gdbstub_port = atoi(arg);
3273 }
3274
3275 static void handle_arg_uname(const char *arg)
3276 {
3277 qemu_uname_release = strdup(arg);
3278 }
3279
3280 static void handle_arg_cpu(const char *arg)
3281 {
3282 cpu_model = strdup(arg);
3283 if (cpu_model == NULL || is_help_option(cpu_model)) {
3284 /* XXX: implement xxx_cpu_list for targets that still miss it */
3285 #if defined(cpu_list)
3286 cpu_list(stdout, &fprintf);
3287 #endif
3288 exit(1);
3289 }
3290 }
3291
3292 #if defined(CONFIG_USE_GUEST_BASE)
3293 static void handle_arg_guest_base(const char *arg)
3294 {
3295 guest_base = strtol(arg, NULL, 0);
3296 have_guest_base = 1;
3297 }
3298
3299 static void handle_arg_reserved_va(const char *arg)
3300 {
3301 char *p;
3302 int shift = 0;
3303 reserved_va = strtoul(arg, &p, 0);
3304 switch (*p) {
3305 case 'k':
3306 case 'K':
3307 shift = 10;
3308 break;
3309 case 'M':
3310 shift = 20;
3311 break;
3312 case 'G':
3313 shift = 30;
3314 break;
3315 }
3316 if (shift) {
3317 unsigned long unshifted = reserved_va;
3318 p++;
3319 reserved_va <<= shift;
3320 if (((reserved_va >> shift) != unshifted)
3321 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3322 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3323 #endif
3324 ) {
3325 fprintf(stderr, "Reserved virtual address too big\n");
3326 exit(1);
3327 }
3328 }
3329 if (*p) {
3330 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3331 exit(1);
3332 }
3333 }
3334 #endif
3335
3336 static void handle_arg_singlestep(const char *arg)
3337 {
3338 singlestep = 1;
3339 }
3340
3341 static void handle_arg_strace(const char *arg)
3342 {
3343 do_strace = 1;
3344 }
3345
3346 static void handle_arg_version(const char *arg)
3347 {
3348 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3349 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3350 exit(0);
3351 }
3352
3353 struct qemu_argument {
3354 const char *argv;
3355 const char *env;
3356 bool has_arg;
3357 void (*handle_opt)(const char *arg);
3358 const char *example;
3359 const char *help;
3360 };
3361
3362 static const struct qemu_argument arg_table[] = {
3363 {"h", "", false, handle_arg_help,
3364 "", "print this help"},
3365 {"g", "QEMU_GDB", true, handle_arg_gdb,
3366 "port", "wait gdb connection to 'port'"},
3367 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3368 "path", "set the elf interpreter prefix to 'path'"},
3369 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3370 "size", "set the stack size to 'size' bytes"},
3371 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3372 "model", "select CPU (-cpu help for list)"},
3373 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3374 "var=value", "sets targets environment variable (see below)"},
3375 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3376 "var", "unsets targets environment variable (see below)"},
3377 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3378 "argv0", "forces target process argv[0] to be 'argv0'"},
3379 {"r", "QEMU_UNAME", true, handle_arg_uname,
3380 "uname", "set qemu uname release string to 'uname'"},
3381 #if defined(CONFIG_USE_GUEST_BASE)
3382 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3383 "address", "set guest_base address to 'address'"},
3384 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3385 "size", "reserve 'size' bytes for guest virtual address space"},
3386 #endif
3387 {"d", "QEMU_LOG", true, handle_arg_log,
3388 "item[,...]", "enable logging of specified items "
3389 "(use '-d help' for a list of items)"},
3390 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3391 "logfile", "write logs to 'logfile' (default stderr)"},
3392 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3393 "pagesize", "set the host page size to 'pagesize'"},
3394 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3395 "", "run in singlestep mode"},
3396 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3397 "", "log system calls"},
3398 {"version", "QEMU_VERSION", false, handle_arg_version,
3399 "", "display version information and exit"},
3400 {NULL, NULL, false, NULL, NULL, NULL}
3401 };
3402
3403 static void usage(void)
3404 {
3405 const struct qemu_argument *arginfo;
3406 int maxarglen;
3407 int maxenvlen;
3408
3409 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3410 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3411 "\n"
3412 "Options and associated environment variables:\n"
3413 "\n");
3414
3415 /* Calculate column widths. We must always have at least enough space
3416 * for the column header.
3417 */
3418 maxarglen = strlen("Argument");
3419 maxenvlen = strlen("Env-variable");
3420
3421 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3422 int arglen = strlen(arginfo->argv);
3423 if (arginfo->has_arg) {
3424 arglen += strlen(arginfo->example) + 1;
3425 }
3426 if (strlen(arginfo->env) > maxenvlen) {
3427 maxenvlen = strlen(arginfo->env);
3428 }
3429 if (arglen > maxarglen) {
3430 maxarglen = arglen;
3431 }
3432 }
3433
3434 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3435 maxenvlen, "Env-variable");
3436
3437 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3438 if (arginfo->has_arg) {
3439 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3440 (int)(maxarglen - strlen(arginfo->argv) - 1),
3441 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3442 } else {
3443 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3444 maxenvlen, arginfo->env,
3445 arginfo->help);
3446 }
3447 }
3448
3449 printf("\n"
3450 "Defaults:\n"
3451 "QEMU_LD_PREFIX = %s\n"
3452 "QEMU_STACK_SIZE = %ld byte\n",
3453 interp_prefix,
3454 guest_stack_size);
3455
3456 printf("\n"
3457 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3458 "QEMU_UNSET_ENV environment variables to set and unset\n"
3459 "environment variables for the target process.\n"
3460 "It is possible to provide several variables by separating them\n"
3461 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3462 "provide the -E and -U options multiple times.\n"
3463 "The following lines are equivalent:\n"
3464 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3465 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3466 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3467 "Note that if you provide several changes to a single variable\n"
3468 "the last change will stay in effect.\n");
3469
3470 exit(1);
3471 }
3472
3473 static int parse_args(int argc, char **argv)
3474 {
3475 const char *r;
3476 int optind;
3477 const struct qemu_argument *arginfo;
3478
3479 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3480 if (arginfo->env == NULL) {
3481 continue;
3482 }
3483
3484 r = getenv(arginfo->env);
3485 if (r != NULL) {
3486 arginfo->handle_opt(r);
3487 }
3488 }
3489
3490 optind = 1;
3491 for (;;) {
3492 if (optind >= argc) {
3493 break;
3494 }
3495 r = argv[optind];
3496 if (r[0] != '-') {
3497 break;
3498 }
3499 optind++;
3500 r++;
3501 if (!strcmp(r, "-")) {
3502 break;
3503 }
3504
3505 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3506 if (!strcmp(r, arginfo->argv)) {
3507 if (arginfo->has_arg) {
3508 if (optind >= argc) {
3509 usage();
3510 }
3511 arginfo->handle_opt(argv[optind]);
3512 optind++;
3513 } else {
3514 arginfo->handle_opt(NULL);
3515 }
3516 break;
3517 }
3518 }
3519
3520 /* no option matched the current argv */
3521 if (arginfo->handle_opt == NULL) {
3522 usage();
3523 }
3524 }
3525
3526 if (optind >= argc) {
3527 usage();
3528 }
3529
3530 filename = argv[optind];
3531 exec_path = argv[optind];
3532
3533 return optind;
3534 }
3535
3536 int main(int argc, char **argv, char **envp)
3537 {
3538 struct target_pt_regs regs1, *regs = &regs1;
3539 struct image_info info1, *info = &info1;
3540 struct linux_binprm bprm;
3541 TaskState *ts;
3542 CPUArchState *env;
3543 int optind;
3544 char **target_environ, **wrk;
3545 char **target_argv;
3546 int target_argc;
3547 int i;
3548 int ret;
3549
3550 module_call_init(MODULE_INIT_QOM);
3551
3552 qemu_cache_utils_init(envp);
3553
3554 if ((envlist = envlist_create()) == NULL) {
3555 (void) fprintf(stderr, "Unable to allocate envlist\n");
3556 exit(1);
3557 }
3558
3559 /* add current environment into the list */
3560 for (wrk = environ; *wrk != NULL; wrk++) {
3561 (void) envlist_setenv(envlist, *wrk);
3562 }
3563
3564 /* Read the stack limit from the kernel. If it's "unlimited",
3565 then we can do little else besides use the default. */
3566 {
3567 struct rlimit lim;
3568 if (getrlimit(RLIMIT_STACK, &lim) == 0
3569 && lim.rlim_cur != RLIM_INFINITY
3570 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3571 guest_stack_size = lim.rlim_cur;
3572 }
3573 }
3574
3575 cpu_model = NULL;
3576 #if defined(cpudef_setup)
3577 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3578 #endif
3579
3580 optind = parse_args(argc, argv);
3581
3582 /* Zero out regs */
3583 memset(regs, 0, sizeof(struct target_pt_regs));
3584
3585 /* Zero out image_info */
3586 memset(info, 0, sizeof(struct image_info));
3587
3588 memset(&bprm, 0, sizeof (bprm));
3589
3590 /* Scan interp_prefix dir for replacement files. */
3591 init_paths(interp_prefix);
3592
3593 if (cpu_model == NULL) {
3594 #if defined(TARGET_I386)
3595 #ifdef TARGET_X86_64
3596 cpu_model = "qemu64";
3597 #else
3598 cpu_model = "qemu32";
3599 #endif
3600 #elif defined(TARGET_ARM)
3601 cpu_model = "any";
3602 #elif defined(TARGET_UNICORE32)
3603 cpu_model = "any";
3604 #elif defined(TARGET_M68K)
3605 cpu_model = "any";
3606 #elif defined(TARGET_SPARC)
3607 #ifdef TARGET_SPARC64
3608 cpu_model = "TI UltraSparc II";
3609 #else
3610 cpu_model = "Fujitsu MB86904";
3611 #endif
3612 #elif defined(TARGET_MIPS)
3613 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3614 cpu_model = "20Kc";
3615 #else
3616 cpu_model = "24Kf";
3617 #endif
3618 #elif defined TARGET_OPENRISC
3619 cpu_model = "or1200";
3620 #elif defined(TARGET_PPC)
3621 #ifdef TARGET_PPC64
3622 cpu_model = "970fx";
3623 #else
3624 cpu_model = "750";
3625 #endif
3626 #else
3627 cpu_model = "any";
3628 #endif
3629 }
3630 tcg_exec_init(0);
3631 cpu_exec_init_all();
3632 /* NOTE: we need to init the CPU at this stage to get
3633 qemu_host_page_size */
3634 env = cpu_init(cpu_model);
3635 if (!env) {
3636 fprintf(stderr, "Unable to find CPU definition\n");
3637 exit(1);
3638 }
3639 #if defined(TARGET_SPARC) || defined(TARGET_PPC)
3640 cpu_reset(ENV_GET_CPU(env));
3641 #endif
3642
3643 thread_env = env;
3644
3645 if (getenv("QEMU_STRACE")) {
3646 do_strace = 1;
3647 }
3648
3649 target_environ = envlist_to_environ(envlist, NULL);
3650 envlist_free(envlist);
3651
3652 #if defined(CONFIG_USE_GUEST_BASE)
3653 /*
3654 * Now that page sizes are configured in cpu_init() we can do
3655 * proper page alignment for guest_base.
3656 */
3657 guest_base = HOST_PAGE_ALIGN(guest_base);
3658
3659 if (reserved_va || have_guest_base) {
3660 guest_base = init_guest_space(guest_base, reserved_va, 0,
3661 have_guest_base);
3662 if (guest_base == (unsigned long)-1) {
3663 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3664 "space for use as guest address space (check your virtual "
3665 "memory ulimit setting or reserve less using -R option)\n",
3666 reserved_va);
3667 exit(1);
3668 }
3669
3670 if (reserved_va) {
3671 mmap_next_start = reserved_va;
3672 }
3673 }
3674 #endif /* CONFIG_USE_GUEST_BASE */
3675
3676 /*
3677 * Read in mmap_min_addr kernel parameter. This value is used
3678 * When loading the ELF image to determine whether guest_base
3679 * is needed. It is also used in mmap_find_vma.
3680 */
3681 {
3682 FILE *fp;
3683
3684 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3685 unsigned long tmp;
3686 if (fscanf(fp, "%lu", &tmp) == 1) {
3687 mmap_min_addr = tmp;
3688 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3689 }
3690 fclose(fp);
3691 }
3692 }
3693
3694 /*
3695 * Prepare copy of argv vector for target.
3696 */
3697 target_argc = argc - optind;
3698 target_argv = calloc(target_argc + 1, sizeof (char *));
3699 if (target_argv == NULL) {
3700 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3701 exit(1);
3702 }
3703
3704 /*
3705 * If argv0 is specified (using '-0' switch) we replace
3706 * argv[0] pointer with the given one.
3707 */
3708 i = 0;
3709 if (argv0 != NULL) {
3710 target_argv[i++] = strdup(argv0);
3711 }
3712 for (; i < target_argc; i++) {
3713 target_argv[i] = strdup(argv[optind + i]);
3714 }
3715 target_argv[target_argc] = NULL;
3716
3717 ts = g_malloc0 (sizeof(TaskState));
3718 init_task_state(ts);
3719 /* build Task State */
3720 ts->info = info;
3721 ts->bprm = &bprm;
3722 env->opaque = ts;
3723 task_settid(ts);
3724
3725 ret = loader_exec(filename, target_argv, target_environ, regs,
3726 info, &bprm);
3727 if (ret != 0) {
3728 printf("Error while loading %s: %s\n", filename, strerror(-ret));
3729 _exit(1);
3730 }
3731
3732 for (wrk = target_environ; *wrk; wrk++) {
3733 free(*wrk);
3734 }
3735
3736 free(target_environ);
3737
3738 if (qemu_log_enabled()) {
3739 #if defined(CONFIG_USE_GUEST_BASE)
3740 qemu_log("guest_base 0x%lx\n", guest_base);
3741 #endif
3742 log_page_dump();
3743
3744 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
3745 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
3746 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
3747 info->start_code);
3748 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
3749 info->start_data);
3750 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
3751 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
3752 info->start_stack);
3753 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
3754 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
3755 }
3756
3757 target_set_brk(info->brk);
3758 syscall_init();
3759 signal_init();
3760
3761 #if defined(CONFIG_USE_GUEST_BASE)
3762 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
3763 generating the prologue until now so that the prologue can take
3764 the real value of GUEST_BASE into account. */
3765 tcg_prologue_init(&tcg_ctx);
3766 #endif
3767
3768 #if defined(TARGET_I386)
3769 cpu_x86_set_cpl(env, 3);
3770
3771 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
3772 env->hflags |= HF_PE_MASK;
3773 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
3774 env->cr[4] |= CR4_OSFXSR_MASK;
3775 env->hflags |= HF_OSFXSR_MASK;
3776 }
3777 #ifndef TARGET_ABI32
3778 /* enable 64 bit mode if possible */
3779 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
3780 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
3781 exit(1);
3782 }
3783 env->cr[4] |= CR4_PAE_MASK;
3784 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
3785 env->hflags |= HF_LMA_MASK;
3786 #endif
3787
3788 /* flags setup : we activate the IRQs by default as in user mode */
3789 env->eflags |= IF_MASK;
3790
3791 /* linux register setup */
3792 #ifndef TARGET_ABI32
3793 env->regs[R_EAX] = regs->rax;
3794 env->regs[R_EBX] = regs->rbx;
3795 env->regs[R_ECX] = regs->rcx;
3796 env->regs[R_EDX] = regs->rdx;
3797 env->regs[R_ESI] = regs->rsi;
3798 env->regs[R_EDI] = regs->rdi;
3799 env->regs[R_EBP] = regs->rbp;
3800 env->regs[R_ESP] = regs->rsp;
3801 env->eip = regs->rip;
3802 #else
3803 env->regs[R_EAX] = regs->eax;
3804 env->regs[R_EBX] = regs->ebx;
3805 env->regs[R_ECX] = regs->ecx;
3806 env->regs[R_EDX] = regs->edx;
3807 env->regs[R_ESI] = regs->esi;
3808 env->regs[R_EDI] = regs->edi;
3809 env->regs[R_EBP] = regs->ebp;
3810 env->regs[R_ESP] = regs->esp;
3811 env->eip = regs->eip;
3812 #endif
3813
3814 /* linux interrupt setup */
3815 #ifndef TARGET_ABI32
3816 env->idt.limit = 511;
3817 #else
3818 env->idt.limit = 255;
3819 #endif
3820 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
3821 PROT_READ|PROT_WRITE,
3822 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3823 idt_table = g2h(env->idt.base);
3824 set_idt(0, 0);
3825 set_idt(1, 0);
3826 set_idt(2, 0);
3827 set_idt(3, 3);
3828 set_idt(4, 3);
3829 set_idt(5, 0);
3830 set_idt(6, 0);
3831 set_idt(7, 0);
3832 set_idt(8, 0);
3833 set_idt(9, 0);
3834 set_idt(10, 0);
3835 set_idt(11, 0);
3836 set_idt(12, 0);
3837 set_idt(13, 0);
3838 set_idt(14, 0);
3839 set_idt(15, 0);
3840 set_idt(16, 0);
3841 set_idt(17, 0);
3842 set_idt(18, 0);
3843 set_idt(19, 0);
3844 set_idt(0x80, 3);
3845
3846 /* linux segment setup */
3847 {
3848 uint64_t *gdt_table;
3849 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
3850 PROT_READ|PROT_WRITE,
3851 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
3852 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
3853 gdt_table = g2h(env->gdt.base);
3854 #ifdef TARGET_ABI32
3855 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3856 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3857 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3858 #else
3859 /* 64 bit code segment */
3860 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
3861 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3862 DESC_L_MASK |
3863 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
3864 #endif
3865 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
3866 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
3867 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
3868 }
3869 cpu_x86_load_seg(env, R_CS, __USER_CS);
3870 cpu_x86_load_seg(env, R_SS, __USER_DS);
3871 #ifdef TARGET_ABI32
3872 cpu_x86_load_seg(env, R_DS, __USER_DS);
3873 cpu_x86_load_seg(env, R_ES, __USER_DS);
3874 cpu_x86_load_seg(env, R_FS, __USER_DS);
3875 cpu_x86_load_seg(env, R_GS, __USER_DS);
3876 /* This hack makes Wine work... */
3877 env->segs[R_FS].selector = 0;
3878 #else
3879 cpu_x86_load_seg(env, R_DS, 0);
3880 cpu_x86_load_seg(env, R_ES, 0);
3881 cpu_x86_load_seg(env, R_FS, 0);
3882 cpu_x86_load_seg(env, R_GS, 0);
3883 #endif
3884 #elif defined(TARGET_ARM)
3885 {
3886 int i;
3887 cpsr_write(env, regs->uregs[16], 0xffffffff);
3888 for(i = 0; i < 16; i++) {
3889 env->regs[i] = regs->uregs[i];
3890 }
3891 /* Enable BE8. */
3892 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
3893 && (info->elf_flags & EF_ARM_BE8)) {
3894 env->bswap_code = 1;
3895 }
3896 }
3897 #elif defined(TARGET_UNICORE32)
3898 {
3899 int i;
3900 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
3901 for (i = 0; i < 32; i++) {
3902 env->regs[i] = regs->uregs[i];
3903 }
3904 }
3905 #elif defined(TARGET_SPARC)
3906 {
3907 int i;
3908 env->pc = regs->pc;
3909 env->npc = regs->npc;
3910 env->y = regs->y;
3911 for(i = 0; i < 8; i++)
3912 env->gregs[i] = regs->u_regs[i];
3913 for(i = 0; i < 8; i++)
3914 env->regwptr[i] = regs->u_regs[i + 8];
3915 }
3916 #elif defined(TARGET_PPC)
3917 {
3918 int i;
3919
3920 #if defined(TARGET_PPC64)
3921 #if defined(TARGET_ABI32)
3922 env->msr &= ~((target_ulong)1 << MSR_SF);
3923 #else
3924 env->msr |= (target_ulong)1 << MSR_SF;
3925 #endif
3926 #endif
3927 env->nip = regs->nip;
3928 for(i = 0; i < 32; i++) {
3929 env->gpr[i] = regs->gpr[i];
3930 }
3931 }
3932 #elif defined(TARGET_M68K)
3933 {
3934 env->pc = regs->pc;
3935 env->dregs[0] = regs->d0;
3936 env->dregs[1] = regs->d1;
3937 env->dregs[2] = regs->d2;
3938 env->dregs[3] = regs->d3;
3939 env->dregs[4] = regs->d4;
3940 env->dregs[5] = regs->d5;
3941 env->dregs[6] = regs->d6;
3942 env->dregs[7] = regs->d7;
3943 env->aregs[0] = regs->a0;
3944 env->aregs[1] = regs->a1;
3945 env->aregs[2] = regs->a2;
3946 env->aregs[3] = regs->a3;
3947 env->aregs[4] = regs->a4;
3948 env->aregs[5] = regs->a5;
3949 env->aregs[6] = regs->a6;
3950 env->aregs[7] = regs->usp;
3951 env->sr = regs->sr;
3952 ts->sim_syscalls = 1;
3953 }
3954 #elif defined(TARGET_MICROBLAZE)
3955 {
3956 env->regs[0] = regs->r0;
3957 env->regs[1] = regs->r1;
3958 env->regs[2] = regs->r2;
3959 env->regs[3] = regs->r3;
3960 env->regs[4] = regs->r4;
3961 env->regs[5] = regs->r5;
3962 env->regs[6] = regs->r6;
3963 env->regs[7] = regs->r7;
3964 env->regs[8] = regs->r8;
3965 env->regs[9] = regs->r9;
3966 env->regs[10] = regs->r10;
3967 env->regs[11] = regs->r11;
3968 env->regs[12] = regs->r12;
3969 env->regs[13] = regs->r13;
3970 env->regs[14] = regs->r14;
3971 env->regs[15] = regs->r15;
3972 env->regs[16] = regs->r16;
3973 env->regs[17] = regs->r17;
3974 env->regs[18] = regs->r18;
3975 env->regs[19] = regs->r19;
3976 env->regs[20] = regs->r20;
3977 env->regs[21] = regs->r21;
3978 env->regs[22] = regs->r22;
3979 env->regs[23] = regs->r23;
3980 env->regs[24] = regs->r24;
3981 env->regs[25] = regs->r25;
3982 env->regs[26] = regs->r26;
3983 env->regs[27] = regs->r27;
3984 env->regs[28] = regs->r28;
3985 env->regs[29] = regs->r29;
3986 env->regs[30] = regs->r30;
3987 env->regs[31] = regs->r31;
3988 env->sregs[SR_PC] = regs->pc;
3989 }
3990 #elif defined(TARGET_MIPS)
3991 {
3992 int i;
3993
3994 for(i = 0; i < 32; i++) {
3995 env->active_tc.gpr[i] = regs->regs[i];
3996 }
3997 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
3998 if (regs->cp0_epc & 1) {
3999 env->hflags |= MIPS_HFLAG_M16;
4000 }
4001 }
4002 #elif defined(TARGET_OPENRISC)
4003 {
4004 int i;
4005
4006 for (i = 0; i < 32; i++) {
4007 env->gpr[i] = regs->gpr[i];
4008 }
4009
4010 env->sr = regs->sr;
4011 env->pc = regs->pc;
4012 }
4013 #elif defined(TARGET_SH4)
4014 {
4015 int i;
4016
4017 for(i = 0; i < 16; i++) {
4018 env->gregs[i] = regs->regs[i];
4019 }
4020 env->pc = regs->pc;
4021 }
4022 #elif defined(TARGET_ALPHA)
4023 {
4024 int i;
4025
4026 for(i = 0; i < 28; i++) {
4027 env->ir[i] = ((abi_ulong *)regs)[i];
4028 }
4029 env->ir[IR_SP] = regs->usp;
4030 env->pc = regs->pc;
4031 }
4032 #elif defined(TARGET_CRIS)
4033 {
4034 env->regs[0] = regs->r0;
4035 env->regs[1] = regs->r1;
4036 env->regs[2] = regs->r2;
4037 env->regs[3] = regs->r3;
4038 env->regs[4] = regs->r4;
4039 env->regs[5] = regs->r5;
4040 env->regs[6] = regs->r6;
4041 env->regs[7] = regs->r7;
4042 env->regs[8] = regs->r8;
4043 env->regs[9] = regs->r9;
4044 env->regs[10] = regs->r10;
4045 env->regs[11] = regs->r11;
4046 env->regs[12] = regs->r12;
4047 env->regs[13] = regs->r13;
4048 env->regs[14] = info->start_stack;
4049 env->regs[15] = regs->acr;
4050 env->pc = regs->erp;
4051 }
4052 #elif defined(TARGET_S390X)
4053 {
4054 int i;
4055 for (i = 0; i < 16; i++) {
4056 env->regs[i] = regs->gprs[i];
4057 }
4058 env->psw.mask = regs->psw.mask;
4059 env->psw.addr = regs->psw.addr;
4060 }
4061 #else
4062 #error unsupported target CPU
4063 #endif
4064
4065 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4066 ts->stack_base = info->start_stack;
4067 ts->heap_base = info->brk;
4068 /* This will be filled in on the first SYS_HEAPINFO call. */
4069 ts->heap_limit = 0;
4070 #endif
4071
4072 if (gdbstub_port) {
4073 if (gdbserver_start(gdbstub_port) < 0) {
4074 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4075 gdbstub_port);
4076 exit(1);
4077 }
4078 gdb_handlesig(env, 0);
4079 }
4080 cpu_loop(env);
4081 /* never exits */
4082 return 0;
4083 }
Qemu copy for testing