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Fix Sparc/Linux host breakage by df70204db53e3611af986f434e74a882bce190ca
[qemu.git] / linux-user / main.c
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27
28 #include "qemu.h"
29 #include "qemu-common.h"
30 #include "cache-utils.h"
31 /* For tb_lock */
32 #include "exec-all.h"
33
34
35 #include "envlist.h"
36
37 #define DEBUG_LOGFILE "/tmp/qemu.log"
38
39 char *exec_path;
40
41 int singlestep;
42 #if defined(CONFIG_USE_GUEST_BASE)
43 unsigned long mmap_min_addr;
44 unsigned long guest_base;
45 int have_guest_base;
46 #endif
47
48 static const char *interp_prefix = CONFIG_QEMU_PREFIX;
49 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
50
51 /* for recent libc, we add these dummy symbols which are not declared
52 when generating a linked object (bug in ld ?) */
53 #if ((__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 3)) && \
54 !defined(CONFIG_STATIC)) && !defined(CONFIG_USER_PIE)
55 asm(".globl __preinit_array_start\n"
56 ".globl __preinit_array_end\n"
57 ".globl __init_array_start\n"
58 ".globl __init_array_end\n"
59 ".globl __fini_array_start\n"
60 ".globl __fini_array_end\n"
61 ".section \".rodata\"\n"
62 "__preinit_array_start:\n"
63 "__preinit_array_end:\n"
64 "__init_array_start:\n"
65 "__init_array_end:\n"
66 "__fini_array_start:\n"
67 "__fini_array_end:\n"
68 ".long 0\n"
69 ".previous\n");
70 #endif
71
72 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
73 we allocate a bigger stack. Need a better solution, for example
74 by remapping the process stack directly at the right place */
75 unsigned long x86_stack_size = 512 * 1024;
76
77 void gemu_log(const char *fmt, ...)
78 {
79 va_list ap;
80
81 va_start(ap, fmt);
82 vfprintf(stderr, fmt, ap);
83 va_end(ap);
84 }
85
86 #if defined(TARGET_I386)
87 int cpu_get_pic_interrupt(CPUState *env)
88 {
89 return -1;
90 }
91 #endif
92
93 /* timers for rdtsc */
94
95 #if 0
96
97 static uint64_t emu_time;
98
99 int64_t cpu_get_real_ticks(void)
100 {
101 return emu_time++;
102 }
103
104 #endif
105
106 #if defined(CONFIG_USE_NPTL)
107 /***********************************************************/
108 /* Helper routines for implementing atomic operations. */
109
110 /* To implement exclusive operations we force all cpus to syncronise.
111 We don't require a full sync, only that no cpus are executing guest code.
112 The alternative is to map target atomic ops onto host equivalents,
113 which requires quite a lot of per host/target work. */
114 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
115 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
116 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
117 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
118 static int pending_cpus;
119
120 /* Make sure everything is in a consistent state for calling fork(). */
121 void fork_start(void)
122 {
123 mmap_fork_start();
124 pthread_mutex_lock(&tb_lock);
125 pthread_mutex_lock(&exclusive_lock);
126 }
127
128 void fork_end(int child)
129 {
130 if (child) {
131 /* Child processes created by fork() only have a single thread.
132 Discard information about the parent threads. */
133 first_cpu = thread_env;
134 thread_env->next_cpu = NULL;
135 pending_cpus = 0;
136 pthread_mutex_init(&exclusive_lock, NULL);
137 pthread_mutex_init(&cpu_list_mutex, NULL);
138 pthread_cond_init(&exclusive_cond, NULL);
139 pthread_cond_init(&exclusive_resume, NULL);
140 pthread_mutex_init(&tb_lock, NULL);
141 gdbserver_fork(thread_env);
142 } else {
143 pthread_mutex_unlock(&exclusive_lock);
144 pthread_mutex_unlock(&tb_lock);
145 }
146 mmap_fork_end(child);
147 }
148
149 /* Wait for pending exclusive operations to complete. The exclusive lock
150 must be held. */
151 static inline void exclusive_idle(void)
152 {
153 while (pending_cpus) {
154 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
155 }
156 }
157
158 /* Start an exclusive operation.
159 Must only be called from outside cpu_arm_exec. */
160 static inline void start_exclusive(void)
161 {
162 CPUState *other;
163 pthread_mutex_lock(&exclusive_lock);
164 exclusive_idle();
165
166 pending_cpus = 1;
167 /* Make all other cpus stop executing. */
168 for (other = first_cpu; other; other = other->next_cpu) {
169 if (other->running) {
170 pending_cpus++;
171 cpu_exit(other);
172 }
173 }
174 if (pending_cpus > 1) {
175 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
176 }
177 }
178
179 /* Finish an exclusive operation. */
180 static inline void end_exclusive(void)
181 {
182 pending_cpus = 0;
183 pthread_cond_broadcast(&exclusive_resume);
184 pthread_mutex_unlock(&exclusive_lock);
185 }
186
187 /* Wait for exclusive ops to finish, and begin cpu execution. */
188 static inline void cpu_exec_start(CPUState *env)
189 {
190 pthread_mutex_lock(&exclusive_lock);
191 exclusive_idle();
192 env->running = 1;
193 pthread_mutex_unlock(&exclusive_lock);
194 }
195
196 /* Mark cpu as not executing, and release pending exclusive ops. */
197 static inline void cpu_exec_end(CPUState *env)
198 {
199 pthread_mutex_lock(&exclusive_lock);
200 env->running = 0;
201 if (pending_cpus > 1) {
202 pending_cpus--;
203 if (pending_cpus == 1) {
204 pthread_cond_signal(&exclusive_cond);
205 }
206 }
207 exclusive_idle();
208 pthread_mutex_unlock(&exclusive_lock);
209 }
210
211 void cpu_list_lock(void)
212 {
213 pthread_mutex_lock(&cpu_list_mutex);
214 }
215
216 void cpu_list_unlock(void)
217 {
218 pthread_mutex_unlock(&cpu_list_mutex);
219 }
220 #else /* if !CONFIG_USE_NPTL */
221 /* These are no-ops because we are not threadsafe. */
222 static inline void cpu_exec_start(CPUState *env)
223 {
224 }
225
226 static inline void cpu_exec_end(CPUState *env)
227 {
228 }
229
230 static inline void start_exclusive(void)
231 {
232 }
233
234 static inline void end_exclusive(void)
235 {
236 }
237
238 void fork_start(void)
239 {
240 }
241
242 void fork_end(int child)
243 {
244 if (child) {
245 gdbserver_fork(thread_env);
246 }
247 }
248
249 void cpu_list_lock(void)
250 {
251 }
252
253 void cpu_list_unlock(void)
254 {
255 }
256 #endif
257
258
259 #ifdef TARGET_I386
260 /***********************************************************/
261 /* CPUX86 core interface */
262
263 void cpu_smm_update(CPUState *env)
264 {
265 }
266
267 uint64_t cpu_get_tsc(CPUX86State *env)
268 {
269 return cpu_get_real_ticks();
270 }
271
272 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
273 int flags)
274 {
275 unsigned int e1, e2;
276 uint32_t *p;
277 e1 = (addr << 16) | (limit & 0xffff);
278 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
279 e2 |= flags;
280 p = ptr;
281 p[0] = tswap32(e1);
282 p[1] = tswap32(e2);
283 }
284
285 static uint64_t *idt_table;
286 #ifdef TARGET_X86_64
287 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
288 uint64_t addr, unsigned int sel)
289 {
290 uint32_t *p, e1, e2;
291 e1 = (addr & 0xffff) | (sel << 16);
292 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
293 p = ptr;
294 p[0] = tswap32(e1);
295 p[1] = tswap32(e2);
296 p[2] = tswap32(addr >> 32);
297 p[3] = 0;
298 }
299 /* only dpl matters as we do only user space emulation */
300 static void set_idt(int n, unsigned int dpl)
301 {
302 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
303 }
304 #else
305 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
306 uint32_t addr, unsigned int sel)
307 {
308 uint32_t *p, e1, e2;
309 e1 = (addr & 0xffff) | (sel << 16);
310 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
311 p = ptr;
312 p[0] = tswap32(e1);
313 p[1] = tswap32(e2);
314 }
315
316 /* only dpl matters as we do only user space emulation */
317 static void set_idt(int n, unsigned int dpl)
318 {
319 set_gate(idt_table + n, 0, dpl, 0, 0);
320 }
321 #endif
322
323 void cpu_loop(CPUX86State *env)
324 {
325 int trapnr;
326 abi_ulong pc;
327 target_siginfo_t info;
328
329 for(;;) {
330 trapnr = cpu_x86_exec(env);
331 switch(trapnr) {
332 case 0x80:
333 /* linux syscall from int $0x80 */
334 env->regs[R_EAX] = do_syscall(env,
335 env->regs[R_EAX],
336 env->regs[R_EBX],
337 env->regs[R_ECX],
338 env->regs[R_EDX],
339 env->regs[R_ESI],
340 env->regs[R_EDI],
341 env->regs[R_EBP]);
342 break;
343 #ifndef TARGET_ABI32
344 case EXCP_SYSCALL:
345 /* linux syscall from syscall intruction */
346 env->regs[R_EAX] = do_syscall(env,
347 env->regs[R_EAX],
348 env->regs[R_EDI],
349 env->regs[R_ESI],
350 env->regs[R_EDX],
351 env->regs[10],
352 env->regs[8],
353 env->regs[9]);
354 env->eip = env->exception_next_eip;
355 break;
356 #endif
357 case EXCP0B_NOSEG:
358 case EXCP0C_STACK:
359 info.si_signo = SIGBUS;
360 info.si_errno = 0;
361 info.si_code = TARGET_SI_KERNEL;
362 info._sifields._sigfault._addr = 0;
363 queue_signal(env, info.si_signo, &info);
364 break;
365 case EXCP0D_GPF:
366 /* XXX: potential problem if ABI32 */
367 #ifndef TARGET_X86_64
368 if (env->eflags & VM_MASK) {
369 handle_vm86_fault(env);
370 } else
371 #endif
372 {
373 info.si_signo = SIGSEGV;
374 info.si_errno = 0;
375 info.si_code = TARGET_SI_KERNEL;
376 info._sifields._sigfault._addr = 0;
377 queue_signal(env, info.si_signo, &info);
378 }
379 break;
380 case EXCP0E_PAGE:
381 info.si_signo = SIGSEGV;
382 info.si_errno = 0;
383 if (!(env->error_code & 1))
384 info.si_code = TARGET_SEGV_MAPERR;
385 else
386 info.si_code = TARGET_SEGV_ACCERR;
387 info._sifields._sigfault._addr = env->cr[2];
388 queue_signal(env, info.si_signo, &info);
389 break;
390 case EXCP00_DIVZ:
391 #ifndef TARGET_X86_64
392 if (env->eflags & VM_MASK) {
393 handle_vm86_trap(env, trapnr);
394 } else
395 #endif
396 {
397 /* division by zero */
398 info.si_signo = SIGFPE;
399 info.si_errno = 0;
400 info.si_code = TARGET_FPE_INTDIV;
401 info._sifields._sigfault._addr = env->eip;
402 queue_signal(env, info.si_signo, &info);
403 }
404 break;
405 case EXCP01_DB:
406 case EXCP03_INT3:
407 #ifndef TARGET_X86_64
408 if (env->eflags & VM_MASK) {
409 handle_vm86_trap(env, trapnr);
410 } else
411 #endif
412 {
413 info.si_signo = SIGTRAP;
414 info.si_errno = 0;
415 if (trapnr == EXCP01_DB) {
416 info.si_code = TARGET_TRAP_BRKPT;
417 info._sifields._sigfault._addr = env->eip;
418 } else {
419 info.si_code = TARGET_SI_KERNEL;
420 info._sifields._sigfault._addr = 0;
421 }
422 queue_signal(env, info.si_signo, &info);
423 }
424 break;
425 case EXCP04_INTO:
426 case EXCP05_BOUND:
427 #ifndef TARGET_X86_64
428 if (env->eflags & VM_MASK) {
429 handle_vm86_trap(env, trapnr);
430 } else
431 #endif
432 {
433 info.si_signo = SIGSEGV;
434 info.si_errno = 0;
435 info.si_code = TARGET_SI_KERNEL;
436 info._sifields._sigfault._addr = 0;
437 queue_signal(env, info.si_signo, &info);
438 }
439 break;
440 case EXCP06_ILLOP:
441 info.si_signo = SIGILL;
442 info.si_errno = 0;
443 info.si_code = TARGET_ILL_ILLOPN;
444 info._sifields._sigfault._addr = env->eip;
445 queue_signal(env, info.si_signo, &info);
446 break;
447 case EXCP_INTERRUPT:
448 /* just indicate that signals should be handled asap */
449 break;
450 case EXCP_DEBUG:
451 {
452 int sig;
453
454 sig = gdb_handlesig (env, TARGET_SIGTRAP);
455 if (sig)
456 {
457 info.si_signo = sig;
458 info.si_errno = 0;
459 info.si_code = TARGET_TRAP_BRKPT;
460 queue_signal(env, info.si_signo, &info);
461 }
462 }
463 break;
464 default:
465 pc = env->segs[R_CS].base + env->eip;
466 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
467 (long)pc, trapnr);
468 abort();
469 }
470 process_pending_signals(env);
471 }
472 }
473 #endif
474
475 #ifdef TARGET_ARM
476
477 static void arm_cache_flush(abi_ulong start, abi_ulong last)
478 {
479 abi_ulong addr, last1;
480
481 if (last < start)
482 return;
483 addr = start;
484 for(;;) {
485 last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
486 if (last1 > last)
487 last1 = last;
488 tb_invalidate_page_range(addr, last1 + 1);
489 if (last1 == last)
490 break;
491 addr = last1 + 1;
492 }
493 }
494
495 /* Handle a jump to the kernel code page. */
496 static int
497 do_kernel_trap(CPUARMState *env)
498 {
499 uint32_t addr;
500 uint32_t cpsr;
501 uint32_t val;
502
503 switch (env->regs[15]) {
504 case 0xffff0fa0: /* __kernel_memory_barrier */
505 /* ??? No-op. Will need to do better for SMP. */
506 break;
507 case 0xffff0fc0: /* __kernel_cmpxchg */
508 /* XXX: This only works between threads, not between processes.
509 It's probably possible to implement this with native host
510 operations. However things like ldrex/strex are much harder so
511 there's not much point trying. */
512 start_exclusive();
513 cpsr = cpsr_read(env);
514 addr = env->regs[2];
515 /* FIXME: This should SEGV if the access fails. */
516 if (get_user_u32(val, addr))
517 val = ~env->regs[0];
518 if (val == env->regs[0]) {
519 val = env->regs[1];
520 /* FIXME: Check for segfaults. */
521 put_user_u32(val, addr);
522 env->regs[0] = 0;
523 cpsr |= CPSR_C;
524 } else {
525 env->regs[0] = -1;
526 cpsr &= ~CPSR_C;
527 }
528 cpsr_write(env, cpsr, CPSR_C);
529 end_exclusive();
530 break;
531 case 0xffff0fe0: /* __kernel_get_tls */
532 env->regs[0] = env->cp15.c13_tls2;
533 break;
534 default:
535 return 1;
536 }
537 /* Jump back to the caller. */
538 addr = env->regs[14];
539 if (addr & 1) {
540 env->thumb = 1;
541 addr &= ~1;
542 }
543 env->regs[15] = addr;
544
545 return 0;
546 }
547
548 void cpu_loop(CPUARMState *env)
549 {
550 int trapnr;
551 unsigned int n, insn;
552 target_siginfo_t info;
553 uint32_t addr;
554
555 for(;;) {
556 cpu_exec_start(env);
557 trapnr = cpu_arm_exec(env);
558 cpu_exec_end(env);
559 switch(trapnr) {
560 case EXCP_UDEF:
561 {
562 TaskState *ts = env->opaque;
563 uint32_t opcode;
564 int rc;
565
566 /* we handle the FPU emulation here, as Linux */
567 /* we get the opcode */
568 /* FIXME - what to do if get_user() fails? */
569 get_user_u32(opcode, env->regs[15]);
570
571 rc = EmulateAll(opcode, &ts->fpa, env);
572 if (rc == 0) { /* illegal instruction */
573 info.si_signo = SIGILL;
574 info.si_errno = 0;
575 info.si_code = TARGET_ILL_ILLOPN;
576 info._sifields._sigfault._addr = env->regs[15];
577 queue_signal(env, info.si_signo, &info);
578 } else if (rc < 0) { /* FP exception */
579 int arm_fpe=0;
580
581 /* translate softfloat flags to FPSR flags */
582 if (-rc & float_flag_invalid)
583 arm_fpe |= BIT_IOC;
584 if (-rc & float_flag_divbyzero)
585 arm_fpe |= BIT_DZC;
586 if (-rc & float_flag_overflow)
587 arm_fpe |= BIT_OFC;
588 if (-rc & float_flag_underflow)
589 arm_fpe |= BIT_UFC;
590 if (-rc & float_flag_inexact)
591 arm_fpe |= BIT_IXC;
592
593 FPSR fpsr = ts->fpa.fpsr;
594 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
595
596 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
597 info.si_signo = SIGFPE;
598 info.si_errno = 0;
599
600 /* ordered by priority, least first */
601 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
602 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
603 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
604 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
605 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
606
607 info._sifields._sigfault._addr = env->regs[15];
608 queue_signal(env, info.si_signo, &info);
609 } else {
610 env->regs[15] += 4;
611 }
612
613 /* accumulate unenabled exceptions */
614 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
615 fpsr |= BIT_IXC;
616 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
617 fpsr |= BIT_UFC;
618 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
619 fpsr |= BIT_OFC;
620 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
621 fpsr |= BIT_DZC;
622 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
623 fpsr |= BIT_IOC;
624 ts->fpa.fpsr=fpsr;
625 } else { /* everything OK */
626 /* increment PC */
627 env->regs[15] += 4;
628 }
629 }
630 break;
631 case EXCP_SWI:
632 case EXCP_BKPT:
633 {
634 env->eabi = 1;
635 /* system call */
636 if (trapnr == EXCP_BKPT) {
637 if (env->thumb) {
638 /* FIXME - what to do if get_user() fails? */
639 get_user_u16(insn, env->regs[15]);
640 n = insn & 0xff;
641 env->regs[15] += 2;
642 } else {
643 /* FIXME - what to do if get_user() fails? */
644 get_user_u32(insn, env->regs[15]);
645 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
646 env->regs[15] += 4;
647 }
648 } else {
649 if (env->thumb) {
650 /* FIXME - what to do if get_user() fails? */
651 get_user_u16(insn, env->regs[15] - 2);
652 n = insn & 0xff;
653 } else {
654 /* FIXME - what to do if get_user() fails? */
655 get_user_u32(insn, env->regs[15] - 4);
656 n = insn & 0xffffff;
657 }
658 }
659
660 if (n == ARM_NR_cacheflush) {
661 arm_cache_flush(env->regs[0], env->regs[1]);
662 } else if (n == ARM_NR_semihosting
663 || n == ARM_NR_thumb_semihosting) {
664 env->regs[0] = do_arm_semihosting (env);
665 } else if (n == 0 || n >= ARM_SYSCALL_BASE
666 || (env->thumb && n == ARM_THUMB_SYSCALL)) {
667 /* linux syscall */
668 if (env->thumb || n == 0) {
669 n = env->regs[7];
670 } else {
671 n -= ARM_SYSCALL_BASE;
672 env->eabi = 0;
673 }
674 if ( n > ARM_NR_BASE) {
675 switch (n) {
676 case ARM_NR_cacheflush:
677 arm_cache_flush(env->regs[0], env->regs[1]);
678 break;
679 case ARM_NR_set_tls:
680 cpu_set_tls(env, env->regs[0]);
681 env->regs[0] = 0;
682 break;
683 default:
684 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
685 n);
686 env->regs[0] = -TARGET_ENOSYS;
687 break;
688 }
689 } else {
690 env->regs[0] = do_syscall(env,
691 n,
692 env->regs[0],
693 env->regs[1],
694 env->regs[2],
695 env->regs[3],
696 env->regs[4],
697 env->regs[5]);
698 }
699 } else {
700 goto error;
701 }
702 }
703 break;
704 case EXCP_INTERRUPT:
705 /* just indicate that signals should be handled asap */
706 break;
707 case EXCP_PREFETCH_ABORT:
708 addr = env->cp15.c6_insn;
709 goto do_segv;
710 case EXCP_DATA_ABORT:
711 addr = env->cp15.c6_data;
712 goto do_segv;
713 do_segv:
714 {
715 info.si_signo = SIGSEGV;
716 info.si_errno = 0;
717 /* XXX: check env->error_code */
718 info.si_code = TARGET_SEGV_MAPERR;
719 info._sifields._sigfault._addr = addr;
720 queue_signal(env, info.si_signo, &info);
721 }
722 break;
723 case EXCP_DEBUG:
724 {
725 int sig;
726
727 sig = gdb_handlesig (env, TARGET_SIGTRAP);
728 if (sig)
729 {
730 info.si_signo = sig;
731 info.si_errno = 0;
732 info.si_code = TARGET_TRAP_BRKPT;
733 queue_signal(env, info.si_signo, &info);
734 }
735 }
736 break;
737 case EXCP_KERNEL_TRAP:
738 if (do_kernel_trap(env))
739 goto error;
740 break;
741 default:
742 error:
743 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
744 trapnr);
745 cpu_dump_state(env, stderr, fprintf, 0);
746 abort();
747 }
748 process_pending_signals(env);
749 }
750 }
751
752 #endif
753
754 #ifdef TARGET_SPARC
755 #define SPARC64_STACK_BIAS 2047
756
757 //#define DEBUG_WIN
758
759 /* WARNING: dealing with register windows _is_ complicated. More info
760 can be found at http://www.sics.se/~psm/sparcstack.html */
761 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
762 {
763 index = (index + cwp * 16) % (16 * env->nwindows);
764 /* wrap handling : if cwp is on the last window, then we use the
765 registers 'after' the end */
766 if (index < 8 && env->cwp == env->nwindows - 1)
767 index += 16 * env->nwindows;
768 return index;
769 }
770
771 /* save the register window 'cwp1' */
772 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
773 {
774 unsigned int i;
775 abi_ulong sp_ptr;
776
777 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
778 #ifdef TARGET_SPARC64
779 if (sp_ptr & 3)
780 sp_ptr += SPARC64_STACK_BIAS;
781 #endif
782 #if defined(DEBUG_WIN)
783 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
784 sp_ptr, cwp1);
785 #endif
786 for(i = 0; i < 16; i++) {
787 /* FIXME - what to do if put_user() fails? */
788 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
789 sp_ptr += sizeof(abi_ulong);
790 }
791 }
792
793 static void save_window(CPUSPARCState *env)
794 {
795 #ifndef TARGET_SPARC64
796 unsigned int new_wim;
797 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
798 ((1LL << env->nwindows) - 1);
799 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
800 env->wim = new_wim;
801 #else
802 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
803 env->cansave++;
804 env->canrestore--;
805 #endif
806 }
807
808 static void restore_window(CPUSPARCState *env)
809 {
810 #ifndef TARGET_SPARC64
811 unsigned int new_wim;
812 #endif
813 unsigned int i, cwp1;
814 abi_ulong sp_ptr;
815
816 #ifndef TARGET_SPARC64
817 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
818 ((1LL << env->nwindows) - 1);
819 #endif
820
821 /* restore the invalid window */
822 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
823 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
824 #ifdef TARGET_SPARC64
825 if (sp_ptr & 3)
826 sp_ptr += SPARC64_STACK_BIAS;
827 #endif
828 #if defined(DEBUG_WIN)
829 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
830 sp_ptr, cwp1);
831 #endif
832 for(i = 0; i < 16; i++) {
833 /* FIXME - what to do if get_user() fails? */
834 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
835 sp_ptr += sizeof(abi_ulong);
836 }
837 #ifdef TARGET_SPARC64
838 env->canrestore++;
839 if (env->cleanwin < env->nwindows - 1)
840 env->cleanwin++;
841 env->cansave--;
842 #else
843 env->wim = new_wim;
844 #endif
845 }
846
847 static void flush_windows(CPUSPARCState *env)
848 {
849 int offset, cwp1;
850
851 offset = 1;
852 for(;;) {
853 /* if restore would invoke restore_window(), then we can stop */
854 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
855 #ifndef TARGET_SPARC64
856 if (env->wim & (1 << cwp1))
857 break;
858 #else
859 if (env->canrestore == 0)
860 break;
861 env->cansave++;
862 env->canrestore--;
863 #endif
864 save_window_offset(env, cwp1);
865 offset++;
866 }
867 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
868 #ifndef TARGET_SPARC64
869 /* set wim so that restore will reload the registers */
870 env->wim = 1 << cwp1;
871 #endif
872 #if defined(DEBUG_WIN)
873 printf("flush_windows: nb=%d\n", offset - 1);
874 #endif
875 }
876
877 void cpu_loop (CPUSPARCState *env)
878 {
879 int trapnr, ret;
880 target_siginfo_t info;
881
882 while (1) {
883 trapnr = cpu_sparc_exec (env);
884
885 switch (trapnr) {
886 #ifndef TARGET_SPARC64
887 case 0x88:
888 case 0x90:
889 #else
890 case 0x110:
891 case 0x16d:
892 #endif
893 ret = do_syscall (env, env->gregs[1],
894 env->regwptr[0], env->regwptr[1],
895 env->regwptr[2], env->regwptr[3],
896 env->regwptr[4], env->regwptr[5]);
897 if ((unsigned int)ret >= (unsigned int)(-515)) {
898 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
899 env->xcc |= PSR_CARRY;
900 #else
901 env->psr |= PSR_CARRY;
902 #endif
903 ret = -ret;
904 } else {
905 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
906 env->xcc &= ~PSR_CARRY;
907 #else
908 env->psr &= ~PSR_CARRY;
909 #endif
910 }
911 env->regwptr[0] = ret;
912 /* next instruction */
913 env->pc = env->npc;
914 env->npc = env->npc + 4;
915 break;
916 case 0x83: /* flush windows */
917 #ifdef TARGET_ABI32
918 case 0x103:
919 #endif
920 flush_windows(env);
921 /* next instruction */
922 env->pc = env->npc;
923 env->npc = env->npc + 4;
924 break;
925 #ifndef TARGET_SPARC64
926 case TT_WIN_OVF: /* window overflow */
927 save_window(env);
928 break;
929 case TT_WIN_UNF: /* window underflow */
930 restore_window(env);
931 break;
932 case TT_TFAULT:
933 case TT_DFAULT:
934 {
935 info.si_signo = SIGSEGV;
936 info.si_errno = 0;
937 /* XXX: check env->error_code */
938 info.si_code = TARGET_SEGV_MAPERR;
939 info._sifields._sigfault._addr = env->mmuregs[4];
940 queue_signal(env, info.si_signo, &info);
941 }
942 break;
943 #else
944 case TT_SPILL: /* window overflow */
945 save_window(env);
946 break;
947 case TT_FILL: /* window underflow */
948 restore_window(env);
949 break;
950 case TT_TFAULT:
951 case TT_DFAULT:
952 {
953 info.si_signo = SIGSEGV;
954 info.si_errno = 0;
955 /* XXX: check env->error_code */
956 info.si_code = TARGET_SEGV_MAPERR;
957 if (trapnr == TT_DFAULT)
958 info._sifields._sigfault._addr = env->dmmuregs[4];
959 else
960 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
961 queue_signal(env, info.si_signo, &info);
962 }
963 break;
964 #ifndef TARGET_ABI32
965 case 0x16e:
966 flush_windows(env);
967 sparc64_get_context(env);
968 break;
969 case 0x16f:
970 flush_windows(env);
971 sparc64_set_context(env);
972 break;
973 #endif
974 #endif
975 case EXCP_INTERRUPT:
976 /* just indicate that signals should be handled asap */
977 break;
978 case EXCP_DEBUG:
979 {
980 int sig;
981
982 sig = gdb_handlesig (env, TARGET_SIGTRAP);
983 if (sig)
984 {
985 info.si_signo = sig;
986 info.si_errno = 0;
987 info.si_code = TARGET_TRAP_BRKPT;
988 queue_signal(env, info.si_signo, &info);
989 }
990 }
991 break;
992 default:
993 printf ("Unhandled trap: 0x%x\n", trapnr);
994 cpu_dump_state(env, stderr, fprintf, 0);
995 exit (1);
996 }
997 process_pending_signals (env);
998 }
999 }
1000
1001 #endif
1002
1003 #ifdef TARGET_PPC
1004 static inline uint64_t cpu_ppc_get_tb (CPUState *env)
1005 {
1006 /* TO FIX */
1007 return 0;
1008 }
1009
1010 uint32_t cpu_ppc_load_tbl (CPUState *env)
1011 {
1012 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1013 }
1014
1015 uint32_t cpu_ppc_load_tbu (CPUState *env)
1016 {
1017 return cpu_ppc_get_tb(env) >> 32;
1018 }
1019
1020 uint32_t cpu_ppc_load_atbl (CPUState *env)
1021 {
1022 return cpu_ppc_get_tb(env) & 0xFFFFFFFF;
1023 }
1024
1025 uint32_t cpu_ppc_load_atbu (CPUState *env)
1026 {
1027 return cpu_ppc_get_tb(env) >> 32;
1028 }
1029
1030 uint32_t cpu_ppc601_load_rtcu (CPUState *env)
1031 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1032
1033 uint32_t cpu_ppc601_load_rtcl (CPUState *env)
1034 {
1035 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1036 }
1037
1038 /* XXX: to be fixed */
1039 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
1040 {
1041 return -1;
1042 }
1043
1044 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
1045 {
1046 return -1;
1047 }
1048
1049 #define EXCP_DUMP(env, fmt, ...) \
1050 do { \
1051 fprintf(stderr, fmt , ## __VA_ARGS__); \
1052 cpu_dump_state(env, stderr, fprintf, 0); \
1053 qemu_log(fmt, ## __VA_ARGS__); \
1054 if (logfile) \
1055 log_cpu_state(env, 0); \
1056 } while (0)
1057
1058 static int do_store_exclusive(CPUPPCState *env)
1059 {
1060 target_ulong addr;
1061 target_ulong page_addr;
1062 target_ulong val;
1063 int flags;
1064 int segv = 0;
1065
1066 addr = env->reserve_ea;
1067 page_addr = addr & TARGET_PAGE_MASK;
1068 start_exclusive();
1069 mmap_lock();
1070 flags = page_get_flags(page_addr);
1071 if ((flags & PAGE_READ) == 0) {
1072 segv = 1;
1073 } else {
1074 int reg = env->reserve_info & 0x1f;
1075 int size = (env->reserve_info >> 5) & 0xf;
1076 int stored = 0;
1077
1078 if (addr == env->reserve_addr) {
1079 switch (size) {
1080 case 1: segv = get_user_u8(val, addr); break;
1081 case 2: segv = get_user_u16(val, addr); break;
1082 case 4: segv = get_user_u32(val, addr); break;
1083 #if defined(TARGET_PPC64)
1084 case 8: segv = get_user_u64(val, addr); break;
1085 #endif
1086 default: abort();
1087 }
1088 if (!segv && val == env->reserve_val) {
1089 val = env->gpr[reg];
1090 switch (size) {
1091 case 1: segv = put_user_u8(val, addr); break;
1092 case 2: segv = put_user_u16(val, addr); break;
1093 case 4: segv = put_user_u32(val, addr); break;
1094 #if defined(TARGET_PPC64)
1095 case 8: segv = put_user_u64(val, addr); break;
1096 #endif
1097 default: abort();
1098 }
1099 if (!segv) {
1100 stored = 1;
1101 }
1102 }
1103 }
1104 env->crf[0] = (stored << 1) | xer_so;
1105 env->reserve_addr = (target_ulong)-1;
1106 }
1107 if (!segv) {
1108 env->nip += 4;
1109 }
1110 mmap_unlock();
1111 end_exclusive();
1112 return segv;
1113 }
1114
1115 void cpu_loop(CPUPPCState *env)
1116 {
1117 target_siginfo_t info;
1118 int trapnr;
1119 uint32_t ret;
1120
1121 for(;;) {
1122 cpu_exec_start(env);
1123 trapnr = cpu_ppc_exec(env);
1124 cpu_exec_end(env);
1125 switch(trapnr) {
1126 case POWERPC_EXCP_NONE:
1127 /* Just go on */
1128 break;
1129 case POWERPC_EXCP_CRITICAL: /* Critical input */
1130 cpu_abort(env, "Critical interrupt while in user mode. "
1131 "Aborting\n");
1132 break;
1133 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1134 cpu_abort(env, "Machine check exception while in user mode. "
1135 "Aborting\n");
1136 break;
1137 case POWERPC_EXCP_DSI: /* Data storage exception */
1138 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1139 env->spr[SPR_DAR]);
1140 /* XXX: check this. Seems bugged */
1141 switch (env->error_code & 0xFF000000) {
1142 case 0x40000000:
1143 info.si_signo = TARGET_SIGSEGV;
1144 info.si_errno = 0;
1145 info.si_code = TARGET_SEGV_MAPERR;
1146 break;
1147 case 0x04000000:
1148 info.si_signo = TARGET_SIGILL;
1149 info.si_errno = 0;
1150 info.si_code = TARGET_ILL_ILLADR;
1151 break;
1152 case 0x08000000:
1153 info.si_signo = TARGET_SIGSEGV;
1154 info.si_errno = 0;
1155 info.si_code = TARGET_SEGV_ACCERR;
1156 break;
1157 default:
1158 /* Let's send a regular segfault... */
1159 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1160 env->error_code);
1161 info.si_signo = TARGET_SIGSEGV;
1162 info.si_errno = 0;
1163 info.si_code = TARGET_SEGV_MAPERR;
1164 break;
1165 }
1166 info._sifields._sigfault._addr = env->nip;
1167 queue_signal(env, info.si_signo, &info);
1168 break;
1169 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1170 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1171 "\n", env->spr[SPR_SRR0]);
1172 /* XXX: check this */
1173 switch (env->error_code & 0xFF000000) {
1174 case 0x40000000:
1175 info.si_signo = TARGET_SIGSEGV;
1176 info.si_errno = 0;
1177 info.si_code = TARGET_SEGV_MAPERR;
1178 break;
1179 case 0x10000000:
1180 case 0x08000000:
1181 info.si_signo = TARGET_SIGSEGV;
1182 info.si_errno = 0;
1183 info.si_code = TARGET_SEGV_ACCERR;
1184 break;
1185 default:
1186 /* Let's send a regular segfault... */
1187 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1188 env->error_code);
1189 info.si_signo = TARGET_SIGSEGV;
1190 info.si_errno = 0;
1191 info.si_code = TARGET_SEGV_MAPERR;
1192 break;
1193 }
1194 info._sifields._sigfault._addr = env->nip - 4;
1195 queue_signal(env, info.si_signo, &info);
1196 break;
1197 case POWERPC_EXCP_EXTERNAL: /* External input */
1198 cpu_abort(env, "External interrupt while in user mode. "
1199 "Aborting\n");
1200 break;
1201 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1202 EXCP_DUMP(env, "Unaligned memory access\n");
1203 /* XXX: check this */
1204 info.si_signo = TARGET_SIGBUS;
1205 info.si_errno = 0;
1206 info.si_code = TARGET_BUS_ADRALN;
1207 info._sifields._sigfault._addr = env->nip - 4;
1208 queue_signal(env, info.si_signo, &info);
1209 break;
1210 case POWERPC_EXCP_PROGRAM: /* Program exception */
1211 /* XXX: check this */
1212 switch (env->error_code & ~0xF) {
1213 case POWERPC_EXCP_FP:
1214 EXCP_DUMP(env, "Floating point program exception\n");
1215 info.si_signo = TARGET_SIGFPE;
1216 info.si_errno = 0;
1217 switch (env->error_code & 0xF) {
1218 case POWERPC_EXCP_FP_OX:
1219 info.si_code = TARGET_FPE_FLTOVF;
1220 break;
1221 case POWERPC_EXCP_FP_UX:
1222 info.si_code = TARGET_FPE_FLTUND;
1223 break;
1224 case POWERPC_EXCP_FP_ZX:
1225 case POWERPC_EXCP_FP_VXZDZ:
1226 info.si_code = TARGET_FPE_FLTDIV;
1227 break;
1228 case POWERPC_EXCP_FP_XX:
1229 info.si_code = TARGET_FPE_FLTRES;
1230 break;
1231 case POWERPC_EXCP_FP_VXSOFT:
1232 info.si_code = TARGET_FPE_FLTINV;
1233 break;
1234 case POWERPC_EXCP_FP_VXSNAN:
1235 case POWERPC_EXCP_FP_VXISI:
1236 case POWERPC_EXCP_FP_VXIDI:
1237 case POWERPC_EXCP_FP_VXIMZ:
1238 case POWERPC_EXCP_FP_VXVC:
1239 case POWERPC_EXCP_FP_VXSQRT:
1240 case POWERPC_EXCP_FP_VXCVI:
1241 info.si_code = TARGET_FPE_FLTSUB;
1242 break;
1243 default:
1244 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1245 env->error_code);
1246 break;
1247 }
1248 break;
1249 case POWERPC_EXCP_INVAL:
1250 EXCP_DUMP(env, "Invalid instruction\n");
1251 info.si_signo = TARGET_SIGILL;
1252 info.si_errno = 0;
1253 switch (env->error_code & 0xF) {
1254 case POWERPC_EXCP_INVAL_INVAL:
1255 info.si_code = TARGET_ILL_ILLOPC;
1256 break;
1257 case POWERPC_EXCP_INVAL_LSWX:
1258 info.si_code = TARGET_ILL_ILLOPN;
1259 break;
1260 case POWERPC_EXCP_INVAL_SPR:
1261 info.si_code = TARGET_ILL_PRVREG;
1262 break;
1263 case POWERPC_EXCP_INVAL_FP:
1264 info.si_code = TARGET_ILL_COPROC;
1265 break;
1266 default:
1267 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1268 env->error_code & 0xF);
1269 info.si_code = TARGET_ILL_ILLADR;
1270 break;
1271 }
1272 break;
1273 case POWERPC_EXCP_PRIV:
1274 EXCP_DUMP(env, "Privilege violation\n");
1275 info.si_signo = TARGET_SIGILL;
1276 info.si_errno = 0;
1277 switch (env->error_code & 0xF) {
1278 case POWERPC_EXCP_PRIV_OPC:
1279 info.si_code = TARGET_ILL_PRVOPC;
1280 break;
1281 case POWERPC_EXCP_PRIV_REG:
1282 info.si_code = TARGET_ILL_PRVREG;
1283 break;
1284 default:
1285 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1286 env->error_code & 0xF);
1287 info.si_code = TARGET_ILL_PRVOPC;
1288 break;
1289 }
1290 break;
1291 case POWERPC_EXCP_TRAP:
1292 cpu_abort(env, "Tried to call a TRAP\n");
1293 break;
1294 default:
1295 /* Should not happen ! */
1296 cpu_abort(env, "Unknown program exception (%02x)\n",
1297 env->error_code);
1298 break;
1299 }
1300 info._sifields._sigfault._addr = env->nip - 4;
1301 queue_signal(env, info.si_signo, &info);
1302 break;
1303 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1304 EXCP_DUMP(env, "No floating point allowed\n");
1305 info.si_signo = TARGET_SIGILL;
1306 info.si_errno = 0;
1307 info.si_code = TARGET_ILL_COPROC;
1308 info._sifields._sigfault._addr = env->nip - 4;
1309 queue_signal(env, info.si_signo, &info);
1310 break;
1311 case POWERPC_EXCP_SYSCALL: /* System call exception */
1312 cpu_abort(env, "Syscall exception while in user mode. "
1313 "Aborting\n");
1314 break;
1315 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1316 EXCP_DUMP(env, "No APU instruction allowed\n");
1317 info.si_signo = TARGET_SIGILL;
1318 info.si_errno = 0;
1319 info.si_code = TARGET_ILL_COPROC;
1320 info._sifields._sigfault._addr = env->nip - 4;
1321 queue_signal(env, info.si_signo, &info);
1322 break;
1323 case POWERPC_EXCP_DECR: /* Decrementer exception */
1324 cpu_abort(env, "Decrementer interrupt while in user mode. "
1325 "Aborting\n");
1326 break;
1327 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1328 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1329 "Aborting\n");
1330 break;
1331 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1332 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1333 "Aborting\n");
1334 break;
1335 case POWERPC_EXCP_DTLB: /* Data TLB error */
1336 cpu_abort(env, "Data TLB exception while in user mode. "
1337 "Aborting\n");
1338 break;
1339 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1340 cpu_abort(env, "Instruction TLB exception while in user mode. "
1341 "Aborting\n");
1342 break;
1343 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1344 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1345 info.si_signo = TARGET_SIGILL;
1346 info.si_errno = 0;
1347 info.si_code = TARGET_ILL_COPROC;
1348 info._sifields._sigfault._addr = env->nip - 4;
1349 queue_signal(env, info.si_signo, &info);
1350 break;
1351 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1352 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1353 break;
1354 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1355 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1356 break;
1357 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1358 cpu_abort(env, "Performance monitor exception not handled\n");
1359 break;
1360 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1361 cpu_abort(env, "Doorbell interrupt while in user mode. "
1362 "Aborting\n");
1363 break;
1364 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1365 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1366 "Aborting\n");
1367 break;
1368 case POWERPC_EXCP_RESET: /* System reset exception */
1369 cpu_abort(env, "Reset interrupt while in user mode. "
1370 "Aborting\n");
1371 break;
1372 case POWERPC_EXCP_DSEG: /* Data segment exception */
1373 cpu_abort(env, "Data segment exception while in user mode. "
1374 "Aborting\n");
1375 break;
1376 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1377 cpu_abort(env, "Instruction segment exception "
1378 "while in user mode. Aborting\n");
1379 break;
1380 /* PowerPC 64 with hypervisor mode support */
1381 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1382 cpu_abort(env, "Hypervisor decrementer interrupt "
1383 "while in user mode. Aborting\n");
1384 break;
1385 case POWERPC_EXCP_TRACE: /* Trace exception */
1386 /* Nothing to do:
1387 * we use this exception to emulate step-by-step execution mode.
1388 */
1389 break;
1390 /* PowerPC 64 with hypervisor mode support */
1391 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1392 cpu_abort(env, "Hypervisor data storage exception "
1393 "while in user mode. Aborting\n");
1394 break;
1395 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1396 cpu_abort(env, "Hypervisor instruction storage exception "
1397 "while in user mode. Aborting\n");
1398 break;
1399 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1400 cpu_abort(env, "Hypervisor data segment exception "
1401 "while in user mode. Aborting\n");
1402 break;
1403 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1404 cpu_abort(env, "Hypervisor instruction segment exception "
1405 "while in user mode. Aborting\n");
1406 break;
1407 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1408 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1409 info.si_signo = TARGET_SIGILL;
1410 info.si_errno = 0;
1411 info.si_code = TARGET_ILL_COPROC;
1412 info._sifields._sigfault._addr = env->nip - 4;
1413 queue_signal(env, info.si_signo, &info);
1414 break;
1415 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1416 cpu_abort(env, "Programable interval timer interrupt "
1417 "while in user mode. Aborting\n");
1418 break;
1419 case POWERPC_EXCP_IO: /* IO error exception */
1420 cpu_abort(env, "IO error exception while in user mode. "
1421 "Aborting\n");
1422 break;
1423 case POWERPC_EXCP_RUNM: /* Run mode exception */
1424 cpu_abort(env, "Run mode exception while in user mode. "
1425 "Aborting\n");
1426 break;
1427 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1428 cpu_abort(env, "Emulation trap exception not handled\n");
1429 break;
1430 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1431 cpu_abort(env, "Instruction fetch TLB exception "
1432 "while in user-mode. Aborting");
1433 break;
1434 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1435 cpu_abort(env, "Data load TLB exception while in user-mode. "
1436 "Aborting");
1437 break;
1438 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1439 cpu_abort(env, "Data store TLB exception while in user-mode. "
1440 "Aborting");
1441 break;
1442 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1443 cpu_abort(env, "Floating-point assist exception not handled\n");
1444 break;
1445 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1446 cpu_abort(env, "Instruction address breakpoint exception "
1447 "not handled\n");
1448 break;
1449 case POWERPC_EXCP_SMI: /* System management interrupt */
1450 cpu_abort(env, "System management interrupt while in user mode. "
1451 "Aborting\n");
1452 break;
1453 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1454 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1455 "Aborting\n");
1456 break;
1457 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1458 cpu_abort(env, "Performance monitor exception not handled\n");
1459 break;
1460 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1461 cpu_abort(env, "Vector assist exception not handled\n");
1462 break;
1463 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1464 cpu_abort(env, "Soft patch exception not handled\n");
1465 break;
1466 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1467 cpu_abort(env, "Maintenance exception while in user mode. "
1468 "Aborting\n");
1469 break;
1470 case POWERPC_EXCP_STOP: /* stop translation */
1471 /* We did invalidate the instruction cache. Go on */
1472 break;
1473 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1474 /* We just stopped because of a branch. Go on */
1475 break;
1476 case POWERPC_EXCP_SYSCALL_USER:
1477 /* system call in user-mode emulation */
1478 /* WARNING:
1479 * PPC ABI uses overflow flag in cr0 to signal an error
1480 * in syscalls.
1481 */
1482 #if 0
1483 printf("syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n", env->gpr[0],
1484 env->gpr[3], env->gpr[4], env->gpr[5], env->gpr[6]);
1485 #endif
1486 env->crf[0] &= ~0x1;
1487 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1488 env->gpr[5], env->gpr[6], env->gpr[7],
1489 env->gpr[8]);
1490 if (ret == (uint32_t)(-TARGET_QEMU_ESIGRETURN)) {
1491 /* Returning from a successful sigreturn syscall.
1492 Avoid corrupting register state. */
1493 break;
1494 }
1495 if (ret > (uint32_t)(-515)) {
1496 env->crf[0] |= 0x1;
1497 ret = -ret;
1498 }
1499 env->gpr[3] = ret;
1500 #if 0
1501 printf("syscall returned 0x%08x (%d)\n", ret, ret);
1502 #endif
1503 break;
1504 case POWERPC_EXCP_STCX:
1505 if (do_store_exclusive(env)) {
1506 info.si_signo = TARGET_SIGSEGV;
1507 info.si_errno = 0;
1508 info.si_code = TARGET_SEGV_MAPERR;
1509 info._sifields._sigfault._addr = env->nip;
1510 queue_signal(env, info.si_signo, &info);
1511 }
1512 break;
1513 case EXCP_DEBUG:
1514 {
1515 int sig;
1516
1517 sig = gdb_handlesig(env, TARGET_SIGTRAP);
1518 if (sig) {
1519 info.si_signo = sig;
1520 info.si_errno = 0;
1521 info.si_code = TARGET_TRAP_BRKPT;
1522 queue_signal(env, info.si_signo, &info);
1523 }
1524 }
1525 break;
1526 case EXCP_INTERRUPT:
1527 /* just indicate that signals should be handled asap */
1528 break;
1529 default:
1530 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1531 break;
1532 }
1533 process_pending_signals(env);
1534 }
1535 }
1536 #endif
1537
1538 #ifdef TARGET_MIPS
1539
1540 #define MIPS_SYS(name, args) args,
1541
1542 static const uint8_t mips_syscall_args[] = {
1543 MIPS_SYS(sys_syscall , 0) /* 4000 */
1544 MIPS_SYS(sys_exit , 1)
1545 MIPS_SYS(sys_fork , 0)
1546 MIPS_SYS(sys_read , 3)
1547 MIPS_SYS(sys_write , 3)
1548 MIPS_SYS(sys_open , 3) /* 4005 */
1549 MIPS_SYS(sys_close , 1)
1550 MIPS_SYS(sys_waitpid , 3)
1551 MIPS_SYS(sys_creat , 2)
1552 MIPS_SYS(sys_link , 2)
1553 MIPS_SYS(sys_unlink , 1) /* 4010 */
1554 MIPS_SYS(sys_execve , 0)
1555 MIPS_SYS(sys_chdir , 1)
1556 MIPS_SYS(sys_time , 1)
1557 MIPS_SYS(sys_mknod , 3)
1558 MIPS_SYS(sys_chmod , 2) /* 4015 */
1559 MIPS_SYS(sys_lchown , 3)
1560 MIPS_SYS(sys_ni_syscall , 0)
1561 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1562 MIPS_SYS(sys_lseek , 3)
1563 MIPS_SYS(sys_getpid , 0) /* 4020 */
1564 MIPS_SYS(sys_mount , 5)
1565 MIPS_SYS(sys_oldumount , 1)
1566 MIPS_SYS(sys_setuid , 1)
1567 MIPS_SYS(sys_getuid , 0)
1568 MIPS_SYS(sys_stime , 1) /* 4025 */
1569 MIPS_SYS(sys_ptrace , 4)
1570 MIPS_SYS(sys_alarm , 1)
1571 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1572 MIPS_SYS(sys_pause , 0)
1573 MIPS_SYS(sys_utime , 2) /* 4030 */
1574 MIPS_SYS(sys_ni_syscall , 0)
1575 MIPS_SYS(sys_ni_syscall , 0)
1576 MIPS_SYS(sys_access , 2)
1577 MIPS_SYS(sys_nice , 1)
1578 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1579 MIPS_SYS(sys_sync , 0)
1580 MIPS_SYS(sys_kill , 2)
1581 MIPS_SYS(sys_rename , 2)
1582 MIPS_SYS(sys_mkdir , 2)
1583 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1584 MIPS_SYS(sys_dup , 1)
1585 MIPS_SYS(sys_pipe , 0)
1586 MIPS_SYS(sys_times , 1)
1587 MIPS_SYS(sys_ni_syscall , 0)
1588 MIPS_SYS(sys_brk , 1) /* 4045 */
1589 MIPS_SYS(sys_setgid , 1)
1590 MIPS_SYS(sys_getgid , 0)
1591 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1592 MIPS_SYS(sys_geteuid , 0)
1593 MIPS_SYS(sys_getegid , 0) /* 4050 */
1594 MIPS_SYS(sys_acct , 0)
1595 MIPS_SYS(sys_umount , 2)
1596 MIPS_SYS(sys_ni_syscall , 0)
1597 MIPS_SYS(sys_ioctl , 3)
1598 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1599 MIPS_SYS(sys_ni_syscall , 2)
1600 MIPS_SYS(sys_setpgid , 2)
1601 MIPS_SYS(sys_ni_syscall , 0)
1602 MIPS_SYS(sys_olduname , 1)
1603 MIPS_SYS(sys_umask , 1) /* 4060 */
1604 MIPS_SYS(sys_chroot , 1)
1605 MIPS_SYS(sys_ustat , 2)
1606 MIPS_SYS(sys_dup2 , 2)
1607 MIPS_SYS(sys_getppid , 0)
1608 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1609 MIPS_SYS(sys_setsid , 0)
1610 MIPS_SYS(sys_sigaction , 3)
1611 MIPS_SYS(sys_sgetmask , 0)
1612 MIPS_SYS(sys_ssetmask , 1)
1613 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1614 MIPS_SYS(sys_setregid , 2)
1615 MIPS_SYS(sys_sigsuspend , 0)
1616 MIPS_SYS(sys_sigpending , 1)
1617 MIPS_SYS(sys_sethostname , 2)
1618 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1619 MIPS_SYS(sys_getrlimit , 2)
1620 MIPS_SYS(sys_getrusage , 2)
1621 MIPS_SYS(sys_gettimeofday, 2)
1622 MIPS_SYS(sys_settimeofday, 2)
1623 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1624 MIPS_SYS(sys_setgroups , 2)
1625 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1626 MIPS_SYS(sys_symlink , 2)
1627 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1628 MIPS_SYS(sys_readlink , 3) /* 4085 */
1629 MIPS_SYS(sys_uselib , 1)
1630 MIPS_SYS(sys_swapon , 2)
1631 MIPS_SYS(sys_reboot , 3)
1632 MIPS_SYS(old_readdir , 3)
1633 MIPS_SYS(old_mmap , 6) /* 4090 */
1634 MIPS_SYS(sys_munmap , 2)
1635 MIPS_SYS(sys_truncate , 2)
1636 MIPS_SYS(sys_ftruncate , 2)
1637 MIPS_SYS(sys_fchmod , 2)
1638 MIPS_SYS(sys_fchown , 3) /* 4095 */
1639 MIPS_SYS(sys_getpriority , 2)
1640 MIPS_SYS(sys_setpriority , 3)
1641 MIPS_SYS(sys_ni_syscall , 0)
1642 MIPS_SYS(sys_statfs , 2)
1643 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1644 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1645 MIPS_SYS(sys_socketcall , 2)
1646 MIPS_SYS(sys_syslog , 3)
1647 MIPS_SYS(sys_setitimer , 3)
1648 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1649 MIPS_SYS(sys_newstat , 2)
1650 MIPS_SYS(sys_newlstat , 2)
1651 MIPS_SYS(sys_newfstat , 2)
1652 MIPS_SYS(sys_uname , 1)
1653 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1654 MIPS_SYS(sys_vhangup , 0)
1655 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1656 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1657 MIPS_SYS(sys_wait4 , 4)
1658 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1659 MIPS_SYS(sys_sysinfo , 1)
1660 MIPS_SYS(sys_ipc , 6)
1661 MIPS_SYS(sys_fsync , 1)
1662 MIPS_SYS(sys_sigreturn , 0)
1663 MIPS_SYS(sys_clone , 6) /* 4120 */
1664 MIPS_SYS(sys_setdomainname, 2)
1665 MIPS_SYS(sys_newuname , 1)
1666 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1667 MIPS_SYS(sys_adjtimex , 1)
1668 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1669 MIPS_SYS(sys_sigprocmask , 3)
1670 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1671 MIPS_SYS(sys_init_module , 5)
1672 MIPS_SYS(sys_delete_module, 1)
1673 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1674 MIPS_SYS(sys_quotactl , 0)
1675 MIPS_SYS(sys_getpgid , 1)
1676 MIPS_SYS(sys_fchdir , 1)
1677 MIPS_SYS(sys_bdflush , 2)
1678 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1679 MIPS_SYS(sys_personality , 1)
1680 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1681 MIPS_SYS(sys_setfsuid , 1)
1682 MIPS_SYS(sys_setfsgid , 1)
1683 MIPS_SYS(sys_llseek , 5) /* 4140 */
1684 MIPS_SYS(sys_getdents , 3)
1685 MIPS_SYS(sys_select , 5)
1686 MIPS_SYS(sys_flock , 2)
1687 MIPS_SYS(sys_msync , 3)
1688 MIPS_SYS(sys_readv , 3) /* 4145 */
1689 MIPS_SYS(sys_writev , 3)
1690 MIPS_SYS(sys_cacheflush , 3)
1691 MIPS_SYS(sys_cachectl , 3)
1692 MIPS_SYS(sys_sysmips , 4)
1693 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1694 MIPS_SYS(sys_getsid , 1)
1695 MIPS_SYS(sys_fdatasync , 0)
1696 MIPS_SYS(sys_sysctl , 1)
1697 MIPS_SYS(sys_mlock , 2)
1698 MIPS_SYS(sys_munlock , 2) /* 4155 */
1699 MIPS_SYS(sys_mlockall , 1)
1700 MIPS_SYS(sys_munlockall , 0)
1701 MIPS_SYS(sys_sched_setparam, 2)
1702 MIPS_SYS(sys_sched_getparam, 2)
1703 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1704 MIPS_SYS(sys_sched_getscheduler, 1)
1705 MIPS_SYS(sys_sched_yield , 0)
1706 MIPS_SYS(sys_sched_get_priority_max, 1)
1707 MIPS_SYS(sys_sched_get_priority_min, 1)
1708 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1709 MIPS_SYS(sys_nanosleep, 2)
1710 MIPS_SYS(sys_mremap , 4)
1711 MIPS_SYS(sys_accept , 3)
1712 MIPS_SYS(sys_bind , 3)
1713 MIPS_SYS(sys_connect , 3) /* 4170 */
1714 MIPS_SYS(sys_getpeername , 3)
1715 MIPS_SYS(sys_getsockname , 3)
1716 MIPS_SYS(sys_getsockopt , 5)
1717 MIPS_SYS(sys_listen , 2)
1718 MIPS_SYS(sys_recv , 4) /* 4175 */
1719 MIPS_SYS(sys_recvfrom , 6)
1720 MIPS_SYS(sys_recvmsg , 3)
1721 MIPS_SYS(sys_send , 4)
1722 MIPS_SYS(sys_sendmsg , 3)
1723 MIPS_SYS(sys_sendto , 6) /* 4180 */
1724 MIPS_SYS(sys_setsockopt , 5)
1725 MIPS_SYS(sys_shutdown , 2)
1726 MIPS_SYS(sys_socket , 3)
1727 MIPS_SYS(sys_socketpair , 4)
1728 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1729 MIPS_SYS(sys_getresuid , 3)
1730 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1731 MIPS_SYS(sys_poll , 3)
1732 MIPS_SYS(sys_nfsservctl , 3)
1733 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1734 MIPS_SYS(sys_getresgid , 3)
1735 MIPS_SYS(sys_prctl , 5)
1736 MIPS_SYS(sys_rt_sigreturn, 0)
1737 MIPS_SYS(sys_rt_sigaction, 4)
1738 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1739 MIPS_SYS(sys_rt_sigpending, 2)
1740 MIPS_SYS(sys_rt_sigtimedwait, 4)
1741 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1742 MIPS_SYS(sys_rt_sigsuspend, 0)
1743 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1744 MIPS_SYS(sys_pwrite64 , 6)
1745 MIPS_SYS(sys_chown , 3)
1746 MIPS_SYS(sys_getcwd , 2)
1747 MIPS_SYS(sys_capget , 2)
1748 MIPS_SYS(sys_capset , 2) /* 4205 */
1749 MIPS_SYS(sys_sigaltstack , 0)
1750 MIPS_SYS(sys_sendfile , 4)
1751 MIPS_SYS(sys_ni_syscall , 0)
1752 MIPS_SYS(sys_ni_syscall , 0)
1753 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1754 MIPS_SYS(sys_truncate64 , 4)
1755 MIPS_SYS(sys_ftruncate64 , 4)
1756 MIPS_SYS(sys_stat64 , 2)
1757 MIPS_SYS(sys_lstat64 , 2)
1758 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1759 MIPS_SYS(sys_pivot_root , 2)
1760 MIPS_SYS(sys_mincore , 3)
1761 MIPS_SYS(sys_madvise , 3)
1762 MIPS_SYS(sys_getdents64 , 3)
1763 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1764 MIPS_SYS(sys_ni_syscall , 0)
1765 MIPS_SYS(sys_gettid , 0)
1766 MIPS_SYS(sys_readahead , 5)
1767 MIPS_SYS(sys_setxattr , 5)
1768 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1769 MIPS_SYS(sys_fsetxattr , 5)
1770 MIPS_SYS(sys_getxattr , 4)
1771 MIPS_SYS(sys_lgetxattr , 4)
1772 MIPS_SYS(sys_fgetxattr , 4)
1773 MIPS_SYS(sys_listxattr , 3) /* 4230 */
1774 MIPS_SYS(sys_llistxattr , 3)
1775 MIPS_SYS(sys_flistxattr , 3)
1776 MIPS_SYS(sys_removexattr , 2)
1777 MIPS_SYS(sys_lremovexattr, 2)
1778 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
1779 MIPS_SYS(sys_tkill , 2)
1780 MIPS_SYS(sys_sendfile64 , 5)
1781 MIPS_SYS(sys_futex , 2)
1782 MIPS_SYS(sys_sched_setaffinity, 3)
1783 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
1784 MIPS_SYS(sys_io_setup , 2)
1785 MIPS_SYS(sys_io_destroy , 1)
1786 MIPS_SYS(sys_io_getevents, 5)
1787 MIPS_SYS(sys_io_submit , 3)
1788 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
1789 MIPS_SYS(sys_exit_group , 1)
1790 MIPS_SYS(sys_lookup_dcookie, 3)
1791 MIPS_SYS(sys_epoll_create, 1)
1792 MIPS_SYS(sys_epoll_ctl , 4)
1793 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
1794 MIPS_SYS(sys_remap_file_pages, 5)
1795 MIPS_SYS(sys_set_tid_address, 1)
1796 MIPS_SYS(sys_restart_syscall, 0)
1797 MIPS_SYS(sys_fadvise64_64, 7)
1798 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
1799 MIPS_SYS(sys_fstatfs64 , 2)
1800 MIPS_SYS(sys_timer_create, 3)
1801 MIPS_SYS(sys_timer_settime, 4)
1802 MIPS_SYS(sys_timer_gettime, 2)
1803 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
1804 MIPS_SYS(sys_timer_delete, 1)
1805 MIPS_SYS(sys_clock_settime, 2)
1806 MIPS_SYS(sys_clock_gettime, 2)
1807 MIPS_SYS(sys_clock_getres, 2)
1808 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
1809 MIPS_SYS(sys_tgkill , 3)
1810 MIPS_SYS(sys_utimes , 2)
1811 MIPS_SYS(sys_mbind , 4)
1812 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
1813 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
1814 MIPS_SYS(sys_mq_open , 4)
1815 MIPS_SYS(sys_mq_unlink , 1)
1816 MIPS_SYS(sys_mq_timedsend, 5)
1817 MIPS_SYS(sys_mq_timedreceive, 5)
1818 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
1819 MIPS_SYS(sys_mq_getsetattr, 3)
1820 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
1821 MIPS_SYS(sys_waitid , 4)
1822 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
1823 MIPS_SYS(sys_add_key , 5)
1824 MIPS_SYS(sys_request_key, 4)
1825 MIPS_SYS(sys_keyctl , 5)
1826 MIPS_SYS(sys_set_thread_area, 1)
1827 MIPS_SYS(sys_inotify_init, 0)
1828 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
1829 MIPS_SYS(sys_inotify_rm_watch, 2)
1830 MIPS_SYS(sys_migrate_pages, 4)
1831 MIPS_SYS(sys_openat, 4)
1832 MIPS_SYS(sys_mkdirat, 3)
1833 MIPS_SYS(sys_mknodat, 4) /* 4290 */
1834 MIPS_SYS(sys_fchownat, 5)
1835 MIPS_SYS(sys_futimesat, 3)
1836 MIPS_SYS(sys_fstatat64, 4)
1837 MIPS_SYS(sys_unlinkat, 3)
1838 MIPS_SYS(sys_renameat, 4) /* 4295 */
1839 MIPS_SYS(sys_linkat, 5)
1840 MIPS_SYS(sys_symlinkat, 3)
1841 MIPS_SYS(sys_readlinkat, 4)
1842 MIPS_SYS(sys_fchmodat, 3)
1843 MIPS_SYS(sys_faccessat, 3) /* 4300 */
1844 MIPS_SYS(sys_pselect6, 6)
1845 MIPS_SYS(sys_ppoll, 5)
1846 MIPS_SYS(sys_unshare, 1)
1847 MIPS_SYS(sys_splice, 4)
1848 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
1849 MIPS_SYS(sys_tee, 4)
1850 MIPS_SYS(sys_vmsplice, 4)
1851 MIPS_SYS(sys_move_pages, 6)
1852 MIPS_SYS(sys_set_robust_list, 2)
1853 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
1854 MIPS_SYS(sys_kexec_load, 4)
1855 MIPS_SYS(sys_getcpu, 3)
1856 MIPS_SYS(sys_epoll_pwait, 6)
1857 MIPS_SYS(sys_ioprio_set, 3)
1858 MIPS_SYS(sys_ioprio_get, 2)
1859 };
1860
1861 #undef MIPS_SYS
1862
1863 static int do_store_exclusive(CPUMIPSState *env)
1864 {
1865 target_ulong addr;
1866 target_ulong page_addr;
1867 target_ulong val;
1868 int flags;
1869 int segv = 0;
1870 int reg;
1871 int d;
1872
1873 addr = env->CP0_LLAddr;
1874 page_addr = addr & TARGET_PAGE_MASK;
1875 start_exclusive();
1876 mmap_lock();
1877 flags = page_get_flags(page_addr);
1878 if ((flags & PAGE_READ) == 0) {
1879 segv = 1;
1880 } else {
1881 reg = env->llreg & 0x1f;
1882 d = (env->llreg & 0x20) != 0;
1883 if (d) {
1884 segv = get_user_s64(val, addr);
1885 } else {
1886 segv = get_user_s32(val, addr);
1887 }
1888 if (!segv) {
1889 if (val != env->llval) {
1890 env->active_tc.gpr[reg] = 0;
1891 } else {
1892 if (d) {
1893 segv = put_user_u64(env->llnewval, addr);
1894 } else {
1895 segv = put_user_u32(env->llnewval, addr);
1896 }
1897 if (!segv) {
1898 env->active_tc.gpr[reg] = 1;
1899 }
1900 }
1901 }
1902 }
1903 env->CP0_LLAddr = -1;
1904 if (!segv) {
1905 env->active_tc.PC += 4;
1906 }
1907 mmap_unlock();
1908 end_exclusive();
1909 return segv;
1910 }
1911
1912 void cpu_loop(CPUMIPSState *env)
1913 {
1914 target_siginfo_t info;
1915 int trapnr, ret;
1916 unsigned int syscall_num;
1917
1918 for(;;) {
1919 cpu_exec_start(env);
1920 trapnr = cpu_mips_exec(env);
1921 cpu_exec_end(env);
1922 switch(trapnr) {
1923 case EXCP_SYSCALL:
1924 syscall_num = env->active_tc.gpr[2] - 4000;
1925 env->active_tc.PC += 4;
1926 if (syscall_num >= sizeof(mips_syscall_args)) {
1927 ret = -ENOSYS;
1928 } else {
1929 int nb_args;
1930 abi_ulong sp_reg;
1931 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
1932
1933 nb_args = mips_syscall_args[syscall_num];
1934 sp_reg = env->active_tc.gpr[29];
1935 switch (nb_args) {
1936 /* these arguments are taken from the stack */
1937 /* FIXME - what to do if get_user() fails? */
1938 case 8: get_user_ual(arg8, sp_reg + 28);
1939 case 7: get_user_ual(arg7, sp_reg + 24);
1940 case 6: get_user_ual(arg6, sp_reg + 20);
1941 case 5: get_user_ual(arg5, sp_reg + 16);
1942 default:
1943 break;
1944 }
1945 ret = do_syscall(env, env->active_tc.gpr[2],
1946 env->active_tc.gpr[4],
1947 env->active_tc.gpr[5],
1948 env->active_tc.gpr[6],
1949 env->active_tc.gpr[7],
1950 arg5, arg6/*, arg7, arg8*/);
1951 }
1952 if (ret == -TARGET_QEMU_ESIGRETURN) {
1953 /* Returning from a successful sigreturn syscall.
1954 Avoid clobbering register state. */
1955 break;
1956 }
1957 if ((unsigned int)ret >= (unsigned int)(-1133)) {
1958 env->active_tc.gpr[7] = 1; /* error flag */
1959 ret = -ret;
1960 } else {
1961 env->active_tc.gpr[7] = 0; /* error flag */
1962 }
1963 env->active_tc.gpr[2] = ret;
1964 break;
1965 case EXCP_TLBL:
1966 case EXCP_TLBS:
1967 info.si_signo = TARGET_SIGSEGV;
1968 info.si_errno = 0;
1969 /* XXX: check env->error_code */
1970 info.si_code = TARGET_SEGV_MAPERR;
1971 info._sifields._sigfault._addr = env->CP0_BadVAddr;
1972 queue_signal(env, info.si_signo, &info);
1973 break;
1974 case EXCP_CpU:
1975 case EXCP_RI:
1976 info.si_signo = TARGET_SIGILL;
1977 info.si_errno = 0;
1978 info.si_code = 0;
1979 queue_signal(env, info.si_signo, &info);
1980 break;
1981 case EXCP_INTERRUPT:
1982 /* just indicate that signals should be handled asap */
1983 break;
1984 case EXCP_DEBUG:
1985 {
1986 int sig;
1987
1988 sig = gdb_handlesig (env, TARGET_SIGTRAP);
1989 if (sig)
1990 {
1991 info.si_signo = sig;
1992 info.si_errno = 0;
1993 info.si_code = TARGET_TRAP_BRKPT;
1994 queue_signal(env, info.si_signo, &info);
1995 }
1996 }
1997 break;
1998 case EXCP_SC:
1999 if (do_store_exclusive(env)) {
2000 info.si_signo = TARGET_SIGSEGV;
2001 info.si_errno = 0;
2002 info.si_code = TARGET_SEGV_MAPERR;
2003 info._sifields._sigfault._addr = env->active_tc.PC;
2004 queue_signal(env, info.si_signo, &info);
2005 }
2006 break;
2007 default:
2008 // error:
2009 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2010 trapnr);
2011 cpu_dump_state(env, stderr, fprintf, 0);
2012 abort();
2013 }
2014 process_pending_signals(env);
2015 }
2016 }
2017 #endif
2018
2019 #ifdef TARGET_SH4
2020 void cpu_loop (CPUState *env)
2021 {
2022 int trapnr, ret;
2023 target_siginfo_t info;
2024
2025 while (1) {
2026 trapnr = cpu_sh4_exec (env);
2027
2028 switch (trapnr) {
2029 case 0x160:
2030 env->pc += 2;
2031 ret = do_syscall(env,
2032 env->gregs[3],
2033 env->gregs[4],
2034 env->gregs[5],
2035 env->gregs[6],
2036 env->gregs[7],
2037 env->gregs[0],
2038 env->gregs[1]);
2039 env->gregs[0] = ret;
2040 break;
2041 case EXCP_INTERRUPT:
2042 /* just indicate that signals should be handled asap */
2043 break;
2044 case EXCP_DEBUG:
2045 {
2046 int sig;
2047
2048 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2049 if (sig)
2050 {
2051 info.si_signo = sig;
2052 info.si_errno = 0;
2053 info.si_code = TARGET_TRAP_BRKPT;
2054 queue_signal(env, info.si_signo, &info);
2055 }
2056 }
2057 break;
2058 case 0xa0:
2059 case 0xc0:
2060 info.si_signo = SIGSEGV;
2061 info.si_errno = 0;
2062 info.si_code = TARGET_SEGV_MAPERR;
2063 info._sifields._sigfault._addr = env->tea;
2064 queue_signal(env, info.si_signo, &info);
2065 break;
2066
2067 default:
2068 printf ("Unhandled trap: 0x%x\n", trapnr);
2069 cpu_dump_state(env, stderr, fprintf, 0);
2070 exit (1);
2071 }
2072 process_pending_signals (env);
2073 }
2074 }
2075 #endif
2076
2077 #ifdef TARGET_CRIS
2078 void cpu_loop (CPUState *env)
2079 {
2080 int trapnr, ret;
2081 target_siginfo_t info;
2082
2083 while (1) {
2084 trapnr = cpu_cris_exec (env);
2085 switch (trapnr) {
2086 case 0xaa:
2087 {
2088 info.si_signo = SIGSEGV;
2089 info.si_errno = 0;
2090 /* XXX: check env->error_code */
2091 info.si_code = TARGET_SEGV_MAPERR;
2092 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2093 queue_signal(env, info.si_signo, &info);
2094 }
2095 break;
2096 case EXCP_INTERRUPT:
2097 /* just indicate that signals should be handled asap */
2098 break;
2099 case EXCP_BREAK:
2100 ret = do_syscall(env,
2101 env->regs[9],
2102 env->regs[10],
2103 env->regs[11],
2104 env->regs[12],
2105 env->regs[13],
2106 env->pregs[7],
2107 env->pregs[11]);
2108 env->regs[10] = ret;
2109 break;
2110 case EXCP_DEBUG:
2111 {
2112 int sig;
2113
2114 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2115 if (sig)
2116 {
2117 info.si_signo = sig;
2118 info.si_errno = 0;
2119 info.si_code = TARGET_TRAP_BRKPT;
2120 queue_signal(env, info.si_signo, &info);
2121 }
2122 }
2123 break;
2124 default:
2125 printf ("Unhandled trap: 0x%x\n", trapnr);
2126 cpu_dump_state(env, stderr, fprintf, 0);
2127 exit (1);
2128 }
2129 process_pending_signals (env);
2130 }
2131 }
2132 #endif
2133
2134 #ifdef TARGET_MICROBLAZE
2135 void cpu_loop (CPUState *env)
2136 {
2137 int trapnr, ret;
2138 target_siginfo_t info;
2139
2140 while (1) {
2141 trapnr = cpu_mb_exec (env);
2142 switch (trapnr) {
2143 case 0xaa:
2144 {
2145 info.si_signo = SIGSEGV;
2146 info.si_errno = 0;
2147 /* XXX: check env->error_code */
2148 info.si_code = TARGET_SEGV_MAPERR;
2149 info._sifields._sigfault._addr = 0;
2150 queue_signal(env, info.si_signo, &info);
2151 }
2152 break;
2153 case EXCP_INTERRUPT:
2154 /* just indicate that signals should be handled asap */
2155 break;
2156 case EXCP_BREAK:
2157 /* Return address is 4 bytes after the call. */
2158 env->regs[14] += 4;
2159 ret = do_syscall(env,
2160 env->regs[12],
2161 env->regs[5],
2162 env->regs[6],
2163 env->regs[7],
2164 env->regs[8],
2165 env->regs[9],
2166 env->regs[10]);
2167 env->regs[3] = ret;
2168 env->sregs[SR_PC] = env->regs[14];
2169 break;
2170 case EXCP_DEBUG:
2171 {
2172 int sig;
2173
2174 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2175 if (sig)
2176 {
2177 info.si_signo = sig;
2178 info.si_errno = 0;
2179 info.si_code = TARGET_TRAP_BRKPT;
2180 queue_signal(env, info.si_signo, &info);
2181 }
2182 }
2183 break;
2184 default:
2185 printf ("Unhandled trap: 0x%x\n", trapnr);
2186 cpu_dump_state(env, stderr, fprintf, 0);
2187 exit (1);
2188 }
2189 process_pending_signals (env);
2190 }
2191 }
2192 #endif
2193
2194 #ifdef TARGET_M68K
2195
2196 void cpu_loop(CPUM68KState *env)
2197 {
2198 int trapnr;
2199 unsigned int n;
2200 target_siginfo_t info;
2201 TaskState *ts = env->opaque;
2202
2203 for(;;) {
2204 trapnr = cpu_m68k_exec(env);
2205 switch(trapnr) {
2206 case EXCP_ILLEGAL:
2207 {
2208 if (ts->sim_syscalls) {
2209 uint16_t nr;
2210 nr = lduw(env->pc + 2);
2211 env->pc += 4;
2212 do_m68k_simcall(env, nr);
2213 } else {
2214 goto do_sigill;
2215 }
2216 }
2217 break;
2218 case EXCP_HALT_INSN:
2219 /* Semihosing syscall. */
2220 env->pc += 4;
2221 do_m68k_semihosting(env, env->dregs[0]);
2222 break;
2223 case EXCP_LINEA:
2224 case EXCP_LINEF:
2225 case EXCP_UNSUPPORTED:
2226 do_sigill:
2227 info.si_signo = SIGILL;
2228 info.si_errno = 0;
2229 info.si_code = TARGET_ILL_ILLOPN;
2230 info._sifields._sigfault._addr = env->pc;
2231 queue_signal(env, info.si_signo, &info);
2232 break;
2233 case EXCP_TRAP0:
2234 {
2235 ts->sim_syscalls = 0;
2236 n = env->dregs[0];
2237 env->pc += 2;
2238 env->dregs[0] = do_syscall(env,
2239 n,
2240 env->dregs[1],
2241 env->dregs[2],
2242 env->dregs[3],
2243 env->dregs[4],
2244 env->dregs[5],
2245 env->aregs[0]);
2246 }
2247 break;
2248 case EXCP_INTERRUPT:
2249 /* just indicate that signals should be handled asap */
2250 break;
2251 case EXCP_ACCESS:
2252 {
2253 info.si_signo = SIGSEGV;
2254 info.si_errno = 0;
2255 /* XXX: check env->error_code */
2256 info.si_code = TARGET_SEGV_MAPERR;
2257 info._sifields._sigfault._addr = env->mmu.ar;
2258 queue_signal(env, info.si_signo, &info);
2259 }
2260 break;
2261 case EXCP_DEBUG:
2262 {
2263 int sig;
2264
2265 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2266 if (sig)
2267 {
2268 info.si_signo = sig;
2269 info.si_errno = 0;
2270 info.si_code = TARGET_TRAP_BRKPT;
2271 queue_signal(env, info.si_signo, &info);
2272 }
2273 }
2274 break;
2275 default:
2276 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2277 trapnr);
2278 cpu_dump_state(env, stderr, fprintf, 0);
2279 abort();
2280 }
2281 process_pending_signals(env);
2282 }
2283 }
2284 #endif /* TARGET_M68K */
2285
2286 #ifdef TARGET_ALPHA
2287 void cpu_loop (CPUState *env)
2288 {
2289 int trapnr;
2290 target_siginfo_t info;
2291
2292 while (1) {
2293 trapnr = cpu_alpha_exec (env);
2294
2295 switch (trapnr) {
2296 case EXCP_RESET:
2297 fprintf(stderr, "Reset requested. Exit\n");
2298 exit(1);
2299 break;
2300 case EXCP_MCHK:
2301 fprintf(stderr, "Machine check exception. Exit\n");
2302 exit(1);
2303 break;
2304 case EXCP_ARITH:
2305 fprintf(stderr, "Arithmetic trap.\n");
2306 exit(1);
2307 break;
2308 case EXCP_HW_INTERRUPT:
2309 fprintf(stderr, "External interrupt. Exit\n");
2310 exit(1);
2311 break;
2312 case EXCP_DFAULT:
2313 fprintf(stderr, "MMU data fault\n");
2314 exit(1);
2315 break;
2316 case EXCP_DTB_MISS_PAL:
2317 fprintf(stderr, "MMU data TLB miss in PALcode\n");
2318 exit(1);
2319 break;
2320 case EXCP_ITB_MISS:
2321 fprintf(stderr, "MMU instruction TLB miss\n");
2322 exit(1);
2323 break;
2324 case EXCP_ITB_ACV:
2325 fprintf(stderr, "MMU instruction access violation\n");
2326 exit(1);
2327 break;
2328 case EXCP_DTB_MISS_NATIVE:
2329 fprintf(stderr, "MMU data TLB miss\n");
2330 exit(1);
2331 break;
2332 case EXCP_UNALIGN:
2333 fprintf(stderr, "Unaligned access\n");
2334 exit(1);
2335 break;
2336 case EXCP_OPCDEC:
2337 fprintf(stderr, "Invalid instruction\n");
2338 exit(1);
2339 break;
2340 case EXCP_FEN:
2341 fprintf(stderr, "Floating-point not allowed\n");
2342 exit(1);
2343 break;
2344 case EXCP_CALL_PAL ... (EXCP_CALL_PALP - 1):
2345 call_pal(env, (trapnr >> 6) | 0x80);
2346 break;
2347 case EXCP_CALL_PALP ... (EXCP_CALL_PALE - 1):
2348 fprintf(stderr, "Privileged call to PALcode\n");
2349 exit(1);
2350 break;
2351 case EXCP_DEBUG:
2352 {
2353 int sig;
2354
2355 sig = gdb_handlesig (env, TARGET_SIGTRAP);
2356 if (sig)
2357 {
2358 info.si_signo = sig;
2359 info.si_errno = 0;
2360 info.si_code = TARGET_TRAP_BRKPT;
2361 queue_signal(env, info.si_signo, &info);
2362 }
2363 }
2364 break;
2365 default:
2366 printf ("Unhandled trap: 0x%x\n", trapnr);
2367 cpu_dump_state(env, stderr, fprintf, 0);
2368 exit (1);
2369 }
2370 process_pending_signals (env);
2371 }
2372 }
2373 #endif /* TARGET_ALPHA */
2374
2375 static void usage(void)
2376 {
2377 printf("qemu-" TARGET_ARCH " version " QEMU_VERSION QEMU_PKGVERSION ", Copyright (c) 2003-2008 Fabrice Bellard\n"
2378 "usage: qemu-" TARGET_ARCH " [options] program [arguments...]\n"
2379 "Linux CPU emulator (compiled for %s emulation)\n"
2380 "\n"
2381 "Standard options:\n"
2382 "-h print this help\n"
2383 "-g port wait gdb connection to port\n"
2384 "-L path set the elf interpreter prefix (default=%s)\n"
2385 "-s size set the stack size in bytes (default=%ld)\n"
2386 "-cpu model select CPU (-cpu ? for list)\n"
2387 "-drop-ld-preload drop LD_PRELOAD for target process\n"
2388 "-E var=value sets/modifies targets environment variable(s)\n"
2389 "-U var unsets targets environment variable(s)\n"
2390 "-0 argv0 forces target process argv[0] to be argv0\n"
2391 #if defined(CONFIG_USE_GUEST_BASE)
2392 "-B address set guest_base address to address\n"
2393 #endif
2394 "\n"
2395 "Debug options:\n"
2396 "-d options activate log (logfile=%s)\n"
2397 "-p pagesize set the host page size to 'pagesize'\n"
2398 "-singlestep always run in singlestep mode\n"
2399 "-strace log system calls\n"
2400 "\n"
2401 "Environment variables:\n"
2402 "QEMU_STRACE Print system calls and arguments similar to the\n"
2403 " 'strace' program. Enable by setting to any value.\n"
2404 "You can use -E and -U options to set/unset environment variables\n"
2405 "for target process. It is possible to provide several variables\n"
2406 "by repeating the option. For example:\n"
2407 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
2408 "Note that if you provide several changes to single variable\n"
2409 "last change will stay in effect.\n"
2410 ,
2411 TARGET_ARCH,
2412 interp_prefix,
2413 x86_stack_size,
2414 DEBUG_LOGFILE);
2415 exit(1);
2416 }
2417
2418 THREAD CPUState *thread_env;
2419
2420 void task_settid(TaskState *ts)
2421 {
2422 if (ts->ts_tid == 0) {
2423 #ifdef CONFIG_USE_NPTL
2424 ts->ts_tid = (pid_t)syscall(SYS_gettid);
2425 #else
2426 /* when no threads are used, tid becomes pid */
2427 ts->ts_tid = getpid();
2428 #endif
2429 }
2430 }
2431
2432 void stop_all_tasks(void)
2433 {
2434 /*
2435 * We trust that when using NPTL, start_exclusive()
2436 * handles thread stopping correctly.
2437 */
2438 start_exclusive();
2439 }
2440
2441 /* Assumes contents are already zeroed. */
2442 void init_task_state(TaskState *ts)
2443 {
2444 int i;
2445
2446 ts->used = 1;
2447 ts->first_free = ts->sigqueue_table;
2448 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
2449 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
2450 }
2451 ts->sigqueue_table[i].next = NULL;
2452 }
2453
2454 int main(int argc, char **argv, char **envp)
2455 {
2456 const char *filename;
2457 const char *cpu_model;
2458 struct target_pt_regs regs1, *regs = &regs1;
2459 struct image_info info1, *info = &info1;
2460 struct linux_binprm bprm;
2461 TaskState ts1, *ts = &ts1;
2462 CPUState *env;
2463 int optind;
2464 const char *r;
2465 int gdbstub_port = 0;
2466 char **target_environ, **wrk;
2467 char **target_argv;
2468 int target_argc;
2469 envlist_t *envlist = NULL;
2470 const char *argv0 = NULL;
2471 int i;
2472 int ret;
2473
2474 if (argc <= 1)
2475 usage();
2476
2477 qemu_cache_utils_init(envp);
2478
2479 /* init debug */
2480 cpu_set_log_filename(DEBUG_LOGFILE);
2481
2482 if ((envlist = envlist_create()) == NULL) {
2483 (void) fprintf(stderr, "Unable to allocate envlist\n");
2484 exit(1);
2485 }
2486
2487 /* add current environment into the list */
2488 for (wrk = environ; *wrk != NULL; wrk++) {
2489 (void) envlist_setenv(envlist, *wrk);
2490 }
2491
2492 cpu_model = NULL;
2493 optind = 1;
2494 for(;;) {
2495 if (optind >= argc)
2496 break;
2497 r = argv[optind];
2498 if (r[0] != '-')
2499 break;
2500 optind++;
2501 r++;
2502 if (!strcmp(r, "-")) {
2503 break;
2504 } else if (!strcmp(r, "d")) {
2505 int mask;
2506 const CPULogItem *item;
2507
2508 if (optind >= argc)
2509 break;
2510
2511 r = argv[optind++];
2512 mask = cpu_str_to_log_mask(r);
2513 if (!mask) {
2514 printf("Log items (comma separated):\n");
2515 for(item = cpu_log_items; item->mask != 0; item++) {
2516 printf("%-10s %s\n", item->name, item->help);
2517 }
2518 exit(1);
2519 }
2520 cpu_set_log(mask);
2521 } else if (!strcmp(r, "E")) {
2522 r = argv[optind++];
2523 if (envlist_setenv(envlist, r) != 0)
2524 usage();
2525 } else if (!strcmp(r, "U")) {
2526 r = argv[optind++];
2527 if (envlist_unsetenv(envlist, r) != 0)
2528 usage();
2529 } else if (!strcmp(r, "0")) {
2530 r = argv[optind++];
2531 argv0 = r;
2532 } else if (!strcmp(r, "s")) {
2533 if (optind >= argc)
2534 break;
2535 r = argv[optind++];
2536 x86_stack_size = strtol(r, (char **)&r, 0);
2537 if (x86_stack_size <= 0)
2538 usage();
2539 if (*r == 'M')
2540 x86_stack_size *= 1024 * 1024;
2541 else if (*r == 'k' || *r == 'K')
2542 x86_stack_size *= 1024;
2543 } else if (!strcmp(r, "L")) {
2544 interp_prefix = argv[optind++];
2545 } else if (!strcmp(r, "p")) {
2546 if (optind >= argc)
2547 break;
2548 qemu_host_page_size = atoi(argv[optind++]);
2549 if (qemu_host_page_size == 0 ||
2550 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
2551 fprintf(stderr, "page size must be a power of two\n");
2552 exit(1);
2553 }
2554 } else if (!strcmp(r, "g")) {
2555 if (optind >= argc)
2556 break;
2557 gdbstub_port = atoi(argv[optind++]);
2558 } else if (!strcmp(r, "r")) {
2559 qemu_uname_release = argv[optind++];
2560 } else if (!strcmp(r, "cpu")) {
2561 cpu_model = argv[optind++];
2562 if (cpu_model == NULL || strcmp(cpu_model, "?") == 0) {
2563 /* XXX: implement xxx_cpu_list for targets that still miss it */
2564 #if defined(cpu_list)
2565 cpu_list(stdout, &fprintf);
2566 #endif
2567 exit(1);
2568 }
2569 #if defined(CONFIG_USE_GUEST_BASE)
2570 } else if (!strcmp(r, "B")) {
2571 guest_base = strtol(argv[optind++], NULL, 0);
2572 have_guest_base = 1;
2573 #endif
2574 } else if (!strcmp(r, "drop-ld-preload")) {
2575 (void) envlist_unsetenv(envlist, "LD_PRELOAD");
2576 } else if (!strcmp(r, "singlestep")) {
2577 singlestep = 1;
2578 } else if (!strcmp(r, "strace")) {
2579 do_strace = 1;
2580 } else
2581 {
2582 usage();
2583 }
2584 }
2585 if (optind >= argc)
2586 usage();
2587 filename = argv[optind];
2588 exec_path = argv[optind];
2589
2590 /* Zero out regs */
2591 memset(regs, 0, sizeof(struct target_pt_regs));
2592
2593 /* Zero out image_info */
2594 memset(info, 0, sizeof(struct image_info));
2595
2596 memset(&bprm, 0, sizeof (bprm));
2597
2598 /* Scan interp_prefix dir for replacement files. */
2599 init_paths(interp_prefix);
2600
2601 if (cpu_model == NULL) {
2602 #if defined(TARGET_I386)
2603 #ifdef TARGET_X86_64
2604 cpu_model = "qemu64";
2605 #else
2606 cpu_model = "qemu32";
2607 #endif
2608 #elif defined(TARGET_ARM)
2609 cpu_model = "any";
2610 #elif defined(TARGET_M68K)
2611 cpu_model = "any";
2612 #elif defined(TARGET_SPARC)
2613 #ifdef TARGET_SPARC64
2614 cpu_model = "TI UltraSparc II";
2615 #else
2616 cpu_model = "Fujitsu MB86904";
2617 #endif
2618 #elif defined(TARGET_MIPS)
2619 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
2620 cpu_model = "20Kc";
2621 #else
2622 cpu_model = "24Kf";
2623 #endif
2624 #elif defined(TARGET_PPC)
2625 #ifdef TARGET_PPC64
2626 cpu_model = "970";
2627 #else
2628 cpu_model = "750";
2629 #endif
2630 #else
2631 cpu_model = "any";
2632 #endif
2633 }
2634 cpu_exec_init_all(0);
2635 /* NOTE: we need to init the CPU at this stage to get
2636 qemu_host_page_size */
2637 env = cpu_init(cpu_model);
2638 if (!env) {
2639 fprintf(stderr, "Unable to find CPU definition\n");
2640 exit(1);
2641 }
2642 thread_env = env;
2643
2644 if (getenv("QEMU_STRACE")) {
2645 do_strace = 1;
2646 }
2647
2648 target_environ = envlist_to_environ(envlist, NULL);
2649 envlist_free(envlist);
2650
2651 #if defined(CONFIG_USE_GUEST_BASE)
2652 /*
2653 * Now that page sizes are configured in cpu_init() we can do
2654 * proper page alignment for guest_base.
2655 */
2656 guest_base = HOST_PAGE_ALIGN(guest_base);
2657
2658 /*
2659 * Read in mmap_min_addr kernel parameter. This value is used
2660 * When loading the ELF image to determine whether guest_base
2661 * is needed.
2662 *
2663 * When user has explicitly set the quest base, we skip this
2664 * test.
2665 */
2666 if (!have_guest_base) {
2667 FILE *fp;
2668
2669 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
2670 unsigned long tmp;
2671 if (fscanf(fp, "%lu", &tmp) == 1) {
2672 mmap_min_addr = tmp;
2673 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
2674 }
2675 fclose(fp);
2676 }
2677 }
2678 #endif /* CONFIG_USE_GUEST_BASE */
2679
2680 /*
2681 * Prepare copy of argv vector for target.
2682 */
2683 target_argc = argc - optind;
2684 target_argv = calloc(target_argc + 1, sizeof (char *));
2685 if (target_argv == NULL) {
2686 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
2687 exit(1);
2688 }
2689
2690 /*
2691 * If argv0 is specified (using '-0' switch) we replace
2692 * argv[0] pointer with the given one.
2693 */
2694 i = 0;
2695 if (argv0 != NULL) {
2696 target_argv[i++] = strdup(argv0);
2697 }
2698 for (; i < target_argc; i++) {
2699 target_argv[i] = strdup(argv[optind + i]);
2700 }
2701 target_argv[target_argc] = NULL;
2702
2703 memset(ts, 0, sizeof(TaskState));
2704 init_task_state(ts);
2705 /* build Task State */
2706 ts->info = info;
2707 ts->bprm = &bprm;
2708 env->opaque = ts;
2709 task_settid(ts);
2710
2711 ret = loader_exec(filename, target_argv, target_environ, regs,
2712 info, &bprm);
2713 if (ret != 0) {
2714 printf("Error %d while loading %s\n", ret, filename);
2715 _exit(1);
2716 }
2717
2718 for (i = 0; i < target_argc; i++) {
2719 free(target_argv[i]);
2720 }
2721 free(target_argv);
2722
2723 for (wrk = target_environ; *wrk; wrk++) {
2724 free(*wrk);
2725 }
2726
2727 free(target_environ);
2728
2729 if (qemu_log_enabled()) {
2730 #if defined(CONFIG_USE_GUEST_BASE)
2731 qemu_log("guest_base 0x%lx\n", guest_base);
2732 #endif
2733 log_page_dump();
2734
2735 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
2736 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
2737 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
2738 info->start_code);
2739 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
2740 info->start_data);
2741 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
2742 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
2743 info->start_stack);
2744 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
2745 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
2746 }
2747
2748 target_set_brk(info->brk);
2749 syscall_init();
2750 signal_init();
2751
2752 #if defined(TARGET_I386)
2753 cpu_x86_set_cpl(env, 3);
2754
2755 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
2756 env->hflags |= HF_PE_MASK;
2757 if (env->cpuid_features & CPUID_SSE) {
2758 env->cr[4] |= CR4_OSFXSR_MASK;
2759 env->hflags |= HF_OSFXSR_MASK;
2760 }
2761 #ifndef TARGET_ABI32
2762 /* enable 64 bit mode if possible */
2763 if (!(env->cpuid_ext2_features & CPUID_EXT2_LM)) {
2764 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
2765 exit(1);
2766 }
2767 env->cr[4] |= CR4_PAE_MASK;
2768 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
2769 env->hflags |= HF_LMA_MASK;
2770 #endif
2771
2772 /* flags setup : we activate the IRQs by default as in user mode */
2773 env->eflags |= IF_MASK;
2774
2775 /* linux register setup */
2776 #ifndef TARGET_ABI32
2777 env->regs[R_EAX] = regs->rax;
2778 env->regs[R_EBX] = regs->rbx;
2779 env->regs[R_ECX] = regs->rcx;
2780 env->regs[R_EDX] = regs->rdx;
2781 env->regs[R_ESI] = regs->rsi;
2782 env->regs[R_EDI] = regs->rdi;
2783 env->regs[R_EBP] = regs->rbp;
2784 env->regs[R_ESP] = regs->rsp;
2785 env->eip = regs->rip;
2786 #else
2787 env->regs[R_EAX] = regs->eax;
2788 env->regs[R_EBX] = regs->ebx;
2789 env->regs[R_ECX] = regs->ecx;
2790 env->regs[R_EDX] = regs->edx;
2791 env->regs[R_ESI] = regs->esi;
2792 env->regs[R_EDI] = regs->edi;
2793 env->regs[R_EBP] = regs->ebp;
2794 env->regs[R_ESP] = regs->esp;
2795 env->eip = regs->eip;
2796 #endif
2797
2798 /* linux interrupt setup */
2799 #ifndef TARGET_ABI32
2800 env->idt.limit = 511;
2801 #else
2802 env->idt.limit = 255;
2803 #endif
2804 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
2805 PROT_READ|PROT_WRITE,
2806 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2807 idt_table = g2h(env->idt.base);
2808 set_idt(0, 0);
2809 set_idt(1, 0);
2810 set_idt(2, 0);
2811 set_idt(3, 3);
2812 set_idt(4, 3);
2813 set_idt(5, 0);
2814 set_idt(6, 0);
2815 set_idt(7, 0);
2816 set_idt(8, 0);
2817 set_idt(9, 0);
2818 set_idt(10, 0);
2819 set_idt(11, 0);
2820 set_idt(12, 0);
2821 set_idt(13, 0);
2822 set_idt(14, 0);
2823 set_idt(15, 0);
2824 set_idt(16, 0);
2825 set_idt(17, 0);
2826 set_idt(18, 0);
2827 set_idt(19, 0);
2828 set_idt(0x80, 3);
2829
2830 /* linux segment setup */
2831 {
2832 uint64_t *gdt_table;
2833 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
2834 PROT_READ|PROT_WRITE,
2835 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
2836 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
2837 gdt_table = g2h(env->gdt.base);
2838 #ifdef TARGET_ABI32
2839 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2840 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2841 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2842 #else
2843 /* 64 bit code segment */
2844 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
2845 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2846 DESC_L_MASK |
2847 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
2848 #endif
2849 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
2850 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
2851 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
2852 }
2853 cpu_x86_load_seg(env, R_CS, __USER_CS);
2854 cpu_x86_load_seg(env, R_SS, __USER_DS);
2855 #ifdef TARGET_ABI32
2856 cpu_x86_load_seg(env, R_DS, __USER_DS);
2857 cpu_x86_load_seg(env, R_ES, __USER_DS);
2858 cpu_x86_load_seg(env, R_FS, __USER_DS);
2859 cpu_x86_load_seg(env, R_GS, __USER_DS);
2860 /* This hack makes Wine work... */
2861 env->segs[R_FS].selector = 0;
2862 #else
2863 cpu_x86_load_seg(env, R_DS, 0);
2864 cpu_x86_load_seg(env, R_ES, 0);
2865 cpu_x86_load_seg(env, R_FS, 0);
2866 cpu_x86_load_seg(env, R_GS, 0);
2867 #endif
2868 #elif defined(TARGET_ARM)
2869 {
2870 int i;
2871 cpsr_write(env, regs->uregs[16], 0xffffffff);
2872 for(i = 0; i < 16; i++) {
2873 env->regs[i] = regs->uregs[i];
2874 }
2875 }
2876 #elif defined(TARGET_SPARC)
2877 {
2878 int i;
2879 env->pc = regs->pc;
2880 env->npc = regs->npc;
2881 env->y = regs->y;
2882 for(i = 0; i < 8; i++)
2883 env->gregs[i] = regs->u_regs[i];
2884 for(i = 0; i < 8; i++)
2885 env->regwptr[i] = regs->u_regs[i + 8];
2886 }
2887 #elif defined(TARGET_PPC)
2888 {
2889 int i;
2890
2891 #if defined(TARGET_PPC64)
2892 #if defined(TARGET_ABI32)
2893 env->msr &= ~((target_ulong)1 << MSR_SF);
2894 #else
2895 env->msr |= (target_ulong)1 << MSR_SF;
2896 #endif
2897 #endif
2898 env->nip = regs->nip;
2899 for(i = 0; i < 32; i++) {
2900 env->gpr[i] = regs->gpr[i];
2901 }
2902 }
2903 #elif defined(TARGET_M68K)
2904 {
2905 env->pc = regs->pc;
2906 env->dregs[0] = regs->d0;
2907 env->dregs[1] = regs->d1;
2908 env->dregs[2] = regs->d2;
2909 env->dregs[3] = regs->d3;
2910 env->dregs[4] = regs->d4;
2911 env->dregs[5] = regs->d5;
2912 env->dregs[6] = regs->d6;
2913 env->dregs[7] = regs->d7;
2914 env->aregs[0] = regs->a0;
2915 env->aregs[1] = regs->a1;
2916 env->aregs[2] = regs->a2;
2917 env->aregs[3] = regs->a3;
2918 env->aregs[4] = regs->a4;
2919 env->aregs[5] = regs->a5;
2920 env->aregs[6] = regs->a6;
2921 env->aregs[7] = regs->usp;
2922 env->sr = regs->sr;
2923 ts->sim_syscalls = 1;
2924 }
2925 #elif defined(TARGET_MICROBLAZE)
2926 {
2927 env->regs[0] = regs->r0;
2928 env->regs[1] = regs->r1;
2929 env->regs[2] = regs->r2;
2930 env->regs[3] = regs->r3;
2931 env->regs[4] = regs->r4;
2932 env->regs[5] = regs->r5;
2933 env->regs[6] = regs->r6;
2934 env->regs[7] = regs->r7;
2935 env->regs[8] = regs->r8;
2936 env->regs[9] = regs->r9;
2937 env->regs[10] = regs->r10;
2938 env->regs[11] = regs->r11;
2939 env->regs[12] = regs->r12;
2940 env->regs[13] = regs->r13;
2941 env->regs[14] = regs->r14;
2942 env->regs[15] = regs->r15;
2943 env->regs[16] = regs->r16;
2944 env->regs[17] = regs->r17;
2945 env->regs[18] = regs->r18;
2946 env->regs[19] = regs->r19;
2947 env->regs[20] = regs->r20;
2948 env->regs[21] = regs->r21;
2949 env->regs[22] = regs->r22;
2950 env->regs[23] = regs->r23;
2951 env->regs[24] = regs->r24;
2952 env->regs[25] = regs->r25;
2953 env->regs[26] = regs->r26;
2954 env->regs[27] = regs->r27;
2955 env->regs[28] = regs->r28;
2956 env->regs[29] = regs->r29;
2957 env->regs[30] = regs->r30;
2958 env->regs[31] = regs->r31;
2959 env->sregs[SR_PC] = regs->pc;
2960 }
2961 #elif defined(TARGET_MIPS)
2962 {
2963 int i;
2964
2965 for(i = 0; i < 32; i++) {
2966 env->active_tc.gpr[i] = regs->regs[i];
2967 }
2968 env->active_tc.PC = regs->cp0_epc;
2969 }
2970 #elif defined(TARGET_SH4)
2971 {
2972 int i;
2973
2974 for(i = 0; i < 16; i++) {
2975 env->gregs[i] = regs->regs[i];
2976 }
2977 env->pc = regs->pc;
2978 }
2979 #elif defined(TARGET_ALPHA)
2980 {
2981 int i;
2982
2983 for(i = 0; i < 28; i++) {
2984 env->ir[i] = ((abi_ulong *)regs)[i];
2985 }
2986 env->ipr[IPR_USP] = regs->usp;
2987 env->ir[30] = regs->usp;
2988 env->pc = regs->pc;
2989 env->unique = regs->unique;
2990 }
2991 #elif defined(TARGET_CRIS)
2992 {
2993 env->regs[0] = regs->r0;
2994 env->regs[1] = regs->r1;
2995 env->regs[2] = regs->r2;
2996 env->regs[3] = regs->r3;
2997 env->regs[4] = regs->r4;
2998 env->regs[5] = regs->r5;
2999 env->regs[6] = regs->r6;
3000 env->regs[7] = regs->r7;
3001 env->regs[8] = regs->r8;
3002 env->regs[9] = regs->r9;
3003 env->regs[10] = regs->r10;
3004 env->regs[11] = regs->r11;
3005 env->regs[12] = regs->r12;
3006 env->regs[13] = regs->r13;
3007 env->regs[14] = info->start_stack;
3008 env->regs[15] = regs->acr;
3009 env->pc = regs->erp;
3010 }
3011 #else
3012 #error unsupported target CPU
3013 #endif
3014
3015 #if defined(TARGET_ARM) || defined(TARGET_M68K)
3016 ts->stack_base = info->start_stack;
3017 ts->heap_base = info->brk;
3018 /* This will be filled in on the first SYS_HEAPINFO call. */
3019 ts->heap_limit = 0;
3020 #endif
3021
3022 if (gdbstub_port) {
3023 gdbserver_start (gdbstub_port);
3024 gdb_handlesig(env, 0);
3025 }
3026 cpu_loop(env);
3027 /* never exits */
3028 return 0;
3029 }
Qemu copy for testing