qemu-barrier.h

   1 #ifndef __QEMU_BARRIER_H
   2 #define __QEMU_BARRIER_H 1
   3
   4 /* Compiler barrier */
   5 #define barrier()   asm volatile("" ::: "memory")
   6
   7 #if defined(__i386__)
   8
   9 /*
  10  * Because of the strongly ordered x86 storage model, wmb() is a nop
  11  * on x86(well, a compiler barrier only).  Well, at least as long as
  12  * qemu doesn't do accesses to write-combining memory or non-temporal
  13  * load/stores from C code.
  14  */
  15 #define smp_wmb()   barrier()
  16 /*
  17  * We use GCC builtin if it's available, as that can use
  18  * mfence on 32 bit as well, e.g. if built with -march=pentium-m.
  19  * However, on i386, there seem to be known bugs as recently as 4.3.
  20  * */
  21 #if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 4
  22 #define smp_mb() __sync_synchronize()
  23 #else
  24 #define smp_mb() asm volatile("lock; addl $0,0(%%esp) " ::: "memory")
  25 #endif
  26
  27 #elif defined(__x86_64__)
  28
  29 #define smp_wmb()   barrier()
  30 #define smp_mb() asm volatile("mfence" ::: "memory")
  31
  32 #elif defined(_ARCH_PPC)
  33
  34 /*
  35  * We use an eieio() for wmb() on powerpc.  This assumes we don't
  36  * need to order cacheable and non-cacheable stores with respect to
  37  * each other
  38  */
  39 #define smp_wmb()   asm volatile("eieio" ::: "memory")
  40 #define smp_mb()   asm volatile("sync" ::: "memory")
  41
  42 #else
  43
  44 /*
  45  * For (host) platforms we don't have explicit barrier definitions
  46  * for, we use the gcc __sync_synchronize() primitive to generate a
  47  * full barrier.  This should be safe on all platforms, though it may
  48  * be overkill for wmb().
  49  */
  50 #define smp_wmb()   __sync_synchronize()
  51 #define smp_mb()   __sync_synchronize()
  52
  53 #endif
  54
  55 #endif