softmmu_header.h

   1 /*
   2  *  Software MMU support
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #if DATA_SIZE == 8
  21 #define SUFFIX q
  22 #define USUFFIX q
  23 #define DATA_TYPE uint64_t
  24 #elif DATA_SIZE == 4
  25 #define SUFFIX l
  26 #define USUFFIX l
  27 #define DATA_TYPE uint32_t
  28 #elif DATA_SIZE == 2
  29 #define SUFFIX w
  30 #define USUFFIX uw
  31 #define DATA_TYPE uint16_t
  32 #define DATA_STYPE int16_t
  33 #elif DATA_SIZE == 1
  34 #define SUFFIX b
  35 #define USUFFIX ub
  36 #define DATA_TYPE uint8_t
  37 #define DATA_STYPE int8_t
  38 #else
  39 #error unsupported data size
  40 #endif
  41
  42 #if ACCESS_TYPE == 0
  43
  44 #define CPU_MEM_INDEX 0
  45 #define MMUSUFFIX _mmu
  46
  47 #elif ACCESS_TYPE == 1
  48
  49 #define CPU_MEM_INDEX 1
  50 #define MMUSUFFIX _mmu
  51
  52 #elif ACCESS_TYPE == 2
  53
  54 #ifdef TARGET_I386
  55 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
  56 #elif defined (TARGET_PPC)
  57 #define CPU_MEM_INDEX (msr_pr)
  58 #elif defined (TARGET_MIPS)
  59 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
  60 #elif defined (TARGET_SPARC)
  61 #define CPU_MEM_INDEX ((env->psrs) == 0)
  62 #elif defined (TARGET_ARM)
  63 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
  64 #else
  65 #error unsupported CPU
  66 #endif
  67 #define MMUSUFFIX _mmu
  68
  69 #elif ACCESS_TYPE == 3
  70
  71 #ifdef TARGET_I386
  72 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
  73 #elif defined (TARGET_PPC)
  74 #define CPU_MEM_INDEX (msr_pr)
  75 #elif defined (TARGET_MIPS)
  76 #define CPU_MEM_INDEX ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM)
  77 #elif defined (TARGET_SPARC)
  78 #define CPU_MEM_INDEX ((env->psrs) == 0)
  79 #elif defined (TARGET_ARM)
  80 #define CPU_MEM_INDEX ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)
  81 #else
  82 #error unsupported CPU
  83 #endif
  84 #define MMUSUFFIX _cmmu
  85
  86 #else
  87 #error invalid ACCESS_TYPE
  88 #endif
  89
  90 #if DATA_SIZE == 8
  91 #define RES_TYPE uint64_t
  92 #else
  93 #define RES_TYPE int
  94 #endif
  95
  96
  97 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  98                                                          int is_user);
  99 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
 100
 101 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
 102     (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
 103
 104 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
 105 {
 106     int res;
 107
 108     asm volatile ("movl %1, %%edx\n"
 109                   "movl %1, %%eax\n"
 110                   "shrl %3, %%edx\n"
 111                   "andl %4, %%eax\n"
 112                   "andl %2, %%edx\n"
 113                   "leal %5(%%edx, %%ebp), %%edx\n"
 114                   "cmpl (%%edx), %%eax\n"
 115                   "movl %1, %%eax\n"
 116                   "je 1f\n"
 117                   "pushl %6\n"
 118                   "call %7\n"
 119                   "popl %%edx\n"
 120                   "movl %%eax, %0\n"
 121                   "jmp 2f\n"
 122                   "1:\n"
 123                   "addl 4(%%edx), %%eax\n"
 124 #if DATA_SIZE == 1
 125                   "movzbl (%%eax), %0\n"
 126 #elif DATA_SIZE == 2
 127                   "movzwl (%%eax), %0\n"
 128 #elif DATA_SIZE == 4
 129                   "movl (%%eax), %0\n"
 130 #else
 131 #error unsupported size
 132 #endif
 133                   "2:\n"
 134                   : "=r" (res)
 135                   : "r" (ptr),
 136                   "i" ((CPU_TLB_SIZE - 1) << 3),
 137                   "i" (TARGET_PAGE_BITS - 3),
 138                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 139                   "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
 140                   "i" (CPU_MEM_INDEX),
 141                   "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
 142                   : "%eax", "%ecx", "%edx", "memory", "cc");
 143     return res;
 144 }
 145
 146 #if DATA_SIZE <= 2
 147 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
 148 {
 149     int res;
 150
 151     asm volatile ("movl %1, %%edx\n"
 152                   "movl %1, %%eax\n"
 153                   "shrl %3, %%edx\n"
 154                   "andl %4, %%eax\n"
 155                   "andl %2, %%edx\n"
 156                   "leal %5(%%edx, %%ebp), %%edx\n"
 157                   "cmpl (%%edx), %%eax\n"
 158                   "movl %1, %%eax\n"
 159                   "je 1f\n"
 160                   "pushl %6\n"
 161                   "call %7\n"
 162                   "popl %%edx\n"
 163 #if DATA_SIZE == 1
 164                   "movsbl %%al, %0\n"
 165 #elif DATA_SIZE == 2
 166                   "movswl %%ax, %0\n"
 167 #else
 168 #error unsupported size
 169 #endif
 170                   "jmp 2f\n"
 171                   "1:\n"
 172                   "addl 4(%%edx), %%eax\n"
 173 #if DATA_SIZE == 1
 174                   "movsbl (%%eax), %0\n"
 175 #elif DATA_SIZE == 2
 176                   "movswl (%%eax), %0\n"
 177 #else
 178 #error unsupported size
 179 #endif
 180                   "2:\n"
 181                   : "=r" (res)
 182                   : "r" (ptr),
 183                   "i" ((CPU_TLB_SIZE - 1) << 3),
 184                   "i" (TARGET_PAGE_BITS - 3),
 185                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 186                   "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
 187                   "i" (CPU_MEM_INDEX),
 188                   "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
 189                   : "%eax", "%ecx", "%edx", "memory", "cc");
 190     return res;
 191 }
 192 #endif
 193
 194 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
 195 {
 196     asm volatile ("movl %0, %%edx\n"
 197                   "movl %0, %%eax\n"
 198                   "shrl %3, %%edx\n"
 199                   "andl %4, %%eax\n"
 200                   "andl %2, %%edx\n"
 201                   "leal %5(%%edx, %%ebp), %%edx\n"
 202                   "cmpl (%%edx), %%eax\n"
 203                   "movl %0, %%eax\n"
 204                   "je 1f\n"
 205 #if DATA_SIZE == 1
 206                   "movzbl %b1, %%edx\n"
 207 #elif DATA_SIZE == 2
 208                   "movzwl %w1, %%edx\n"
 209 #elif DATA_SIZE == 4
 210                   "movl %1, %%edx\n"
 211 #else
 212 #error unsupported size
 213 #endif
 214                   "pushl %6\n"
 215                   "call %7\n"
 216                   "popl %%eax\n"
 217                   "jmp 2f\n"
 218                   "1:\n"
 219                   "addl 4(%%edx), %%eax\n"
 220 #if DATA_SIZE == 1
 221                   "movb %b1, (%%eax)\n"
 222 #elif DATA_SIZE == 2
 223                   "movw %w1, (%%eax)\n"
 224 #elif DATA_SIZE == 4
 225                   "movl %1, (%%eax)\n"
 226 #else
 227 #error unsupported size
 228 #endif
 229                   "2:\n"
 230                   :
 231                   : "r" (ptr),
 232 /* NOTE: 'q' would be needed as constraint, but we could not use it
 233    with T1 ! */
 234                   "r" (v),
 235                   "i" ((CPU_TLB_SIZE - 1) << 3),
 236                   "i" (TARGET_PAGE_BITS - 3),
 237                   "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
 238                   "m" (*(uint32_t *)offsetof(CPUState, tlb_write[CPU_MEM_INDEX][0].address)),
 239                   "i" (CPU_MEM_INDEX),
 240                   "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
 241                   : "%eax", "%ecx", "%edx", "memory", "cc");
 242 }
 243
 244 #else
 245
 246 /* generic load/store macros */
 247
 248 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
 249 {
 250     int index;
 251     RES_TYPE res;
 252     target_ulong addr;
 253     unsigned long physaddr;
 254     int is_user;
 255
 256     addr = ptr;
 257     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 258     is_user = CPU_MEM_INDEX;
 259     if (__builtin_expect(env->tlb_read[is_user][index].address !=
 260                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 261         res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
 262     } else {
 263         physaddr = addr + env->tlb_read[is_user][index].addend;
 264         res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
 265     }
 266     return res;
 267 }
 268
 269 #if DATA_SIZE <= 2
 270 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
 271 {
 272     int res, index;
 273     target_ulong addr;
 274     unsigned long physaddr;
 275     int is_user;
 276
 277     addr = ptr;
 278     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 279     is_user = CPU_MEM_INDEX;
 280     if (__builtin_expect(env->tlb_read[is_user][index].address !=
 281                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 282         res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
 283     } else {
 284         physaddr = addr + env->tlb_read[is_user][index].addend;
 285         res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
 286     }
 287     return res;
 288 }
 289 #endif
 290
 291 /* generic store macro */
 292
 293 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
 294 {
 295     int index;
 296     target_ulong addr;
 297     unsigned long physaddr;
 298     int is_user;
 299
 300     addr = ptr;
 301     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 302     is_user = CPU_MEM_INDEX;
 303     if (__builtin_expect(env->tlb_write[is_user][index].address !=
 304                          (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
 305         glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
 306     } else {
 307         physaddr = addr + env->tlb_write[is_user][index].addend;
 308         glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
 309     }
 310 }
 311
 312 #endif
 313
 314 #if DATA_SIZE == 8
 315 static inline float64 glue(ldfq, MEMSUFFIX)(target_ulong ptr)
 316 {
 317     union {
 318         float64 d;
 319         uint64_t i;
 320     } u;
 321     u.i = glue(ldq, MEMSUFFIX)(ptr);
 322     return u.d;
 323 }
 324
 325 static inline void glue(stfq, MEMSUFFIX)(target_ulong ptr, float64 v)
 326 {
 327     union {
 328         float64 d;
 329         uint64_t i;
 330     } u;
 331     u.d = v;
 332     glue(stq, MEMSUFFIX)(ptr, u.i);
 333 }
 334 #endif /* DATA_SIZE == 8 */
 335
 336 #if DATA_SIZE == 4
 337 static inline float32 glue(ldfl, MEMSUFFIX)(target_ulong ptr)
 338 {
 339     union {
 340         float32 f;
 341         uint32_t i;
 342     } u;
 343     u.i = glue(ldl, MEMSUFFIX)(ptr);
 344     return u.f;
 345 }
 346
 347 static inline void glue(stfl, MEMSUFFIX)(target_ulong ptr, float32 v)
 348 {
 349     union {
 350         float32 f;
 351         uint32_t i;
 352     } u;
 353     u.f = v;
 354     glue(stl, MEMSUFFIX)(ptr, u.i);
 355 }
 356 #endif /* DATA_SIZE == 4 */
 357
 358 #undef RES_TYPE
 359 #undef DATA_TYPE
 360 #undef DATA_STYPE
 361 #undef SUFFIX
 362 #undef USUFFIX
 363 #undef DATA_SIZE
 364 #undef CPU_MEM_INDEX
 365 #undef MMUSUFFIX