softmmu_template.h

   1 /*
   2  *  Software MMU support
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #define DATA_SIZE (1 << SHIFT)
  21
  22 #if DATA_SIZE == 8
  23 #define SUFFIX q
  24 #define USUFFIX q
  25 #define DATA_TYPE uint64_t
  26 #elif DATA_SIZE == 4
  27 #define SUFFIX l
  28 #define USUFFIX l
  29 #define DATA_TYPE uint32_t
  30 #elif DATA_SIZE == 2
  31 #define SUFFIX w
  32 #define USUFFIX uw
  33 #define DATA_TYPE uint16_t
  34 #elif DATA_SIZE == 1
  35 #define SUFFIX b
  36 #define USUFFIX ub
  37 #define DATA_TYPE uint8_t
  38 #else
  39 #error unsupported data size
  40 #endif
  41
  42 #ifdef SOFTMMU_CODE_ACCESS
  43 #define READ_ACCESS_TYPE 2
  44 #define ADDR_READ addr_code
  45 #else
  46 #define READ_ACCESS_TYPE 0
  47 #define ADDR_READ addr_read
  48 #endif
  49
  50 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  51                                                         int is_user,
  52                                                         void *retaddr);
  53 static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
  54                                               target_ulong tlb_addr)
  55 {
  56     DATA_TYPE res;
  57     int index;
  58
  59     index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
  60 #if SHIFT <= 2
  61     res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
  62 #else
  63 #ifdef TARGET_WORDS_BIGENDIAN
  64     res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
  65     res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
  66 #else
  67     res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
  68     res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
  69 #endif
  70 #endif /* SHIFT > 2 */
  71     return res;
  72 }
  73
  74 /* handle all cases except unaligned access which span two pages */
  75 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  76                                                          int is_user)
  77 {
  78     DATA_TYPE res;
  79     int index;
  80     target_ulong tlb_addr;
  81     target_phys_addr_t physaddr;
  82     void *retaddr;
  83
  84     /* test if there is match for unaligned or IO access */
  85     /* XXX: could done more in memory macro in a non portable way */
  86     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
  87  redo:
  88     tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
  89     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
  90         physaddr = addr + env->tlb_table[is_user][index].addend;
  91         if (tlb_addr & ~TARGET_PAGE_MASK) {
  92             /* IO access */
  93             if ((addr & (DATA_SIZE - 1)) != 0)
  94                 goto do_unaligned_access;
  95             res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
  96         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
  97             /* slow unaligned access (it spans two pages or IO) */
  98         do_unaligned_access:
  99             retaddr = GETPC();
 100             res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
 101                                                          is_user, retaddr);
 102         } else {
 103             /* unaligned access in the same page */
 104             res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
 105         }
 106     } else {
 107         /* the page is not in the TLB : fill it */
 108         retaddr = GETPC();
 109         tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
 110         goto redo;
 111     }
 112     return res;
 113 }
 114
 115 /* handle all unaligned cases */
 116 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
 117                                                         int is_user,
 118                                                         void *retaddr)
 119 {
 120     DATA_TYPE res, res1, res2;
 121     int index, shift;
 122     target_phys_addr_t physaddr;
 123     target_ulong tlb_addr, addr1, addr2;
 124
 125     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 126  redo:
 127     tlb_addr = env->tlb_table[is_user][index].ADDR_READ;
 128     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 129         physaddr = addr + env->tlb_table[is_user][index].addend;
 130         if (tlb_addr & ~TARGET_PAGE_MASK) {
 131             /* IO access */
 132             if ((addr & (DATA_SIZE - 1)) != 0)
 133                 goto do_unaligned_access;
 134             res = glue(io_read, SUFFIX)(physaddr, tlb_addr);
 135         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 136         do_unaligned_access:
 137             /* slow unaligned access (it spans two pages) */
 138             addr1 = addr & ~(DATA_SIZE - 1);
 139             addr2 = addr1 + DATA_SIZE;
 140             res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
 141                                                           is_user, retaddr);
 142             res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
 143                                                           is_user, retaddr);
 144             shift = (addr & (DATA_SIZE - 1)) * 8;
 145 #ifdef TARGET_WORDS_BIGENDIAN
 146             res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
 147 #else
 148             res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
 149 #endif
 150             res = (DATA_TYPE)res;
 151         } else {
 152             /* unaligned/aligned access in the same page */
 153             res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)physaddr);
 154         }
 155     } else {
 156         /* the page is not in the TLB : fill it */
 157         tlb_fill(addr, READ_ACCESS_TYPE, is_user, retaddr);
 158         goto redo;
 159     }
 160     return res;
 161 }
 162
 163 #ifndef SOFTMMU_CODE_ACCESS
 164
 165 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 166                                                    DATA_TYPE val,
 167                                                    int is_user,
 168                                                    void *retaddr);
 169
 170 static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
 171                                           DATA_TYPE val,
 172                                           target_ulong tlb_addr,
 173                                           void *retaddr)
 174 {
 175     int index;
 176
 177     index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
 178     env->mem_write_vaddr = tlb_addr;
 179     env->mem_write_pc = (unsigned long)retaddr;
 180 #if SHIFT <= 2
 181     io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
 182 #else
 183 #ifdef TARGET_WORDS_BIGENDIAN
 184     io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
 185     io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
 186 #else
 187     io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
 188     io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
 189 #endif
 190 #endif /* SHIFT > 2 */
 191 }
 192
 193 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 194                                                     DATA_TYPE val,
 195                                                     int is_user)
 196 {
 197     target_phys_addr_t physaddr;
 198     target_ulong tlb_addr;
 199     void *retaddr;
 200     int index;
 201
 202     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 203  redo:
 204     tlb_addr = env->tlb_table[is_user][index].addr_write;
 205     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 206         physaddr = addr + env->tlb_table[is_user][index].addend;
 207         if (tlb_addr & ~TARGET_PAGE_MASK) {
 208             /* IO access */
 209             if ((addr & (DATA_SIZE - 1)) != 0)
 210                 goto do_unaligned_access;
 211             retaddr = GETPC();
 212             glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
 213         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 214         do_unaligned_access:
 215             retaddr = GETPC();
 216             glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
 217                                                    is_user, retaddr);
 218         } else {
 219             /* aligned/unaligned access in the same page */
 220             glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
 221         }
 222     } else {
 223         /* the page is not in the TLB : fill it */
 224         retaddr = GETPC();
 225         tlb_fill(addr, 1, is_user, retaddr);
 226         goto redo;
 227     }
 228 }
 229
 230 /* handles all unaligned cases */
 231 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
 232                                                    DATA_TYPE val,
 233                                                    int is_user,
 234                                                    void *retaddr)
 235 {
 236     target_phys_addr_t physaddr;
 237     target_ulong tlb_addr;
 238     int index, i;
 239
 240     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 241  redo:
 242     tlb_addr = env->tlb_table[is_user][index].addr_write;
 243     if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
 244         physaddr = addr + env->tlb_table[is_user][index].addend;
 245         if (tlb_addr & ~TARGET_PAGE_MASK) {
 246             /* IO access */
 247             if ((addr & (DATA_SIZE - 1)) != 0)
 248                 goto do_unaligned_access;
 249             glue(io_write, SUFFIX)(physaddr, val, tlb_addr, retaddr);
 250         } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
 251         do_unaligned_access:
 252             /* XXX: not efficient, but simple */
 253             for(i = 0;i < DATA_SIZE; i++) {
 254 #ifdef TARGET_WORDS_BIGENDIAN
 255                 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
 256                                           is_user, retaddr);
 257 #else
 258                 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
 259                                           is_user, retaddr);
 260 #endif
 261             }
 262         } else {
 263             /* aligned/unaligned access in the same page */
 264             glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)physaddr, val);
 265         }
 266     } else {
 267         /* the page is not in the TLB : fill it */
 268         tlb_fill(addr, 1, is_user, retaddr);
 269         goto redo;
 270     }
 271 }
 272
 273 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
 274
 275 #undef READ_ACCESS_TYPE
 276 #undef SHIFT
 277 #undef DATA_TYPE
 278 #undef SUFFIX
 279 #undef USUFFIX
 280 #undef DATA_SIZE
 281 #undef ADDR_READ