target/arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include <sys/ioctl.h>
  13
  14 #include <linux/kvm.h>
  15
  16 #include "qemu-common.h"
  17 #include "cpu.h"
  18 #include "qemu/timer.h"
  19 #include "sysemu/runstate.h"
  20 #include "sysemu/kvm.h"
  21 #include "kvm_arm.h"
  22 #include "internals.h"
  23 #include "qemu/log.h"
  24
  25 static inline void set_feature(uint64_t *features, int feature)
  26 {
  27     *features |= 1ULL << feature;
  28 }
  29
  30 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
  31 {
  32     struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
  33
  34     assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
  35     return ioctl(fd, KVM_GET_ONE_REG, &idreg);
  36 }
  37
  38 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  39 {
  40     /* Identify the feature bits corresponding to the host CPU, and
  41      * fill out the ARMHostCPUClass fields accordingly. To do this
  42      * we have to create a scratch VM, create a single CPU inside it,
  43      * and then query that CPU for the relevant ID registers.
  44      */
  45     int err = 0, fdarray[3];
  46     uint32_t midr, id_pfr0;
  47     uint64_t features = 0;
  48
  49     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  50      * we know these will only support creating one kind of guest CPU,
  51      * which is its preferred CPU type.
  52      */
  53     static const uint32_t cpus_to_try[] = {
  54         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  55         QEMU_KVM_ARM_TARGET_NONE
  56     };
  57     /*
  58      * target = -1 informs kvm_arm_create_scratch_host_vcpu()
  59      * to use the preferred target
  60      */
  61     struct kvm_vcpu_init init = { .target = -1, };
  62
  63     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  64         return false;
  65     }
  66
  67     ahcf->target = init.target;
  68
  69     /* This is not strictly blessed by the device tree binding docs yet,
  70      * but in practice the kernel does not care about this string so
  71      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  72      */
  73     ahcf->dtb_compatible = "arm,arm-v7";
  74
  75     err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
  76     err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
  77
  78     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
  79                           ARM_CP15_REG32(0, 0, 2, 0));
  80     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
  81                           ARM_CP15_REG32(0, 0, 2, 1));
  82     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
  83                           ARM_CP15_REG32(0, 0, 2, 2));
  84     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
  85                           ARM_CP15_REG32(0, 0, 2, 3));
  86     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
  87                           ARM_CP15_REG32(0, 0, 2, 4));
  88     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
  89                           ARM_CP15_REG32(0, 0, 2, 5));
  90     if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
  91                        ARM_CP15_REG32(0, 0, 2, 7))) {
  92         /*
  93          * Older kernels don't support reading ID_ISAR6. This register was
  94          * only introduced in ARMv8, so we can assume that it is zero on a
  95          * CPU that a kernel this old is running on.
  96          */
  97         ahcf->isar.id_isar6 = 0;
  98     }
  99
 100     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
 101                           ARM_CP15_REG32(0, 0, 1, 2));
 102
 103     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
 104                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
 105                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
 106     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
 107                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
 108                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 109     /*
 110      * FIXME: There is not yet a way to read MVFR2.
 111      * Fortunately there is not yet anything in there that affects migration.
 112      */
 113
 114     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
 115                           ARM_CP15_REG32(0, 0, 1, 4));
 116     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
 117                           ARM_CP15_REG32(0, 0, 1, 5));
 118     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
 119                           ARM_CP15_REG32(0, 0, 1, 6));
 120     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
 121                           ARM_CP15_REG32(0, 0, 1, 7));
 122     if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
 123                        ARM_CP15_REG32(0, 0, 2, 6))) {
 124         /*
 125          * Older kernels don't support reading ID_MMFR4 (a new in v8
 126          * register); assume it's zero.
 127          */
 128         ahcf->isar.id_mmfr4 = 0;
 129     }
 130
 131     /*
 132      * There is no way to read DBGDIDR, because currently 32-bit KVM
 133      * doesn't implement debug at all. Leave it at zero.
 134      */
 135
 136     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 137
 138     if (err < 0) {
 139         return false;
 140     }
 141
 142     /* Now we've retrieved all the register information we can
 143      * set the feature bits based on the ID register fields.
 144      * We can assume any KVM supporting CPU is at least a v7
 145      * with VFPv3, virtualization extensions, and the generic
 146      * timers; this in turn implies most of the other feature
 147      * bits, but a few must be tested.
 148      */
 149     set_feature(&features, ARM_FEATURE_V7VE);
 150     set_feature(&features, ARM_FEATURE_VFP3);
 151     set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 152
 153     if (extract32(id_pfr0, 12, 4) == 1) {
 154         set_feature(&features, ARM_FEATURE_THUMB2EE);
 155     }
 156     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
 157         set_feature(&features, ARM_FEATURE_NEON);
 158     }
 159     if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
 160         /* FMAC support implies VFPv4 */
 161         set_feature(&features, ARM_FEATURE_VFP4);
 162     }
 163
 164     ahcf->features = features;
 165
 166     return true;
 167 }
 168
 169 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 170 {
 171     /* Return true if the regidx is a register we should synchronize
 172      * via the cpreg_tuples array (ie is not a core reg we sync by
 173      * hand in kvm_arch_get/put_registers())
 174      */
 175     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 176     case KVM_REG_ARM_CORE:
 177     case KVM_REG_ARM_VFP:
 178         return false;
 179     default:
 180         return true;
 181     }
 182 }
 183
 184 typedef struct CPRegStateLevel {
 185     uint64_t regidx;
 186     int level;
 187 } CPRegStateLevel;
 188
 189 /* All coprocessor registers not listed in the following table are assumed to
 190  * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
 191  * often, you must add it to this table with a state of either
 192  * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
 193  */
 194 static const CPRegStateLevel non_runtime_cpregs[] = {
 195     { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
 196 };
 197
 198 int kvm_arm_cpreg_level(uint64_t regidx)
 199 {
 200     int i;
 201
 202     for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
 203         const CPRegStateLevel *l = &non_runtime_cpregs[i];
 204         if (l->regidx == regidx) {
 205             return l->level;
 206         }
 207     }
 208
 209     return KVM_PUT_RUNTIME_STATE;
 210 }
 211
 212 #define ARM_CPU_ID_MPIDR       0, 0, 0, 5
 213
 214 int kvm_arch_init_vcpu(CPUState *cs)
 215 {
 216     int ret;
 217     uint64_t v;
 218     uint32_t mpidr;
 219     struct kvm_one_reg r;
 220     ARMCPU *cpu = ARM_CPU(cs);
 221
 222     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 223         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 224         return -EINVAL;
 225     }
 226
 227     qemu_add_vm_change_state_handler(kvm_arm_vm_state_change, cs);
 228
 229     /* Determine init features for this CPU */
 230     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 231     if (cpu->start_powered_off) {
 232         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 233     }
 234     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 235         cpu->psci_version = 2;
 236         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 237     }
 238
 239     /* Do KVM_ARM_VCPU_INIT ioctl */
 240     ret = kvm_arm_vcpu_init(cs);
 241     if (ret) {
 242         return ret;
 243     }
 244
 245     /* Query the kernel to make sure it supports 32 VFP
 246      * registers: QEMU's "cortex-a15" CPU is always a
 247      * VFP-D32 core. The simplest way to do this is just
 248      * to attempt to read register d31.
 249      */
 250     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 251     r.addr = (uintptr_t)(&v);
 252     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 253     if (ret == -ENOENT) {
 254         return -EINVAL;
 255     }
 256
 257     /*
 258      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 259      * Currently KVM has its own idea about MPIDR assignment, so we
 260      * override our defaults with what we get from KVM.
 261      */
 262     ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
 263     if (ret) {
 264         return ret;
 265     }
 266     cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 267
 268     /* Check whether userspace can specify guest syndrome value */
 269     kvm_arm_init_serror_injection(cs);
 270
 271     return kvm_arm_init_cpreg_list(cpu);
 272 }
 273
 274 int kvm_arch_destroy_vcpu(CPUState *cs)
 275 {
 276         return 0;
 277 }
 278
 279 typedef struct Reg {
 280     uint64_t id;
 281     int offset;
 282 } Reg;
 283
 284 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 285     {                                                        \
 286         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 287         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 288         offsetof(CPUARMState, QEMUFIELD)                     \
 289     }
 290
 291 #define VFPSYSREG(R)                                       \
 292     {                                                      \
 293         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 294         KVM_REG_ARM_VFP_##R,                               \
 295         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 296     }
 297
 298 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 299 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 300     {                                                        \
 301         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 302         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 303         offsetoflow32(CPUARMState, QEMUFIELD)                \
 304     }
 305
 306 static const Reg regs[] = {
 307     /* R0_usr .. R14_usr */
 308     COREREG(usr_regs.uregs[0], regs[0]),
 309     COREREG(usr_regs.uregs[1], regs[1]),
 310     COREREG(usr_regs.uregs[2], regs[2]),
 311     COREREG(usr_regs.uregs[3], regs[3]),
 312     COREREG(usr_regs.uregs[4], regs[4]),
 313     COREREG(usr_regs.uregs[5], regs[5]),
 314     COREREG(usr_regs.uregs[6], regs[6]),
 315     COREREG(usr_regs.uregs[7], regs[7]),
 316     COREREG(usr_regs.uregs[8], usr_regs[0]),
 317     COREREG(usr_regs.uregs[9], usr_regs[1]),
 318     COREREG(usr_regs.uregs[10], usr_regs[2]),
 319     COREREG(usr_regs.uregs[11], usr_regs[3]),
 320     COREREG(usr_regs.uregs[12], usr_regs[4]),
 321     COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
 322     COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
 323     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 324     COREREG(svc_regs[0], banked_r13[BANK_SVC]),
 325     COREREG(svc_regs[1], banked_r14[BANK_SVC]),
 326     COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
 327     COREREG(abt_regs[0], banked_r13[BANK_ABT]),
 328     COREREG(abt_regs[1], banked_r14[BANK_ABT]),
 329     COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
 330     COREREG(und_regs[0], banked_r13[BANK_UND]),
 331     COREREG(und_regs[1], banked_r14[BANK_UND]),
 332     COREREG64(und_regs[2], banked_spsr[BANK_UND]),
 333     COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
 334     COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
 335     COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
 336     /* R8_fiq .. R14_fiq and SPSR_fiq */
 337     COREREG(fiq_regs[0], fiq_regs[0]),
 338     COREREG(fiq_regs[1], fiq_regs[1]),
 339     COREREG(fiq_regs[2], fiq_regs[2]),
 340     COREREG(fiq_regs[3], fiq_regs[3]),
 341     COREREG(fiq_regs[4], fiq_regs[4]),
 342     COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
 343     COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
 344     COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
 345     /* R15 */
 346     COREREG(usr_regs.uregs[15], regs[15]),
 347     /* VFP system registers */
 348     VFPSYSREG(FPSID),
 349     VFPSYSREG(MVFR1),
 350     VFPSYSREG(MVFR0),
 351     VFPSYSREG(FPEXC),
 352     VFPSYSREG(FPINST),
 353     VFPSYSREG(FPINST2),
 354 };
 355
 356 int kvm_arch_put_registers(CPUState *cs, int level)
 357 {
 358     ARMCPU *cpu = ARM_CPU(cs);
 359     CPUARMState *env = &cpu->env;
 360     struct kvm_one_reg r;
 361     int mode, bn;
 362     int ret, i;
 363     uint32_t cpsr, fpscr;
 364
 365     /* Make sure the banked regs are properly set */
 366     mode = env->uncached_cpsr & CPSR_M;
 367     bn = bank_number(mode);
 368     if (mode == ARM_CPU_MODE_FIQ) {
 369         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 370     } else {
 371         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 372     }
 373     env->banked_r13[bn] = env->regs[13];
 374     env->banked_spsr[bn] = env->spsr;
 375     env->banked_r14[r14_bank_number(mode)] = env->regs[14];
 376
 377     /* Now we can safely copy stuff down to the kernel */
 378     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 379         r.id = regs[i].id;
 380         r.addr = (uintptr_t)(env) + regs[i].offset;
 381         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 382         if (ret) {
 383             return ret;
 384         }
 385     }
 386
 387     /* Special cases which aren't a single CPUARMState field */
 388     cpsr = cpsr_read(env);
 389     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 390         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 391     r.addr = (uintptr_t)(&cpsr);
 392     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 393     if (ret) {
 394         return ret;
 395     }
 396
 397     /* VFP registers */
 398     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 399     for (i = 0; i < 32; i++) {
 400         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 401         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 402         if (ret) {
 403             return ret;
 404         }
 405         r.id++;
 406     }
 407
 408     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 409         KVM_REG_ARM_VFP_FPSCR;
 410     fpscr = vfp_get_fpscr(env);
 411     r.addr = (uintptr_t)&fpscr;
 412     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 413     if (ret) {
 414         return ret;
 415     }
 416
 417     ret = kvm_put_vcpu_events(cpu);
 418     if (ret) {
 419         return ret;
 420     }
 421
 422     write_cpustate_to_list(cpu, true);
 423
 424     if (!write_list_to_kvmstate(cpu, level)) {
 425         return EINVAL;
 426     }
 427
 428     kvm_arm_sync_mpstate_to_kvm(cpu);
 429
 430     return ret;
 431 }
 432
 433 int kvm_arch_get_registers(CPUState *cs)
 434 {
 435     ARMCPU *cpu = ARM_CPU(cs);
 436     CPUARMState *env = &cpu->env;
 437     struct kvm_one_reg r;
 438     int mode, bn;
 439     int ret, i;
 440     uint32_t cpsr, fpscr;
 441
 442     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 443         r.id = regs[i].id;
 444         r.addr = (uintptr_t)(env) + regs[i].offset;
 445         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 446         if (ret) {
 447             return ret;
 448         }
 449     }
 450
 451     /* Special cases which aren't a single CPUARMState field */
 452     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 453         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 454     r.addr = (uintptr_t)(&cpsr);
 455     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 456     if (ret) {
 457         return ret;
 458     }
 459     cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
 460
 461     /* Make sure the current mode regs are properly set */
 462     mode = env->uncached_cpsr & CPSR_M;
 463     bn = bank_number(mode);
 464     if (mode == ARM_CPU_MODE_FIQ) {
 465         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 466     } else {
 467         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 468     }
 469     env->regs[13] = env->banked_r13[bn];
 470     env->spsr = env->banked_spsr[bn];
 471     env->regs[14] = env->banked_r14[r14_bank_number(mode)];
 472
 473     /* VFP registers */
 474     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 475     for (i = 0; i < 32; i++) {
 476         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 477         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 478         if (ret) {
 479             return ret;
 480         }
 481         r.id++;
 482     }
 483
 484     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 485         KVM_REG_ARM_VFP_FPSCR;
 486     r.addr = (uintptr_t)&fpscr;
 487     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 488     if (ret) {
 489         return ret;
 490     }
 491     vfp_set_fpscr(env, fpscr);
 492
 493     ret = kvm_get_vcpu_events(cpu);
 494     if (ret) {
 495         return ret;
 496     }
 497
 498     if (!write_kvmstate_to_list(cpu)) {
 499         return EINVAL;
 500     }
 501     /* Note that it's OK to have registers which aren't in CPUState,
 502      * so we can ignore a failure return here.
 503      */
 504     write_list_to_cpustate(cpu);
 505
 506     kvm_arm_sync_mpstate_to_qemu(cpu);
 507
 508     return 0;
 509 }
 510
 511 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 512 {
 513     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 514     return -EINVAL;
 515 }
 516
 517 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 518 {
 519     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 520     return -EINVAL;
 521 }
 522
 523 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 524 {
 525     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 526     return false;
 527 }
 528
 529 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 530                                   target_ulong len, int type)
 531 {
 532     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 533     return -EINVAL;
 534 }
 535
 536 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 537                                   target_ulong len, int type)
 538 {
 539     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 540     return -EINVAL;
 541 }
 542
 543 void kvm_arch_remove_all_hw_breakpoints(void)
 544 {
 545     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 546 }
 547
 548 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
 549 {
 550     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 551 }
 552
 553 bool kvm_arm_hw_debug_active(CPUState *cs)
 554 {
 555     return false;
 556 }
 557
 558 void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
 559 {
 560     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 561 }
 562
 563 void kvm_arm_pmu_init(CPUState *cs)
 564 {
 565     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 566 }