3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg/tcg-op.h"
38 #include "qemu/qemu-print.h"
39 #include "exec/cpu_ldst.h"
40 #include "semihosting/semihost.h"
41 #include "exec/translator.h"
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
48 #define HELPER_H "helper.h"
49 #include "exec/helper-info.c.inc"
54 DisasContextBase base
;
55 const XtensaConfig
*config
;
77 xtensa_insnbuf_word insnbuf
[MAX_INSNBUF_LENGTH
];
78 xtensa_insnbuf_word slotbuf
[MAX_INSNBUF_LENGTH
];
81 static TCGv_i32 cpu_pc
;
82 static TCGv_i32 cpu_R
[16];
83 static TCGv_i32 cpu_FR
[16];
84 static TCGv_i64 cpu_FRD
[16];
85 static TCGv_i32 cpu_MR
[4];
86 static TCGv_i32 cpu_BR
[16];
87 static TCGv_i32 cpu_BR4
[4];
88 static TCGv_i32 cpu_BR8
[2];
89 static TCGv_i32 cpu_SR
[256];
90 static TCGv_i32 cpu_UR
[256];
91 static TCGv_i32 cpu_windowbase_next
;
92 static TCGv_i32 cpu_exclusive_addr
;
93 static TCGv_i32 cpu_exclusive_val
;
95 static GHashTable
*xtensa_regfile_table
;
97 static char *sr_name
[256];
98 static char *ur_name
[256];
100 void xtensa_collect_sr_names(const XtensaConfig
*config
)
102 xtensa_isa isa
= config
->isa
;
103 int n
= xtensa_isa_num_sysregs(isa
);
106 for (i
= 0; i
< n
; ++i
) {
107 int sr
= xtensa_sysreg_number(isa
, i
);
109 if (sr
>= 0 && sr
< 256) {
110 const char *name
= xtensa_sysreg_name(isa
, i
);
112 (xtensa_sysreg_is_user(isa
, i
) ? ur_name
: sr_name
) + sr
;
115 if (strstr(*pname
, name
) == NULL
) {
117 malloc(strlen(*pname
) + strlen(name
) + 2);
119 strcpy(new_name
, *pname
);
120 strcat(new_name
, "/");
121 strcat(new_name
, name
);
126 *pname
= strdup(name
);
132 void xtensa_translate_init(void)
134 static const char * const regnames
[] = {
135 "ar0", "ar1", "ar2", "ar3",
136 "ar4", "ar5", "ar6", "ar7",
137 "ar8", "ar9", "ar10", "ar11",
138 "ar12", "ar13", "ar14", "ar15",
140 static const char * const fregnames
[] = {
141 "f0", "f1", "f2", "f3",
142 "f4", "f5", "f6", "f7",
143 "f8", "f9", "f10", "f11",
144 "f12", "f13", "f14", "f15",
146 static const char * const mregnames
[] = {
147 "m0", "m1", "m2", "m3",
149 static const char * const bregnames
[] = {
150 "b0", "b1", "b2", "b3",
151 "b4", "b5", "b6", "b7",
152 "b8", "b9", "b10", "b11",
153 "b12", "b13", "b14", "b15",
157 cpu_pc
= tcg_global_mem_new_i32(tcg_env
,
158 offsetof(CPUXtensaState
, pc
), "pc");
160 for (i
= 0; i
< 16; i
++) {
161 cpu_R
[i
] = tcg_global_mem_new_i32(tcg_env
,
162 offsetof(CPUXtensaState
, regs
[i
]),
166 for (i
= 0; i
< 16; i
++) {
167 cpu_FR
[i
] = tcg_global_mem_new_i32(tcg_env
,
168 offsetof(CPUXtensaState
,
169 fregs
[i
].f32
[FP_F32_LOW
]),
173 for (i
= 0; i
< 16; i
++) {
174 cpu_FRD
[i
] = tcg_global_mem_new_i64(tcg_env
,
175 offsetof(CPUXtensaState
,
180 for (i
= 0; i
< 4; i
++) {
181 cpu_MR
[i
] = tcg_global_mem_new_i32(tcg_env
,
182 offsetof(CPUXtensaState
,
187 for (i
= 0; i
< 16; i
++) {
188 cpu_BR
[i
] = tcg_global_mem_new_i32(tcg_env
,
189 offsetof(CPUXtensaState
,
193 cpu_BR4
[i
/ 4] = tcg_global_mem_new_i32(tcg_env
,
194 offsetof(CPUXtensaState
,
199 cpu_BR8
[i
/ 8] = tcg_global_mem_new_i32(tcg_env
,
200 offsetof(CPUXtensaState
,
206 for (i
= 0; i
< 256; ++i
) {
208 cpu_SR
[i
] = tcg_global_mem_new_i32(tcg_env
,
209 offsetof(CPUXtensaState
,
215 for (i
= 0; i
< 256; ++i
) {
217 cpu_UR
[i
] = tcg_global_mem_new_i32(tcg_env
,
218 offsetof(CPUXtensaState
,
224 cpu_windowbase_next
=
225 tcg_global_mem_new_i32(tcg_env
,
226 offsetof(CPUXtensaState
, windowbase_next
),
229 tcg_global_mem_new_i32(tcg_env
,
230 offsetof(CPUXtensaState
, exclusive_addr
),
233 tcg_global_mem_new_i32(tcg_env
,
234 offsetof(CPUXtensaState
, exclusive_val
),
238 void **xtensa_get_regfile_by_name(const char *name
, int entries
, int bits
)
243 if (xtensa_regfile_table
== NULL
) {
244 xtensa_regfile_table
= g_hash_table_new(g_str_hash
, g_str_equal
);
246 * AR is special. Xtensa translator uses it as a current register
247 * window, but configuration overlays represent it as a complete
248 * physical register file.
250 g_hash_table_insert(xtensa_regfile_table
,
251 (void *)"AR 16x32", (void *)cpu_R
);
252 g_hash_table_insert(xtensa_regfile_table
,
253 (void *)"AR 32x32", (void *)cpu_R
);
254 g_hash_table_insert(xtensa_regfile_table
,
255 (void *)"AR 64x32", (void *)cpu_R
);
257 g_hash_table_insert(xtensa_regfile_table
,
258 (void *)"MR 4x32", (void *)cpu_MR
);
260 g_hash_table_insert(xtensa_regfile_table
,
261 (void *)"FR 16x32", (void *)cpu_FR
);
262 g_hash_table_insert(xtensa_regfile_table
,
263 (void *)"FR 16x64", (void *)cpu_FRD
);
265 g_hash_table_insert(xtensa_regfile_table
,
266 (void *)"BR 16x1", (void *)cpu_BR
);
267 g_hash_table_insert(xtensa_regfile_table
,
268 (void *)"BR4 4x4", (void *)cpu_BR4
);
269 g_hash_table_insert(xtensa_regfile_table
,
270 (void *)"BR8 2x8", (void *)cpu_BR8
);
273 geometry_name
= g_strdup_printf("%s %dx%d", name
, entries
, bits
);
274 res
= (void **)g_hash_table_lookup(xtensa_regfile_table
, geometry_name
);
275 g_free(geometry_name
);
279 static inline bool option_enabled(DisasContext
*dc
, int opt
)
281 return xtensa_option_enabled(dc
->config
, opt
);
284 static void init_sar_tracker(DisasContext
*dc
)
286 dc
->sar_5bit
= false;
287 dc
->sar_m32_5bit
= false;
291 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
293 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
294 if (dc
->sar_m32_5bit
) {
295 tcg_gen_discard_i32(dc
->sar_m32
);
298 dc
->sar_m32_5bit
= false;
301 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
304 dc
->sar_m32
= tcg_temp_new_i32();
306 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
307 tcg_gen_sub_i32(cpu_SR
[SAR
], tcg_constant_i32(32), dc
->sar_m32
);
308 dc
->sar_5bit
= false;
309 dc
->sar_m32_5bit
= true;
312 static void gen_exception(DisasContext
*dc
, int excp
)
314 gen_helper_exception(tcg_env
, tcg_constant_i32(excp
));
317 static void gen_exception_cause(DisasContext
*dc
, uint32_t cause
)
319 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
320 gen_helper_exception_cause(tcg_env
, pc
, tcg_constant_i32(cause
));
321 if (cause
== ILLEGAL_INSTRUCTION_CAUSE
||
322 cause
== SYSCALL_CAUSE
) {
323 dc
->base
.is_jmp
= DISAS_NORETURN
;
327 static void gen_debug_exception(DisasContext
*dc
, uint32_t cause
)
329 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
330 gen_helper_debug_exception(tcg_env
, pc
, tcg_constant_i32(cause
));
331 if (cause
& (DEBUGCAUSE_IB
| DEBUGCAUSE_BI
| DEBUGCAUSE_BN
)) {
332 dc
->base
.is_jmp
= DISAS_NORETURN
;
336 static bool gen_check_privilege(DisasContext
*dc
)
338 #ifndef CONFIG_USER_ONLY
343 gen_exception_cause(dc
, PRIVILEGED_CAUSE
);
344 dc
->base
.is_jmp
= DISAS_NORETURN
;
348 static bool gen_check_cpenable(DisasContext
*dc
, uint32_t cp_mask
)
350 cp_mask
&= ~dc
->cpenable
;
352 if (option_enabled(dc
, XTENSA_OPTION_COPROCESSOR
) && cp_mask
) {
353 gen_exception_cause(dc
, COPROCESSOR0_DISABLED
+ ctz32(cp_mask
));
354 dc
->base
.is_jmp
= DISAS_NORETURN
;
360 static int gen_postprocess(DisasContext
*dc
, int slot
);
362 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
364 tcg_gen_mov_i32(cpu_pc
, dest
);
366 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
368 if (dc
->op_flags
& XTENSA_OP_POSTPROCESS
) {
369 slot
= gen_postprocess(dc
, slot
);
372 tcg_gen_goto_tb(slot
);
373 tcg_gen_exit_tb(dc
->base
.tb
, slot
);
375 tcg_gen_exit_tb(NULL
, 0);
377 dc
->base
.is_jmp
= DISAS_NORETURN
;
380 static void gen_jump(DisasContext
*dc
, TCGv dest
)
382 gen_jump_slot(dc
, dest
, -1);
385 static int adjust_jump_slot(DisasContext
*dc
, uint32_t dest
, int slot
)
387 return translator_use_goto_tb(&dc
->base
, dest
) ? slot
: -1;
390 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
392 gen_jump_slot(dc
, tcg_constant_i32(dest
),
393 adjust_jump_slot(dc
, dest
, slot
));
396 static void gen_callw_slot(DisasContext
*dc
, int callinc
, TCGv_i32 dest
,
399 tcg_gen_deposit_i32(cpu_SR
[PS
], cpu_SR
[PS
],
400 tcg_constant_i32(callinc
), PS_CALLINC_SHIFT
, PS_CALLINC_LEN
);
401 tcg_gen_movi_i32(cpu_R
[callinc
<< 2],
402 (callinc
<< 30) | (dc
->base
.pc_next
& 0x3fffffff));
403 gen_jump_slot(dc
, dest
, slot
);
406 static bool gen_check_loop_end(DisasContext
*dc
, int slot
)
408 if (dc
->base
.pc_next
== dc
->lend
) {
409 TCGLabel
*label
= gen_new_label();
411 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_SR
[LCOUNT
], 0, label
);
412 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], cpu_SR
[LCOUNT
], 1);
414 gen_jumpi(dc
, dc
->base
.pc_next
- dc
->lbeg_off
, slot
);
416 gen_jump(dc
, cpu_SR
[LBEG
]);
418 gen_set_label(label
);
419 gen_jumpi(dc
, dc
->base
.pc_next
, -1);
425 static void gen_jumpi_check_loop_end(DisasContext
*dc
, int slot
)
427 if (!gen_check_loop_end(dc
, slot
)) {
428 gen_jumpi(dc
, dc
->base
.pc_next
, slot
);
432 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
433 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t addr
)
435 TCGLabel
*label
= gen_new_label();
437 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
438 gen_jumpi_check_loop_end(dc
, 0);
439 gen_set_label(label
);
440 gen_jumpi(dc
, addr
, 1);
443 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
444 TCGv_i32 t0
, uint32_t t1
, uint32_t addr
)
446 gen_brcond(dc
, cond
, t0
, tcg_constant_i32(t1
), addr
);
449 static uint32_t test_exceptions_sr(DisasContext
*dc
, const OpcodeArg arg
[],
450 const uint32_t par
[])
452 return xtensa_option_enabled(dc
->config
, par
[1]) ? 0 : XTENSA_OP_ILL
;
455 static uint32_t test_exceptions_ccompare(DisasContext
*dc
,
456 const OpcodeArg arg
[],
457 const uint32_t par
[])
459 unsigned n
= par
[0] - CCOMPARE
;
461 if (n
>= dc
->config
->nccompare
) {
462 return XTENSA_OP_ILL
;
464 return test_exceptions_sr(dc
, arg
, par
);
467 static uint32_t test_exceptions_dbreak(DisasContext
*dc
, const OpcodeArg arg
[],
468 const uint32_t par
[])
470 unsigned n
= MAX_NDBREAK
;
472 if (par
[0] >= DBREAKA
&& par
[0] < DBREAKA
+ MAX_NDBREAK
) {
473 n
= par
[0] - DBREAKA
;
475 if (par
[0] >= DBREAKC
&& par
[0] < DBREAKC
+ MAX_NDBREAK
) {
476 n
= par
[0] - DBREAKC
;
478 if (n
>= dc
->config
->ndbreak
) {
479 return XTENSA_OP_ILL
;
481 return test_exceptions_sr(dc
, arg
, par
);
484 static uint32_t test_exceptions_ibreak(DisasContext
*dc
, const OpcodeArg arg
[],
485 const uint32_t par
[])
487 unsigned n
= par
[0] - IBREAKA
;
489 if (n
>= dc
->config
->nibreak
) {
490 return XTENSA_OP_ILL
;
492 return test_exceptions_sr(dc
, arg
, par
);
495 static uint32_t test_exceptions_hpi(DisasContext
*dc
, const OpcodeArg arg
[],
496 const uint32_t par
[])
498 unsigned n
= MAX_NLEVEL
+ 1;
500 if (par
[0] >= EXCSAVE1
&& par
[0] < EXCSAVE1
+ MAX_NLEVEL
) {
501 n
= par
[0] - EXCSAVE1
+ 1;
503 if (par
[0] >= EPC1
&& par
[0] < EPC1
+ MAX_NLEVEL
) {
504 n
= par
[0] - EPC1
+ 1;
506 if (par
[0] >= EPS2
&& par
[0] < EPS2
+ MAX_NLEVEL
- 1) {
507 n
= par
[0] - EPS2
+ 2;
509 if (n
> dc
->config
->nlevel
) {
510 return XTENSA_OP_ILL
;
512 return test_exceptions_sr(dc
, arg
, par
);
515 static MemOp
gen_load_store_alignment(DisasContext
*dc
, MemOp mop
,
518 if ((mop
& MO_SIZE
) == MO_8
) {
521 if ((mop
& MO_AMASK
) == MO_UNALN
&&
522 !option_enabled(dc
, XTENSA_OPTION_HW_ALIGNMENT
)) {
525 if (!option_enabled(dc
, XTENSA_OPTION_UNALIGNED_EXCEPTION
)) {
526 tcg_gen_andi_i32(addr
, addr
, ~0 << get_alignment_bits(mop
));
531 static bool gen_window_check(DisasContext
*dc
, uint32_t mask
)
533 unsigned r
= 31 - clz32(mask
);
535 if (r
/ 4 > dc
->window
) {
536 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
537 TCGv_i32 w
= tcg_constant_i32(r
/ 4);
539 gen_helper_window_check(tcg_env
, pc
, w
);
540 dc
->base
.is_jmp
= DISAS_NORETURN
;
546 static TCGv_i32
gen_mac16_m(TCGv_i32 v
, bool hi
, bool is_unsigned
)
548 TCGv_i32 m
= tcg_temp_new_i32();
551 (is_unsigned
? tcg_gen_shri_i32
: tcg_gen_sari_i32
)(m
, v
, 16);
553 (is_unsigned
? tcg_gen_ext16u_i32
: tcg_gen_ext16s_i32
)(m
, v
);
558 static void gen_zero_check(DisasContext
*dc
, const OpcodeArg arg
[])
560 TCGLabel
*label
= gen_new_label();
562 tcg_gen_brcondi_i32(TCG_COND_NE
, arg
[2].in
, 0, label
);
563 gen_exception_cause(dc
, INTEGER_DIVIDE_BY_ZERO_CAUSE
);
564 gen_set_label(label
);
567 static inline unsigned xtensa_op0_insn_len(DisasContext
*dc
, uint8_t op0
)
569 return xtensa_isa_length_from_chars(dc
->config
->isa
, &op0
);
572 static int gen_postprocess(DisasContext
*dc
, int slot
)
574 uint32_t op_flags
= dc
->op_flags
;
576 #ifndef CONFIG_USER_ONLY
577 if (op_flags
& XTENSA_OP_CHECK_INTERRUPTS
) {
578 translator_io_start(&dc
->base
);
579 gen_helper_check_interrupts(tcg_env
);
582 if (op_flags
& XTENSA_OP_SYNC_REGISTER_WINDOW
) {
583 gen_helper_sync_windowbase(tcg_env
);
585 if (op_flags
& XTENSA_OP_EXIT_TB_M1
) {
591 struct opcode_arg_copy
{
597 struct opcode_arg_info
{
603 XtensaOpcodeOps
*ops
;
604 OpcodeArg arg
[MAX_OPCODE_ARGS
];
605 struct opcode_arg_info in
[MAX_OPCODE_ARGS
];
606 struct opcode_arg_info out
[MAX_OPCODE_ARGS
];
618 static uint32_t encode_resource(enum resource_type r
, unsigned g
, unsigned n
)
620 assert(r
< RES_MAX
&& g
< 256 && n
< 65536);
621 return (r
<< 24) | (g
<< 16) | n
;
624 static enum resource_type
get_resource_type(uint32_t resource
)
626 return resource
>> 24;
630 * a depends on b if b must be executed before a,
631 * because a's side effects will destroy b's inputs.
633 static bool op_depends_on(const struct slot_prop
*a
,
634 const struct slot_prop
*b
)
639 if (a
->op_flags
& XTENSA_OP_CONTROL_FLOW
) {
642 if ((a
->op_flags
& XTENSA_OP_LOAD_STORE
) <
643 (b
->op_flags
& XTENSA_OP_LOAD_STORE
)) {
646 while (i
< a
->n_out
&& j
< b
->n_in
) {
647 if (a
->out
[i
].resource
< b
->in
[j
].resource
) {
649 } else if (a
->out
[i
].resource
> b
->in
[j
].resource
) {
659 * Try to break a dependency on b, append temporary register copy records
660 * to the end of copy and update n_copy in case of success.
661 * This is not always possible: e.g. control flow must always be the last,
662 * load/store must be first and state dependencies are not supported yet.
664 static bool break_dependency(struct slot_prop
*a
,
666 struct opcode_arg_copy
*copy
,
671 unsigned n
= *n_copy
;
674 if (a
->op_flags
& XTENSA_OP_CONTROL_FLOW
) {
677 if ((a
->op_flags
& XTENSA_OP_LOAD_STORE
) <
678 (b
->op_flags
& XTENSA_OP_LOAD_STORE
)) {
681 while (i
< a
->n_out
&& j
< b
->n_in
) {
682 if (a
->out
[i
].resource
< b
->in
[j
].resource
) {
684 } else if (a
->out
[i
].resource
> b
->in
[j
].resource
) {
687 int index
= b
->in
[j
].index
;
689 if (get_resource_type(a
->out
[i
].resource
) != RES_REGFILE
||
693 copy
[n
].resource
= b
->in
[j
].resource
;
694 copy
[n
].arg
= b
->arg
+ index
;
705 * Calculate evaluation order for slot opcodes.
706 * Build opcode order graph and output its nodes in topological sort order.
707 * An edge a -> b in the graph means that opcode a must be followed by
710 static bool tsort(struct slot_prop
*slot
,
711 struct slot_prop
*sorted
[],
713 struct opcode_arg_copy
*copy
,
719 unsigned out_edge
[MAX_INSN_SLOTS
];
720 } node
[MAX_INSN_SLOTS
];
722 unsigned in
[MAX_INSN_SLOTS
];
728 unsigned node_idx
= 0;
730 for (i
= 0; i
< n
; ++i
) {
731 node
[i
].n_in_edge
= 0;
732 node
[i
].n_out_edge
= 0;
735 for (i
= 0; i
< n
; ++i
) {
736 unsigned n_out_edge
= 0;
738 for (j
= 0; j
< n
; ++j
) {
739 if (i
!= j
&& op_depends_on(slot
+ j
, slot
+ i
)) {
740 node
[i
].out_edge
[n_out_edge
] = j
;
746 node
[i
].n_out_edge
= n_out_edge
;
749 for (i
= 0; i
< n
; ++i
) {
750 if (!node
[i
].n_in_edge
) {
757 for (; in_idx
< n_in
; ++in_idx
) {
759 sorted
[n_out
] = slot
+ i
;
761 for (j
= 0; j
< node
[i
].n_out_edge
; ++j
) {
763 if (--node
[node
[i
].out_edge
[j
]].n_in_edge
== 0) {
764 in
[n_in
] = node
[i
].out_edge
[j
];
770 for (; node_idx
< n
; ++node_idx
) {
771 struct tsnode
*cnode
= node
+ node_idx
;
773 if (cnode
->n_in_edge
) {
774 for (j
= 0; j
< cnode
->n_out_edge
; ++j
) {
775 unsigned k
= cnode
->out_edge
[j
];
777 if (break_dependency(slot
+ k
, slot
+ node_idx
,
779 --node
[k
].n_in_edge
== 0) {
784 cnode
->out_edge
[cnode
->n_out_edge
- 1];
795 static void opcode_add_resource(struct slot_prop
*op
,
796 uint32_t resource
, char direction
,
802 assert(op
->n_in
< ARRAY_SIZE(op
->in
));
803 op
->in
[op
->n_in
].resource
= resource
;
804 op
->in
[op
->n_in
].index
= index
;
808 if (direction
== 'm' || direction
== 'o') {
809 assert(op
->n_out
< ARRAY_SIZE(op
->out
));
810 op
->out
[op
->n_out
].resource
= resource
;
811 op
->out
[op
->n_out
].index
= index
;
816 g_assert_not_reached();
820 static int resource_compare(const void *a
, const void *b
)
822 const struct opcode_arg_info
*pa
= a
;
823 const struct opcode_arg_info
*pb
= b
;
825 return pa
->resource
< pb
->resource
?
826 -1 : (pa
->resource
> pb
->resource
? 1 : 0);
829 static int arg_copy_compare(const void *a
, const void *b
)
831 const struct opcode_arg_copy
*pa
= a
;
832 const struct opcode_arg_copy
*pb
= b
;
834 return pa
->resource
< pb
->resource
?
835 -1 : (pa
->resource
> pb
->resource
? 1 : 0);
838 static void disas_xtensa_insn(CPUXtensaState
*env
, DisasContext
*dc
)
840 xtensa_isa isa
= dc
->config
->isa
;
841 unsigned char b
[MAX_INSN_LENGTH
] = {translator_ldub(env
, &dc
->base
,
843 unsigned len
= xtensa_op0_insn_len(dc
, b
[0]);
847 uint32_t op_flags
= 0;
848 struct slot_prop slot_prop
[MAX_INSN_SLOTS
];
849 struct slot_prop
*ordered
[MAX_INSN_SLOTS
];
850 struct opcode_arg_copy arg_copy
[MAX_INSN_SLOTS
* MAX_OPCODE_ARGS
];
851 unsigned n_arg_copy
= 0;
852 uint32_t debug_cause
= 0;
853 uint32_t windowed_register
= 0;
854 uint32_t coprocessor
= 0;
856 if (len
== XTENSA_UNDEFINED
) {
857 qemu_log_mask(LOG_GUEST_ERROR
,
858 "unknown instruction length (pc = %08x)\n",
860 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
861 dc
->base
.pc_next
= dc
->pc
+ 1;
865 dc
->base
.pc_next
= dc
->pc
+ len
;
866 for (i
= 1; i
< len
; ++i
) {
867 b
[i
] = translator_ldub(env
, &dc
->base
, dc
->pc
+ i
);
869 xtensa_insnbuf_from_chars(isa
, dc
->insnbuf
, b
, len
);
870 fmt
= xtensa_format_decode(isa
, dc
->insnbuf
);
871 if (fmt
== XTENSA_UNDEFINED
) {
872 qemu_log_mask(LOG_GUEST_ERROR
,
873 "unrecognized instruction format (pc = %08x)\n",
875 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
878 slots
= xtensa_format_num_slots(isa
, fmt
);
879 for (slot
= 0; slot
< slots
; ++slot
) {
881 int opnd
, vopnd
, opnds
;
882 OpcodeArg
*arg
= slot_prop
[slot
].arg
;
883 XtensaOpcodeOps
*ops
;
885 xtensa_format_get_slot(isa
, fmt
, slot
, dc
->insnbuf
, dc
->slotbuf
);
886 opc
= xtensa_opcode_decode(isa
, fmt
, slot
, dc
->slotbuf
);
887 if (opc
== XTENSA_UNDEFINED
) {
888 qemu_log_mask(LOG_GUEST_ERROR
,
889 "unrecognized opcode in slot %d (pc = %08x)\n",
891 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
894 opnds
= xtensa_opcode_num_operands(isa
, opc
);
896 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
897 void **register_file
= NULL
;
900 if (xtensa_operand_is_register(isa
, opc
, opnd
)) {
901 rf
= xtensa_operand_regfile(isa
, opc
, opnd
);
902 register_file
= dc
->config
->regfile
[rf
];
904 if (rf
== dc
->config
->a_regfile
) {
907 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
909 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
910 windowed_register
|= 1u << v
;
913 if (xtensa_operand_is_visible(isa
, opc
, opnd
)) {
916 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
918 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
919 arg
[vopnd
].raw_imm
= v
;
920 if (xtensa_operand_is_PCrelative(isa
, opc
, opnd
)) {
921 xtensa_operand_undo_reloc(isa
, opc
, opnd
, &v
, dc
->pc
);
925 arg
[vopnd
].in
= register_file
[v
];
926 arg
[vopnd
].out
= register_file
[v
];
927 arg
[vopnd
].num_bits
= xtensa_regfile_num_bits(isa
, rf
);
929 arg
[vopnd
].num_bits
= 32;
934 ops
= dc
->config
->opcode_ops
[opc
];
935 slot_prop
[slot
].ops
= ops
;
938 op_flags
|= ops
->op_flags
;
939 if (ops
->test_exceptions
) {
940 op_flags
|= ops
->test_exceptions(dc
, arg
, ops
->par
);
943 qemu_log_mask(LOG_UNIMP
,
944 "unimplemented opcode '%s' in slot %d (pc = %08x)\n",
945 xtensa_opcode_name(isa
, opc
), slot
, dc
->pc
);
946 op_flags
|= XTENSA_OP_ILL
;
948 if (op_flags
& XTENSA_OP_ILL
) {
949 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
952 if (op_flags
& XTENSA_OP_DEBUG_BREAK
) {
953 debug_cause
|= ops
->par
[0];
955 if (ops
->test_overflow
) {
956 windowed_register
|= ops
->test_overflow(dc
, arg
, ops
->par
);
958 coprocessor
|= ops
->coprocessor
;
961 slot_prop
[slot
].n_in
= 0;
962 slot_prop
[slot
].n_out
= 0;
963 slot_prop
[slot
].op_flags
= ops
->op_flags
& XTENSA_OP_LOAD_STORE
;
965 opnds
= xtensa_opcode_num_operands(isa
, opc
);
967 for (opnd
= vopnd
= 0; opnd
< opnds
; ++opnd
) {
968 bool visible
= xtensa_operand_is_visible(isa
, opc
, opnd
);
970 if (xtensa_operand_is_register(isa
, opc
, opnd
)) {
971 xtensa_regfile rf
= xtensa_operand_regfile(isa
, opc
, opnd
);
974 xtensa_operand_get_field(isa
, opc
, opnd
, fmt
, slot
,
976 xtensa_operand_decode(isa
, opc
, opnd
, &v
);
977 opcode_add_resource(slot_prop
+ slot
,
978 encode_resource(RES_REGFILE
, rf
, v
),
979 xtensa_operand_inout(isa
, opc
, opnd
),
980 visible
? vopnd
: -1);
987 opnds
= xtensa_opcode_num_stateOperands(isa
, opc
);
989 for (opnd
= 0; opnd
< opnds
; ++opnd
) {
990 xtensa_state state
= xtensa_stateOperand_state(isa
, opc
, opnd
);
992 opcode_add_resource(slot_prop
+ slot
,
993 encode_resource(RES_STATE
, 0, state
),
994 xtensa_stateOperand_inout(isa
, opc
, opnd
),
997 if (xtensa_opcode_is_branch(isa
, opc
) ||
998 xtensa_opcode_is_jump(isa
, opc
) ||
999 xtensa_opcode_is_loop(isa
, opc
) ||
1000 xtensa_opcode_is_call(isa
, opc
)) {
1001 slot_prop
[slot
].op_flags
|= XTENSA_OP_CONTROL_FLOW
;
1004 qsort(slot_prop
[slot
].in
, slot_prop
[slot
].n_in
,
1005 sizeof(slot_prop
[slot
].in
[0]), resource_compare
);
1006 qsort(slot_prop
[slot
].out
, slot_prop
[slot
].n_out
,
1007 sizeof(slot_prop
[slot
].out
[0]), resource_compare
);
1012 if (!tsort(slot_prop
, ordered
, slots
, arg_copy
, &n_arg_copy
)) {
1013 qemu_log_mask(LOG_UNIMP
,
1014 "Circular resource dependencies (pc = %08x)\n",
1016 gen_exception_cause(dc
, ILLEGAL_INSTRUCTION_CAUSE
);
1020 ordered
[0] = slot_prop
+ 0;
1023 if ((op_flags
& XTENSA_OP_PRIVILEGED
) &&
1024 !gen_check_privilege(dc
)) {
1028 if (op_flags
& XTENSA_OP_SYSCALL
) {
1029 gen_exception_cause(dc
, SYSCALL_CAUSE
);
1033 if ((op_flags
& XTENSA_OP_DEBUG_BREAK
) && dc
->debug
) {
1034 gen_debug_exception(dc
, debug_cause
);
1038 if (windowed_register
&& !gen_window_check(dc
, windowed_register
)) {
1042 if (op_flags
& XTENSA_OP_UNDERFLOW
) {
1043 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
1045 gen_helper_test_underflow_retw(tcg_env
, pc
);
1048 if (op_flags
& XTENSA_OP_ALLOCA
) {
1049 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
1051 gen_helper_movsp(tcg_env
, pc
);
1054 if (coprocessor
&& !gen_check_cpenable(dc
, coprocessor
)) {
1063 qsort(arg_copy
, n_arg_copy
, sizeof(*arg_copy
), arg_copy_compare
);
1064 for (i
= j
= 0; i
< n_arg_copy
; ++i
) {
1065 if (i
== 0 || arg_copy
[i
].resource
!= resource
) {
1066 resource
= arg_copy
[i
].resource
;
1067 if (arg_copy
[i
].arg
->num_bits
<= 32) {
1068 temp
= tcg_temp_new_i32();
1069 tcg_gen_mov_i32(temp
, arg_copy
[i
].arg
->in
);
1070 } else if (arg_copy
[i
].arg
->num_bits
<= 64) {
1071 temp
= tcg_temp_new_i64();
1072 tcg_gen_mov_i64(temp
, arg_copy
[i
].arg
->in
);
1074 g_assert_not_reached();
1076 arg_copy
[i
].temp
= temp
;
1079 arg_copy
[j
] = arg_copy
[i
];
1083 arg_copy
[i
].arg
->in
= temp
;
1088 if (op_flags
& XTENSA_OP_DIVIDE_BY_ZERO
) {
1089 for (slot
= 0; slot
< slots
; ++slot
) {
1090 if (slot_prop
[slot
].ops
->op_flags
& XTENSA_OP_DIVIDE_BY_ZERO
) {
1091 gen_zero_check(dc
, slot_prop
[slot
].arg
);
1096 dc
->op_flags
= op_flags
;
1098 for (slot
= 0; slot
< slots
; ++slot
) {
1099 struct slot_prop
*pslot
= ordered
[slot
];
1100 XtensaOpcodeOps
*ops
= pslot
->ops
;
1102 ops
->translate(dc
, pslot
->arg
, ops
->par
);
1105 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
1106 gen_postprocess(dc
, 0);
1108 if (op_flags
& XTENSA_OP_EXIT_TB_M1
) {
1109 /* Change in mmu index, memory mapping or tb->flags; exit tb */
1110 gen_jumpi_check_loop_end(dc
, -1);
1111 } else if (op_flags
& XTENSA_OP_EXIT_TB_0
) {
1112 gen_jumpi_check_loop_end(dc
, 0);
1114 gen_check_loop_end(dc
, 0);
1117 dc
->pc
= dc
->base
.pc_next
;
1120 static inline unsigned xtensa_insn_len(CPUXtensaState
*env
, DisasContext
*dc
)
1122 uint8_t b0
= cpu_ldub_code(env
, dc
->pc
);
1123 return xtensa_op0_insn_len(dc
, b0
);
1126 static void gen_ibreak_check(CPUXtensaState
*env
, DisasContext
*dc
)
1130 for (i
= 0; i
< dc
->config
->nibreak
; ++i
) {
1131 if ((env
->sregs
[IBREAKENABLE
] & (1 << i
)) &&
1132 env
->sregs
[IBREAKA
+ i
] == dc
->pc
) {
1133 gen_debug_exception(dc
, DEBUGCAUSE_IB
);
1139 static void xtensa_tr_init_disas_context(DisasContextBase
*dcbase
,
1142 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1143 CPUXtensaState
*env
= cpu_env(cpu
);
1144 uint32_t tb_flags
= dc
->base
.tb
->flags
;
1146 dc
->config
= env
->config
;
1147 dc
->pc
= dc
->base
.pc_first
;
1148 dc
->ring
= tb_flags
& XTENSA_TBFLAG_RING_MASK
;
1149 dc
->cring
= (tb_flags
& XTENSA_TBFLAG_EXCM
) ? 0 : dc
->ring
;
1150 dc
->lbeg_off
= (dc
->base
.tb
->cs_base
& XTENSA_CSBASE_LBEG_OFF_MASK
) >>
1151 XTENSA_CSBASE_LBEG_OFF_SHIFT
;
1152 dc
->lend
= (dc
->base
.tb
->cs_base
& XTENSA_CSBASE_LEND_MASK
) +
1153 (dc
->base
.pc_first
& TARGET_PAGE_MASK
);
1154 dc
->debug
= tb_flags
& XTENSA_TBFLAG_DEBUG
;
1155 dc
->icount
= tb_flags
& XTENSA_TBFLAG_ICOUNT
;
1156 dc
->cpenable
= (tb_flags
& XTENSA_TBFLAG_CPENABLE_MASK
) >>
1157 XTENSA_TBFLAG_CPENABLE_SHIFT
;
1158 dc
->window
= ((tb_flags
& XTENSA_TBFLAG_WINDOW_MASK
) >>
1159 XTENSA_TBFLAG_WINDOW_SHIFT
);
1160 dc
->cwoe
= tb_flags
& XTENSA_TBFLAG_CWOE
;
1161 dc
->callinc
= ((tb_flags
& XTENSA_TBFLAG_CALLINC_MASK
) >>
1162 XTENSA_TBFLAG_CALLINC_SHIFT
);
1163 init_sar_tracker(dc
);
1166 static void xtensa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1168 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1171 dc
->next_icount
= tcg_temp_new_i32();
1175 static void xtensa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
1177 tcg_gen_insn_start(dcbase
->pc_next
);
1180 static void xtensa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
1182 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1183 CPUXtensaState
*env
= cpu_env(cpu
);
1184 target_ulong page_start
;
1186 /* These two conditions only apply to the first insn in the TB,
1187 but this is the first TranslateOps hook that allows exiting. */
1188 if ((tb_cflags(dc
->base
.tb
) & CF_USE_ICOUNT
)
1189 && (dc
->base
.tb
->flags
& XTENSA_TBFLAG_YIELD
)) {
1190 gen_exception(dc
, EXCP_YIELD
);
1191 dc
->base
.pc_next
= dc
->pc
+ 1;
1192 dc
->base
.is_jmp
= DISAS_NORETURN
;
1197 TCGLabel
*label
= gen_new_label();
1199 tcg_gen_addi_i32(dc
->next_icount
, cpu_SR
[ICOUNT
], 1);
1200 tcg_gen_brcondi_i32(TCG_COND_NE
, dc
->next_icount
, 0, label
);
1201 tcg_gen_mov_i32(dc
->next_icount
, cpu_SR
[ICOUNT
]);
1203 gen_debug_exception(dc
, DEBUGCAUSE_IC
);
1205 gen_set_label(label
);
1209 gen_ibreak_check(env
, dc
);
1212 disas_xtensa_insn(env
, dc
);
1215 tcg_gen_mov_i32(cpu_SR
[ICOUNT
], dc
->next_icount
);
1218 /* End the TB if the next insn will cross into the next page. */
1219 page_start
= dc
->base
.pc_first
& TARGET_PAGE_MASK
;
1220 if (dc
->base
.is_jmp
== DISAS_NEXT
&&
1221 (dc
->pc
- page_start
>= TARGET_PAGE_SIZE
||
1222 dc
->pc
- page_start
+ xtensa_insn_len(env
, dc
) > TARGET_PAGE_SIZE
)) {
1223 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
1227 static void xtensa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
1229 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
1231 switch (dc
->base
.is_jmp
) {
1232 case DISAS_NORETURN
:
1234 case DISAS_TOO_MANY
:
1235 gen_jumpi(dc
, dc
->pc
, 0);
1238 g_assert_not_reached();
1242 static void xtensa_tr_disas_log(const DisasContextBase
*dcbase
,
1243 CPUState
*cpu
, FILE *logfile
)
1245 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
1246 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
1249 static const TranslatorOps xtensa_translator_ops
= {
1250 .init_disas_context
= xtensa_tr_init_disas_context
,
1251 .tb_start
= xtensa_tr_tb_start
,
1252 .insn_start
= xtensa_tr_insn_start
,
1253 .translate_insn
= xtensa_tr_translate_insn
,
1254 .tb_stop
= xtensa_tr_tb_stop
,
1255 .disas_log
= xtensa_tr_disas_log
,
1258 void gen_intermediate_code(CPUState
*cpu
, TranslationBlock
*tb
, int *max_insns
,
1259 target_ulong pc
, void *host_pc
)
1261 DisasContext dc
= {};
1262 translator_loop(cpu
, tb
, max_insns
, pc
, host_pc
,
1263 &xtensa_translator_ops
, &dc
.base
);
1266 void xtensa_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1268 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
1269 CPUXtensaState
*env
= &cpu
->env
;
1270 xtensa_isa isa
= env
->config
->isa
;
1273 qemu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1275 for (i
= j
= 0; i
< xtensa_isa_num_sysregs(isa
); ++i
) {
1276 const uint32_t *reg
=
1277 xtensa_sysreg_is_user(isa
, i
) ? env
->uregs
: env
->sregs
;
1278 int regno
= xtensa_sysreg_number(isa
, i
);
1281 qemu_fprintf(f
, "%12s=%08x%c",
1282 xtensa_sysreg_name(isa
, i
),
1284 (j
++ % 4) == 3 ? '\n' : ' ');
1288 qemu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1290 for (i
= 0; i
< 16; ++i
) {
1291 qemu_fprintf(f
, " A%02d=%08x%c",
1292 i
, env
->regs
[i
], (i
% 4) == 3 ? '\n' : ' ');
1295 xtensa_sync_phys_from_window(env
);
1296 qemu_fprintf(f
, "\n");
1298 for (i
= 0; i
< env
->config
->nareg
; ++i
) {
1299 qemu_fprintf(f
, "AR%02d=%08x ", i
, env
->phys_regs
[i
]);
1301 bool ws
= (env
->sregs
[WINDOW_START
] & (1 << (i
/ 4))) != 0;
1302 bool cw
= env
->sregs
[WINDOW_BASE
] == i
/ 4;
1304 qemu_fprintf(f
, "%c%c\n", ws
? '<' : ' ', cw
? '=' : ' ');
1308 if ((flags
& CPU_DUMP_FPU
) &&
1309 xtensa_option_enabled(env
->config
, XTENSA_OPTION_FP_COPROCESSOR
)) {
1310 qemu_fprintf(f
, "\n");
1312 for (i
= 0; i
< 16; ++i
) {
1313 qemu_fprintf(f
, "F%02d=%08x (%-+15.8e)%c", i
,
1314 float32_val(env
->fregs
[i
].f32
[FP_F32_LOW
]),
1315 *(float *)(env
->fregs
[i
].f32
+ FP_F32_LOW
),
1316 (i
% 2) == 1 ? '\n' : ' ');
1320 if ((flags
& CPU_DUMP_FPU
) &&
1321 xtensa_option_enabled(env
->config
, XTENSA_OPTION_DFP_COPROCESSOR
) &&
1322 !xtensa_option_enabled(env
->config
, XTENSA_OPTION_DFPU_SINGLE_ONLY
)) {
1323 qemu_fprintf(f
, "\n");
1325 for (i
= 0; i
< 16; ++i
) {
1326 qemu_fprintf(f
, "F%02d=%016"PRIx64
" (%-+24.16le)%c", i
,
1327 float64_val(env
->fregs
[i
].f64
),
1328 *(double *)(&env
->fregs
[i
].f64
),
1329 (i
% 2) == 1 ? '\n' : ' ');
1334 static void translate_abs(DisasContext
*dc
, const OpcodeArg arg
[],
1335 const uint32_t par
[])
1337 tcg_gen_abs_i32(arg
[0].out
, arg
[1].in
);
1340 static void translate_add(DisasContext
*dc
, const OpcodeArg arg
[],
1341 const uint32_t par
[])
1343 tcg_gen_add_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1346 static void translate_addi(DisasContext
*dc
, const OpcodeArg arg
[],
1347 const uint32_t par
[])
1349 tcg_gen_addi_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
);
1352 static void translate_addx(DisasContext
*dc
, const OpcodeArg arg
[],
1353 const uint32_t par
[])
1355 TCGv_i32 tmp
= tcg_temp_new_i32();
1356 tcg_gen_shli_i32(tmp
, arg
[1].in
, par
[0]);
1357 tcg_gen_add_i32(arg
[0].out
, tmp
, arg
[2].in
);
1360 static void translate_all(DisasContext
*dc
, const OpcodeArg arg
[],
1361 const uint32_t par
[])
1363 uint32_t shift
= par
[1];
1364 TCGv_i32 mask
= tcg_constant_i32(((1 << shift
) - 1) << arg
[1].imm
);
1365 TCGv_i32 tmp
= tcg_temp_new_i32();
1367 tcg_gen_and_i32(tmp
, arg
[1].in
, mask
);
1369 tcg_gen_addi_i32(tmp
, tmp
, 1 << arg
[1].imm
);
1371 tcg_gen_add_i32(tmp
, tmp
, mask
);
1373 tcg_gen_shri_i32(tmp
, tmp
, arg
[1].imm
+ shift
);
1374 tcg_gen_deposit_i32(arg
[0].out
, arg
[0].out
,
1375 tmp
, arg
[0].imm
, 1);
1378 static void translate_and(DisasContext
*dc
, const OpcodeArg arg
[],
1379 const uint32_t par
[])
1381 tcg_gen_and_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1384 static void translate_ball(DisasContext
*dc
, const OpcodeArg arg
[],
1385 const uint32_t par
[])
1387 TCGv_i32 tmp
= tcg_temp_new_i32();
1388 tcg_gen_and_i32(tmp
, arg
[0].in
, arg
[1].in
);
1389 gen_brcond(dc
, par
[0], tmp
, arg
[1].in
, arg
[2].imm
);
1392 static void translate_bany(DisasContext
*dc
, const OpcodeArg arg
[],
1393 const uint32_t par
[])
1395 TCGv_i32 tmp
= tcg_temp_new_i32();
1396 tcg_gen_and_i32(tmp
, arg
[0].in
, arg
[1].in
);
1397 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2].imm
);
1400 static void translate_b(DisasContext
*dc
, const OpcodeArg arg
[],
1401 const uint32_t par
[])
1403 gen_brcond(dc
, par
[0], arg
[0].in
, arg
[1].in
, arg
[2].imm
);
1406 static void translate_bb(DisasContext
*dc
, const OpcodeArg arg
[],
1407 const uint32_t par
[])
1409 TCGv_i32 tmp
= tcg_temp_new_i32();
1411 tcg_gen_andi_i32(tmp
, arg
[1].in
, 0x1f);
1412 if (TARGET_BIG_ENDIAN
) {
1413 tcg_gen_shr_i32(tmp
, tcg_constant_i32(0x80000000u
), tmp
);
1415 tcg_gen_shl_i32(tmp
, tcg_constant_i32(0x00000001u
), tmp
);
1417 tcg_gen_and_i32(tmp
, arg
[0].in
, tmp
);
1418 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2].imm
);
1421 static void translate_bbi(DisasContext
*dc
, const OpcodeArg arg
[],
1422 const uint32_t par
[])
1424 TCGv_i32 tmp
= tcg_temp_new_i32();
1425 #if TARGET_BIG_ENDIAN
1426 tcg_gen_andi_i32(tmp
, arg
[0].in
, 0x80000000u
>> arg
[1].imm
);
1428 tcg_gen_andi_i32(tmp
, arg
[0].in
, 0x00000001u
<< arg
[1].imm
);
1430 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[2].imm
);
1433 static void translate_bi(DisasContext
*dc
, const OpcodeArg arg
[],
1434 const uint32_t par
[])
1436 gen_brcondi(dc
, par
[0], arg
[0].in
, arg
[1].imm
, arg
[2].imm
);
1439 static void translate_bz(DisasContext
*dc
, const OpcodeArg arg
[],
1440 const uint32_t par
[])
1442 gen_brcondi(dc
, par
[0], arg
[0].in
, 0, arg
[1].imm
);
1453 static void translate_boolean(DisasContext
*dc
, const OpcodeArg arg
[],
1454 const uint32_t par
[])
1456 static void (* const op
[])(TCGv_i32
, TCGv_i32
, TCGv_i32
) = {
1457 [BOOLEAN_AND
] = tcg_gen_and_i32
,
1458 [BOOLEAN_ANDC
] = tcg_gen_andc_i32
,
1459 [BOOLEAN_OR
] = tcg_gen_or_i32
,
1460 [BOOLEAN_ORC
] = tcg_gen_orc_i32
,
1461 [BOOLEAN_XOR
] = tcg_gen_xor_i32
,
1464 TCGv_i32 tmp1
= tcg_temp_new_i32();
1465 TCGv_i32 tmp2
= tcg_temp_new_i32();
1467 tcg_gen_shri_i32(tmp1
, arg
[1].in
, arg
[1].imm
);
1468 tcg_gen_shri_i32(tmp2
, arg
[2].in
, arg
[2].imm
);
1469 op
[par
[0]](tmp1
, tmp1
, tmp2
);
1470 tcg_gen_deposit_i32(arg
[0].out
, arg
[0].out
, tmp1
, arg
[0].imm
, 1);
1473 static void translate_bp(DisasContext
*dc
, const OpcodeArg arg
[],
1474 const uint32_t par
[])
1476 TCGv_i32 tmp
= tcg_temp_new_i32();
1478 tcg_gen_andi_i32(tmp
, arg
[0].in
, 1 << arg
[0].imm
);
1479 gen_brcondi(dc
, par
[0], tmp
, 0, arg
[1].imm
);
1482 static void translate_call0(DisasContext
*dc
, const OpcodeArg arg
[],
1483 const uint32_t par
[])
1485 tcg_gen_movi_i32(cpu_R
[0], dc
->base
.pc_next
);
1486 gen_jumpi(dc
, arg
[0].imm
, 0);
1489 static void translate_callw(DisasContext
*dc
, const OpcodeArg arg
[],
1490 const uint32_t par
[])
1492 TCGv_i32 tmp
= tcg_constant_i32(arg
[0].imm
);
1493 gen_callw_slot(dc
, par
[0], tmp
, adjust_jump_slot(dc
, arg
[0].imm
, 0));
1496 static void translate_callx0(DisasContext
*dc
, const OpcodeArg arg
[],
1497 const uint32_t par
[])
1499 TCGv_i32 tmp
= tcg_temp_new_i32();
1500 tcg_gen_mov_i32(tmp
, arg
[0].in
);
1501 tcg_gen_movi_i32(cpu_R
[0], dc
->base
.pc_next
);
1505 static void translate_callxw(DisasContext
*dc
, const OpcodeArg arg
[],
1506 const uint32_t par
[])
1508 TCGv_i32 tmp
= tcg_temp_new_i32();
1510 tcg_gen_mov_i32(tmp
, arg
[0].in
);
1511 gen_callw_slot(dc
, par
[0], tmp
, -1);
1514 static void translate_clamps(DisasContext
*dc
, const OpcodeArg arg
[],
1515 const uint32_t par
[])
1517 TCGv_i32 tmp1
= tcg_constant_i32(-1u << arg
[2].imm
);
1518 TCGv_i32 tmp2
= tcg_constant_i32((1 << arg
[2].imm
) - 1);
1520 tcg_gen_smax_i32(arg
[0].out
, tmp1
, arg
[1].in
);
1521 tcg_gen_smin_i32(arg
[0].out
, arg
[0].out
, tmp2
);
1524 static void translate_clrb_expstate(DisasContext
*dc
, const OpcodeArg arg
[],
1525 const uint32_t par
[])
1527 /* TODO: GPIO32 may be a part of coprocessor */
1528 tcg_gen_andi_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], ~(1u << arg
[0].imm
));
1531 static void translate_clrex(DisasContext
*dc
, const OpcodeArg arg
[],
1532 const uint32_t par
[])
1534 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
1537 static void translate_const16(DisasContext
*dc
, const OpcodeArg arg
[],
1538 const uint32_t par
[])
1540 TCGv_i32 c
= tcg_constant_i32(arg
[1].imm
);
1542 tcg_gen_deposit_i32(arg
[0].out
, c
, arg
[0].in
, 16, 16);
1545 static void translate_dcache(DisasContext
*dc
, const OpcodeArg arg
[],
1546 const uint32_t par
[])
1548 TCGv_i32 addr
= tcg_temp_new_i32();
1549 TCGv_i32 res
= tcg_temp_new_i32();
1551 tcg_gen_addi_i32(addr
, arg
[0].in
, arg
[1].imm
);
1552 tcg_gen_qemu_ld_i32(res
, addr
, dc
->cring
, MO_UB
);
1555 static void translate_depbits(DisasContext
*dc
, const OpcodeArg arg
[],
1556 const uint32_t par
[])
1558 tcg_gen_deposit_i32(arg
[1].out
, arg
[1].in
, arg
[0].in
,
1559 arg
[2].imm
, arg
[3].imm
);
1562 static void translate_diwbuip(DisasContext
*dc
, const OpcodeArg arg
[],
1563 const uint32_t par
[])
1565 tcg_gen_addi_i32(arg
[0].out
, arg
[0].in
, dc
->config
->dcache_line_bytes
);
1568 static uint32_t test_exceptions_entry(DisasContext
*dc
, const OpcodeArg arg
[],
1569 const uint32_t par
[])
1571 if (arg
[0].imm
> 3 || !dc
->cwoe
) {
1572 qemu_log_mask(LOG_GUEST_ERROR
,
1573 "Illegal entry instruction(pc = %08x)\n", dc
->pc
);
1574 return XTENSA_OP_ILL
;
1580 static uint32_t test_overflow_entry(DisasContext
*dc
, const OpcodeArg arg
[],
1581 const uint32_t par
[])
1583 return 1 << (dc
->callinc
* 4);
1586 static void translate_entry(DisasContext
*dc
, const OpcodeArg arg
[],
1587 const uint32_t par
[])
1589 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
1590 TCGv_i32 s
= tcg_constant_i32(arg
[0].imm
);
1591 TCGv_i32 imm
= tcg_constant_i32(arg
[1].imm
);
1592 gen_helper_entry(tcg_env
, pc
, s
, imm
);
1595 static void translate_extui(DisasContext
*dc
, const OpcodeArg arg
[],
1596 const uint32_t par
[])
1598 int maskimm
= (1 << arg
[3].imm
) - 1;
1600 TCGv_i32 tmp
= tcg_temp_new_i32();
1601 tcg_gen_shri_i32(tmp
, arg
[1].in
, arg
[2].imm
);
1602 tcg_gen_andi_i32(arg
[0].out
, tmp
, maskimm
);
1605 static void translate_getex(DisasContext
*dc
, const OpcodeArg arg
[],
1606 const uint32_t par
[])
1608 TCGv_i32 tmp
= tcg_temp_new_i32();
1610 tcg_gen_extract_i32(tmp
, cpu_SR
[ATOMCTL
], 8, 1);
1611 tcg_gen_deposit_i32(cpu_SR
[ATOMCTL
], cpu_SR
[ATOMCTL
], arg
[0].in
, 8, 1);
1612 tcg_gen_mov_i32(arg
[0].out
, tmp
);
1615 static void translate_icache(DisasContext
*dc
, const OpcodeArg arg
[],
1616 const uint32_t par
[])
1618 #ifndef CONFIG_USER_ONLY
1619 TCGv_i32 addr
= tcg_temp_new_i32();
1621 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1622 tcg_gen_addi_i32(addr
, arg
[0].in
, arg
[1].imm
);
1623 gen_helper_itlb_hit_test(tcg_env
, addr
);
1627 static void translate_itlb(DisasContext
*dc
, const OpcodeArg arg
[],
1628 const uint32_t par
[])
1630 #ifndef CONFIG_USER_ONLY
1631 TCGv_i32 dtlb
= tcg_constant_i32(par
[0]);
1633 gen_helper_itlb(tcg_env
, arg
[0].in
, dtlb
);
1637 static void translate_j(DisasContext
*dc
, const OpcodeArg arg
[],
1638 const uint32_t par
[])
1640 gen_jumpi(dc
, arg
[0].imm
, 0);
1643 static void translate_jx(DisasContext
*dc
, const OpcodeArg arg
[],
1644 const uint32_t par
[])
1646 gen_jump(dc
, arg
[0].in
);
1649 static void translate_l32e(DisasContext
*dc
, const OpcodeArg arg
[],
1650 const uint32_t par
[])
1652 TCGv_i32 addr
= tcg_temp_new_i32();
1655 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
1656 mop
= gen_load_store_alignment(dc
, MO_TEUL
, addr
);
1657 tcg_gen_qemu_ld_tl(arg
[0].out
, addr
, dc
->ring
, mop
);
1660 #ifdef CONFIG_USER_ONLY
1661 static void gen_check_exclusive(DisasContext
*dc
, TCGv_i32 addr
, bool is_write
)
1665 static void gen_check_exclusive(DisasContext
*dc
, TCGv_i32 addr
, bool is_write
)
1667 if (!option_enabled(dc
, XTENSA_OPTION_MPU
)) {
1668 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
1670 gen_helper_check_exclusive(tcg_env
, pc
, addr
,
1671 tcg_constant_i32(is_write
));
1676 static void translate_l32ex(DisasContext
*dc
, const OpcodeArg arg
[],
1677 const uint32_t par
[])
1679 TCGv_i32 addr
= tcg_temp_new_i32();
1682 tcg_gen_mov_i32(addr
, arg
[1].in
);
1683 mop
= gen_load_store_alignment(dc
, MO_TEUL
| MO_ALIGN
, addr
);
1684 gen_check_exclusive(dc
, addr
, false);
1685 tcg_gen_qemu_ld_i32(arg
[0].out
, addr
, dc
->cring
, mop
);
1686 tcg_gen_mov_i32(cpu_exclusive_addr
, addr
);
1687 tcg_gen_mov_i32(cpu_exclusive_val
, arg
[0].out
);
1690 static void translate_ldst(DisasContext
*dc
, const OpcodeArg arg
[],
1691 const uint32_t par
[])
1693 TCGv_i32 addr
= tcg_temp_new_i32();
1696 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
1697 mop
= gen_load_store_alignment(dc
, par
[0], addr
);
1701 tcg_gen_mb(TCG_BAR_STRL
| TCG_MO_ALL
);
1703 tcg_gen_qemu_st_tl(arg
[0].in
, addr
, dc
->cring
, mop
);
1705 tcg_gen_qemu_ld_tl(arg
[0].out
, addr
, dc
->cring
, mop
);
1707 tcg_gen_mb(TCG_BAR_LDAQ
| TCG_MO_ALL
);
1712 static void translate_lct(DisasContext
*dc
, const OpcodeArg arg
[],
1713 const uint32_t par
[])
1715 tcg_gen_movi_i32(arg
[0].out
, 0);
1718 static void translate_l32r(DisasContext
*dc
, const OpcodeArg arg
[],
1719 const uint32_t par
[])
1723 if (dc
->base
.tb
->flags
& XTENSA_TBFLAG_LITBASE
) {
1724 tmp
= tcg_temp_new();
1725 tcg_gen_addi_i32(tmp
, cpu_SR
[LITBASE
], arg
[1].raw_imm
- 1);
1727 tmp
= tcg_constant_i32(arg
[1].imm
);
1729 tcg_gen_qemu_ld_i32(arg
[0].out
, tmp
, dc
->cring
, MO_TEUL
);
1732 static void translate_loop(DisasContext
*dc
, const OpcodeArg arg
[],
1733 const uint32_t par
[])
1735 uint32_t lend
= arg
[1].imm
;
1737 tcg_gen_subi_i32(cpu_SR
[LCOUNT
], arg
[0].in
, 1);
1738 tcg_gen_movi_i32(cpu_SR
[LBEG
], dc
->base
.pc_next
);
1739 tcg_gen_movi_i32(cpu_SR
[LEND
], lend
);
1741 if (par
[0] != TCG_COND_NEVER
) {
1742 TCGLabel
*label
= gen_new_label();
1743 tcg_gen_brcondi_i32(par
[0], arg
[0].in
, 0, label
);
1744 gen_jumpi(dc
, lend
, 1);
1745 gen_set_label(label
);
1748 gen_jumpi(dc
, dc
->base
.pc_next
, 0);
1769 static void translate_mac16(DisasContext
*dc
, const OpcodeArg arg
[],
1770 const uint32_t par
[])
1773 unsigned half
= par
[1];
1774 uint32_t ld_offset
= par
[2];
1775 unsigned off
= ld_offset
? 2 : 0;
1776 TCGv_i32 vaddr
= tcg_temp_new_i32();
1777 TCGv_i32 mem32
= tcg_temp_new_i32();
1782 tcg_gen_addi_i32(vaddr
, arg
[1].in
, ld_offset
);
1783 mop
= gen_load_store_alignment(dc
, MO_TEUL
, vaddr
);
1784 tcg_gen_qemu_ld_tl(mem32
, vaddr
, dc
->cring
, mop
);
1786 if (op
!= MAC16_NONE
) {
1787 TCGv_i32 m1
= gen_mac16_m(arg
[off
].in
,
1788 half
& MAC16_HX
, op
== MAC16_UMUL
);
1789 TCGv_i32 m2
= gen_mac16_m(arg
[off
+ 1].in
,
1790 half
& MAC16_XH
, op
== MAC16_UMUL
);
1792 if (op
== MAC16_MUL
|| op
== MAC16_UMUL
) {
1793 tcg_gen_mul_i32(cpu_SR
[ACCLO
], m1
, m2
);
1794 if (op
== MAC16_UMUL
) {
1795 tcg_gen_movi_i32(cpu_SR
[ACCHI
], 0);
1797 tcg_gen_sari_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCLO
], 31);
1800 TCGv_i32 lo
= tcg_temp_new_i32();
1801 TCGv_i32 hi
= tcg_temp_new_i32();
1803 tcg_gen_mul_i32(lo
, m1
, m2
);
1804 tcg_gen_sari_i32(hi
, lo
, 31);
1805 if (op
== MAC16_MULA
) {
1806 tcg_gen_add2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1807 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1810 tcg_gen_sub2_i32(cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1811 cpu_SR
[ACCLO
], cpu_SR
[ACCHI
],
1814 tcg_gen_ext8s_i32(cpu_SR
[ACCHI
], cpu_SR
[ACCHI
]);
1818 tcg_gen_mov_i32(arg
[1].out
, vaddr
);
1819 tcg_gen_mov_i32(cpu_SR
[MR
+ arg
[0].imm
], mem32
);
1823 static void translate_memw(DisasContext
*dc
, const OpcodeArg arg
[],
1824 const uint32_t par
[])
1826 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
1829 static void translate_smin(DisasContext
*dc
, const OpcodeArg arg
[],
1830 const uint32_t par
[])
1832 tcg_gen_smin_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1835 static void translate_umin(DisasContext
*dc
, const OpcodeArg arg
[],
1836 const uint32_t par
[])
1838 tcg_gen_umin_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1841 static void translate_smax(DisasContext
*dc
, const OpcodeArg arg
[],
1842 const uint32_t par
[])
1844 tcg_gen_smax_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1847 static void translate_umax(DisasContext
*dc
, const OpcodeArg arg
[],
1848 const uint32_t par
[])
1850 tcg_gen_umax_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1853 static void translate_mov(DisasContext
*dc
, const OpcodeArg arg
[],
1854 const uint32_t par
[])
1856 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
1859 static void translate_movcond(DisasContext
*dc
, const OpcodeArg arg
[],
1860 const uint32_t par
[])
1862 TCGv_i32 zero
= tcg_constant_i32(0);
1864 tcg_gen_movcond_i32(par
[0], arg
[0].out
,
1865 arg
[2].in
, zero
, arg
[1].in
, arg
[0].in
);
1868 static void translate_movi(DisasContext
*dc
, const OpcodeArg arg
[],
1869 const uint32_t par
[])
1871 tcg_gen_movi_i32(arg
[0].out
, arg
[1].imm
);
1874 static void translate_movp(DisasContext
*dc
, const OpcodeArg arg
[],
1875 const uint32_t par
[])
1877 TCGv_i32 zero
= tcg_constant_i32(0);
1878 TCGv_i32 tmp
= tcg_temp_new_i32();
1880 tcg_gen_andi_i32(tmp
, arg
[2].in
, 1 << arg
[2].imm
);
1881 tcg_gen_movcond_i32(par
[0],
1882 arg
[0].out
, tmp
, zero
,
1883 arg
[1].in
, arg
[0].in
);
1886 static void translate_movsp(DisasContext
*dc
, const OpcodeArg arg
[],
1887 const uint32_t par
[])
1889 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
1892 static void translate_mul16(DisasContext
*dc
, const OpcodeArg arg
[],
1893 const uint32_t par
[])
1895 TCGv_i32 v1
= tcg_temp_new_i32();
1896 TCGv_i32 v2
= tcg_temp_new_i32();
1899 tcg_gen_ext16s_i32(v1
, arg
[1].in
);
1900 tcg_gen_ext16s_i32(v2
, arg
[2].in
);
1902 tcg_gen_ext16u_i32(v1
, arg
[1].in
);
1903 tcg_gen_ext16u_i32(v2
, arg
[2].in
);
1905 tcg_gen_mul_i32(arg
[0].out
, v1
, v2
);
1908 static void translate_mull(DisasContext
*dc
, const OpcodeArg arg
[],
1909 const uint32_t par
[])
1911 tcg_gen_mul_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1914 static void translate_mulh(DisasContext
*dc
, const OpcodeArg arg
[],
1915 const uint32_t par
[])
1917 TCGv_i32 lo
= tcg_temp_new();
1920 tcg_gen_muls2_i32(lo
, arg
[0].out
, arg
[1].in
, arg
[2].in
);
1922 tcg_gen_mulu2_i32(lo
, arg
[0].out
, arg
[1].in
, arg
[2].in
);
1926 static void translate_neg(DisasContext
*dc
, const OpcodeArg arg
[],
1927 const uint32_t par
[])
1929 tcg_gen_neg_i32(arg
[0].out
, arg
[1].in
);
1932 static void translate_nop(DisasContext
*dc
, const OpcodeArg arg
[],
1933 const uint32_t par
[])
1937 static void translate_nsa(DisasContext
*dc
, const OpcodeArg arg
[],
1938 const uint32_t par
[])
1940 tcg_gen_clrsb_i32(arg
[0].out
, arg
[1].in
);
1943 static void translate_nsau(DisasContext
*dc
, const OpcodeArg arg
[],
1944 const uint32_t par
[])
1946 tcg_gen_clzi_i32(arg
[0].out
, arg
[1].in
, 32);
1949 static void translate_or(DisasContext
*dc
, const OpcodeArg arg
[],
1950 const uint32_t par
[])
1952 tcg_gen_or_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
1955 static void translate_ptlb(DisasContext
*dc
, const OpcodeArg arg
[],
1956 const uint32_t par
[])
1958 #ifndef CONFIG_USER_ONLY
1959 TCGv_i32 dtlb
= tcg_constant_i32(par
[0]);
1961 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1962 gen_helper_ptlb(arg
[0].out
, tcg_env
, arg
[1].in
, dtlb
);
1966 static void translate_pptlb(DisasContext
*dc
, const OpcodeArg arg
[],
1967 const uint32_t par
[])
1969 #ifndef CONFIG_USER_ONLY
1970 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1971 gen_helper_pptlb(arg
[0].out
, tcg_env
, arg
[1].in
);
1975 static void translate_quos(DisasContext
*dc
, const OpcodeArg arg
[],
1976 const uint32_t par
[])
1978 TCGLabel
*label1
= gen_new_label();
1979 TCGLabel
*label2
= gen_new_label();
1981 tcg_gen_brcondi_i32(TCG_COND_NE
, arg
[1].in
, 0x80000000,
1983 tcg_gen_brcondi_i32(TCG_COND_NE
, arg
[2].in
, 0xffffffff,
1985 tcg_gen_movi_i32(arg
[0].out
,
1986 par
[0] ? 0x80000000 : 0);
1988 gen_set_label(label1
);
1990 tcg_gen_div_i32(arg
[0].out
,
1991 arg
[1].in
, arg
[2].in
);
1993 tcg_gen_rem_i32(arg
[0].out
,
1994 arg
[1].in
, arg
[2].in
);
1996 gen_set_label(label2
);
1999 static void translate_quou(DisasContext
*dc
, const OpcodeArg arg
[],
2000 const uint32_t par
[])
2002 tcg_gen_divu_i32(arg
[0].out
,
2003 arg
[1].in
, arg
[2].in
);
2006 static void translate_read_impwire(DisasContext
*dc
, const OpcodeArg arg
[],
2007 const uint32_t par
[])
2009 /* TODO: GPIO32 may be a part of coprocessor */
2010 tcg_gen_movi_i32(arg
[0].out
, 0);
2013 static void translate_remu(DisasContext
*dc
, const OpcodeArg arg
[],
2014 const uint32_t par
[])
2016 tcg_gen_remu_i32(arg
[0].out
,
2017 arg
[1].in
, arg
[2].in
);
2020 static void translate_rer(DisasContext
*dc
, const OpcodeArg arg
[],
2021 const uint32_t par
[])
2023 gen_helper_rer(arg
[0].out
, tcg_env
, arg
[1].in
);
2026 static void translate_ret(DisasContext
*dc
, const OpcodeArg arg
[],
2027 const uint32_t par
[])
2029 gen_jump(dc
, cpu_R
[0]);
2032 static uint32_t test_exceptions_retw(DisasContext
*dc
, const OpcodeArg arg
[],
2033 const uint32_t par
[])
2036 qemu_log_mask(LOG_GUEST_ERROR
,
2037 "Illegal retw instruction(pc = %08x)\n", dc
->pc
);
2038 return XTENSA_OP_ILL
;
2040 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
2042 gen_helper_test_ill_retw(tcg_env
, pc
);
2047 static void translate_retw(DisasContext
*dc
, const OpcodeArg arg
[],
2048 const uint32_t par
[])
2050 TCGv_i32 tmp
= tcg_temp_new();
2051 tcg_gen_shl_i32(tmp
, tcg_constant_i32(1), cpu_SR
[WINDOW_BASE
]);
2052 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2053 cpu_SR
[WINDOW_START
], tmp
);
2054 tcg_gen_movi_i32(tmp
, dc
->pc
);
2055 tcg_gen_deposit_i32(tmp
, tmp
, cpu_R
[0], 0, 30);
2056 gen_helper_retw(tcg_env
, cpu_R
[0]);
2060 static void translate_rfde(DisasContext
*dc
, const OpcodeArg arg
[],
2061 const uint32_t par
[])
2063 gen_jump(dc
, cpu_SR
[dc
->config
->ndepc
? DEPC
: EPC1
]);
2066 static void translate_rfe(DisasContext
*dc
, const OpcodeArg arg
[],
2067 const uint32_t par
[])
2069 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2070 gen_jump(dc
, cpu_SR
[EPC1
]);
2073 static void translate_rfi(DisasContext
*dc
, const OpcodeArg arg
[],
2074 const uint32_t par
[])
2076 tcg_gen_mov_i32(cpu_SR
[PS
], cpu_SR
[EPS2
+ arg
[0].imm
- 2]);
2077 gen_jump(dc
, cpu_SR
[EPC1
+ arg
[0].imm
- 1]);
2080 static void translate_rfw(DisasContext
*dc
, const OpcodeArg arg
[],
2081 const uint32_t par
[])
2083 TCGv_i32 tmp
= tcg_temp_new();
2085 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_EXCM
);
2086 tcg_gen_shl_i32(tmp
, tcg_constant_i32(1), cpu_SR
[WINDOW_BASE
]);
2089 tcg_gen_andc_i32(cpu_SR
[WINDOW_START
],
2090 cpu_SR
[WINDOW_START
], tmp
);
2092 tcg_gen_or_i32(cpu_SR
[WINDOW_START
],
2093 cpu_SR
[WINDOW_START
], tmp
);
2096 gen_helper_restore_owb(tcg_env
);
2097 gen_jump(dc
, cpu_SR
[EPC1
]);
2100 static void translate_rotw(DisasContext
*dc
, const OpcodeArg arg
[],
2101 const uint32_t par
[])
2103 tcg_gen_addi_i32(cpu_windowbase_next
, cpu_SR
[WINDOW_BASE
], arg
[0].imm
);
2106 static void translate_rsil(DisasContext
*dc
, const OpcodeArg arg
[],
2107 const uint32_t par
[])
2109 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[PS
]);
2110 tcg_gen_andi_i32(cpu_SR
[PS
], cpu_SR
[PS
], ~PS_INTLEVEL
);
2111 tcg_gen_ori_i32(cpu_SR
[PS
], cpu_SR
[PS
], arg
[1].imm
);
2114 static void translate_rsr(DisasContext
*dc
, const OpcodeArg arg
[],
2115 const uint32_t par
[])
2117 if (sr_name
[par
[0]]) {
2118 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2120 tcg_gen_movi_i32(arg
[0].out
, 0);
2124 static void translate_rsr_ccount(DisasContext
*dc
, const OpcodeArg arg
[],
2125 const uint32_t par
[])
2127 #ifndef CONFIG_USER_ONLY
2128 translator_io_start(&dc
->base
);
2129 gen_helper_update_ccount(tcg_env
);
2130 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2134 static void translate_rsr_ptevaddr(DisasContext
*dc
, const OpcodeArg arg
[],
2135 const uint32_t par
[])
2137 #ifndef CONFIG_USER_ONLY
2138 TCGv_i32 tmp
= tcg_temp_new_i32();
2140 tcg_gen_shri_i32(tmp
, cpu_SR
[EXCVADDR
], 10);
2141 tcg_gen_or_i32(tmp
, tmp
, cpu_SR
[PTEVADDR
]);
2142 tcg_gen_andi_i32(arg
[0].out
, tmp
, 0xfffffffc);
2146 static void translate_rtlb(DisasContext
*dc
, const OpcodeArg arg
[],
2147 const uint32_t par
[])
2149 #ifndef CONFIG_USER_ONLY
2150 static void (* const helper
[])(TCGv_i32 r
, TCGv_env env
, TCGv_i32 a1
,
2155 TCGv_i32 dtlb
= tcg_constant_i32(par
[0]);
2157 helper
[par
[1]](arg
[0].out
, tcg_env
, arg
[1].in
, dtlb
);
2161 static void translate_rptlb0(DisasContext
*dc
, const OpcodeArg arg
[],
2162 const uint32_t par
[])
2164 #ifndef CONFIG_USER_ONLY
2165 gen_helper_rptlb0(arg
[0].out
, tcg_env
, arg
[1].in
);
2169 static void translate_rptlb1(DisasContext
*dc
, const OpcodeArg arg
[],
2170 const uint32_t par
[])
2172 #ifndef CONFIG_USER_ONLY
2173 gen_helper_rptlb1(arg
[0].out
, tcg_env
, arg
[1].in
);
2177 static void translate_rur(DisasContext
*dc
, const OpcodeArg arg
[],
2178 const uint32_t par
[])
2180 tcg_gen_mov_i32(arg
[0].out
, cpu_UR
[par
[0]]);
2183 static void translate_setb_expstate(DisasContext
*dc
, const OpcodeArg arg
[],
2184 const uint32_t par
[])
2186 /* TODO: GPIO32 may be a part of coprocessor */
2187 tcg_gen_ori_i32(cpu_UR
[EXPSTATE
], cpu_UR
[EXPSTATE
], 1u << arg
[0].imm
);
2190 #ifdef CONFIG_USER_ONLY
2191 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2195 static void gen_check_atomctl(DisasContext
*dc
, TCGv_i32 addr
)
2197 TCGv_i32 pc
= tcg_constant_i32(dc
->pc
);
2199 gen_helper_check_atomctl(tcg_env
, pc
, addr
);
2203 static void translate_s32c1i(DisasContext
*dc
, const OpcodeArg arg
[],
2204 const uint32_t par
[])
2206 TCGv_i32 tmp
= tcg_temp_new_i32();
2207 TCGv_i32 addr
= tcg_temp_new_i32();
2210 tcg_gen_mov_i32(tmp
, arg
[0].in
);
2211 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
2212 mop
= gen_load_store_alignment(dc
, MO_TEUL
| MO_ALIGN
, addr
);
2213 gen_check_atomctl(dc
, addr
);
2214 tcg_gen_atomic_cmpxchg_i32(arg
[0].out
, addr
, cpu_SR
[SCOMPARE1
],
2215 tmp
, dc
->cring
, mop
);
2218 static void translate_s32e(DisasContext
*dc
, const OpcodeArg arg
[],
2219 const uint32_t par
[])
2221 TCGv_i32 addr
= tcg_temp_new_i32();
2224 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
2225 mop
= gen_load_store_alignment(dc
, MO_TEUL
, addr
);
2226 tcg_gen_qemu_st_tl(arg
[0].in
, addr
, dc
->ring
, mop
);
2229 static void translate_s32ex(DisasContext
*dc
, const OpcodeArg arg
[],
2230 const uint32_t par
[])
2232 TCGv_i32 prev
= tcg_temp_new_i32();
2233 TCGv_i32 addr
= tcg_temp_new_i32();
2234 TCGv_i32 res
= tcg_temp_new_i32();
2235 TCGLabel
*label
= gen_new_label();
2238 tcg_gen_movi_i32(res
, 0);
2239 tcg_gen_mov_i32(addr
, arg
[1].in
);
2240 mop
= gen_load_store_alignment(dc
, MO_TEUL
| MO_ALIGN
, addr
);
2241 tcg_gen_brcond_i32(TCG_COND_NE
, addr
, cpu_exclusive_addr
, label
);
2242 gen_check_exclusive(dc
, addr
, true);
2243 tcg_gen_atomic_cmpxchg_i32(prev
, cpu_exclusive_addr
, cpu_exclusive_val
,
2244 arg
[0].in
, dc
->cring
, mop
);
2245 tcg_gen_setcond_i32(TCG_COND_EQ
, res
, prev
, cpu_exclusive_val
);
2246 tcg_gen_movcond_i32(TCG_COND_EQ
, cpu_exclusive_val
,
2247 prev
, cpu_exclusive_val
, prev
, cpu_exclusive_val
);
2248 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
2249 gen_set_label(label
);
2250 tcg_gen_extract_i32(arg
[0].out
, cpu_SR
[ATOMCTL
], 8, 1);
2251 tcg_gen_deposit_i32(cpu_SR
[ATOMCTL
], cpu_SR
[ATOMCTL
], res
, 8, 1);
2254 static void translate_salt(DisasContext
*dc
, const OpcodeArg arg
[],
2255 const uint32_t par
[])
2257 tcg_gen_setcond_i32(par
[0],
2259 arg
[1].in
, arg
[2].in
);
2262 static void translate_sext(DisasContext
*dc
, const OpcodeArg arg
[],
2263 const uint32_t par
[])
2265 int shift
= 31 - arg
[2].imm
;
2268 tcg_gen_ext8s_i32(arg
[0].out
, arg
[1].in
);
2269 } else if (shift
== 16) {
2270 tcg_gen_ext16s_i32(arg
[0].out
, arg
[1].in
);
2272 TCGv_i32 tmp
= tcg_temp_new_i32();
2273 tcg_gen_shli_i32(tmp
, arg
[1].in
, shift
);
2274 tcg_gen_sari_i32(arg
[0].out
, tmp
, shift
);
2278 static uint32_t test_exceptions_simcall(DisasContext
*dc
,
2279 const OpcodeArg arg
[],
2280 const uint32_t par
[])
2282 bool is_semi
= semihosting_enabled(dc
->cring
!= 0);
2283 #ifdef CONFIG_USER_ONLY
2286 /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
2287 bool ill
= dc
->config
->hw_version
<= 250002 && !is_semi
;
2289 if (ill
|| !is_semi
) {
2290 qemu_log_mask(LOG_GUEST_ERROR
, "SIMCALL but semihosting is disabled\n");
2292 return ill
? XTENSA_OP_ILL
: 0;
2295 static void translate_simcall(DisasContext
*dc
, const OpcodeArg arg
[],
2296 const uint32_t par
[])
2298 #ifndef CONFIG_USER_ONLY
2299 if (semihosting_enabled(dc
->cring
!= 0)) {
2300 gen_helper_simcall(tcg_env
);
2306 * Note: 64 bit ops are used here solely because SAR values
2309 #define gen_shift_reg(cmd, reg) do { \
2310 TCGv_i64 tmp = tcg_temp_new_i64(); \
2311 tcg_gen_extu_i32_i64(tmp, reg); \
2312 tcg_gen_##cmd##_i64(v, v, tmp); \
2313 tcg_gen_extrl_i64_i32(arg[0].out, v); \
2316 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
2318 static void translate_sll(DisasContext
*dc
, const OpcodeArg arg
[],
2319 const uint32_t par
[])
2321 if (dc
->sar_m32_5bit
) {
2322 tcg_gen_shl_i32(arg
[0].out
, arg
[1].in
, dc
->sar_m32
);
2324 TCGv_i64 v
= tcg_temp_new_i64();
2325 TCGv_i32 s
= tcg_temp_new();
2326 tcg_gen_subfi_i32(s
, 32, cpu_SR
[SAR
]);
2327 tcg_gen_andi_i32(s
, s
, 0x3f);
2328 tcg_gen_extu_i32_i64(v
, arg
[1].in
);
2329 gen_shift_reg(shl
, s
);
2333 static void translate_slli(DisasContext
*dc
, const OpcodeArg arg
[],
2334 const uint32_t par
[])
2336 if (arg
[2].imm
== 32) {
2337 qemu_log_mask(LOG_GUEST_ERROR
, "slli a%d, a%d, 32 is undefined\n",
2338 arg
[0].imm
, arg
[1].imm
);
2340 tcg_gen_shli_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
& 0x1f);
2343 static void translate_sra(DisasContext
*dc
, const OpcodeArg arg
[],
2344 const uint32_t par
[])
2346 if (dc
->sar_m32_5bit
) {
2347 tcg_gen_sar_i32(arg
[0].out
, arg
[1].in
, cpu_SR
[SAR
]);
2349 TCGv_i64 v
= tcg_temp_new_i64();
2350 tcg_gen_ext_i32_i64(v
, arg
[1].in
);
2355 static void translate_srai(DisasContext
*dc
, const OpcodeArg arg
[],
2356 const uint32_t par
[])
2358 tcg_gen_sari_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
);
2361 static void translate_src(DisasContext
*dc
, const OpcodeArg arg
[],
2362 const uint32_t par
[])
2364 TCGv_i64 v
= tcg_temp_new_i64();
2365 tcg_gen_concat_i32_i64(v
, arg
[2].in
, arg
[1].in
);
2369 static void translate_srl(DisasContext
*dc
, const OpcodeArg arg
[],
2370 const uint32_t par
[])
2372 if (dc
->sar_m32_5bit
) {
2373 tcg_gen_shr_i32(arg
[0].out
, arg
[1].in
, cpu_SR
[SAR
]);
2375 TCGv_i64 v
= tcg_temp_new_i64();
2376 tcg_gen_extu_i32_i64(v
, arg
[1].in
);
2382 #undef gen_shift_reg
2384 static void translate_srli(DisasContext
*dc
, const OpcodeArg arg
[],
2385 const uint32_t par
[])
2387 tcg_gen_shri_i32(arg
[0].out
, arg
[1].in
, arg
[2].imm
);
2390 static void translate_ssa8b(DisasContext
*dc
, const OpcodeArg arg
[],
2391 const uint32_t par
[])
2393 TCGv_i32 tmp
= tcg_temp_new_i32();
2394 tcg_gen_shli_i32(tmp
, arg
[0].in
, 3);
2395 gen_left_shift_sar(dc
, tmp
);
2398 static void translate_ssa8l(DisasContext
*dc
, const OpcodeArg arg
[],
2399 const uint32_t par
[])
2401 TCGv_i32 tmp
= tcg_temp_new_i32();
2402 tcg_gen_shli_i32(tmp
, arg
[0].in
, 3);
2403 gen_right_shift_sar(dc
, tmp
);
2406 static void translate_ssai(DisasContext
*dc
, const OpcodeArg arg
[],
2407 const uint32_t par
[])
2409 gen_right_shift_sar(dc
, tcg_constant_i32(arg
[0].imm
));
2412 static void translate_ssl(DisasContext
*dc
, const OpcodeArg arg
[],
2413 const uint32_t par
[])
2415 gen_left_shift_sar(dc
, arg
[0].in
);
2418 static void translate_ssr(DisasContext
*dc
, const OpcodeArg arg
[],
2419 const uint32_t par
[])
2421 gen_right_shift_sar(dc
, arg
[0].in
);
2424 static void translate_sub(DisasContext
*dc
, const OpcodeArg arg
[],
2425 const uint32_t par
[])
2427 tcg_gen_sub_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
2430 static void translate_subx(DisasContext
*dc
, const OpcodeArg arg
[],
2431 const uint32_t par
[])
2433 TCGv_i32 tmp
= tcg_temp_new_i32();
2434 tcg_gen_shli_i32(tmp
, arg
[1].in
, par
[0]);
2435 tcg_gen_sub_i32(arg
[0].out
, tmp
, arg
[2].in
);
2438 static void translate_waiti(DisasContext
*dc
, const OpcodeArg arg
[],
2439 const uint32_t par
[])
2441 #ifndef CONFIG_USER_ONLY
2442 TCGv_i32 pc
= tcg_constant_i32(dc
->base
.pc_next
);
2444 translator_io_start(&dc
->base
);
2445 gen_helper_waiti(tcg_env
, pc
, tcg_constant_i32(arg
[0].imm
));
2449 static void translate_wtlb(DisasContext
*dc
, const OpcodeArg arg
[],
2450 const uint32_t par
[])
2452 #ifndef CONFIG_USER_ONLY
2453 TCGv_i32 dtlb
= tcg_constant_i32(par
[0]);
2455 gen_helper_wtlb(tcg_env
, arg
[0].in
, arg
[1].in
, dtlb
);
2459 static void translate_wptlb(DisasContext
*dc
, const OpcodeArg arg
[],
2460 const uint32_t par
[])
2462 #ifndef CONFIG_USER_ONLY
2463 gen_helper_wptlb(tcg_env
, arg
[0].in
, arg
[1].in
);
2467 static void translate_wer(DisasContext
*dc
, const OpcodeArg arg
[],
2468 const uint32_t par
[])
2470 gen_helper_wer(tcg_env
, arg
[0].in
, arg
[1].in
);
2473 static void translate_wrmsk_expstate(DisasContext
*dc
, const OpcodeArg arg
[],
2474 const uint32_t par
[])
2476 /* TODO: GPIO32 may be a part of coprocessor */
2477 tcg_gen_and_i32(cpu_UR
[EXPSTATE
], arg
[0].in
, arg
[1].in
);
2480 static void translate_wsr(DisasContext
*dc
, const OpcodeArg arg
[],
2481 const uint32_t par
[])
2483 if (sr_name
[par
[0]]) {
2484 tcg_gen_mov_i32(cpu_SR
[par
[0]], arg
[0].in
);
2488 static void translate_wsr_mask(DisasContext
*dc
, const OpcodeArg arg
[],
2489 const uint32_t par
[])
2491 if (sr_name
[par
[0]]) {
2492 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
, par
[2]);
2496 static void translate_wsr_acchi(DisasContext
*dc
, const OpcodeArg arg
[],
2497 const uint32_t par
[])
2499 tcg_gen_ext8s_i32(cpu_SR
[par
[0]], arg
[0].in
);
2502 static void translate_wsr_ccompare(DisasContext
*dc
, const OpcodeArg arg
[],
2503 const uint32_t par
[])
2505 #ifndef CONFIG_USER_ONLY
2506 uint32_t id
= par
[0] - CCOMPARE
;
2508 assert(id
< dc
->config
->nccompare
);
2509 translator_io_start(&dc
->base
);
2510 tcg_gen_mov_i32(cpu_SR
[par
[0]], arg
[0].in
);
2511 gen_helper_update_ccompare(tcg_env
, tcg_constant_i32(id
));
2515 static void translate_wsr_ccount(DisasContext
*dc
, const OpcodeArg arg
[],
2516 const uint32_t par
[])
2518 #ifndef CONFIG_USER_ONLY
2519 translator_io_start(&dc
->base
);
2520 gen_helper_wsr_ccount(tcg_env
, arg
[0].in
);
2524 static void translate_wsr_dbreaka(DisasContext
*dc
, const OpcodeArg arg
[],
2525 const uint32_t par
[])
2527 #ifndef CONFIG_USER_ONLY
2528 unsigned id
= par
[0] - DBREAKA
;
2530 assert(id
< dc
->config
->ndbreak
);
2531 gen_helper_wsr_dbreaka(tcg_env
, tcg_constant_i32(id
), arg
[0].in
);
2535 static void translate_wsr_dbreakc(DisasContext
*dc
, const OpcodeArg arg
[],
2536 const uint32_t par
[])
2538 #ifndef CONFIG_USER_ONLY
2539 unsigned id
= par
[0] - DBREAKC
;
2541 assert(id
< dc
->config
->ndbreak
);
2542 gen_helper_wsr_dbreakc(tcg_env
, tcg_constant_i32(id
), arg
[0].in
);
2546 static void translate_wsr_ibreaka(DisasContext
*dc
, const OpcodeArg arg
[],
2547 const uint32_t par
[])
2549 #ifndef CONFIG_USER_ONLY
2550 unsigned id
= par
[0] - IBREAKA
;
2552 assert(id
< dc
->config
->nibreak
);
2553 gen_helper_wsr_ibreaka(tcg_env
, tcg_constant_i32(id
), arg
[0].in
);
2557 static void translate_wsr_ibreakenable(DisasContext
*dc
, const OpcodeArg arg
[],
2558 const uint32_t par
[])
2560 #ifndef CONFIG_USER_ONLY
2561 gen_helper_wsr_ibreakenable(tcg_env
, arg
[0].in
);
2565 static void translate_wsr_icount(DisasContext
*dc
, const OpcodeArg arg
[],
2566 const uint32_t par
[])
2568 #ifndef CONFIG_USER_ONLY
2570 tcg_gen_mov_i32(dc
->next_icount
, arg
[0].in
);
2572 tcg_gen_mov_i32(cpu_SR
[par
[0]], arg
[0].in
);
2577 static void translate_wsr_intclear(DisasContext
*dc
, const OpcodeArg arg
[],
2578 const uint32_t par
[])
2580 #ifndef CONFIG_USER_ONLY
2581 gen_helper_intclear(tcg_env
, arg
[0].in
);
2585 static void translate_wsr_intset(DisasContext
*dc
, const OpcodeArg arg
[],
2586 const uint32_t par
[])
2588 #ifndef CONFIG_USER_ONLY
2589 gen_helper_intset(tcg_env
, arg
[0].in
);
2593 static void translate_wsr_memctl(DisasContext
*dc
, const OpcodeArg arg
[],
2594 const uint32_t par
[])
2596 #ifndef CONFIG_USER_ONLY
2597 gen_helper_wsr_memctl(tcg_env
, arg
[0].in
);
2601 static void translate_wsr_mpuenb(DisasContext
*dc
, const OpcodeArg arg
[],
2602 const uint32_t par
[])
2604 #ifndef CONFIG_USER_ONLY
2605 gen_helper_wsr_mpuenb(tcg_env
, arg
[0].in
);
2609 static void translate_wsr_ps(DisasContext
*dc
, const OpcodeArg arg
[],
2610 const uint32_t par
[])
2612 #ifndef CONFIG_USER_ONLY
2613 uint32_t mask
= PS_WOE
| PS_CALLINC
| PS_OWB
|
2614 PS_UM
| PS_EXCM
| PS_INTLEVEL
;
2616 if (option_enabled(dc
, XTENSA_OPTION_MMU
) ||
2617 option_enabled(dc
, XTENSA_OPTION_MPU
)) {
2620 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
, mask
);
2624 static void translate_wsr_rasid(DisasContext
*dc
, const OpcodeArg arg
[],
2625 const uint32_t par
[])
2627 #ifndef CONFIG_USER_ONLY
2628 gen_helper_wsr_rasid(tcg_env
, arg
[0].in
);
2632 static void translate_wsr_sar(DisasContext
*dc
, const OpcodeArg arg
[],
2633 const uint32_t par
[])
2635 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
, 0x3f);
2636 if (dc
->sar_m32_5bit
) {
2637 tcg_gen_discard_i32(dc
->sar_m32
);
2639 dc
->sar_5bit
= false;
2640 dc
->sar_m32_5bit
= false;
2643 static void translate_wsr_windowbase(DisasContext
*dc
, const OpcodeArg arg
[],
2644 const uint32_t par
[])
2646 #ifndef CONFIG_USER_ONLY
2647 tcg_gen_mov_i32(cpu_windowbase_next
, arg
[0].in
);
2651 static void translate_wsr_windowstart(DisasContext
*dc
, const OpcodeArg arg
[],
2652 const uint32_t par
[])
2654 #ifndef CONFIG_USER_ONLY
2655 tcg_gen_andi_i32(cpu_SR
[par
[0]], arg
[0].in
,
2656 (1 << dc
->config
->nareg
/ 4) - 1);
2660 static void translate_wur(DisasContext
*dc
, const OpcodeArg arg
[],
2661 const uint32_t par
[])
2663 tcg_gen_mov_i32(cpu_UR
[par
[0]], arg
[0].in
);
2666 static void translate_xor(DisasContext
*dc
, const OpcodeArg arg
[],
2667 const uint32_t par
[])
2669 tcg_gen_xor_i32(arg
[0].out
, arg
[1].in
, arg
[2].in
);
2672 static void translate_xsr(DisasContext
*dc
, const OpcodeArg arg
[],
2673 const uint32_t par
[])
2675 if (sr_name
[par
[0]]) {
2676 TCGv_i32 tmp
= tcg_temp_new_i32();
2678 tcg_gen_mov_i32(tmp
, arg
[0].in
);
2679 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2680 tcg_gen_mov_i32(cpu_SR
[par
[0]], tmp
);
2682 tcg_gen_movi_i32(arg
[0].out
, 0);
2686 static void translate_xsr_mask(DisasContext
*dc
, const OpcodeArg arg
[],
2687 const uint32_t par
[])
2689 if (sr_name
[par
[0]]) {
2690 TCGv_i32 tmp
= tcg_temp_new_i32();
2692 tcg_gen_mov_i32(tmp
, arg
[0].in
);
2693 tcg_gen_mov_i32(arg
[0].out
, cpu_SR
[par
[0]]);
2694 tcg_gen_andi_i32(cpu_SR
[par
[0]], tmp
, par
[2]);
2696 tcg_gen_movi_i32(arg
[0].out
, 0);
2700 static void translate_xsr_ccount(DisasContext
*dc
, const OpcodeArg arg
[],
2701 const uint32_t par
[])
2703 #ifndef CONFIG_USER_ONLY
2704 TCGv_i32 tmp
= tcg_temp_new_i32();
2706 translator_io_start(&dc
->base
);
2707 gen_helper_update_ccount(tcg_env
);
2708 tcg_gen_mov_i32(tmp
, cpu_SR
[par
[0]]);
2709 gen_helper_wsr_ccount(tcg_env
, arg
[0].in
);
2710 tcg_gen_mov_i32(arg
[0].out
, tmp
);
2715 #define gen_translate_xsr(name) \
2716 static void translate_xsr_##name(DisasContext *dc, const OpcodeArg arg[], \
2717 const uint32_t par[]) \
2719 TCGv_i32 tmp = tcg_temp_new_i32(); \
2721 if (sr_name[par[0]]) { \
2722 tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); \
2724 tcg_gen_movi_i32(tmp, 0); \
2726 translate_wsr_##name(dc, arg, par); \
2727 tcg_gen_mov_i32(arg[0].out, tmp); \
2730 gen_translate_xsr(acchi
)
2731 gen_translate_xsr(ccompare
)
2732 gen_translate_xsr(dbreaka
)
2733 gen_translate_xsr(dbreakc
)
2734 gen_translate_xsr(ibreaka
)
2735 gen_translate_xsr(ibreakenable
)
2736 gen_translate_xsr(icount
)
2737 gen_translate_xsr(memctl
)
2738 gen_translate_xsr(mpuenb
)
2739 gen_translate_xsr(ps
)
2740 gen_translate_xsr(rasid
)
2741 gen_translate_xsr(sar
)
2742 gen_translate_xsr(windowbase
)
2743 gen_translate_xsr(windowstart
)
2745 #undef gen_translate_xsr
2747 static const XtensaOpcodeOps core_ops
[] = {
2750 .translate
= translate_abs
,
2752 .name
= (const char * const[]) {
2753 "add", "add.n", NULL
,
2755 .translate
= translate_add
,
2756 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2758 .name
= (const char * const[]) {
2759 "addi", "addi.n", NULL
,
2761 .translate
= translate_addi
,
2762 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2765 .translate
= translate_addi
,
2768 .translate
= translate_addx
,
2769 .par
= (const uint32_t[]){1},
2772 .translate
= translate_addx
,
2773 .par
= (const uint32_t[]){2},
2776 .translate
= translate_addx
,
2777 .par
= (const uint32_t[]){3},
2780 .translate
= translate_all
,
2781 .par
= (const uint32_t[]){true, 4},
2784 .translate
= translate_all
,
2785 .par
= (const uint32_t[]){true, 8},
2788 .translate
= translate_and
,
2791 .translate
= translate_boolean
,
2792 .par
= (const uint32_t[]){BOOLEAN_AND
},
2795 .translate
= translate_boolean
,
2796 .par
= (const uint32_t[]){BOOLEAN_ANDC
},
2799 .translate
= translate_all
,
2800 .par
= (const uint32_t[]){false, 4},
2803 .translate
= translate_all
,
2804 .par
= (const uint32_t[]){false, 8},
2806 .name
= (const char * const[]) {
2807 "ball", "ball.w15", "ball.w18", NULL
,
2809 .translate
= translate_ball
,
2810 .par
= (const uint32_t[]){TCG_COND_EQ
},
2811 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2813 .name
= (const char * const[]) {
2814 "bany", "bany.w15", "bany.w18", NULL
,
2816 .translate
= translate_bany
,
2817 .par
= (const uint32_t[]){TCG_COND_NE
},
2818 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2820 .name
= (const char * const[]) {
2821 "bbc", "bbc.w15", "bbc.w18", NULL
,
2823 .translate
= translate_bb
,
2824 .par
= (const uint32_t[]){TCG_COND_EQ
},
2825 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2827 .name
= (const char * const[]) {
2828 "bbci", "bbci.w15", "bbci.w18", NULL
,
2830 .translate
= translate_bbi
,
2831 .par
= (const uint32_t[]){TCG_COND_EQ
},
2832 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2834 .name
= (const char * const[]) {
2835 "bbs", "bbs.w15", "bbs.w18", NULL
,
2837 .translate
= translate_bb
,
2838 .par
= (const uint32_t[]){TCG_COND_NE
},
2839 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2841 .name
= (const char * const[]) {
2842 "bbsi", "bbsi.w15", "bbsi.w18", NULL
,
2844 .translate
= translate_bbi
,
2845 .par
= (const uint32_t[]){TCG_COND_NE
},
2846 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2848 .name
= (const char * const[]) {
2849 "beq", "beq.w15", "beq.w18", NULL
,
2851 .translate
= translate_b
,
2852 .par
= (const uint32_t[]){TCG_COND_EQ
},
2853 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2855 .name
= (const char * const[]) {
2856 "beqi", "beqi.w15", "beqi.w18", NULL
,
2858 .translate
= translate_bi
,
2859 .par
= (const uint32_t[]){TCG_COND_EQ
},
2860 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2862 .name
= (const char * const[]) {
2863 "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL
,
2865 .translate
= translate_bz
,
2866 .par
= (const uint32_t[]){TCG_COND_EQ
},
2867 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2870 .translate
= translate_bp
,
2871 .par
= (const uint32_t[]){TCG_COND_EQ
},
2873 .name
= (const char * const[]) {
2874 "bge", "bge.w15", "bge.w18", NULL
,
2876 .translate
= translate_b
,
2877 .par
= (const uint32_t[]){TCG_COND_GE
},
2878 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2880 .name
= (const char * const[]) {
2881 "bgei", "bgei.w15", "bgei.w18", NULL
,
2883 .translate
= translate_bi
,
2884 .par
= (const uint32_t[]){TCG_COND_GE
},
2885 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2887 .name
= (const char * const[]) {
2888 "bgeu", "bgeu.w15", "bgeu.w18", NULL
,
2890 .translate
= translate_b
,
2891 .par
= (const uint32_t[]){TCG_COND_GEU
},
2892 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2894 .name
= (const char * const[]) {
2895 "bgeui", "bgeui.w15", "bgeui.w18", NULL
,
2897 .translate
= translate_bi
,
2898 .par
= (const uint32_t[]){TCG_COND_GEU
},
2899 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2901 .name
= (const char * const[]) {
2902 "bgez", "bgez.w15", "bgez.w18", NULL
,
2904 .translate
= translate_bz
,
2905 .par
= (const uint32_t[]){TCG_COND_GE
},
2906 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2908 .name
= (const char * const[]) {
2909 "blt", "blt.w15", "blt.w18", NULL
,
2911 .translate
= translate_b
,
2912 .par
= (const uint32_t[]){TCG_COND_LT
},
2913 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2915 .name
= (const char * const[]) {
2916 "blti", "blti.w15", "blti.w18", NULL
,
2918 .translate
= translate_bi
,
2919 .par
= (const uint32_t[]){TCG_COND_LT
},
2920 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2922 .name
= (const char * const[]) {
2923 "bltu", "bltu.w15", "bltu.w18", NULL
,
2925 .translate
= translate_b
,
2926 .par
= (const uint32_t[]){TCG_COND_LTU
},
2927 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2929 .name
= (const char * const[]) {
2930 "bltui", "bltui.w15", "bltui.w18", NULL
,
2932 .translate
= translate_bi
,
2933 .par
= (const uint32_t[]){TCG_COND_LTU
},
2934 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2936 .name
= (const char * const[]) {
2937 "bltz", "bltz.w15", "bltz.w18", NULL
,
2939 .translate
= translate_bz
,
2940 .par
= (const uint32_t[]){TCG_COND_LT
},
2941 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2943 .name
= (const char * const[]) {
2944 "bnall", "bnall.w15", "bnall.w18", NULL
,
2946 .translate
= translate_ball
,
2947 .par
= (const uint32_t[]){TCG_COND_NE
},
2948 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2950 .name
= (const char * const[]) {
2951 "bne", "bne.w15", "bne.w18", NULL
,
2953 .translate
= translate_b
,
2954 .par
= (const uint32_t[]){TCG_COND_NE
},
2955 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2957 .name
= (const char * const[]) {
2958 "bnei", "bnei.w15", "bnei.w18", NULL
,
2960 .translate
= translate_bi
,
2961 .par
= (const uint32_t[]){TCG_COND_NE
},
2962 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2964 .name
= (const char * const[]) {
2965 "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL
,
2967 .translate
= translate_bz
,
2968 .par
= (const uint32_t[]){TCG_COND_NE
},
2969 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2971 .name
= (const char * const[]) {
2972 "bnone", "bnone.w15", "bnone.w18", NULL
,
2974 .translate
= translate_bany
,
2975 .par
= (const uint32_t[]){TCG_COND_EQ
},
2976 .op_flags
= XTENSA_OP_NAME_ARRAY
,
2979 .translate
= translate_nop
,
2980 .par
= (const uint32_t[]){DEBUGCAUSE_BI
},
2981 .op_flags
= XTENSA_OP_DEBUG_BREAK
,
2984 .translate
= translate_nop
,
2985 .par
= (const uint32_t[]){DEBUGCAUSE_BN
},
2986 .op_flags
= XTENSA_OP_DEBUG_BREAK
,
2989 .translate
= translate_bp
,
2990 .par
= (const uint32_t[]){TCG_COND_NE
},
2993 .translate
= translate_call0
,
2996 .translate
= translate_callw
,
2997 .par
= (const uint32_t[]){3},
3000 .translate
= translate_callw
,
3001 .par
= (const uint32_t[]){1},
3004 .translate
= translate_callw
,
3005 .par
= (const uint32_t[]){2},
3008 .translate
= translate_callx0
,
3011 .translate
= translate_callxw
,
3012 .par
= (const uint32_t[]){3},
3015 .translate
= translate_callxw
,
3016 .par
= (const uint32_t[]){1},
3019 .translate
= translate_callxw
,
3020 .par
= (const uint32_t[]){2},
3023 .translate
= translate_clamps
,
3025 .name
= "clrb_expstate",
3026 .translate
= translate_clrb_expstate
,
3029 .translate
= translate_clrex
,
3032 .translate
= translate_const16
,
3035 .translate
= translate_depbits
,
3038 .translate
= translate_dcache
,
3039 .op_flags
= XTENSA_OP_PRIVILEGED
,
3042 .translate
= translate_nop
,
3045 .translate
= translate_dcache
,
3046 .op_flags
= XTENSA_OP_PRIVILEGED
,
3049 .translate
= translate_dcache
,
3052 .translate
= translate_nop
,
3055 .translate
= translate_dcache
,
3058 .translate
= translate_nop
,
3061 .translate
= translate_nop
,
3062 .op_flags
= XTENSA_OP_PRIVILEGED
,
3065 .translate
= translate_nop
,
3066 .op_flags
= XTENSA_OP_PRIVILEGED
,
3069 .translate
= translate_nop
,
3070 .op_flags
= XTENSA_OP_PRIVILEGED
,
3073 .translate
= translate_nop
,
3074 .op_flags
= XTENSA_OP_PRIVILEGED
,
3077 .translate
= translate_diwbuip
,
3078 .op_flags
= XTENSA_OP_PRIVILEGED
,
3081 .translate
= translate_dcache
,
3082 .op_flags
= XTENSA_OP_PRIVILEGED
,
3085 .translate
= translate_nop
,
3088 .translate
= translate_nop
,
3091 .translate
= translate_nop
,
3094 .translate
= translate_nop
,
3097 .translate
= translate_nop
,
3100 .translate
= translate_nop
,
3103 .translate
= translate_nop
,
3106 .translate
= translate_nop
,
3109 .translate
= translate_nop
,
3112 .translate
= translate_nop
,
3115 .translate
= translate_nop
,
3118 .translate
= translate_entry
,
3119 .test_exceptions
= test_exceptions_entry
,
3120 .test_overflow
= test_overflow_entry
,
3121 .op_flags
= XTENSA_OP_EXIT_TB_M1
|
3122 XTENSA_OP_SYNC_REGISTER_WINDOW
,
3125 .translate
= translate_nop
,
3128 .translate
= translate_nop
,
3131 .translate
= translate_extui
,
3134 .translate
= translate_memw
,
3137 .translate
= translate_getex
,
3140 .op_flags
= XTENSA_OP_ILL
,
3143 .op_flags
= XTENSA_OP_ILL
,
3146 .translate
= translate_itlb
,
3147 .par
= (const uint32_t[]){true},
3148 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
3151 .translate
= translate_icache
,
3154 .translate
= translate_icache
,
3155 .op_flags
= XTENSA_OP_PRIVILEGED
,
3158 .translate
= translate_nop
,
3159 .op_flags
= XTENSA_OP_PRIVILEGED
,
3162 .translate
= translate_itlb
,
3163 .par
= (const uint32_t[]){false},
3164 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
3167 .translate
= translate_nop
,
3168 .op_flags
= XTENSA_OP_PRIVILEGED
,
3170 .name
= (const char * const[]) {
3171 "ill", "ill.n", NULL
,
3173 .op_flags
= XTENSA_OP_ILL
| XTENSA_OP_NAME_ARRAY
,
3176 .translate
= translate_nop
,
3179 .translate
= translate_icache
,
3180 .op_flags
= XTENSA_OP_PRIVILEGED
,
3183 .translate
= translate_nop
,
3186 .translate
= translate_j
,
3189 .translate
= translate_jx
,
3192 .translate
= translate_ldst
,
3193 .par
= (const uint32_t[]){MO_TESW
, false, false},
3194 .op_flags
= XTENSA_OP_LOAD
,
3197 .translate
= translate_ldst
,
3198 .par
= (const uint32_t[]){MO_TEUW
, false, false},
3199 .op_flags
= XTENSA_OP_LOAD
,
3202 .translate
= translate_ldst
,
3203 .par
= (const uint32_t[]){MO_TEUL
| MO_ALIGN
, true, false},
3204 .op_flags
= XTENSA_OP_LOAD
,
3207 .translate
= translate_l32e
,
3208 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_LOAD
,
3211 .translate
= translate_l32ex
,
3212 .op_flags
= XTENSA_OP_LOAD
,
3214 .name
= (const char * const[]) {
3215 "l32i", "l32i.n", NULL
,
3217 .translate
= translate_ldst
,
3218 .par
= (const uint32_t[]){MO_TEUL
, false, false},
3219 .op_flags
= XTENSA_OP_NAME_ARRAY
| XTENSA_OP_LOAD
,
3222 .translate
= translate_l32r
,
3223 .op_flags
= XTENSA_OP_LOAD
,
3226 .translate
= translate_ldst
,
3227 .par
= (const uint32_t[]){MO_UB
, false, false},
3228 .op_flags
= XTENSA_OP_LOAD
,
3231 .translate
= translate_lct
,
3232 .op_flags
= XTENSA_OP_PRIVILEGED
,
3235 .translate
= translate_nop
,
3236 .op_flags
= XTENSA_OP_PRIVILEGED
,
3239 .translate
= translate_mac16
,
3240 .par
= (const uint32_t[]){MAC16_NONE
, 0, -4},
3241 .op_flags
= XTENSA_OP_LOAD
,
3244 .translate
= translate_mac16
,
3245 .par
= (const uint32_t[]){MAC16_NONE
, 0, 4},
3246 .op_flags
= XTENSA_OP_LOAD
,
3249 .op_flags
= XTENSA_OP_ILL
,
3252 .translate
= translate_lct
,
3253 .op_flags
= XTENSA_OP_PRIVILEGED
,
3256 .translate
= translate_nop
,
3257 .op_flags
= XTENSA_OP_PRIVILEGED
,
3259 .name
= (const char * const[]) {
3260 "loop", "loop.w15", NULL
,
3262 .translate
= translate_loop
,
3263 .par
= (const uint32_t[]){TCG_COND_NEVER
},
3264 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3266 .name
= (const char * const[]) {
3267 "loopgtz", "loopgtz.w15", NULL
,
3269 .translate
= translate_loop
,
3270 .par
= (const uint32_t[]){TCG_COND_GT
},
3271 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3273 .name
= (const char * const[]) {
3274 "loopnez", "loopnez.w15", NULL
,
3276 .translate
= translate_loop
,
3277 .par
= (const uint32_t[]){TCG_COND_NE
},
3278 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3281 .translate
= translate_smax
,
3284 .translate
= translate_umax
,
3287 .translate
= translate_memw
,
3290 .translate
= translate_smin
,
3293 .translate
= translate_umin
,
3295 .name
= (const char * const[]) {
3296 "mov", "mov.n", NULL
,
3298 .translate
= translate_mov
,
3299 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3302 .translate
= translate_movcond
,
3303 .par
= (const uint32_t[]){TCG_COND_EQ
},
3306 .translate
= translate_movp
,
3307 .par
= (const uint32_t[]){TCG_COND_EQ
},
3310 .translate
= translate_movcond
,
3311 .par
= (const uint32_t[]){TCG_COND_GE
},
3314 .translate
= translate_movi
,
3317 .translate
= translate_movi
,
3320 .translate
= translate_movcond
,
3321 .par
= (const uint32_t[]){TCG_COND_LT
},
3324 .translate
= translate_movcond
,
3325 .par
= (const uint32_t[]){TCG_COND_NE
},
3328 .translate
= translate_movsp
,
3329 .op_flags
= XTENSA_OP_ALLOCA
,
3332 .translate
= translate_movp
,
3333 .par
= (const uint32_t[]){TCG_COND_NE
},
3335 .name
= "mul.aa.hh",
3336 .translate
= translate_mac16
,
3337 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3339 .name
= "mul.aa.hl",
3340 .translate
= translate_mac16
,
3341 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3343 .name
= "mul.aa.lh",
3344 .translate
= translate_mac16
,
3345 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3347 .name
= "mul.aa.ll",
3348 .translate
= translate_mac16
,
3349 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3351 .name
= "mul.ad.hh",
3352 .translate
= translate_mac16
,
3353 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3355 .name
= "mul.ad.hl",
3356 .translate
= translate_mac16
,
3357 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3359 .name
= "mul.ad.lh",
3360 .translate
= translate_mac16
,
3361 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3363 .name
= "mul.ad.ll",
3364 .translate
= translate_mac16
,
3365 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3367 .name
= "mul.da.hh",
3368 .translate
= translate_mac16
,
3369 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3371 .name
= "mul.da.hl",
3372 .translate
= translate_mac16
,
3373 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3375 .name
= "mul.da.lh",
3376 .translate
= translate_mac16
,
3377 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3379 .name
= "mul.da.ll",
3380 .translate
= translate_mac16
,
3381 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3383 .name
= "mul.dd.hh",
3384 .translate
= translate_mac16
,
3385 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HH
, 0},
3387 .name
= "mul.dd.hl",
3388 .translate
= translate_mac16
,
3389 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_HL
, 0},
3391 .name
= "mul.dd.lh",
3392 .translate
= translate_mac16
,
3393 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LH
, 0},
3395 .name
= "mul.dd.ll",
3396 .translate
= translate_mac16
,
3397 .par
= (const uint32_t[]){MAC16_MUL
, MAC16_LL
, 0},
3400 .translate
= translate_mul16
,
3401 .par
= (const uint32_t[]){true},
3404 .translate
= translate_mul16
,
3405 .par
= (const uint32_t[]){false},
3407 .name
= "mula.aa.hh",
3408 .translate
= translate_mac16
,
3409 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3411 .name
= "mula.aa.hl",
3412 .translate
= translate_mac16
,
3413 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3415 .name
= "mula.aa.lh",
3416 .translate
= translate_mac16
,
3417 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3419 .name
= "mula.aa.ll",
3420 .translate
= translate_mac16
,
3421 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3423 .name
= "mula.ad.hh",
3424 .translate
= translate_mac16
,
3425 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3427 .name
= "mula.ad.hl",
3428 .translate
= translate_mac16
,
3429 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3431 .name
= "mula.ad.lh",
3432 .translate
= translate_mac16
,
3433 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3435 .name
= "mula.ad.ll",
3436 .translate
= translate_mac16
,
3437 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3439 .name
= "mula.da.hh",
3440 .translate
= translate_mac16
,
3441 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3443 .name
= "mula.da.hh.lddec",
3444 .translate
= translate_mac16
,
3445 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, -4},
3447 .name
= "mula.da.hh.ldinc",
3448 .translate
= translate_mac16
,
3449 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 4},
3451 .name
= "mula.da.hl",
3452 .translate
= translate_mac16
,
3453 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3455 .name
= "mula.da.hl.lddec",
3456 .translate
= translate_mac16
,
3457 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, -4},
3459 .name
= "mula.da.hl.ldinc",
3460 .translate
= translate_mac16
,
3461 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 4},
3463 .name
= "mula.da.lh",
3464 .translate
= translate_mac16
,
3465 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3467 .name
= "mula.da.lh.lddec",
3468 .translate
= translate_mac16
,
3469 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, -4},
3471 .name
= "mula.da.lh.ldinc",
3472 .translate
= translate_mac16
,
3473 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 4},
3475 .name
= "mula.da.ll",
3476 .translate
= translate_mac16
,
3477 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3479 .name
= "mula.da.ll.lddec",
3480 .translate
= translate_mac16
,
3481 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, -4},
3483 .name
= "mula.da.ll.ldinc",
3484 .translate
= translate_mac16
,
3485 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 4},
3487 .name
= "mula.dd.hh",
3488 .translate
= translate_mac16
,
3489 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 0},
3491 .name
= "mula.dd.hh.lddec",
3492 .translate
= translate_mac16
,
3493 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, -4},
3495 .name
= "mula.dd.hh.ldinc",
3496 .translate
= translate_mac16
,
3497 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HH
, 4},
3499 .name
= "mula.dd.hl",
3500 .translate
= translate_mac16
,
3501 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 0},
3503 .name
= "mula.dd.hl.lddec",
3504 .translate
= translate_mac16
,
3505 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, -4},
3507 .name
= "mula.dd.hl.ldinc",
3508 .translate
= translate_mac16
,
3509 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_HL
, 4},
3511 .name
= "mula.dd.lh",
3512 .translate
= translate_mac16
,
3513 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 0},
3515 .name
= "mula.dd.lh.lddec",
3516 .translate
= translate_mac16
,
3517 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, -4},
3519 .name
= "mula.dd.lh.ldinc",
3520 .translate
= translate_mac16
,
3521 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LH
, 4},
3523 .name
= "mula.dd.ll",
3524 .translate
= translate_mac16
,
3525 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 0},
3527 .name
= "mula.dd.ll.lddec",
3528 .translate
= translate_mac16
,
3529 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, -4},
3531 .name
= "mula.dd.ll.ldinc",
3532 .translate
= translate_mac16
,
3533 .par
= (const uint32_t[]){MAC16_MULA
, MAC16_LL
, 4},
3536 .translate
= translate_mull
,
3538 .name
= "muls.aa.hh",
3539 .translate
= translate_mac16
,
3540 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3542 .name
= "muls.aa.hl",
3543 .translate
= translate_mac16
,
3544 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3546 .name
= "muls.aa.lh",
3547 .translate
= translate_mac16
,
3548 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3550 .name
= "muls.aa.ll",
3551 .translate
= translate_mac16
,
3552 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3554 .name
= "muls.ad.hh",
3555 .translate
= translate_mac16
,
3556 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3558 .name
= "muls.ad.hl",
3559 .translate
= translate_mac16
,
3560 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3562 .name
= "muls.ad.lh",
3563 .translate
= translate_mac16
,
3564 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3566 .name
= "muls.ad.ll",
3567 .translate
= translate_mac16
,
3568 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3570 .name
= "muls.da.hh",
3571 .translate
= translate_mac16
,
3572 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3574 .name
= "muls.da.hl",
3575 .translate
= translate_mac16
,
3576 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3578 .name
= "muls.da.lh",
3579 .translate
= translate_mac16
,
3580 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3582 .name
= "muls.da.ll",
3583 .translate
= translate_mac16
,
3584 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3586 .name
= "muls.dd.hh",
3587 .translate
= translate_mac16
,
3588 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HH
, 0},
3590 .name
= "muls.dd.hl",
3591 .translate
= translate_mac16
,
3592 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_HL
, 0},
3594 .name
= "muls.dd.lh",
3595 .translate
= translate_mac16
,
3596 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LH
, 0},
3598 .name
= "muls.dd.ll",
3599 .translate
= translate_mac16
,
3600 .par
= (const uint32_t[]){MAC16_MULS
, MAC16_LL
, 0},
3603 .translate
= translate_mulh
,
3604 .par
= (const uint32_t[]){true},
3607 .translate
= translate_mulh
,
3608 .par
= (const uint32_t[]){false},
3611 .translate
= translate_neg
,
3613 .name
= (const char * const[]) {
3614 "nop", "nop.n", NULL
,
3616 .translate
= translate_nop
,
3617 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3620 .translate
= translate_nsa
,
3623 .translate
= translate_nsau
,
3626 .translate
= translate_or
,
3629 .translate
= translate_boolean
,
3630 .par
= (const uint32_t[]){BOOLEAN_OR
},
3633 .translate
= translate_boolean
,
3634 .par
= (const uint32_t[]){BOOLEAN_ORC
},
3637 .translate
= translate_ptlb
,
3638 .par
= (const uint32_t[]){true},
3639 .op_flags
= XTENSA_OP_PRIVILEGED
,
3642 .translate
= translate_nop
,
3645 .translate
= translate_nop
,
3648 .translate
= translate_nop
,
3651 .translate
= translate_nop
,
3654 .translate
= translate_nop
,
3657 .translate
= translate_ptlb
,
3658 .par
= (const uint32_t[]){false},
3659 .op_flags
= XTENSA_OP_PRIVILEGED
,
3662 .translate
= translate_pptlb
,
3663 .op_flags
= XTENSA_OP_PRIVILEGED
,
3666 .translate
= translate_quos
,
3667 .par
= (const uint32_t[]){true},
3668 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3671 .translate
= translate_quou
,
3672 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3675 .translate
= translate_rtlb
,
3676 .par
= (const uint32_t[]){true, 0},
3677 .op_flags
= XTENSA_OP_PRIVILEGED
,
3680 .translate
= translate_rtlb
,
3681 .par
= (const uint32_t[]){true, 1},
3682 .op_flags
= XTENSA_OP_PRIVILEGED
,
3684 .name
= "read_impwire",
3685 .translate
= translate_read_impwire
,
3688 .translate
= translate_quos
,
3689 .par
= (const uint32_t[]){false},
3690 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3693 .translate
= translate_remu
,
3694 .op_flags
= XTENSA_OP_DIVIDE_BY_ZERO
,
3697 .translate
= translate_rer
,
3698 .op_flags
= XTENSA_OP_PRIVILEGED
,
3700 .name
= (const char * const[]) {
3701 "ret", "ret.n", NULL
,
3703 .translate
= translate_ret
,
3704 .op_flags
= XTENSA_OP_NAME_ARRAY
,
3706 .name
= (const char * const[]) {
3707 "retw", "retw.n", NULL
,
3709 .translate
= translate_retw
,
3710 .test_exceptions
= test_exceptions_retw
,
3711 .op_flags
= XTENSA_OP_UNDERFLOW
| XTENSA_OP_NAME_ARRAY
,
3714 .op_flags
= XTENSA_OP_ILL
,
3717 .translate
= translate_rfde
,
3718 .op_flags
= XTENSA_OP_PRIVILEGED
,
3721 .op_flags
= XTENSA_OP_ILL
,
3724 .translate
= translate_rfe
,
3725 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3728 .translate
= translate_rfi
,
3729 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3732 .translate
= translate_rfw
,
3733 .par
= (const uint32_t[]){true},
3734 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3737 .translate
= translate_rfw
,
3738 .par
= (const uint32_t[]){false},
3739 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_CHECK_INTERRUPTS
,
3742 .translate
= translate_rtlb
,
3743 .par
= (const uint32_t[]){false, 0},
3744 .op_flags
= XTENSA_OP_PRIVILEGED
,
3747 .translate
= translate_rtlb
,
3748 .par
= (const uint32_t[]){false, 1},
3749 .op_flags
= XTENSA_OP_PRIVILEGED
,
3752 .translate
= translate_rptlb0
,
3753 .op_flags
= XTENSA_OP_PRIVILEGED
,
3756 .translate
= translate_rptlb1
,
3757 .op_flags
= XTENSA_OP_PRIVILEGED
,
3760 .translate
= translate_rotw
,
3761 .op_flags
= XTENSA_OP_PRIVILEGED
|
3762 XTENSA_OP_EXIT_TB_M1
|
3763 XTENSA_OP_SYNC_REGISTER_WINDOW
,
3766 .translate
= translate_rsil
,
3768 XTENSA_OP_PRIVILEGED
|
3769 XTENSA_OP_EXIT_TB_0
|
3770 XTENSA_OP_CHECK_INTERRUPTS
,
3773 .translate
= translate_rsr
,
3774 .par
= (const uint32_t[]){176},
3775 .op_flags
= XTENSA_OP_PRIVILEGED
,
3778 .translate
= translate_rsr
,
3779 .par
= (const uint32_t[]){208},
3780 .op_flags
= XTENSA_OP_PRIVILEGED
,
3782 .name
= "rsr.acchi",
3783 .translate
= translate_rsr
,
3784 .test_exceptions
= test_exceptions_sr
,
3785 .par
= (const uint32_t[]){
3787 XTENSA_OPTION_MAC16
,
3790 .name
= "rsr.acclo",
3791 .translate
= translate_rsr
,
3792 .test_exceptions
= test_exceptions_sr
,
3793 .par
= (const uint32_t[]){
3795 XTENSA_OPTION_MAC16
,
3798 .name
= "rsr.atomctl",
3799 .translate
= translate_rsr
,
3800 .test_exceptions
= test_exceptions_sr
,
3801 .par
= (const uint32_t[]){
3803 XTENSA_OPTION_ATOMCTL
,
3805 .op_flags
= XTENSA_OP_PRIVILEGED
,
3808 .translate
= translate_rsr
,
3809 .test_exceptions
= test_exceptions_sr
,
3810 .par
= (const uint32_t[]){
3812 XTENSA_OPTION_BOOLEAN
,
3815 .name
= "rsr.cacheadrdis",
3816 .translate
= translate_rsr
,
3817 .test_exceptions
= test_exceptions_sr
,
3818 .par
= (const uint32_t[]){
3822 .op_flags
= XTENSA_OP_PRIVILEGED
,
3824 .name
= "rsr.cacheattr",
3825 .translate
= translate_rsr
,
3826 .test_exceptions
= test_exceptions_sr
,
3827 .par
= (const uint32_t[]){
3829 XTENSA_OPTION_CACHEATTR
,
3831 .op_flags
= XTENSA_OP_PRIVILEGED
,
3833 .name
= "rsr.ccompare0",
3834 .translate
= translate_rsr
,
3835 .test_exceptions
= test_exceptions_ccompare
,
3836 .par
= (const uint32_t[]){
3838 XTENSA_OPTION_TIMER_INTERRUPT
,
3840 .op_flags
= XTENSA_OP_PRIVILEGED
,
3842 .name
= "rsr.ccompare1",
3843 .translate
= translate_rsr
,
3844 .test_exceptions
= test_exceptions_ccompare
,
3845 .par
= (const uint32_t[]){
3847 XTENSA_OPTION_TIMER_INTERRUPT
,
3849 .op_flags
= XTENSA_OP_PRIVILEGED
,
3851 .name
= "rsr.ccompare2",
3852 .translate
= translate_rsr
,
3853 .test_exceptions
= test_exceptions_ccompare
,
3854 .par
= (const uint32_t[]){
3856 XTENSA_OPTION_TIMER_INTERRUPT
,
3858 .op_flags
= XTENSA_OP_PRIVILEGED
,
3860 .name
= "rsr.ccount",
3861 .translate
= translate_rsr_ccount
,
3862 .test_exceptions
= test_exceptions_sr
,
3863 .par
= (const uint32_t[]){
3865 XTENSA_OPTION_TIMER_INTERRUPT
,
3867 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
3869 .name
= "rsr.configid0",
3870 .translate
= translate_rsr
,
3871 .par
= (const uint32_t[]){CONFIGID0
},
3872 .op_flags
= XTENSA_OP_PRIVILEGED
,
3874 .name
= "rsr.configid1",
3875 .translate
= translate_rsr
,
3876 .par
= (const uint32_t[]){CONFIGID1
},
3877 .op_flags
= XTENSA_OP_PRIVILEGED
,
3879 .name
= "rsr.cpenable",
3880 .translate
= translate_rsr
,
3881 .test_exceptions
= test_exceptions_sr
,
3882 .par
= (const uint32_t[]){
3884 XTENSA_OPTION_COPROCESSOR
,
3886 .op_flags
= XTENSA_OP_PRIVILEGED
,
3888 .name
= "rsr.dbreaka0",
3889 .translate
= translate_rsr
,
3890 .test_exceptions
= test_exceptions_dbreak
,
3891 .par
= (const uint32_t[]){
3893 XTENSA_OPTION_DEBUG
,
3895 .op_flags
= XTENSA_OP_PRIVILEGED
,
3897 .name
= "rsr.dbreaka1",
3898 .translate
= translate_rsr
,
3899 .test_exceptions
= test_exceptions_dbreak
,
3900 .par
= (const uint32_t[]){
3902 XTENSA_OPTION_DEBUG
,
3904 .op_flags
= XTENSA_OP_PRIVILEGED
,
3906 .name
= "rsr.dbreakc0",
3907 .translate
= translate_rsr
,
3908 .test_exceptions
= test_exceptions_dbreak
,
3909 .par
= (const uint32_t[]){
3911 XTENSA_OPTION_DEBUG
,
3913 .op_flags
= XTENSA_OP_PRIVILEGED
,
3915 .name
= "rsr.dbreakc1",
3916 .translate
= translate_rsr
,
3917 .test_exceptions
= test_exceptions_dbreak
,
3918 .par
= (const uint32_t[]){
3920 XTENSA_OPTION_DEBUG
,
3922 .op_flags
= XTENSA_OP_PRIVILEGED
,
3925 .translate
= translate_rsr
,
3926 .test_exceptions
= test_exceptions_sr
,
3927 .par
= (const uint32_t[]){
3929 XTENSA_OPTION_DEBUG
,
3931 .op_flags
= XTENSA_OP_PRIVILEGED
,
3933 .name
= "rsr.debugcause",
3934 .translate
= translate_rsr
,
3935 .test_exceptions
= test_exceptions_sr
,
3936 .par
= (const uint32_t[]){
3938 XTENSA_OPTION_DEBUG
,
3940 .op_flags
= XTENSA_OP_PRIVILEGED
,
3943 .translate
= translate_rsr
,
3944 .test_exceptions
= test_exceptions_sr
,
3945 .par
= (const uint32_t[]){
3947 XTENSA_OPTION_EXCEPTION
,
3949 .op_flags
= XTENSA_OP_PRIVILEGED
,
3951 .name
= "rsr.dtlbcfg",
3952 .translate
= translate_rsr
,
3953 .test_exceptions
= test_exceptions_sr
,
3954 .par
= (const uint32_t[]){
3958 .op_flags
= XTENSA_OP_PRIVILEGED
,
3961 .translate
= translate_rsr
,
3962 .test_exceptions
= test_exceptions_sr
,
3963 .par
= (const uint32_t[]){
3965 XTENSA_OPTION_EXCEPTION
,
3967 .op_flags
= XTENSA_OP_PRIVILEGED
,
3970 .translate
= translate_rsr
,
3971 .test_exceptions
= test_exceptions_hpi
,
3972 .par
= (const uint32_t[]){
3974 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
3976 .op_flags
= XTENSA_OP_PRIVILEGED
,
3979 .translate
= translate_rsr
,
3980 .test_exceptions
= test_exceptions_hpi
,
3981 .par
= (const uint32_t[]){
3983 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
3985 .op_flags
= XTENSA_OP_PRIVILEGED
,
3988 .translate
= translate_rsr
,
3989 .test_exceptions
= test_exceptions_hpi
,
3990 .par
= (const uint32_t[]){
3992 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
3994 .op_flags
= XTENSA_OP_PRIVILEGED
,
3997 .translate
= translate_rsr
,
3998 .test_exceptions
= test_exceptions_hpi
,
3999 .par
= (const uint32_t[]){
4001 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4003 .op_flags
= XTENSA_OP_PRIVILEGED
,
4006 .translate
= translate_rsr
,
4007 .test_exceptions
= test_exceptions_hpi
,
4008 .par
= (const uint32_t[]){
4010 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4012 .op_flags
= XTENSA_OP_PRIVILEGED
,
4015 .translate
= translate_rsr
,
4016 .test_exceptions
= test_exceptions_hpi
,
4017 .par
= (const uint32_t[]){
4019 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4021 .op_flags
= XTENSA_OP_PRIVILEGED
,
4024 .translate
= translate_rsr
,
4025 .test_exceptions
= test_exceptions_hpi
,
4026 .par
= (const uint32_t[]){
4028 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4030 .op_flags
= XTENSA_OP_PRIVILEGED
,
4033 .translate
= translate_rsr
,
4034 .test_exceptions
= test_exceptions_hpi
,
4035 .par
= (const uint32_t[]){
4037 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4039 .op_flags
= XTENSA_OP_PRIVILEGED
,
4042 .translate
= translate_rsr
,
4043 .test_exceptions
= test_exceptions_hpi
,
4044 .par
= (const uint32_t[]){
4046 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4048 .op_flags
= XTENSA_OP_PRIVILEGED
,
4051 .translate
= translate_rsr
,
4052 .test_exceptions
= test_exceptions_hpi
,
4053 .par
= (const uint32_t[]){
4055 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4057 .op_flags
= XTENSA_OP_PRIVILEGED
,
4060 .translate
= translate_rsr
,
4061 .test_exceptions
= test_exceptions_hpi
,
4062 .par
= (const uint32_t[]){
4064 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4066 .op_flags
= XTENSA_OP_PRIVILEGED
,
4069 .translate
= translate_rsr
,
4070 .test_exceptions
= test_exceptions_hpi
,
4071 .par
= (const uint32_t[]){
4073 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4075 .op_flags
= XTENSA_OP_PRIVILEGED
,
4077 .name
= "rsr.eraccess",
4078 .translate
= translate_rsr
,
4079 .par
= (const uint32_t[]){ERACCESS
},
4080 .op_flags
= XTENSA_OP_PRIVILEGED
,
4082 .name
= "rsr.exccause",
4083 .translate
= translate_rsr
,
4084 .test_exceptions
= test_exceptions_sr
,
4085 .par
= (const uint32_t[]){
4087 XTENSA_OPTION_EXCEPTION
,
4089 .op_flags
= XTENSA_OP_PRIVILEGED
,
4091 .name
= "rsr.excsave1",
4092 .translate
= translate_rsr
,
4093 .test_exceptions
= test_exceptions_sr
,
4094 .par
= (const uint32_t[]){
4096 XTENSA_OPTION_EXCEPTION
,
4098 .op_flags
= XTENSA_OP_PRIVILEGED
,
4100 .name
= "rsr.excsave2",
4101 .translate
= translate_rsr
,
4102 .test_exceptions
= test_exceptions_hpi
,
4103 .par
= (const uint32_t[]){
4105 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4107 .op_flags
= XTENSA_OP_PRIVILEGED
,
4109 .name
= "rsr.excsave3",
4110 .translate
= translate_rsr
,
4111 .test_exceptions
= test_exceptions_hpi
,
4112 .par
= (const uint32_t[]){
4114 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4116 .op_flags
= XTENSA_OP_PRIVILEGED
,
4118 .name
= "rsr.excsave4",
4119 .translate
= translate_rsr
,
4120 .test_exceptions
= test_exceptions_hpi
,
4121 .par
= (const uint32_t[]){
4123 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4125 .op_flags
= XTENSA_OP_PRIVILEGED
,
4127 .name
= "rsr.excsave5",
4128 .translate
= translate_rsr
,
4129 .test_exceptions
= test_exceptions_hpi
,
4130 .par
= (const uint32_t[]){
4132 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4134 .op_flags
= XTENSA_OP_PRIVILEGED
,
4136 .name
= "rsr.excsave6",
4137 .translate
= translate_rsr
,
4138 .test_exceptions
= test_exceptions_hpi
,
4139 .par
= (const uint32_t[]){
4141 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4143 .op_flags
= XTENSA_OP_PRIVILEGED
,
4145 .name
= "rsr.excsave7",
4146 .translate
= translate_rsr
,
4147 .test_exceptions
= test_exceptions_hpi
,
4148 .par
= (const uint32_t[]){
4150 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4152 .op_flags
= XTENSA_OP_PRIVILEGED
,
4154 .name
= "rsr.excvaddr",
4155 .translate
= translate_rsr
,
4156 .test_exceptions
= test_exceptions_sr
,
4157 .par
= (const uint32_t[]){
4159 XTENSA_OPTION_EXCEPTION
,
4161 .op_flags
= XTENSA_OP_PRIVILEGED
,
4163 .name
= "rsr.ibreaka0",
4164 .translate
= translate_rsr
,
4165 .test_exceptions
= test_exceptions_ibreak
,
4166 .par
= (const uint32_t[]){
4168 XTENSA_OPTION_DEBUG
,
4170 .op_flags
= XTENSA_OP_PRIVILEGED
,
4172 .name
= "rsr.ibreaka1",
4173 .translate
= translate_rsr
,
4174 .test_exceptions
= test_exceptions_ibreak
,
4175 .par
= (const uint32_t[]){
4177 XTENSA_OPTION_DEBUG
,
4179 .op_flags
= XTENSA_OP_PRIVILEGED
,
4181 .name
= "rsr.ibreakenable",
4182 .translate
= translate_rsr
,
4183 .test_exceptions
= test_exceptions_sr
,
4184 .par
= (const uint32_t[]){
4186 XTENSA_OPTION_DEBUG
,
4188 .op_flags
= XTENSA_OP_PRIVILEGED
,
4190 .name
= "rsr.icount",
4191 .translate
= translate_rsr
,
4192 .test_exceptions
= test_exceptions_sr
,
4193 .par
= (const uint32_t[]){
4195 XTENSA_OPTION_DEBUG
,
4197 .op_flags
= XTENSA_OP_PRIVILEGED
,
4199 .name
= "rsr.icountlevel",
4200 .translate
= translate_rsr
,
4201 .test_exceptions
= test_exceptions_sr
,
4202 .par
= (const uint32_t[]){
4204 XTENSA_OPTION_DEBUG
,
4206 .op_flags
= XTENSA_OP_PRIVILEGED
,
4208 .name
= "rsr.intclear",
4209 .translate
= translate_rsr
,
4210 .test_exceptions
= test_exceptions_sr
,
4211 .par
= (const uint32_t[]){
4213 XTENSA_OPTION_INTERRUPT
,
4215 .op_flags
= XTENSA_OP_PRIVILEGED
,
4217 .name
= "rsr.intenable",
4218 .translate
= translate_rsr
,
4219 .test_exceptions
= test_exceptions_sr
,
4220 .par
= (const uint32_t[]){
4222 XTENSA_OPTION_INTERRUPT
,
4224 .op_flags
= XTENSA_OP_PRIVILEGED
,
4226 .name
= "rsr.interrupt",
4227 .translate
= translate_rsr_ccount
,
4228 .test_exceptions
= test_exceptions_sr
,
4229 .par
= (const uint32_t[]){
4231 XTENSA_OPTION_INTERRUPT
,
4233 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4235 .name
= "rsr.intset",
4236 .translate
= translate_rsr_ccount
,
4237 .test_exceptions
= test_exceptions_sr
,
4238 .par
= (const uint32_t[]){
4240 XTENSA_OPTION_INTERRUPT
,
4242 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4244 .name
= "rsr.itlbcfg",
4245 .translate
= translate_rsr
,
4246 .test_exceptions
= test_exceptions_sr
,
4247 .par
= (const uint32_t[]){
4251 .op_flags
= XTENSA_OP_PRIVILEGED
,
4254 .translate
= translate_rsr
,
4255 .test_exceptions
= test_exceptions_sr
,
4256 .par
= (const uint32_t[]){
4261 .name
= "rsr.lcount",
4262 .translate
= translate_rsr
,
4263 .test_exceptions
= test_exceptions_sr
,
4264 .par
= (const uint32_t[]){
4270 .translate
= translate_rsr
,
4271 .test_exceptions
= test_exceptions_sr
,
4272 .par
= (const uint32_t[]){
4277 .name
= "rsr.litbase",
4278 .translate
= translate_rsr
,
4279 .test_exceptions
= test_exceptions_sr
,
4280 .par
= (const uint32_t[]){
4282 XTENSA_OPTION_EXTENDED_L32R
,
4286 .translate
= translate_rsr
,
4287 .test_exceptions
= test_exceptions_sr
,
4288 .par
= (const uint32_t[]){
4290 XTENSA_OPTION_MAC16
,
4294 .translate
= translate_rsr
,
4295 .test_exceptions
= test_exceptions_sr
,
4296 .par
= (const uint32_t[]){
4298 XTENSA_OPTION_MAC16
,
4302 .translate
= translate_rsr
,
4303 .test_exceptions
= test_exceptions_sr
,
4304 .par
= (const uint32_t[]){
4306 XTENSA_OPTION_MAC16
,
4310 .translate
= translate_rsr
,
4311 .test_exceptions
= test_exceptions_sr
,
4312 .par
= (const uint32_t[]){
4314 XTENSA_OPTION_MAC16
,
4317 .name
= "rsr.memctl",
4318 .translate
= translate_rsr
,
4319 .par
= (const uint32_t[]){MEMCTL
},
4320 .op_flags
= XTENSA_OP_PRIVILEGED
,
4323 .translate
= translate_rsr
,
4324 .test_exceptions
= test_exceptions_sr
,
4325 .par
= (const uint32_t[]){
4327 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4329 .op_flags
= XTENSA_OP_PRIVILEGED
,
4332 .translate
= translate_rsr
,
4333 .test_exceptions
= test_exceptions_sr
,
4334 .par
= (const uint32_t[]){
4336 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4338 .op_flags
= XTENSA_OP_PRIVILEGED
,
4341 .translate
= translate_rsr
,
4342 .test_exceptions
= test_exceptions_sr
,
4343 .par
= (const uint32_t[]){
4345 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4347 .op_flags
= XTENSA_OP_PRIVILEGED
,
4349 .name
= "rsr.mesave",
4350 .translate
= translate_rsr
,
4351 .test_exceptions
= test_exceptions_sr
,
4352 .par
= (const uint32_t[]){
4354 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4356 .op_flags
= XTENSA_OP_PRIVILEGED
,
4359 .translate
= translate_rsr
,
4360 .test_exceptions
= test_exceptions_sr
,
4361 .par
= (const uint32_t[]){
4363 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4365 .op_flags
= XTENSA_OP_PRIVILEGED
,
4367 .name
= "rsr.mevaddr",
4368 .translate
= translate_rsr
,
4369 .test_exceptions
= test_exceptions_sr
,
4370 .par
= (const uint32_t[]){
4372 XTENSA_OPTION_MEMORY_ECC_PARITY
,
4374 .op_flags
= XTENSA_OP_PRIVILEGED
,
4376 .name
= "rsr.misc0",
4377 .translate
= translate_rsr
,
4378 .test_exceptions
= test_exceptions_sr
,
4379 .par
= (const uint32_t[]){
4381 XTENSA_OPTION_MISC_SR
,
4383 .op_flags
= XTENSA_OP_PRIVILEGED
,
4385 .name
= "rsr.misc1",
4386 .translate
= translate_rsr
,
4387 .test_exceptions
= test_exceptions_sr
,
4388 .par
= (const uint32_t[]){
4390 XTENSA_OPTION_MISC_SR
,
4392 .op_flags
= XTENSA_OP_PRIVILEGED
,
4394 .name
= "rsr.misc2",
4395 .translate
= translate_rsr
,
4396 .test_exceptions
= test_exceptions_sr
,
4397 .par
= (const uint32_t[]){
4399 XTENSA_OPTION_MISC_SR
,
4401 .op_flags
= XTENSA_OP_PRIVILEGED
,
4403 .name
= "rsr.misc3",
4404 .translate
= translate_rsr
,
4405 .test_exceptions
= test_exceptions_sr
,
4406 .par
= (const uint32_t[]){
4408 XTENSA_OPTION_MISC_SR
,
4410 .op_flags
= XTENSA_OP_PRIVILEGED
,
4412 .name
= "rsr.mpucfg",
4413 .translate
= translate_rsr
,
4414 .test_exceptions
= test_exceptions_sr
,
4415 .par
= (const uint32_t[]){
4419 .op_flags
= XTENSA_OP_PRIVILEGED
,
4421 .name
= "rsr.mpuenb",
4422 .translate
= translate_rsr
,
4423 .test_exceptions
= test_exceptions_sr
,
4424 .par
= (const uint32_t[]){
4428 .op_flags
= XTENSA_OP_PRIVILEGED
,
4430 .name
= "rsr.prefctl",
4431 .translate
= translate_rsr
,
4432 .par
= (const uint32_t[]){PREFCTL
},
4435 .translate
= translate_rsr
,
4436 .test_exceptions
= test_exceptions_sr
,
4437 .par
= (const uint32_t[]){
4439 XTENSA_OPTION_PROCESSOR_ID
,
4441 .op_flags
= XTENSA_OP_PRIVILEGED
,
4444 .translate
= translate_rsr
,
4445 .test_exceptions
= test_exceptions_sr
,
4446 .par
= (const uint32_t[]){
4448 XTENSA_OPTION_EXCEPTION
,
4450 .op_flags
= XTENSA_OP_PRIVILEGED
,
4452 .name
= "rsr.ptevaddr",
4453 .translate
= translate_rsr_ptevaddr
,
4454 .test_exceptions
= test_exceptions_sr
,
4455 .par
= (const uint32_t[]){
4459 .op_flags
= XTENSA_OP_PRIVILEGED
,
4461 .name
= "rsr.rasid",
4462 .translate
= translate_rsr
,
4463 .test_exceptions
= test_exceptions_sr
,
4464 .par
= (const uint32_t[]){
4468 .op_flags
= XTENSA_OP_PRIVILEGED
,
4471 .translate
= translate_rsr
,
4472 .par
= (const uint32_t[]){SAR
},
4474 .name
= "rsr.scompare1",
4475 .translate
= translate_rsr
,
4476 .test_exceptions
= test_exceptions_sr
,
4477 .par
= (const uint32_t[]){
4479 XTENSA_OPTION_CONDITIONAL_STORE
,
4482 .name
= "rsr.vecbase",
4483 .translate
= translate_rsr
,
4484 .test_exceptions
= test_exceptions_sr
,
4485 .par
= (const uint32_t[]){
4487 XTENSA_OPTION_RELOCATABLE_VECTOR
,
4489 .op_flags
= XTENSA_OP_PRIVILEGED
,
4491 .name
= "rsr.windowbase",
4492 .translate
= translate_rsr
,
4493 .test_exceptions
= test_exceptions_sr
,
4494 .par
= (const uint32_t[]){
4496 XTENSA_OPTION_WINDOWED_REGISTER
,
4498 .op_flags
= XTENSA_OP_PRIVILEGED
,
4500 .name
= "rsr.windowstart",
4501 .translate
= translate_rsr
,
4502 .test_exceptions
= test_exceptions_sr
,
4503 .par
= (const uint32_t[]){
4505 XTENSA_OPTION_WINDOWED_REGISTER
,
4507 .op_flags
= XTENSA_OP_PRIVILEGED
,
4510 .translate
= translate_nop
,
4512 .name
= "rur.expstate",
4513 .translate
= translate_rur
,
4514 .par
= (const uint32_t[]){EXPSTATE
},
4516 .name
= "rur.threadptr",
4517 .translate
= translate_rur
,
4518 .par
= (const uint32_t[]){THREADPTR
},
4521 .translate
= translate_ldst
,
4522 .par
= (const uint32_t[]){MO_TEUW
, false, true},
4523 .op_flags
= XTENSA_OP_STORE
,
4526 .translate
= translate_s32c1i
,
4527 .op_flags
= XTENSA_OP_LOAD
| XTENSA_OP_STORE
,
4530 .translate
= translate_s32e
,
4531 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_STORE
,
4534 .translate
= translate_s32ex
,
4535 .op_flags
= XTENSA_OP_LOAD
| XTENSA_OP_STORE
,
4537 .name
= (const char * const[]) {
4538 "s32i", "s32i.n", "s32nb", NULL
,
4540 .translate
= translate_ldst
,
4541 .par
= (const uint32_t[]){MO_TEUL
, false, true},
4542 .op_flags
= XTENSA_OP_NAME_ARRAY
| XTENSA_OP_STORE
,
4545 .translate
= translate_ldst
,
4546 .par
= (const uint32_t[]){MO_TEUL
| MO_ALIGN
, true, true},
4547 .op_flags
= XTENSA_OP_STORE
,
4550 .translate
= translate_ldst
,
4551 .par
= (const uint32_t[]){MO_UB
, false, true},
4552 .op_flags
= XTENSA_OP_STORE
,
4555 .translate
= translate_salt
,
4556 .par
= (const uint32_t[]){TCG_COND_LT
},
4559 .translate
= translate_salt
,
4560 .par
= (const uint32_t[]){TCG_COND_LTU
},
4563 .translate
= translate_nop
,
4564 .op_flags
= XTENSA_OP_PRIVILEGED
,
4567 .translate
= translate_nop
,
4568 .op_flags
= XTENSA_OP_PRIVILEGED
,
4570 .name
= "setb_expstate",
4571 .translate
= translate_setb_expstate
,
4574 .translate
= translate_sext
,
4577 .translate
= translate_nop
,
4578 .op_flags
= XTENSA_OP_PRIVILEGED
,
4581 .translate
= translate_nop
,
4582 .op_flags
= XTENSA_OP_PRIVILEGED
,
4585 .translate
= translate_simcall
,
4586 .test_exceptions
= test_exceptions_simcall
,
4587 .op_flags
= XTENSA_OP_PRIVILEGED
,
4590 .translate
= translate_sll
,
4593 .translate
= translate_slli
,
4596 .translate
= translate_sra
,
4599 .translate
= translate_srai
,
4602 .translate
= translate_src
,
4605 .translate
= translate_srl
,
4608 .translate
= translate_srli
,
4611 .translate
= translate_ssa8b
,
4614 .translate
= translate_ssa8l
,
4617 .translate
= translate_ssai
,
4620 .translate
= translate_ssl
,
4623 .translate
= translate_ssr
,
4626 .translate
= translate_sub
,
4629 .translate
= translate_subx
,
4630 .par
= (const uint32_t[]){1},
4633 .translate
= translate_subx
,
4634 .par
= (const uint32_t[]){2},
4637 .translate
= translate_subx
,
4638 .par
= (const uint32_t[]){3},
4641 .op_flags
= XTENSA_OP_SYSCALL
,
4643 .name
= "umul.aa.hh",
4644 .translate
= translate_mac16
,
4645 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_HH
, 0},
4647 .name
= "umul.aa.hl",
4648 .translate
= translate_mac16
,
4649 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_HL
, 0},
4651 .name
= "umul.aa.lh",
4652 .translate
= translate_mac16
,
4653 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_LH
, 0},
4655 .name
= "umul.aa.ll",
4656 .translate
= translate_mac16
,
4657 .par
= (const uint32_t[]){MAC16_UMUL
, MAC16_LL
, 0},
4660 .translate
= translate_waiti
,
4661 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4664 .translate
= translate_wtlb
,
4665 .par
= (const uint32_t[]){true},
4666 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4669 .translate
= translate_wer
,
4670 .op_flags
= XTENSA_OP_PRIVILEGED
,
4673 .translate
= translate_wtlb
,
4674 .par
= (const uint32_t[]){false},
4675 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4678 .translate
= translate_wptlb
,
4679 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4681 .name
= "wrmsk_expstate",
4682 .translate
= translate_wrmsk_expstate
,
4685 .op_flags
= XTENSA_OP_ILL
,
4688 .op_flags
= XTENSA_OP_ILL
,
4690 .name
= "wsr.acchi",
4691 .translate
= translate_wsr_acchi
,
4692 .test_exceptions
= test_exceptions_sr
,
4693 .par
= (const uint32_t[]){
4695 XTENSA_OPTION_MAC16
,
4698 .name
= "wsr.acclo",
4699 .translate
= translate_wsr
,
4700 .test_exceptions
= test_exceptions_sr
,
4701 .par
= (const uint32_t[]){
4703 XTENSA_OPTION_MAC16
,
4706 .name
= "wsr.atomctl",
4707 .translate
= translate_wsr_mask
,
4708 .test_exceptions
= test_exceptions_sr
,
4709 .par
= (const uint32_t[]){
4711 XTENSA_OPTION_ATOMCTL
,
4714 .op_flags
= XTENSA_OP_PRIVILEGED
,
4717 .translate
= translate_wsr_mask
,
4718 .test_exceptions
= test_exceptions_sr
,
4719 .par
= (const uint32_t[]){
4721 XTENSA_OPTION_BOOLEAN
,
4725 .name
= "wsr.cacheadrdis",
4726 .translate
= translate_wsr_mask
,
4727 .test_exceptions
= test_exceptions_sr
,
4728 .par
= (const uint32_t[]){
4733 .op_flags
= XTENSA_OP_PRIVILEGED
,
4735 .name
= "wsr.cacheattr",
4736 .translate
= translate_wsr
,
4737 .test_exceptions
= test_exceptions_sr
,
4738 .par
= (const uint32_t[]){
4740 XTENSA_OPTION_CACHEATTR
,
4742 .op_flags
= XTENSA_OP_PRIVILEGED
,
4744 .name
= "wsr.ccompare0",
4745 .translate
= translate_wsr_ccompare
,
4746 .test_exceptions
= test_exceptions_ccompare
,
4747 .par
= (const uint32_t[]){
4749 XTENSA_OPTION_TIMER_INTERRUPT
,
4751 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4753 .name
= "wsr.ccompare1",
4754 .translate
= translate_wsr_ccompare
,
4755 .test_exceptions
= test_exceptions_ccompare
,
4756 .par
= (const uint32_t[]){
4758 XTENSA_OPTION_TIMER_INTERRUPT
,
4760 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4762 .name
= "wsr.ccompare2",
4763 .translate
= translate_wsr_ccompare
,
4764 .test_exceptions
= test_exceptions_ccompare
,
4765 .par
= (const uint32_t[]){
4767 XTENSA_OPTION_TIMER_INTERRUPT
,
4769 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4771 .name
= "wsr.ccount",
4772 .translate
= translate_wsr_ccount
,
4773 .test_exceptions
= test_exceptions_sr
,
4774 .par
= (const uint32_t[]){
4776 XTENSA_OPTION_TIMER_INTERRUPT
,
4778 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
4780 .name
= "wsr.configid0",
4781 .op_flags
= XTENSA_OP_ILL
,
4783 .name
= "wsr.configid1",
4784 .op_flags
= XTENSA_OP_ILL
,
4786 .name
= "wsr.cpenable",
4787 .translate
= translate_wsr_mask
,
4788 .test_exceptions
= test_exceptions_sr
,
4789 .par
= (const uint32_t[]){
4791 XTENSA_OPTION_COPROCESSOR
,
4794 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
4796 .name
= "wsr.dbreaka0",
4797 .translate
= translate_wsr_dbreaka
,
4798 .test_exceptions
= test_exceptions_dbreak
,
4799 .par
= (const uint32_t[]){
4801 XTENSA_OPTION_DEBUG
,
4803 .op_flags
= XTENSA_OP_PRIVILEGED
,
4805 .name
= "wsr.dbreaka1",
4806 .translate
= translate_wsr_dbreaka
,
4807 .test_exceptions
= test_exceptions_dbreak
,
4808 .par
= (const uint32_t[]){
4810 XTENSA_OPTION_DEBUG
,
4812 .op_flags
= XTENSA_OP_PRIVILEGED
,
4814 .name
= "wsr.dbreakc0",
4815 .translate
= translate_wsr_dbreakc
,
4816 .test_exceptions
= test_exceptions_dbreak
,
4817 .par
= (const uint32_t[]){
4819 XTENSA_OPTION_DEBUG
,
4821 .op_flags
= XTENSA_OP_PRIVILEGED
,
4823 .name
= "wsr.dbreakc1",
4824 .translate
= translate_wsr_dbreakc
,
4825 .test_exceptions
= test_exceptions_dbreak
,
4826 .par
= (const uint32_t[]){
4828 XTENSA_OPTION_DEBUG
,
4830 .op_flags
= XTENSA_OP_PRIVILEGED
,
4833 .translate
= translate_wsr
,
4834 .test_exceptions
= test_exceptions_sr
,
4835 .par
= (const uint32_t[]){
4837 XTENSA_OPTION_DEBUG
,
4839 .op_flags
= XTENSA_OP_PRIVILEGED
,
4841 .name
= "wsr.debugcause",
4842 .op_flags
= XTENSA_OP_ILL
,
4845 .translate
= translate_wsr
,
4846 .test_exceptions
= test_exceptions_sr
,
4847 .par
= (const uint32_t[]){
4849 XTENSA_OPTION_EXCEPTION
,
4851 .op_flags
= XTENSA_OP_PRIVILEGED
,
4853 .name
= "wsr.dtlbcfg",
4854 .translate
= translate_wsr_mask
,
4855 .test_exceptions
= test_exceptions_sr
,
4856 .par
= (const uint32_t[]){
4861 .op_flags
= XTENSA_OP_PRIVILEGED
,
4864 .translate
= translate_wsr
,
4865 .test_exceptions
= test_exceptions_sr
,
4866 .par
= (const uint32_t[]){
4868 XTENSA_OPTION_EXCEPTION
,
4870 .op_flags
= XTENSA_OP_PRIVILEGED
,
4873 .translate
= translate_wsr
,
4874 .test_exceptions
= test_exceptions_hpi
,
4875 .par
= (const uint32_t[]){
4877 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4879 .op_flags
= XTENSA_OP_PRIVILEGED
,
4882 .translate
= translate_wsr
,
4883 .test_exceptions
= test_exceptions_hpi
,
4884 .par
= (const uint32_t[]){
4886 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4888 .op_flags
= XTENSA_OP_PRIVILEGED
,
4891 .translate
= translate_wsr
,
4892 .test_exceptions
= test_exceptions_hpi
,
4893 .par
= (const uint32_t[]){
4895 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4897 .op_flags
= XTENSA_OP_PRIVILEGED
,
4900 .translate
= translate_wsr
,
4901 .test_exceptions
= test_exceptions_hpi
,
4902 .par
= (const uint32_t[]){
4904 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4906 .op_flags
= XTENSA_OP_PRIVILEGED
,
4909 .translate
= translate_wsr
,
4910 .test_exceptions
= test_exceptions_hpi
,
4911 .par
= (const uint32_t[]){
4913 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4915 .op_flags
= XTENSA_OP_PRIVILEGED
,
4918 .translate
= translate_wsr
,
4919 .test_exceptions
= test_exceptions_hpi
,
4920 .par
= (const uint32_t[]){
4922 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4924 .op_flags
= XTENSA_OP_PRIVILEGED
,
4927 .translate
= translate_wsr
,
4928 .test_exceptions
= test_exceptions_hpi
,
4929 .par
= (const uint32_t[]){
4931 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4933 .op_flags
= XTENSA_OP_PRIVILEGED
,
4936 .translate
= translate_wsr
,
4937 .test_exceptions
= test_exceptions_hpi
,
4938 .par
= (const uint32_t[]){
4940 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4942 .op_flags
= XTENSA_OP_PRIVILEGED
,
4945 .translate
= translate_wsr
,
4946 .test_exceptions
= test_exceptions_hpi
,
4947 .par
= (const uint32_t[]){
4949 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4951 .op_flags
= XTENSA_OP_PRIVILEGED
,
4954 .translate
= translate_wsr
,
4955 .test_exceptions
= test_exceptions_hpi
,
4956 .par
= (const uint32_t[]){
4958 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4960 .op_flags
= XTENSA_OP_PRIVILEGED
,
4963 .translate
= translate_wsr
,
4964 .test_exceptions
= test_exceptions_hpi
,
4965 .par
= (const uint32_t[]){
4967 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4969 .op_flags
= XTENSA_OP_PRIVILEGED
,
4972 .translate
= translate_wsr
,
4973 .test_exceptions
= test_exceptions_hpi
,
4974 .par
= (const uint32_t[]){
4976 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
4978 .op_flags
= XTENSA_OP_PRIVILEGED
,
4980 .name
= "wsr.eraccess",
4981 .translate
= translate_wsr_mask
,
4982 .par
= (const uint32_t[]){
4987 .op_flags
= XTENSA_OP_PRIVILEGED
,
4989 .name
= "wsr.exccause",
4990 .translate
= translate_wsr
,
4991 .test_exceptions
= test_exceptions_sr
,
4992 .par
= (const uint32_t[]){
4994 XTENSA_OPTION_EXCEPTION
,
4996 .op_flags
= XTENSA_OP_PRIVILEGED
,
4998 .name
= "wsr.excsave1",
4999 .translate
= translate_wsr
,
5000 .test_exceptions
= test_exceptions_sr
,
5001 .par
= (const uint32_t[]){
5003 XTENSA_OPTION_EXCEPTION
,
5005 .op_flags
= XTENSA_OP_PRIVILEGED
,
5007 .name
= "wsr.excsave2",
5008 .translate
= translate_wsr
,
5009 .test_exceptions
= test_exceptions_hpi
,
5010 .par
= (const uint32_t[]){
5012 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5014 .op_flags
= XTENSA_OP_PRIVILEGED
,
5016 .name
= "wsr.excsave3",
5017 .translate
= translate_wsr
,
5018 .test_exceptions
= test_exceptions_hpi
,
5019 .par
= (const uint32_t[]){
5021 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5023 .op_flags
= XTENSA_OP_PRIVILEGED
,
5025 .name
= "wsr.excsave4",
5026 .translate
= translate_wsr
,
5027 .test_exceptions
= test_exceptions_hpi
,
5028 .par
= (const uint32_t[]){
5030 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5032 .op_flags
= XTENSA_OP_PRIVILEGED
,
5034 .name
= "wsr.excsave5",
5035 .translate
= translate_wsr
,
5036 .test_exceptions
= test_exceptions_hpi
,
5037 .par
= (const uint32_t[]){
5039 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5041 .op_flags
= XTENSA_OP_PRIVILEGED
,
5043 .name
= "wsr.excsave6",
5044 .translate
= translate_wsr
,
5045 .test_exceptions
= test_exceptions_hpi
,
5046 .par
= (const uint32_t[]){
5048 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5050 .op_flags
= XTENSA_OP_PRIVILEGED
,
5052 .name
= "wsr.excsave7",
5053 .translate
= translate_wsr
,
5054 .test_exceptions
= test_exceptions_hpi
,
5055 .par
= (const uint32_t[]){
5057 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5059 .op_flags
= XTENSA_OP_PRIVILEGED
,
5061 .name
= "wsr.excvaddr",
5062 .translate
= translate_wsr
,
5063 .test_exceptions
= test_exceptions_sr
,
5064 .par
= (const uint32_t[]){
5066 XTENSA_OPTION_EXCEPTION
,
5068 .op_flags
= XTENSA_OP_PRIVILEGED
,
5070 .name
= "wsr.ibreaka0",
5071 .translate
= translate_wsr_ibreaka
,
5072 .test_exceptions
= test_exceptions_ibreak
,
5073 .par
= (const uint32_t[]){
5075 XTENSA_OPTION_DEBUG
,
5077 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5079 .name
= "wsr.ibreaka1",
5080 .translate
= translate_wsr_ibreaka
,
5081 .test_exceptions
= test_exceptions_ibreak
,
5082 .par
= (const uint32_t[]){
5084 XTENSA_OPTION_DEBUG
,
5086 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5088 .name
= "wsr.ibreakenable",
5089 .translate
= translate_wsr_ibreakenable
,
5090 .test_exceptions
= test_exceptions_sr
,
5091 .par
= (const uint32_t[]){
5093 XTENSA_OPTION_DEBUG
,
5095 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5097 .name
= "wsr.icount",
5098 .translate
= translate_wsr_icount
,
5099 .test_exceptions
= test_exceptions_sr
,
5100 .par
= (const uint32_t[]){
5102 XTENSA_OPTION_DEBUG
,
5104 .op_flags
= XTENSA_OP_PRIVILEGED
,
5106 .name
= "wsr.icountlevel",
5107 .translate
= translate_wsr_mask
,
5108 .test_exceptions
= test_exceptions_sr
,
5109 .par
= (const uint32_t[]){
5111 XTENSA_OPTION_DEBUG
,
5114 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5116 .name
= "wsr.intclear",
5117 .translate
= translate_wsr_intclear
,
5118 .test_exceptions
= test_exceptions_sr
,
5119 .par
= (const uint32_t[]){
5121 XTENSA_OPTION_INTERRUPT
,
5124 XTENSA_OP_PRIVILEGED
|
5125 XTENSA_OP_EXIT_TB_0
|
5126 XTENSA_OP_CHECK_INTERRUPTS
,
5128 .name
= "wsr.intenable",
5129 .translate
= translate_wsr
,
5130 .test_exceptions
= test_exceptions_sr
,
5131 .par
= (const uint32_t[]){
5133 XTENSA_OPTION_INTERRUPT
,
5136 XTENSA_OP_PRIVILEGED
|
5137 XTENSA_OP_EXIT_TB_0
|
5138 XTENSA_OP_CHECK_INTERRUPTS
,
5140 .name
= "wsr.interrupt",
5141 .translate
= translate_wsr
,
5142 .test_exceptions
= test_exceptions_sr
,
5143 .par
= (const uint32_t[]){
5145 XTENSA_OPTION_INTERRUPT
,
5148 XTENSA_OP_PRIVILEGED
|
5149 XTENSA_OP_EXIT_TB_0
|
5150 XTENSA_OP_CHECK_INTERRUPTS
,
5152 .name
= "wsr.intset",
5153 .translate
= translate_wsr_intset
,
5154 .test_exceptions
= test_exceptions_sr
,
5155 .par
= (const uint32_t[]){
5157 XTENSA_OPTION_INTERRUPT
,
5160 XTENSA_OP_PRIVILEGED
|
5161 XTENSA_OP_EXIT_TB_0
|
5162 XTENSA_OP_CHECK_INTERRUPTS
,
5164 .name
= "wsr.itlbcfg",
5165 .translate
= translate_wsr_mask
,
5166 .test_exceptions
= test_exceptions_sr
,
5167 .par
= (const uint32_t[]){
5172 .op_flags
= XTENSA_OP_PRIVILEGED
,
5175 .translate
= translate_wsr
,
5176 .test_exceptions
= test_exceptions_sr
,
5177 .par
= (const uint32_t[]){
5181 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5183 .name
= "wsr.lcount",
5184 .translate
= translate_wsr
,
5185 .test_exceptions
= test_exceptions_sr
,
5186 .par
= (const uint32_t[]){
5192 .translate
= translate_wsr
,
5193 .test_exceptions
= test_exceptions_sr
,
5194 .par
= (const uint32_t[]){
5198 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5200 .name
= "wsr.litbase",
5201 .translate
= translate_wsr_mask
,
5202 .test_exceptions
= test_exceptions_sr
,
5203 .par
= (const uint32_t[]){
5205 XTENSA_OPTION_EXTENDED_L32R
,
5208 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5211 .translate
= translate_wsr
,
5212 .test_exceptions
= test_exceptions_sr
,
5213 .par
= (const uint32_t[]){
5215 XTENSA_OPTION_MAC16
,
5219 .translate
= translate_wsr
,
5220 .test_exceptions
= test_exceptions_sr
,
5221 .par
= (const uint32_t[]){
5223 XTENSA_OPTION_MAC16
,
5227 .translate
= translate_wsr
,
5228 .test_exceptions
= test_exceptions_sr
,
5229 .par
= (const uint32_t[]){
5231 XTENSA_OPTION_MAC16
,
5235 .translate
= translate_wsr
,
5236 .test_exceptions
= test_exceptions_sr
,
5237 .par
= (const uint32_t[]){
5239 XTENSA_OPTION_MAC16
,
5242 .name
= "wsr.memctl",
5243 .translate
= translate_wsr_memctl
,
5244 .par
= (const uint32_t[]){MEMCTL
},
5245 .op_flags
= XTENSA_OP_PRIVILEGED
,
5248 .translate
= translate_wsr
,
5249 .test_exceptions
= test_exceptions_sr
,
5250 .par
= (const uint32_t[]){
5252 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5254 .op_flags
= XTENSA_OP_PRIVILEGED
,
5257 .translate
= translate_wsr
,
5258 .test_exceptions
= test_exceptions_sr
,
5259 .par
= (const uint32_t[]){
5261 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5263 .op_flags
= XTENSA_OP_PRIVILEGED
,
5266 .translate
= translate_wsr
,
5267 .test_exceptions
= test_exceptions_sr
,
5268 .par
= (const uint32_t[]){
5270 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5272 .op_flags
= XTENSA_OP_PRIVILEGED
,
5274 .name
= "wsr.mesave",
5275 .translate
= translate_wsr
,
5276 .test_exceptions
= test_exceptions_sr
,
5277 .par
= (const uint32_t[]){
5279 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5281 .op_flags
= XTENSA_OP_PRIVILEGED
,
5284 .translate
= translate_wsr
,
5285 .test_exceptions
= test_exceptions_sr
,
5286 .par
= (const uint32_t[]){
5288 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5290 .op_flags
= XTENSA_OP_PRIVILEGED
,
5292 .name
= "wsr.mevaddr",
5293 .translate
= translate_wsr
,
5294 .test_exceptions
= test_exceptions_sr
,
5295 .par
= (const uint32_t[]){
5297 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5299 .op_flags
= XTENSA_OP_PRIVILEGED
,
5301 .name
= "wsr.misc0",
5302 .translate
= translate_wsr
,
5303 .test_exceptions
= test_exceptions_sr
,
5304 .par
= (const uint32_t[]){
5306 XTENSA_OPTION_MISC_SR
,
5308 .op_flags
= XTENSA_OP_PRIVILEGED
,
5310 .name
= "wsr.misc1",
5311 .translate
= translate_wsr
,
5312 .test_exceptions
= test_exceptions_sr
,
5313 .par
= (const uint32_t[]){
5315 XTENSA_OPTION_MISC_SR
,
5317 .op_flags
= XTENSA_OP_PRIVILEGED
,
5319 .name
= "wsr.misc2",
5320 .translate
= translate_wsr
,
5321 .test_exceptions
= test_exceptions_sr
,
5322 .par
= (const uint32_t[]){
5324 XTENSA_OPTION_MISC_SR
,
5326 .op_flags
= XTENSA_OP_PRIVILEGED
,
5328 .name
= "wsr.misc3",
5329 .translate
= translate_wsr
,
5330 .test_exceptions
= test_exceptions_sr
,
5331 .par
= (const uint32_t[]){
5333 XTENSA_OPTION_MISC_SR
,
5335 .op_flags
= XTENSA_OP_PRIVILEGED
,
5338 .translate
= translate_wsr
,
5339 .test_exceptions
= test_exceptions_sr
,
5340 .par
= (const uint32_t[]){
5342 XTENSA_OPTION_TRACE_PORT
,
5344 .op_flags
= XTENSA_OP_PRIVILEGED
,
5346 .name
= "wsr.mpuenb",
5347 .translate
= translate_wsr_mpuenb
,
5348 .test_exceptions
= test_exceptions_sr
,
5349 .par
= (const uint32_t[]){
5353 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5355 .name
= "wsr.prefctl",
5356 .translate
= translate_wsr
,
5357 .par
= (const uint32_t[]){PREFCTL
},
5360 .op_flags
= XTENSA_OP_ILL
,
5363 .translate
= translate_wsr_ps
,
5364 .test_exceptions
= test_exceptions_sr
,
5365 .par
= (const uint32_t[]){
5367 XTENSA_OPTION_EXCEPTION
,
5370 XTENSA_OP_PRIVILEGED
|
5371 XTENSA_OP_EXIT_TB_M1
|
5372 XTENSA_OP_CHECK_INTERRUPTS
,
5374 .name
= "wsr.ptevaddr",
5375 .translate
= translate_wsr_mask
,
5376 .test_exceptions
= test_exceptions_sr
,
5377 .par
= (const uint32_t[]){
5382 .op_flags
= XTENSA_OP_PRIVILEGED
,
5384 .name
= "wsr.rasid",
5385 .translate
= translate_wsr_rasid
,
5386 .test_exceptions
= test_exceptions_sr
,
5387 .par
= (const uint32_t[]){
5391 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5394 .translate
= translate_wsr_sar
,
5395 .par
= (const uint32_t[]){SAR
},
5397 .name
= "wsr.scompare1",
5398 .translate
= translate_wsr
,
5399 .test_exceptions
= test_exceptions_sr
,
5400 .par
= (const uint32_t[]){
5402 XTENSA_OPTION_CONDITIONAL_STORE
,
5405 .name
= "wsr.vecbase",
5406 .translate
= translate_wsr
,
5407 .test_exceptions
= test_exceptions_sr
,
5408 .par
= (const uint32_t[]){
5410 XTENSA_OPTION_RELOCATABLE_VECTOR
,
5412 .op_flags
= XTENSA_OP_PRIVILEGED
,
5414 .name
= "wsr.windowbase",
5415 .translate
= translate_wsr_windowbase
,
5416 .test_exceptions
= test_exceptions_sr
,
5417 .par
= (const uint32_t[]){
5419 XTENSA_OPTION_WINDOWED_REGISTER
,
5421 .op_flags
= XTENSA_OP_PRIVILEGED
|
5422 XTENSA_OP_EXIT_TB_M1
|
5423 XTENSA_OP_SYNC_REGISTER_WINDOW
,
5425 .name
= "wsr.windowstart",
5426 .translate
= translate_wsr_windowstart
,
5427 .test_exceptions
= test_exceptions_sr
,
5428 .par
= (const uint32_t[]){
5430 XTENSA_OPTION_WINDOWED_REGISTER
,
5432 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5434 .name
= "wur.expstate",
5435 .translate
= translate_wur
,
5436 .par
= (const uint32_t[]){EXPSTATE
},
5438 .name
= "wur.threadptr",
5439 .translate
= translate_wur
,
5440 .par
= (const uint32_t[]){THREADPTR
},
5443 .translate
= translate_xor
,
5446 .translate
= translate_boolean
,
5447 .par
= (const uint32_t[]){BOOLEAN_XOR
},
5450 .op_flags
= XTENSA_OP_ILL
,
5453 .op_flags
= XTENSA_OP_ILL
,
5455 .name
= "xsr.acchi",
5456 .translate
= translate_xsr_acchi
,
5457 .test_exceptions
= test_exceptions_sr
,
5458 .par
= (const uint32_t[]){
5460 XTENSA_OPTION_MAC16
,
5463 .name
= "xsr.acclo",
5464 .translate
= translate_xsr
,
5465 .test_exceptions
= test_exceptions_sr
,
5466 .par
= (const uint32_t[]){
5468 XTENSA_OPTION_MAC16
,
5471 .name
= "xsr.atomctl",
5472 .translate
= translate_xsr_mask
,
5473 .test_exceptions
= test_exceptions_sr
,
5474 .par
= (const uint32_t[]){
5476 XTENSA_OPTION_ATOMCTL
,
5479 .op_flags
= XTENSA_OP_PRIVILEGED
,
5482 .translate
= translate_xsr_mask
,
5483 .test_exceptions
= test_exceptions_sr
,
5484 .par
= (const uint32_t[]){
5486 XTENSA_OPTION_BOOLEAN
,
5490 .name
= "xsr.cacheadrdis",
5491 .translate
= translate_xsr_mask
,
5492 .test_exceptions
= test_exceptions_sr
,
5493 .par
= (const uint32_t[]){
5498 .op_flags
= XTENSA_OP_PRIVILEGED
,
5500 .name
= "xsr.cacheattr",
5501 .translate
= translate_xsr
,
5502 .test_exceptions
= test_exceptions_sr
,
5503 .par
= (const uint32_t[]){
5505 XTENSA_OPTION_CACHEATTR
,
5507 .op_flags
= XTENSA_OP_PRIVILEGED
,
5509 .name
= "xsr.ccompare0",
5510 .translate
= translate_xsr_ccompare
,
5511 .test_exceptions
= test_exceptions_ccompare
,
5512 .par
= (const uint32_t[]){
5514 XTENSA_OPTION_TIMER_INTERRUPT
,
5516 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5518 .name
= "xsr.ccompare1",
5519 .translate
= translate_xsr_ccompare
,
5520 .test_exceptions
= test_exceptions_ccompare
,
5521 .par
= (const uint32_t[]){
5523 XTENSA_OPTION_TIMER_INTERRUPT
,
5525 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5527 .name
= "xsr.ccompare2",
5528 .translate
= translate_xsr_ccompare
,
5529 .test_exceptions
= test_exceptions_ccompare
,
5530 .par
= (const uint32_t[]){
5532 XTENSA_OPTION_TIMER_INTERRUPT
,
5534 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5536 .name
= "xsr.ccount",
5537 .translate
= translate_xsr_ccount
,
5538 .test_exceptions
= test_exceptions_sr
,
5539 .par
= (const uint32_t[]){
5541 XTENSA_OPTION_TIMER_INTERRUPT
,
5543 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5545 .name
= "xsr.configid0",
5546 .op_flags
= XTENSA_OP_ILL
,
5548 .name
= "xsr.configid1",
5549 .op_flags
= XTENSA_OP_ILL
,
5551 .name
= "xsr.cpenable",
5552 .translate
= translate_xsr_mask
,
5553 .test_exceptions
= test_exceptions_sr
,
5554 .par
= (const uint32_t[]){
5556 XTENSA_OPTION_COPROCESSOR
,
5559 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5561 .name
= "xsr.dbreaka0",
5562 .translate
= translate_xsr_dbreaka
,
5563 .test_exceptions
= test_exceptions_dbreak
,
5564 .par
= (const uint32_t[]){
5566 XTENSA_OPTION_DEBUG
,
5568 .op_flags
= XTENSA_OP_PRIVILEGED
,
5570 .name
= "xsr.dbreaka1",
5571 .translate
= translate_xsr_dbreaka
,
5572 .test_exceptions
= test_exceptions_dbreak
,
5573 .par
= (const uint32_t[]){
5575 XTENSA_OPTION_DEBUG
,
5577 .op_flags
= XTENSA_OP_PRIVILEGED
,
5579 .name
= "xsr.dbreakc0",
5580 .translate
= translate_xsr_dbreakc
,
5581 .test_exceptions
= test_exceptions_dbreak
,
5582 .par
= (const uint32_t[]){
5584 XTENSA_OPTION_DEBUG
,
5586 .op_flags
= XTENSA_OP_PRIVILEGED
,
5588 .name
= "xsr.dbreakc1",
5589 .translate
= translate_xsr_dbreakc
,
5590 .test_exceptions
= test_exceptions_dbreak
,
5591 .par
= (const uint32_t[]){
5593 XTENSA_OPTION_DEBUG
,
5595 .op_flags
= XTENSA_OP_PRIVILEGED
,
5598 .translate
= translate_xsr
,
5599 .test_exceptions
= test_exceptions_sr
,
5600 .par
= (const uint32_t[]){
5602 XTENSA_OPTION_DEBUG
,
5604 .op_flags
= XTENSA_OP_PRIVILEGED
,
5606 .name
= "xsr.debugcause",
5607 .op_flags
= XTENSA_OP_ILL
,
5610 .translate
= translate_xsr
,
5611 .test_exceptions
= test_exceptions_sr
,
5612 .par
= (const uint32_t[]){
5614 XTENSA_OPTION_EXCEPTION
,
5616 .op_flags
= XTENSA_OP_PRIVILEGED
,
5618 .name
= "xsr.dtlbcfg",
5619 .translate
= translate_xsr_mask
,
5620 .test_exceptions
= test_exceptions_sr
,
5621 .par
= (const uint32_t[]){
5626 .op_flags
= XTENSA_OP_PRIVILEGED
,
5629 .translate
= translate_xsr
,
5630 .test_exceptions
= test_exceptions_sr
,
5631 .par
= (const uint32_t[]){
5633 XTENSA_OPTION_EXCEPTION
,
5635 .op_flags
= XTENSA_OP_PRIVILEGED
,
5638 .translate
= translate_xsr
,
5639 .test_exceptions
= test_exceptions_hpi
,
5640 .par
= (const uint32_t[]){
5642 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5644 .op_flags
= XTENSA_OP_PRIVILEGED
,
5647 .translate
= translate_xsr
,
5648 .test_exceptions
= test_exceptions_hpi
,
5649 .par
= (const uint32_t[]){
5651 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5653 .op_flags
= XTENSA_OP_PRIVILEGED
,
5656 .translate
= translate_xsr
,
5657 .test_exceptions
= test_exceptions_hpi
,
5658 .par
= (const uint32_t[]){
5660 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5662 .op_flags
= XTENSA_OP_PRIVILEGED
,
5665 .translate
= translate_xsr
,
5666 .test_exceptions
= test_exceptions_hpi
,
5667 .par
= (const uint32_t[]){
5669 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5671 .op_flags
= XTENSA_OP_PRIVILEGED
,
5674 .translate
= translate_xsr
,
5675 .test_exceptions
= test_exceptions_hpi
,
5676 .par
= (const uint32_t[]){
5678 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5680 .op_flags
= XTENSA_OP_PRIVILEGED
,
5683 .translate
= translate_xsr
,
5684 .test_exceptions
= test_exceptions_hpi
,
5685 .par
= (const uint32_t[]){
5687 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5689 .op_flags
= XTENSA_OP_PRIVILEGED
,
5692 .translate
= translate_xsr
,
5693 .test_exceptions
= test_exceptions_hpi
,
5694 .par
= (const uint32_t[]){
5696 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5698 .op_flags
= XTENSA_OP_PRIVILEGED
,
5701 .translate
= translate_xsr
,
5702 .test_exceptions
= test_exceptions_hpi
,
5703 .par
= (const uint32_t[]){
5705 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5707 .op_flags
= XTENSA_OP_PRIVILEGED
,
5710 .translate
= translate_xsr
,
5711 .test_exceptions
= test_exceptions_hpi
,
5712 .par
= (const uint32_t[]){
5714 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5716 .op_flags
= XTENSA_OP_PRIVILEGED
,
5719 .translate
= translate_xsr
,
5720 .test_exceptions
= test_exceptions_hpi
,
5721 .par
= (const uint32_t[]){
5723 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5725 .op_flags
= XTENSA_OP_PRIVILEGED
,
5728 .translate
= translate_xsr
,
5729 .test_exceptions
= test_exceptions_hpi
,
5730 .par
= (const uint32_t[]){
5732 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5734 .op_flags
= XTENSA_OP_PRIVILEGED
,
5737 .translate
= translate_xsr
,
5738 .test_exceptions
= test_exceptions_hpi
,
5739 .par
= (const uint32_t[]){
5741 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5743 .op_flags
= XTENSA_OP_PRIVILEGED
,
5745 .name
= "xsr.eraccess",
5746 .translate
= translate_xsr_mask
,
5747 .par
= (const uint32_t[]){
5752 .op_flags
= XTENSA_OP_PRIVILEGED
,
5754 .name
= "xsr.exccause",
5755 .translate
= translate_xsr
,
5756 .test_exceptions
= test_exceptions_sr
,
5757 .par
= (const uint32_t[]){
5759 XTENSA_OPTION_EXCEPTION
,
5761 .op_flags
= XTENSA_OP_PRIVILEGED
,
5763 .name
= "xsr.excsave1",
5764 .translate
= translate_xsr
,
5765 .test_exceptions
= test_exceptions_sr
,
5766 .par
= (const uint32_t[]){
5768 XTENSA_OPTION_EXCEPTION
,
5770 .op_flags
= XTENSA_OP_PRIVILEGED
,
5772 .name
= "xsr.excsave2",
5773 .translate
= translate_xsr
,
5774 .test_exceptions
= test_exceptions_hpi
,
5775 .par
= (const uint32_t[]){
5777 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5779 .op_flags
= XTENSA_OP_PRIVILEGED
,
5781 .name
= "xsr.excsave3",
5782 .translate
= translate_xsr
,
5783 .test_exceptions
= test_exceptions_hpi
,
5784 .par
= (const uint32_t[]){
5786 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5788 .op_flags
= XTENSA_OP_PRIVILEGED
,
5790 .name
= "xsr.excsave4",
5791 .translate
= translate_xsr
,
5792 .test_exceptions
= test_exceptions_hpi
,
5793 .par
= (const uint32_t[]){
5795 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5797 .op_flags
= XTENSA_OP_PRIVILEGED
,
5799 .name
= "xsr.excsave5",
5800 .translate
= translate_xsr
,
5801 .test_exceptions
= test_exceptions_hpi
,
5802 .par
= (const uint32_t[]){
5804 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5806 .op_flags
= XTENSA_OP_PRIVILEGED
,
5808 .name
= "xsr.excsave6",
5809 .translate
= translate_xsr
,
5810 .test_exceptions
= test_exceptions_hpi
,
5811 .par
= (const uint32_t[]){
5813 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5815 .op_flags
= XTENSA_OP_PRIVILEGED
,
5817 .name
= "xsr.excsave7",
5818 .translate
= translate_xsr
,
5819 .test_exceptions
= test_exceptions_hpi
,
5820 .par
= (const uint32_t[]){
5822 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT
,
5824 .op_flags
= XTENSA_OP_PRIVILEGED
,
5826 .name
= "xsr.excvaddr",
5827 .translate
= translate_xsr
,
5828 .test_exceptions
= test_exceptions_sr
,
5829 .par
= (const uint32_t[]){
5831 XTENSA_OPTION_EXCEPTION
,
5833 .op_flags
= XTENSA_OP_PRIVILEGED
,
5835 .name
= "xsr.ibreaka0",
5836 .translate
= translate_xsr_ibreaka
,
5837 .test_exceptions
= test_exceptions_ibreak
,
5838 .par
= (const uint32_t[]){
5840 XTENSA_OPTION_DEBUG
,
5842 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5844 .name
= "xsr.ibreaka1",
5845 .translate
= translate_xsr_ibreaka
,
5846 .test_exceptions
= test_exceptions_ibreak
,
5847 .par
= (const uint32_t[]){
5849 XTENSA_OPTION_DEBUG
,
5851 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5853 .name
= "xsr.ibreakenable",
5854 .translate
= translate_xsr_ibreakenable
,
5855 .test_exceptions
= test_exceptions_sr
,
5856 .par
= (const uint32_t[]){
5858 XTENSA_OPTION_DEBUG
,
5860 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_0
,
5862 .name
= "xsr.icount",
5863 .translate
= translate_xsr_icount
,
5864 .test_exceptions
= test_exceptions_sr
,
5865 .par
= (const uint32_t[]){
5867 XTENSA_OPTION_DEBUG
,
5869 .op_flags
= XTENSA_OP_PRIVILEGED
,
5871 .name
= "xsr.icountlevel",
5872 .translate
= translate_xsr_mask
,
5873 .test_exceptions
= test_exceptions_sr
,
5874 .par
= (const uint32_t[]){
5876 XTENSA_OPTION_DEBUG
,
5879 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
5881 .name
= "xsr.intclear",
5882 .op_flags
= XTENSA_OP_ILL
,
5884 .name
= "xsr.intenable",
5885 .translate
= translate_xsr
,
5886 .test_exceptions
= test_exceptions_sr
,
5887 .par
= (const uint32_t[]){
5889 XTENSA_OPTION_INTERRUPT
,
5892 XTENSA_OP_PRIVILEGED
|
5893 XTENSA_OP_EXIT_TB_0
|
5894 XTENSA_OP_CHECK_INTERRUPTS
,
5896 .name
= "xsr.interrupt",
5897 .op_flags
= XTENSA_OP_ILL
,
5899 .name
= "xsr.intset",
5900 .op_flags
= XTENSA_OP_ILL
,
5902 .name
= "xsr.itlbcfg",
5903 .translate
= translate_xsr_mask
,
5904 .test_exceptions
= test_exceptions_sr
,
5905 .par
= (const uint32_t[]){
5910 .op_flags
= XTENSA_OP_PRIVILEGED
,
5913 .translate
= translate_xsr
,
5914 .test_exceptions
= test_exceptions_sr
,
5915 .par
= (const uint32_t[]){
5919 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5921 .name
= "xsr.lcount",
5922 .translate
= translate_xsr
,
5923 .test_exceptions
= test_exceptions_sr
,
5924 .par
= (const uint32_t[]){
5930 .translate
= translate_xsr
,
5931 .test_exceptions
= test_exceptions_sr
,
5932 .par
= (const uint32_t[]){
5936 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5938 .name
= "xsr.litbase",
5939 .translate
= translate_xsr_mask
,
5940 .test_exceptions
= test_exceptions_sr
,
5941 .par
= (const uint32_t[]){
5943 XTENSA_OPTION_EXTENDED_L32R
,
5946 .op_flags
= XTENSA_OP_EXIT_TB_M1
,
5949 .translate
= translate_xsr
,
5950 .test_exceptions
= test_exceptions_sr
,
5951 .par
= (const uint32_t[]){
5953 XTENSA_OPTION_MAC16
,
5957 .translate
= translate_xsr
,
5958 .test_exceptions
= test_exceptions_sr
,
5959 .par
= (const uint32_t[]){
5961 XTENSA_OPTION_MAC16
,
5965 .translate
= translate_xsr
,
5966 .test_exceptions
= test_exceptions_sr
,
5967 .par
= (const uint32_t[]){
5969 XTENSA_OPTION_MAC16
,
5973 .translate
= translate_xsr
,
5974 .test_exceptions
= test_exceptions_sr
,
5975 .par
= (const uint32_t[]){
5977 XTENSA_OPTION_MAC16
,
5980 .name
= "xsr.memctl",
5981 .translate
= translate_xsr_memctl
,
5982 .par
= (const uint32_t[]){MEMCTL
},
5983 .op_flags
= XTENSA_OP_PRIVILEGED
,
5986 .translate
= translate_xsr
,
5987 .test_exceptions
= test_exceptions_sr
,
5988 .par
= (const uint32_t[]){
5990 XTENSA_OPTION_MEMORY_ECC_PARITY
,
5992 .op_flags
= XTENSA_OP_PRIVILEGED
,
5995 .translate
= translate_xsr
,
5996 .test_exceptions
= test_exceptions_sr
,
5997 .par
= (const uint32_t[]){
5999 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6001 .op_flags
= XTENSA_OP_PRIVILEGED
,
6004 .translate
= translate_xsr
,
6005 .test_exceptions
= test_exceptions_sr
,
6006 .par
= (const uint32_t[]){
6008 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6010 .op_flags
= XTENSA_OP_PRIVILEGED
,
6012 .name
= "xsr.mesave",
6013 .translate
= translate_xsr
,
6014 .test_exceptions
= test_exceptions_sr
,
6015 .par
= (const uint32_t[]){
6017 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6019 .op_flags
= XTENSA_OP_PRIVILEGED
,
6022 .translate
= translate_xsr
,
6023 .test_exceptions
= test_exceptions_sr
,
6024 .par
= (const uint32_t[]){
6026 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6028 .op_flags
= XTENSA_OP_PRIVILEGED
,
6030 .name
= "xsr.mevaddr",
6031 .translate
= translate_xsr
,
6032 .test_exceptions
= test_exceptions_sr
,
6033 .par
= (const uint32_t[]){
6035 XTENSA_OPTION_MEMORY_ECC_PARITY
,
6037 .op_flags
= XTENSA_OP_PRIVILEGED
,
6039 .name
= "xsr.misc0",
6040 .translate
= translate_xsr
,
6041 .test_exceptions
= test_exceptions_sr
,
6042 .par
= (const uint32_t[]){
6044 XTENSA_OPTION_MISC_SR
,
6046 .op_flags
= XTENSA_OP_PRIVILEGED
,
6048 .name
= "xsr.misc1",
6049 .translate
= translate_xsr
,
6050 .test_exceptions
= test_exceptions_sr
,
6051 .par
= (const uint32_t[]){
6053 XTENSA_OPTION_MISC_SR
,
6055 .op_flags
= XTENSA_OP_PRIVILEGED
,
6057 .name
= "xsr.misc2",
6058 .translate
= translate_xsr
,
6059 .test_exceptions
= test_exceptions_sr
,
6060 .par
= (const uint32_t[]){
6062 XTENSA_OPTION_MISC_SR
,
6064 .op_flags
= XTENSA_OP_PRIVILEGED
,
6066 .name
= "xsr.misc3",
6067 .translate
= translate_xsr
,
6068 .test_exceptions
= test_exceptions_sr
,
6069 .par
= (const uint32_t[]){
6071 XTENSA_OPTION_MISC_SR
,
6073 .op_flags
= XTENSA_OP_PRIVILEGED
,
6075 .name
= "xsr.mpuenb",
6076 .translate
= translate_xsr_mpuenb
,
6077 .test_exceptions
= test_exceptions_sr
,
6078 .par
= (const uint32_t[]){
6082 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
6084 .name
= "xsr.prefctl",
6085 .translate
= translate_xsr
,
6086 .par
= (const uint32_t[]){PREFCTL
},
6089 .op_flags
= XTENSA_OP_ILL
,
6092 .translate
= translate_xsr_ps
,
6093 .test_exceptions
= test_exceptions_sr
,
6094 .par
= (const uint32_t[]){
6096 XTENSA_OPTION_EXCEPTION
,
6099 XTENSA_OP_PRIVILEGED
|
6100 XTENSA_OP_EXIT_TB_M1
|
6101 XTENSA_OP_CHECK_INTERRUPTS
,
6103 .name
= "xsr.ptevaddr",
6104 .translate
= translate_xsr_mask
,
6105 .test_exceptions
= test_exceptions_sr
,
6106 .par
= (const uint32_t[]){
6111 .op_flags
= XTENSA_OP_PRIVILEGED
,
6113 .name
= "xsr.rasid",
6114 .translate
= translate_xsr_rasid
,
6115 .test_exceptions
= test_exceptions_sr
,
6116 .par
= (const uint32_t[]){
6120 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
6123 .translate
= translate_xsr_sar
,
6124 .par
= (const uint32_t[]){SAR
},
6126 .name
= "xsr.scompare1",
6127 .translate
= translate_xsr
,
6128 .test_exceptions
= test_exceptions_sr
,
6129 .par
= (const uint32_t[]){
6131 XTENSA_OPTION_CONDITIONAL_STORE
,
6134 .name
= "xsr.vecbase",
6135 .translate
= translate_xsr
,
6136 .test_exceptions
= test_exceptions_sr
,
6137 .par
= (const uint32_t[]){
6139 XTENSA_OPTION_RELOCATABLE_VECTOR
,
6141 .op_flags
= XTENSA_OP_PRIVILEGED
,
6143 .name
= "xsr.windowbase",
6144 .translate
= translate_xsr_windowbase
,
6145 .test_exceptions
= test_exceptions_sr
,
6146 .par
= (const uint32_t[]){
6148 XTENSA_OPTION_WINDOWED_REGISTER
,
6150 .op_flags
= XTENSA_OP_PRIVILEGED
|
6151 XTENSA_OP_EXIT_TB_M1
|
6152 XTENSA_OP_SYNC_REGISTER_WINDOW
,
6154 .name
= "xsr.windowstart",
6155 .translate
= translate_xsr_windowstart
,
6156 .test_exceptions
= test_exceptions_sr
,
6157 .par
= (const uint32_t[]){
6159 XTENSA_OPTION_WINDOWED_REGISTER
,
6161 .op_flags
= XTENSA_OP_PRIVILEGED
| XTENSA_OP_EXIT_TB_M1
,
6165 const XtensaOpcodeTranslators xtensa_core_opcodes
= {
6166 .num_opcodes
= ARRAY_SIZE(core_ops
),
6171 static inline void get_f32_o1_i3(const OpcodeArg
*arg
, OpcodeArg
*arg32
,
6172 int o0
, int i0
, int i1
, int i2
)
6174 if ((i0
>= 0 && arg
[i0
].num_bits
== 64) ||
6175 (o0
>= 0 && arg
[o0
].num_bits
== 64)) {
6177 arg32
[o0
].out
= tcg_temp_new_i32();
6180 arg32
[i0
].in
= tcg_temp_new_i32();
6181 tcg_gen_extrl_i64_i32(arg32
[i0
].in
, arg
[i0
].in
);
6184 arg32
[i1
].in
= tcg_temp_new_i32();
6185 tcg_gen_extrl_i64_i32(arg32
[i1
].in
, arg
[i1
].in
);
6188 arg32
[i2
].in
= tcg_temp_new_i32();
6189 tcg_gen_extrl_i64_i32(arg32
[i2
].in
, arg
[i2
].in
);
6193 arg32
[o0
].out
= arg
[o0
].out
;
6196 arg32
[i0
].in
= arg
[i0
].in
;
6199 arg32
[i1
].in
= arg
[i1
].in
;
6202 arg32
[i2
].in
= arg
[i2
].in
;
6207 static inline void put_f32_o1_i3(const OpcodeArg
*arg
, const OpcodeArg
*arg32
,
6208 int o0
, int i0
, int i1
, int i2
)
6210 if ((i0
>= 0 && arg
[i0
].num_bits
== 64) ||
6211 (o0
>= 0 && arg
[o0
].num_bits
== 64)) {
6213 tcg_gen_extu_i32_i64(arg
[o0
].out
, arg32
[o0
].out
);
6218 static inline void get_f32_o1_i2(const OpcodeArg
*arg
, OpcodeArg
*arg32
,
6219 int o0
, int i0
, int i1
)
6221 get_f32_o1_i3(arg
, arg32
, o0
, i0
, i1
, -1);
6224 static inline void put_f32_o1_i2(const OpcodeArg
*arg
, const OpcodeArg
*arg32
,
6225 int o0
, int i0
, int i1
)
6227 put_f32_o1_i3(arg
, arg32
, o0
, i0
, i1
, -1);
6230 static inline void get_f32_o1_i1(const OpcodeArg
*arg
, OpcodeArg
*arg32
,
6233 get_f32_o1_i2(arg
, arg32
, o0
, i0
, -1);
6236 static inline void put_f32_o1_i1(const OpcodeArg
*arg
, const OpcodeArg
*arg32
,
6239 put_f32_o1_i2(arg
, arg32
, o0
, i0
, -1);
6242 static inline void get_f32_o1(const OpcodeArg
*arg
, OpcodeArg
*arg32
,
6245 get_f32_o1_i1(arg
, arg32
, o0
, -1);
6248 static inline void put_f32_o1(const OpcodeArg
*arg
, const OpcodeArg
*arg32
,
6251 put_f32_o1_i1(arg
, arg32
, o0
, -1);
6254 static inline void get_f32_i2(const OpcodeArg
*arg
, OpcodeArg
*arg32
,
6257 get_f32_o1_i2(arg
, arg32
, -1, i0
, i1
);
6260 static inline void put_f32_i2(const OpcodeArg
*arg
, const OpcodeArg
*arg32
,
6263 put_f32_o1_i2(arg
, arg32
, -1, i0
, i1
);
6266 static inline void get_f32_i1(const OpcodeArg
*arg
, OpcodeArg
*arg32
,
6269 get_f32_i2(arg
, arg32
, i0
, -1);
6272 static inline void put_f32_i1(const OpcodeArg
*arg
, const OpcodeArg
*arg32
,
6275 put_f32_i2(arg
, arg32
, i0
, -1);
6279 static void translate_abs_d(DisasContext
*dc
, const OpcodeArg arg
[],
6280 const uint32_t par
[])
6282 gen_helper_abs_d(arg
[0].out
, arg
[1].in
);
6285 static void translate_abs_s(DisasContext
*dc
, const OpcodeArg arg
[],
6286 const uint32_t par
[])
6290 get_f32_o1_i1(arg
, arg32
, 0, 1);
6291 gen_helper_abs_s(arg32
[0].out
, arg32
[1].in
);
6292 put_f32_o1_i1(arg
, arg32
, 0, 1);
6295 static void translate_fpu2k_add_s(DisasContext
*dc
, const OpcodeArg arg
[],
6296 const uint32_t par
[])
6298 gen_helper_fpu2k_add_s(arg
[0].out
, tcg_env
,
6299 arg
[1].in
, arg
[2].in
);
6312 static void translate_compare_d(DisasContext
*dc
, const OpcodeArg arg
[],
6313 const uint32_t par
[])
6315 static void (* const helper
[])(TCGv_i32 res
, TCGv_env env
,
6316 TCGv_i64 s
, TCGv_i64 t
) = {
6317 [COMPARE_UN
] = gen_helper_un_d
,
6318 [COMPARE_OEQ
] = gen_helper_oeq_d
,
6319 [COMPARE_UEQ
] = gen_helper_ueq_d
,
6320 [COMPARE_OLT
] = gen_helper_olt_d
,
6321 [COMPARE_ULT
] = gen_helper_ult_d
,
6322 [COMPARE_OLE
] = gen_helper_ole_d
,
6323 [COMPARE_ULE
] = gen_helper_ule_d
,
6325 TCGv_i32 zero
= tcg_constant_i32(0);
6326 TCGv_i32 res
= tcg_temp_new_i32();
6327 TCGv_i32 set_br
= tcg_temp_new_i32();
6328 TCGv_i32 clr_br
= tcg_temp_new_i32();
6330 tcg_gen_ori_i32(set_br
, arg
[0].in
, 1 << arg
[0].imm
);
6331 tcg_gen_andi_i32(clr_br
, arg
[0].in
, ~(1 << arg
[0].imm
));
6333 helper
[par
[0]](res
, tcg_env
, arg
[1].in
, arg
[2].in
);
6334 tcg_gen_movcond_i32(TCG_COND_NE
,
6335 arg
[0].out
, res
, zero
,
6339 static void translate_compare_s(DisasContext
*dc
, const OpcodeArg arg
[],
6340 const uint32_t par
[])
6342 static void (* const helper
[])(TCGv_i32 res
, TCGv_env env
,
6343 TCGv_i32 s
, TCGv_i32 t
) = {
6344 [COMPARE_UN
] = gen_helper_un_s
,
6345 [COMPARE_OEQ
] = gen_helper_oeq_s
,
6346 [COMPARE_UEQ
] = gen_helper_ueq_s
,
6347 [COMPARE_OLT
] = gen_helper_olt_s
,
6348 [COMPARE_ULT
] = gen_helper_ult_s
,
6349 [COMPARE_OLE
] = gen_helper_ole_s
,
6350 [COMPARE_ULE
] = gen_helper_ule_s
,
6353 TCGv_i32 zero
= tcg_constant_i32(0);
6354 TCGv_i32 res
= tcg_temp_new_i32();
6355 TCGv_i32 set_br
= tcg_temp_new_i32();
6356 TCGv_i32 clr_br
= tcg_temp_new_i32();
6358 tcg_gen_ori_i32(set_br
, arg
[0].in
, 1 << arg
[0].imm
);
6359 tcg_gen_andi_i32(clr_br
, arg
[0].in
, ~(1 << arg
[0].imm
));
6361 get_f32_i2(arg
, arg32
, 1, 2);
6362 helper
[par
[0]](res
, tcg_env
, arg32
[1].in
, arg32
[2].in
);
6363 tcg_gen_movcond_i32(TCG_COND_NE
,
6364 arg
[0].out
, res
, zero
,
6366 put_f32_i2(arg
, arg32
, 1, 2);
6369 static void translate_const_d(DisasContext
*dc
, const OpcodeArg arg
[],
6370 const uint32_t par
[])
6372 static const uint64_t v
[] = {
6373 UINT64_C(0x0000000000000000),
6374 UINT64_C(0x3ff0000000000000),
6375 UINT64_C(0x4000000000000000),
6376 UINT64_C(0x3fe0000000000000),
6379 tcg_gen_movi_i64(arg
[0].out
, v
[arg
[1].imm
% ARRAY_SIZE(v
)]);
6380 if (arg
[1].imm
>= ARRAY_SIZE(v
)) {
6381 qemu_log_mask(LOG_GUEST_ERROR
,
6382 "const.d f%d, #%d, immediate value is reserved\n",
6383 arg
[0].imm
, arg
[1].imm
);
6387 static void translate_const_s(DisasContext
*dc
, const OpcodeArg arg
[],
6388 const uint32_t par
[])
6390 static const uint32_t v
[] = {
6397 if (arg
[0].num_bits
== 32) {
6398 tcg_gen_movi_i32(arg
[0].out
, v
[arg
[1].imm
% ARRAY_SIZE(v
)]);
6400 tcg_gen_movi_i64(arg
[0].out
, v
[arg
[1].imm
% ARRAY_SIZE(v
)]);
6402 if (arg
[1].imm
>= ARRAY_SIZE(v
)) {
6403 qemu_log_mask(LOG_GUEST_ERROR
,
6404 "const.s f%d, #%d, immediate value is reserved\n",
6405 arg
[0].imm
, arg
[1].imm
);
6409 static void translate_float_d(DisasContext
*dc
, const OpcodeArg arg
[],
6410 const uint32_t par
[])
6412 TCGv_i32 scale
= tcg_constant_i32(-arg
[2].imm
);
6415 gen_helper_uitof_d(arg
[0].out
, tcg_env
, arg
[1].in
, scale
);
6417 gen_helper_itof_d(arg
[0].out
, tcg_env
, arg
[1].in
, scale
);
6421 static void translate_float_s(DisasContext
*dc
, const OpcodeArg arg
[],
6422 const uint32_t par
[])
6424 TCGv_i32 scale
= tcg_constant_i32(-arg
[2].imm
);
6427 get_f32_o1(arg
, arg32
, 0);
6429 gen_helper_uitof_s(arg32
[0].out
, tcg_env
, arg
[1].in
, scale
);
6431 gen_helper_itof_s(arg32
[0].out
, tcg_env
, arg
[1].in
, scale
);
6433 put_f32_o1(arg
, arg32
, 0);
6436 static void translate_ftoi_d(DisasContext
*dc
, const OpcodeArg arg
[],
6437 const uint32_t par
[])
6439 TCGv_i32 rounding_mode
= tcg_constant_i32(par
[0]);
6440 TCGv_i32 scale
= tcg_constant_i32(arg
[2].imm
);
6443 gen_helper_ftoui_d(arg
[0].out
, tcg_env
, arg
[1].in
,
6444 rounding_mode
, scale
);
6446 gen_helper_ftoi_d(arg
[0].out
, tcg_env
, arg
[1].in
,
6447 rounding_mode
, scale
);
6451 static void translate_ftoi_s(DisasContext
*dc
, const OpcodeArg arg
[],
6452 const uint32_t par
[])
6454 TCGv_i32 rounding_mode
= tcg_constant_i32(par
[0]);
6455 TCGv_i32 scale
= tcg_constant_i32(arg
[2].imm
);
6458 get_f32_i1(arg
, arg32
, 1);
6460 gen_helper_ftoui_s(arg
[0].out
, tcg_env
, arg32
[1].in
,
6461 rounding_mode
, scale
);
6463 gen_helper_ftoi_s(arg
[0].out
, tcg_env
, arg32
[1].in
,
6464 rounding_mode
, scale
);
6466 put_f32_i1(arg
, arg32
, 1);
6469 static void translate_ldsti(DisasContext
*dc
, const OpcodeArg arg
[],
6470 const uint32_t par
[])
6472 TCGv_i32 addr
= tcg_temp_new_i32();
6475 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
6476 mop
= gen_load_store_alignment(dc
, MO_TEUL
, addr
);
6478 tcg_gen_qemu_st_tl(arg
[0].in
, addr
, dc
->cring
, mop
);
6480 tcg_gen_qemu_ld_tl(arg
[0].out
, addr
, dc
->cring
, mop
);
6483 tcg_gen_mov_i32(arg
[1].out
, addr
);
6487 static void translate_ldstx(DisasContext
*dc
, const OpcodeArg arg
[],
6488 const uint32_t par
[])
6490 TCGv_i32 addr
= tcg_temp_new_i32();
6493 tcg_gen_add_i32(addr
, arg
[1].in
, arg
[2].in
);
6494 mop
= gen_load_store_alignment(dc
, MO_TEUL
, addr
);
6496 tcg_gen_qemu_st_tl(arg
[0].in
, addr
, dc
->cring
, mop
);
6498 tcg_gen_qemu_ld_tl(arg
[0].out
, addr
, dc
->cring
, mop
);
6501 tcg_gen_mov_i32(arg
[1].out
, addr
);
6505 static void translate_fpu2k_madd_s(DisasContext
*dc
, const OpcodeArg arg
[],
6506 const uint32_t par
[])
6508 gen_helper_fpu2k_madd_s(arg
[0].out
, tcg_env
,
6509 arg
[0].in
, arg
[1].in
, arg
[2].in
);
6512 static void translate_mov_d(DisasContext
*dc
, const OpcodeArg arg
[],
6513 const uint32_t par
[])
6515 tcg_gen_mov_i64(arg
[0].out
, arg
[1].in
);
6518 static void translate_mov_s(DisasContext
*dc
, const OpcodeArg arg
[],
6519 const uint32_t par
[])
6521 if (arg
[0].num_bits
== 32) {
6522 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
6524 tcg_gen_mov_i64(arg
[0].out
, arg
[1].in
);
6528 static void translate_movcond_d(DisasContext
*dc
, const OpcodeArg arg
[],
6529 const uint32_t par
[])
6531 TCGv_i64 zero
= tcg_constant_i64(0);
6532 TCGv_i64 arg2
= tcg_temp_new_i64();
6534 tcg_gen_ext_i32_i64(arg2
, arg
[2].in
);
6535 tcg_gen_movcond_i64(par
[0], arg
[0].out
,
6537 arg
[1].in
, arg
[0].in
);
6540 static void translate_movcond_s(DisasContext
*dc
, const OpcodeArg arg
[],
6541 const uint32_t par
[])
6543 if (arg
[0].num_bits
== 32) {
6544 TCGv_i32 zero
= tcg_constant_i32(0);
6546 tcg_gen_movcond_i32(par
[0], arg
[0].out
,
6548 arg
[1].in
, arg
[0].in
);
6550 translate_movcond_d(dc
, arg
, par
);
6554 static void translate_movp_d(DisasContext
*dc
, const OpcodeArg arg
[],
6555 const uint32_t par
[])
6557 TCGv_i64 zero
= tcg_constant_i64(0);
6558 TCGv_i32 tmp1
= tcg_temp_new_i32();
6559 TCGv_i64 tmp2
= tcg_temp_new_i64();
6561 tcg_gen_andi_i32(tmp1
, arg
[2].in
, 1 << arg
[2].imm
);
6562 tcg_gen_extu_i32_i64(tmp2
, tmp1
);
6563 tcg_gen_movcond_i64(par
[0],
6564 arg
[0].out
, tmp2
, zero
,
6565 arg
[1].in
, arg
[0].in
);
6568 static void translate_movp_s(DisasContext
*dc
, const OpcodeArg arg
[],
6569 const uint32_t par
[])
6571 if (arg
[0].num_bits
== 32) {
6572 TCGv_i32 zero
= tcg_constant_i32(0);
6573 TCGv_i32 tmp
= tcg_temp_new_i32();
6575 tcg_gen_andi_i32(tmp
, arg
[2].in
, 1 << arg
[2].imm
);
6576 tcg_gen_movcond_i32(par
[0],
6577 arg
[0].out
, tmp
, zero
,
6578 arg
[1].in
, arg
[0].in
);
6580 translate_movp_d(dc
, arg
, par
);
6584 static void translate_fpu2k_mul_s(DisasContext
*dc
, const OpcodeArg arg
[],
6585 const uint32_t par
[])
6587 gen_helper_fpu2k_mul_s(arg
[0].out
, tcg_env
,
6588 arg
[1].in
, arg
[2].in
);
6591 static void translate_fpu2k_msub_s(DisasContext
*dc
, const OpcodeArg arg
[],
6592 const uint32_t par
[])
6594 gen_helper_fpu2k_msub_s(arg
[0].out
, tcg_env
,
6595 arg
[0].in
, arg
[1].in
, arg
[2].in
);
6598 static void translate_neg_d(DisasContext
*dc
, const OpcodeArg arg
[],
6599 const uint32_t par
[])
6601 gen_helper_neg_d(arg
[0].out
, arg
[1].in
);
6604 static void translate_neg_s(DisasContext
*dc
, const OpcodeArg arg
[],
6605 const uint32_t par
[])
6609 get_f32_o1_i1(arg
, arg32
, 0, 1);
6610 gen_helper_neg_s(arg32
[0].out
, arg32
[1].in
);
6611 put_f32_o1_i1(arg
, arg32
, 0, 1);
6614 static void translate_rfr_d(DisasContext
*dc
, const OpcodeArg arg
[],
6615 const uint32_t par
[])
6617 tcg_gen_extrh_i64_i32(arg
[0].out
, arg
[1].in
);
6620 static void translate_rfr_s(DisasContext
*dc
, const OpcodeArg arg
[],
6621 const uint32_t par
[])
6623 if (arg
[1].num_bits
== 32) {
6624 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
6626 tcg_gen_extrl_i64_i32(arg
[0].out
, arg
[1].in
);
6630 static void translate_fpu2k_sub_s(DisasContext
*dc
, const OpcodeArg arg
[],
6631 const uint32_t par
[])
6633 gen_helper_fpu2k_sub_s(arg
[0].out
, tcg_env
,
6634 arg
[1].in
, arg
[2].in
);
6637 static void translate_wfr_d(DisasContext
*dc
, const OpcodeArg arg
[],
6638 const uint32_t par
[])
6640 tcg_gen_concat_i32_i64(arg
[0].out
, arg
[2].in
, arg
[1].in
);
6643 static void translate_wfr_s(DisasContext
*dc
, const OpcodeArg arg
[],
6644 const uint32_t par
[])
6646 if (arg
[0].num_bits
== 32) {
6647 tcg_gen_mov_i32(arg
[0].out
, arg
[1].in
);
6649 tcg_gen_ext_i32_i64(arg
[0].out
, arg
[1].in
);
6653 static void translate_wur_fpu2k_fcr(DisasContext
*dc
, const OpcodeArg arg
[],
6654 const uint32_t par
[])
6656 gen_helper_wur_fpu2k_fcr(tcg_env
, arg
[0].in
);
6659 static void translate_wur_fpu2k_fsr(DisasContext
*dc
, const OpcodeArg arg
[],
6660 const uint32_t par
[])
6662 tcg_gen_andi_i32(cpu_UR
[par
[0]], arg
[0].in
, 0xffffff80);
6665 static const XtensaOpcodeOps fpu2000_ops
[] = {
6668 .translate
= translate_abs_s
,
6672 .translate
= translate_fpu2k_add_s
,
6676 .translate
= translate_ftoi_s
,
6677 .par
= (const uint32_t[]){float_round_up
, false},
6681 .translate
= translate_float_s
,
6682 .par
= (const uint32_t[]){false},
6686 .translate
= translate_ftoi_s
,
6687 .par
= (const uint32_t[]){float_round_down
, false},
6691 .translate
= translate_ldsti
,
6692 .par
= (const uint32_t[]){false, false},
6693 .op_flags
= XTENSA_OP_LOAD
,
6697 .translate
= translate_ldsti
,
6698 .par
= (const uint32_t[]){false, true},
6699 .op_flags
= XTENSA_OP_LOAD
,
6703 .translate
= translate_ldstx
,
6704 .par
= (const uint32_t[]){false, false},
6705 .op_flags
= XTENSA_OP_LOAD
,
6709 .translate
= translate_ldstx
,
6710 .par
= (const uint32_t[]){false, true},
6711 .op_flags
= XTENSA_OP_LOAD
,
6715 .translate
= translate_fpu2k_madd_s
,
6719 .translate
= translate_mov_s
,
6723 .translate
= translate_movcond_s
,
6724 .par
= (const uint32_t[]){TCG_COND_EQ
},
6728 .translate
= translate_movp_s
,
6729 .par
= (const uint32_t[]){TCG_COND_EQ
},
6733 .translate
= translate_movcond_s
,
6734 .par
= (const uint32_t[]){TCG_COND_GE
},
6738 .translate
= translate_movcond_s
,
6739 .par
= (const uint32_t[]){TCG_COND_LT
},
6743 .translate
= translate_movcond_s
,
6744 .par
= (const uint32_t[]){TCG_COND_NE
},
6748 .translate
= translate_movp_s
,
6749 .par
= (const uint32_t[]){TCG_COND_NE
},
6753 .translate
= translate_fpu2k_msub_s
,
6757 .translate
= translate_fpu2k_mul_s
,
6761 .translate
= translate_neg_s
,
6765 .translate
= translate_compare_s
,
6766 .par
= (const uint32_t[]){COMPARE_OEQ
},
6770 .translate
= translate_compare_s
,
6771 .par
= (const uint32_t[]){COMPARE_OLE
},
6775 .translate
= translate_compare_s
,
6776 .par
= (const uint32_t[]){COMPARE_OLT
},
6780 .translate
= translate_rfr_s
,
6784 .translate
= translate_ftoi_s
,
6785 .par
= (const uint32_t[]){float_round_nearest_even
, false},
6789 .translate
= translate_rur
,
6790 .par
= (const uint32_t[]){FCR
},
6794 .translate
= translate_rur
,
6795 .par
= (const uint32_t[]){FSR
},
6799 .translate
= translate_ldsti
,
6800 .par
= (const uint32_t[]){true, false},
6801 .op_flags
= XTENSA_OP_STORE
,
6805 .translate
= translate_ldsti
,
6806 .par
= (const uint32_t[]){true, true},
6807 .op_flags
= XTENSA_OP_STORE
,
6811 .translate
= translate_ldstx
,
6812 .par
= (const uint32_t[]){true, false},
6813 .op_flags
= XTENSA_OP_STORE
,
6817 .translate
= translate_ldstx
,
6818 .par
= (const uint32_t[]){true, true},
6819 .op_flags
= XTENSA_OP_STORE
,
6823 .translate
= translate_fpu2k_sub_s
,
6827 .translate
= translate_ftoi_s
,
6828 .par
= (const uint32_t[]){float_round_to_zero
, false},
6832 .translate
= translate_compare_s
,
6833 .par
= (const uint32_t[]){COMPARE_UEQ
},
6837 .translate
= translate_float_s
,
6838 .par
= (const uint32_t[]){true},
6842 .translate
= translate_compare_s
,
6843 .par
= (const uint32_t[]){COMPARE_ULE
},
6847 .translate
= translate_compare_s
,
6848 .par
= (const uint32_t[]){COMPARE_ULT
},
6852 .translate
= translate_compare_s
,
6853 .par
= (const uint32_t[]){COMPARE_UN
},
6857 .translate
= translate_ftoi_s
,
6858 .par
= (const uint32_t[]){float_round_to_zero
, true},
6862 .translate
= translate_wfr_s
,
6866 .translate
= translate_wur_fpu2k_fcr
,
6867 .par
= (const uint32_t[]){FCR
},
6871 .translate
= translate_wur_fpu2k_fsr
,
6872 .par
= (const uint32_t[]){FSR
},
6877 const XtensaOpcodeTranslators xtensa_fpu2000_opcodes
= {
6878 .num_opcodes
= ARRAY_SIZE(fpu2000_ops
),
6879 .opcode
= fpu2000_ops
,
6882 static void translate_add_d(DisasContext
*dc
, const OpcodeArg arg
[],
6883 const uint32_t par
[])
6885 gen_helper_add_d(arg
[0].out
, tcg_env
, arg
[1].in
, arg
[2].in
);
6888 static void translate_add_s(DisasContext
*dc
, const OpcodeArg arg
[],
6889 const uint32_t par
[])
6891 if (option_enabled(dc
, XTENSA_OPTION_DFPU_SINGLE_ONLY
)) {
6892 gen_helper_fpu2k_add_s(arg
[0].out
, tcg_env
,
6893 arg
[1].in
, arg
[2].in
);
6897 get_f32_o1_i2(arg
, arg32
, 0, 1, 2);
6898 gen_helper_add_s(arg32
[0].out
, tcg_env
, arg32
[1].in
, arg32
[2].in
);
6899 put_f32_o1_i2(arg
, arg32
, 0, 1, 2);
6903 static void translate_cvtd_s(DisasContext
*dc
, const OpcodeArg arg
[],
6904 const uint32_t par
[])
6906 TCGv_i32 v
= tcg_temp_new_i32();
6908 tcg_gen_extrl_i64_i32(v
, arg
[1].in
);
6909 gen_helper_cvtd_s(arg
[0].out
, tcg_env
, v
);
6912 static void translate_cvts_d(DisasContext
*dc
, const OpcodeArg arg
[],
6913 const uint32_t par
[])
6915 TCGv_i32 v
= tcg_temp_new_i32();
6917 gen_helper_cvts_d(v
, tcg_env
, arg
[1].in
);
6918 tcg_gen_extu_i32_i64(arg
[0].out
, v
);
6921 static void translate_ldsti_d(DisasContext
*dc
, const OpcodeArg arg
[],
6922 const uint32_t par
[])
6928 addr
= tcg_temp_new_i32();
6929 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
6933 mop
= gen_load_store_alignment(dc
, MO_TEUQ
, addr
);
6935 tcg_gen_qemu_st_i64(arg
[0].in
, addr
, dc
->cring
, mop
);
6937 tcg_gen_qemu_ld_i64(arg
[0].out
, addr
, dc
->cring
, mop
);
6941 tcg_gen_mov_i32(arg
[1].out
, addr
);
6943 tcg_gen_addi_i32(arg
[1].out
, arg
[1].in
, arg
[2].imm
);
6948 static void translate_ldsti_s(DisasContext
*dc
, const OpcodeArg arg
[],
6949 const uint32_t par
[])
6956 addr
= tcg_temp_new_i32();
6957 tcg_gen_addi_i32(addr
, arg
[1].in
, arg
[2].imm
);
6961 mop
= gen_load_store_alignment(dc
, MO_TEUL
, addr
);
6963 get_f32_i1(arg
, arg32
, 0);
6964 tcg_gen_qemu_st_tl(arg32
[0].in
, addr
, dc
->cring
, mop
);
6965 put_f32_i1(arg
, arg32
, 0);
6967 get_f32_o1(arg
, arg32
, 0);
6968 tcg_gen_qemu_ld_tl(arg32
[0].out
, addr
, dc
->cring
, mop
);
6969 put_f32_o1(arg
, arg32
, 0);
6973 tcg_gen_mov_i32(arg
[1].out
, addr
);
6975 tcg_gen_addi_i32(arg
[1].out
, arg
[1].in
, arg
[2].imm
);
6980 static void translate_ldstx_d(DisasContext
*dc
, const OpcodeArg arg
[],
6981 const uint32_t par
[])
6987 addr
= tcg_temp_new_i32();
6988 tcg_gen_add_i32(addr
, arg
[1].in
, arg
[2].in
);
6992 mop
= gen_load_store_alignment(dc
, MO_TEUQ
, addr
);
6994 tcg_gen_qemu_st_i64(arg
[0].in
, addr
, dc
->cring
, mop
);
6996 tcg_gen_qemu_ld_i64(arg
[0].out
, addr
, dc
->cring
, mop
);
7000 tcg_gen_mov_i32(arg
[1].out
, addr
);
7002 tcg_gen_add_i32(arg
[1].out
, arg
[1].in
, arg
[2].in
);
7007 static void translate_ldstx_s(DisasContext
*dc
, const OpcodeArg arg
[],
7008 const uint32_t par
[])
7015 addr
= tcg_temp_new_i32();
7016 tcg_gen_add_i32(addr
, arg
[1].in
, arg
[2].in
);
7020 mop
= gen_load_store_alignment(dc
, MO_TEUL
, addr
);
7022 get_f32_i1(arg
, arg32
, 0);
7023 tcg_gen_qemu_st_tl(arg32
[0].in
, addr
, dc
->cring
, mop
);
7024 put_f32_i1(arg
, arg32
, 0);
7026 get_f32_o1(arg
, arg32
, 0);
7027 tcg_gen_qemu_ld_tl(arg32
[0].out
, addr
, dc
->cring
, mop
);
7028 put_f32_o1(arg
, arg32
, 0);
7032 tcg_gen_mov_i32(arg
[1].out
, addr
);
7034 tcg_gen_add_i32(arg
[1].out
, arg
[1].in
, arg
[2].in
);
7039 static void translate_madd_d(DisasContext
*dc
, const OpcodeArg arg
[],
7040 const uint32_t par
[])
7042 gen_helper_madd_d(arg
[0].out
, tcg_env
,
7043 arg
[0].in
, arg
[1].in
, arg
[2].in
);
7046 static void translate_madd_s(DisasContext
*dc
, const OpcodeArg arg
[],
7047 const uint32_t par
[])
7049 if (option_enabled(dc
, XTENSA_OPTION_DFPU_SINGLE_ONLY
)) {
7050 gen_helper_fpu2k_madd_s(arg
[0].out
, tcg_env
,
7051 arg
[0].in
, arg
[1].in
, arg
[2].in
);
7055 get_f32_o1_i3(arg
, arg32
, 0, 0, 1, 2);
7056 gen_helper_madd_s(arg32
[0].out
, tcg_env
,
7057 arg32
[0].in
, arg32
[1].in
, arg32
[2].in
);
7058 put_f32_o1_i3(arg
, arg32
, 0, 0, 1, 2);
7062 static void translate_mul_d(DisasContext
*dc
, const OpcodeArg arg
[],
7063 const uint32_t par
[])
7065 gen_helper_mul_d(arg
[0].out
, tcg_env
, arg
[1].in
, arg
[2].in
);
7068 static void translate_mul_s(DisasContext
*dc
, const OpcodeArg arg
[],
7069 const uint32_t par
[])
7071 if (option_enabled(dc
, XTENSA_OPTION_DFPU_SINGLE_ONLY
)) {
7072 gen_helper_fpu2k_mul_s(arg
[0].out
, tcg_env
,
7073 arg
[1].in
, arg
[2].in
);
7077 get_f32_o1_i2(arg
, arg32
, 0, 1, 2);
7078 gen_helper_mul_s(arg32
[0].out
, tcg_env
, arg32
[1].in
, arg32
[2].in
);
7079 put_f32_o1_i2(arg
, arg32
, 0, 1, 2);
7083 static void translate_msub_d(DisasContext
*dc
, const OpcodeArg arg
[],
7084 const uint32_t par
[])
7086 gen_helper_msub_d(arg
[0].out
, tcg_env
,
7087 arg
[0].in
, arg
[1].in
, arg
[2].in
);
7090 static void translate_msub_s(DisasContext
*dc
, const OpcodeArg arg
[],
7091 const uint32_t par
[])
7093 if (option_enabled(dc
, XTENSA_OPTION_DFPU_SINGLE_ONLY
)) {
7094 gen_helper_fpu2k_msub_s(arg
[0].out
, tcg_env
,
7095 arg
[0].in
, arg
[1].in
, arg
[2].in
);
7099 get_f32_o1_i3(arg
, arg32
, 0, 0, 1, 2);
7100 gen_helper_msub_s(arg32
[0].out
, tcg_env
,
7101 arg32
[0].in
, arg32
[1].in
, arg32
[2].in
);
7102 put_f32_o1_i3(arg
, arg32
, 0, 0, 1, 2);
7106 static void translate_sub_d(DisasContext
*dc
, const OpcodeArg arg
[],
7107 const uint32_t par
[])
7109 gen_helper_sub_d(arg
[0].out
, tcg_env
, arg
[1].in
, arg
[2].in
);
7112 static void translate_sub_s(DisasContext
*dc
, const OpcodeArg arg
[],
7113 const uint32_t par
[])
7115 if (option_enabled(dc
, XTENSA_OPTION_DFPU_SINGLE_ONLY
)) {
7116 gen_helper_fpu2k_sub_s(arg
[0].out
, tcg_env
,
7117 arg
[1].in
, arg
[2].in
);
7121 get_f32_o1_i2(arg
, arg32
, 0, 1, 2);
7122 gen_helper_sub_s(arg32
[0].out
, tcg_env
, arg32
[1].in
, arg32
[2].in
);
7123 put_f32_o1_i2(arg
, arg32
, 0, 1, 2);
7127 static void translate_mkdadj_d(DisasContext
*dc
, const OpcodeArg arg
[],
7128 const uint32_t par
[])
7130 gen_helper_mkdadj_d(arg
[0].out
, tcg_env
, arg
[0].in
, arg
[1].in
);
7133 static void translate_mkdadj_s(DisasContext
*dc
, const OpcodeArg arg
[],
7134 const uint32_t par
[])
7138 get_f32_o1_i2(arg
, arg32
, 0, 0, 1);
7139 gen_helper_mkdadj_s(arg32
[0].out
, tcg_env
, arg32
[0].in
, arg32
[1].in
);
7140 put_f32_o1_i2(arg
, arg32
, 0, 0, 1);
7143 static void translate_mksadj_d(DisasContext
*dc
, const OpcodeArg arg
[],
7144 const uint32_t par
[])
7146 gen_helper_mksadj_d(arg
[0].out
, tcg_env
, arg
[1].in
);
7149 static void translate_mksadj_s(DisasContext
*dc
, const OpcodeArg arg
[],
7150 const uint32_t par
[])
7154 get_f32_o1_i1(arg
, arg32
, 0, 1);
7155 gen_helper_mksadj_s(arg32
[0].out
, tcg_env
, arg32
[1].in
);
7156 put_f32_o1_i1(arg
, arg32
, 0, 1);
7159 static void translate_wur_fpu_fcr(DisasContext
*dc
, const OpcodeArg arg
[],
7160 const uint32_t par
[])
7162 gen_helper_wur_fpu_fcr(tcg_env
, arg
[0].in
);
7165 static void translate_rur_fpu_fsr(DisasContext
*dc
, const OpcodeArg arg
[],
7166 const uint32_t par
[])
7168 gen_helper_rur_fpu_fsr(arg
[0].out
, tcg_env
);
7171 static void translate_wur_fpu_fsr(DisasContext
*dc
, const OpcodeArg arg
[],
7172 const uint32_t par
[])
7174 gen_helper_wur_fpu_fsr(tcg_env
, arg
[0].in
);
7177 static const XtensaOpcodeOps fpu_ops
[] = {
7180 .translate
= translate_abs_d
,
7184 .translate
= translate_abs_s
,
7188 .translate
= translate_add_d
,
7192 .translate
= translate_add_s
,
7196 .translate
= translate_nop
,
7200 .translate
= translate_nop
,
7203 .name
= "addexpm.d",
7204 .translate
= translate_mov_s
,
7207 .name
= "addexpm.s",
7208 .translate
= translate_mov_s
,
7212 .translate
= translate_ftoi_d
,
7213 .par
= (const uint32_t[]){float_round_up
, false},
7217 .translate
= translate_ftoi_s
,
7218 .par
= (const uint32_t[]){float_round_up
, false},
7222 .translate
= translate_const_d
,
7226 .translate
= translate_const_s
,
7230 .translate
= translate_cvtd_s
,
7234 .translate
= translate_cvts_d
,
7238 .translate
= translate_nop
,
7242 .translate
= translate_nop
,
7246 .translate
= translate_nop
,
7250 .translate
= translate_nop
,
7254 .translate
= translate_float_d
,
7255 .par
= (const uint32_t[]){false},
7259 .translate
= translate_float_s
,
7260 .par
= (const uint32_t[]){false},
7264 .translate
= translate_ftoi_d
,
7265 .par
= (const uint32_t[]){float_round_down
, false},
7269 .translate
= translate_ftoi_s
,
7270 .par
= (const uint32_t[]){float_round_down
, false},
7274 .translate
= translate_ldsti_d
,
7275 .par
= (const uint32_t[]){false, true, false},
7276 .op_flags
= XTENSA_OP_LOAD
,
7280 .translate
= translate_ldsti_d
,
7281 .par
= (const uint32_t[]){false, false, true},
7282 .op_flags
= XTENSA_OP_LOAD
,
7286 .translate
= translate_ldsti_d
,
7287 .par
= (const uint32_t[]){false, true, true},
7288 .op_flags
= XTENSA_OP_LOAD
,
7292 .translate
= translate_ldstx_d
,
7293 .par
= (const uint32_t[]){false, true, false},
7294 .op_flags
= XTENSA_OP_LOAD
,
7298 .translate
= translate_ldstx_d
,
7299 .par
= (const uint32_t[]){false, false, true},
7300 .op_flags
= XTENSA_OP_LOAD
,
7304 .translate
= translate_ldstx_d
,
7305 .par
= (const uint32_t[]){false, true, true},
7306 .op_flags
= XTENSA_OP_LOAD
,
7310 .translate
= translate_ldsti_s
,
7311 .par
= (const uint32_t[]){false, true, false},
7312 .op_flags
= XTENSA_OP_LOAD
,
7316 .translate
= translate_ldsti_s
,
7317 .par
= (const uint32_t[]){false, false, true},
7318 .op_flags
= XTENSA_OP_LOAD
,
7322 .translate
= translate_ldsti_s
,
7323 .par
= (const uint32_t[]){false, true, true},
7324 .op_flags
= XTENSA_OP_LOAD
,
7328 .translate
= translate_ldstx_s
,
7329 .par
= (const uint32_t[]){false, true, false},
7330 .op_flags
= XTENSA_OP_LOAD
,
7334 .translate
= translate_ldstx_s
,
7335 .par
= (const uint32_t[]){false, false, true},
7336 .op_flags
= XTENSA_OP_LOAD
,
7340 .translate
= translate_ldstx_s
,
7341 .par
= (const uint32_t[]){false, true, true},
7342 .op_flags
= XTENSA_OP_LOAD
,
7346 .translate
= translate_madd_d
,
7350 .translate
= translate_madd_s
,
7354 .translate
= translate_nop
,
7358 .translate
= translate_nop
,
7362 .translate
= translate_mkdadj_d
,
7366 .translate
= translate_mkdadj_s
,
7370 .translate
= translate_mksadj_d
,
7374 .translate
= translate_mksadj_s
,
7378 .translate
= translate_mov_d
,
7382 .translate
= translate_mov_s
,
7386 .translate
= translate_movcond_d
,
7387 .par
= (const uint32_t[]){TCG_COND_EQ
},
7391 .translate
= translate_movcond_s
,
7392 .par
= (const uint32_t[]){TCG_COND_EQ
},
7396 .translate
= translate_movp_d
,
7397 .par
= (const uint32_t[]){TCG_COND_EQ
},
7401 .translate
= translate_movp_s
,
7402 .par
= (const uint32_t[]){TCG_COND_EQ
},
7406 .translate
= translate_movcond_d
,
7407 .par
= (const uint32_t[]){TCG_COND_GE
},
7411 .translate
= translate_movcond_s
,
7412 .par
= (const uint32_t[]){TCG_COND_GE
},
7416 .translate
= translate_movcond_d
,
7417 .par
= (const uint32_t[]){TCG_COND_LT
},
7421 .translate
= translate_movcond_s
,
7422 .par
= (const uint32_t[]){TCG_COND_LT
},
7426 .translate
= translate_movcond_d
,
7427 .par
= (const uint32_t[]){TCG_COND_NE
},
7431 .translate
= translate_movcond_s
,
7432 .par
= (const uint32_t[]){TCG_COND_NE
},
7436 .translate
= translate_movp_d
,
7437 .par
= (const uint32_t[]){TCG_COND_NE
},
7441 .translate
= translate_movp_s
,
7442 .par
= (const uint32_t[]){TCG_COND_NE
},
7446 .translate
= translate_msub_d
,
7450 .translate
= translate_msub_s
,
7454 .translate
= translate_mul_d
,
7458 .translate
= translate_mul_s
,
7462 .translate
= translate_neg_d
,
7466 .translate
= translate_neg_s
,
7470 .translate
= translate_nop
,
7474 .translate
= translate_nop
,
7478 .translate
= translate_compare_d
,
7479 .par
= (const uint32_t[]){COMPARE_OEQ
},
7483 .translate
= translate_compare_s
,
7484 .par
= (const uint32_t[]){COMPARE_OEQ
},
7488 .translate
= translate_compare_d
,
7489 .par
= (const uint32_t[]){COMPARE_OLE
},
7493 .translate
= translate_compare_s
,
7494 .par
= (const uint32_t[]){COMPARE_OLE
},
7498 .translate
= translate_compare_d
,
7499 .par
= (const uint32_t[]){COMPARE_OLT
},
7503 .translate
= translate_compare_s
,
7504 .par
= (const uint32_t[]){COMPARE_OLT
},
7508 .translate
= translate_rfr_s
,
7512 .translate
= translate_rfr_d
,
7516 .translate
= translate_ftoi_d
,
7517 .par
= (const uint32_t[]){float_round_nearest_even
, false},
7521 .translate
= translate_ftoi_s
,
7522 .par
= (const uint32_t[]){float_round_nearest_even
, false},
7526 .translate
= translate_rur
,
7527 .par
= (const uint32_t[]){FCR
},
7531 .translate
= translate_rur_fpu_fsr
,
7535 .translate
= translate_ldsti_d
,
7536 .par
= (const uint32_t[]){true, true, false},
7537 .op_flags
= XTENSA_OP_STORE
,
7541 .translate
= translate_ldsti_d
,
7542 .par
= (const uint32_t[]){true, false, true},
7543 .op_flags
= XTENSA_OP_STORE
,
7547 .translate
= translate_ldsti_d
,
7548 .par
= (const uint32_t[]){true, true, true},
7549 .op_flags
= XTENSA_OP_STORE
,
7553 .translate
= translate_ldstx_d
,
7554 .par
= (const uint32_t[]){true, true, false},
7555 .op_flags
= XTENSA_OP_STORE
,
7559 .translate
= translate_ldstx_d
,
7560 .par
= (const uint32_t[]){true, false, true},
7561 .op_flags
= XTENSA_OP_STORE
,
7565 .translate
= translate_ldstx_d
,
7566 .par
= (const uint32_t[]){true, true, true},
7567 .op_flags
= XTENSA_OP_STORE
,
7571 .translate
= translate_nop
,
7575 .translate
= translate_nop
,
7579 .translate
= translate_ldsti_s
,
7580 .par
= (const uint32_t[]){true, true, false},
7581 .op_flags
= XTENSA_OP_STORE
,
7585 .translate
= translate_ldsti_s
,
7586 .par
= (const uint32_t[]){true, false, true},
7587 .op_flags
= XTENSA_OP_STORE
,
7591 .translate
= translate_ldsti_s
,
7592 .par
= (const uint32_t[]){true, true, true},
7593 .op_flags
= XTENSA_OP_STORE
,
7597 .translate
= translate_ldstx_s
,
7598 .par
= (const uint32_t[]){true, true, false},
7599 .op_flags
= XTENSA_OP_STORE
,
7603 .translate
= translate_ldstx_s
,
7604 .par
= (const uint32_t[]){true, false, true},
7605 .op_flags
= XTENSA_OP_STORE
,
7609 .translate
= translate_ldstx_s
,
7610 .par
= (const uint32_t[]){true, true, true},
7611 .op_flags
= XTENSA_OP_STORE
,
7615 .translate
= translate_sub_d
,
7619 .translate
= translate_sub_s
,
7623 .translate
= translate_ftoi_d
,
7624 .par
= (const uint32_t[]){float_round_to_zero
, false},
7628 .translate
= translate_ftoi_s
,
7629 .par
= (const uint32_t[]){float_round_to_zero
, false},
7633 .translate
= translate_compare_d
,
7634 .par
= (const uint32_t[]){COMPARE_UEQ
},
7638 .translate
= translate_compare_s
,
7639 .par
= (const uint32_t[]){COMPARE_UEQ
},
7643 .translate
= translate_float_d
,
7644 .par
= (const uint32_t[]){true},
7648 .translate
= translate_float_s
,
7649 .par
= (const uint32_t[]){true},
7653 .translate
= translate_compare_d
,
7654 .par
= (const uint32_t[]){COMPARE_ULE
},
7658 .translate
= translate_compare_s
,
7659 .par
= (const uint32_t[]){COMPARE_ULE
},
7663 .translate
= translate_compare_d
,
7664 .par
= (const uint32_t[]){COMPARE_ULT
},
7668 .translate
= translate_compare_s
,
7669 .par
= (const uint32_t[]){COMPARE_ULT
},
7673 .translate
= translate_compare_d
,
7674 .par
= (const uint32_t[]){COMPARE_UN
},
7678 .translate
= translate_compare_s
,
7679 .par
= (const uint32_t[]){COMPARE_UN
},
7683 .translate
= translate_ftoi_d
,
7684 .par
= (const uint32_t[]){float_round_to_zero
, true},
7688 .translate
= translate_ftoi_s
,
7689 .par
= (const uint32_t[]){float_round_to_zero
, true},
7693 .translate
= translate_wfr_s
,
7697 .translate
= translate_wfr_d
,
7701 .translate
= translate_wur_fpu_fcr
,
7702 .par
= (const uint32_t[]){FCR
},
7706 .translate
= translate_wur_fpu_fsr
,
7711 const XtensaOpcodeTranslators xtensa_fpu_opcodes
= {
7712 .num_opcodes
= ARRAY_SIZE(fpu_ops
),