target-alpha/cpu.h

   1 /*
   2  *  Alpha emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #if !defined (__CPU_ALPHA_H__)
  21 #define __CPU_ALPHA_H__
  22
  23 #include "config.h"
  24
  25 #define TARGET_LONG_BITS 64
  26
  27 #define CPUState struct CPUAlphaState
  28
  29 #include "cpu-defs.h"
  30
  31 #include <setjmp.h>
  32
  33 #include "softfloat.h"
  34
  35 #define TARGET_HAS_ICE 1
  36
  37 #define ELF_MACHINE     EM_ALPHA
  38
  39 #define ICACHE_LINE_SIZE 32
  40 #define DCACHE_LINE_SIZE 32
  41
  42 #define TARGET_PAGE_BITS 13
  43
  44 /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
  45 #define TARGET_PHYS_ADDR_SPACE_BITS     44
  46 #define TARGET_VIRT_ADDR_SPACE_BITS     (30 + TARGET_PAGE_BITS)
  47
  48 /* Alpha major type */
  49 enum {
  50     ALPHA_EV3  = 1,
  51     ALPHA_EV4  = 2,
  52     ALPHA_SIM  = 3,
  53     ALPHA_LCA  = 4,
  54     ALPHA_EV5  = 5, /* 21164 */
  55     ALPHA_EV45 = 6, /* 21064A */
  56     ALPHA_EV56 = 7, /* 21164A */
  57 };
  58
  59 /* EV4 minor type */
  60 enum {
  61     ALPHA_EV4_2 = 0,
  62     ALPHA_EV4_3 = 1,
  63 };
  64
  65 /* LCA minor type */
  66 enum {
  67     ALPHA_LCA_1 = 1, /* 21066 */
  68     ALPHA_LCA_2 = 2, /* 20166 */
  69     ALPHA_LCA_3 = 3, /* 21068 */
  70     ALPHA_LCA_4 = 4, /* 21068 */
  71     ALPHA_LCA_5 = 5, /* 21066A */
  72     ALPHA_LCA_6 = 6, /* 21068A */
  73 };
  74
  75 /* EV5 minor type */
  76 enum {
  77     ALPHA_EV5_1 = 1, /* Rev BA, CA */
  78     ALPHA_EV5_2 = 2, /* Rev DA, EA */
  79     ALPHA_EV5_3 = 3, /* Pass 3 */
  80     ALPHA_EV5_4 = 4, /* Pass 3.2 */
  81     ALPHA_EV5_5 = 5, /* Pass 4 */
  82 };
  83
  84 /* EV45 minor type */
  85 enum {
  86     ALPHA_EV45_1 = 1, /* Pass 1 */
  87     ALPHA_EV45_2 = 2, /* Pass 1.1 */
  88     ALPHA_EV45_3 = 3, /* Pass 2 */
  89 };
  90
  91 /* EV56 minor type */
  92 enum {
  93     ALPHA_EV56_1 = 1, /* Pass 1 */
  94     ALPHA_EV56_2 = 2, /* Pass 2 */
  95 };
  96
  97 enum {
  98     IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
  99     IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
 100     IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
 101     IMPLVER_21364 = 3, /* EV7 & EV79 */
 102 };
 103
 104 enum {
 105     AMASK_BWX      = 0x00000001,
 106     AMASK_FIX      = 0x00000002,
 107     AMASK_CIX      = 0x00000004,
 108     AMASK_MVI      = 0x00000100,
 109     AMASK_TRAP     = 0x00000200,
 110     AMASK_PREFETCH = 0x00001000,
 111 };
 112
 113 enum {
 114     VAX_ROUND_NORMAL = 0,
 115     VAX_ROUND_CHOPPED,
 116 };
 117
 118 enum {
 119     IEEE_ROUND_NORMAL = 0,
 120     IEEE_ROUND_DYNAMIC,
 121     IEEE_ROUND_PLUS,
 122     IEEE_ROUND_MINUS,
 123     IEEE_ROUND_CHOPPED,
 124 };
 125
 126 /* IEEE floating-point operations encoding */
 127 /* Trap mode */
 128 enum {
 129     FP_TRAP_I   = 0x0,
 130     FP_TRAP_U   = 0x1,
 131     FP_TRAP_S  = 0x4,
 132     FP_TRAP_SU  = 0x5,
 133     FP_TRAP_SUI = 0x7,
 134 };
 135
 136 /* Rounding mode */
 137 enum {
 138     FP_ROUND_CHOPPED = 0x0,
 139     FP_ROUND_MINUS   = 0x1,
 140     FP_ROUND_NORMAL  = 0x2,
 141     FP_ROUND_DYNAMIC = 0x3,
 142 };
 143
 144 /* FPCR bits */
 145 #define FPCR_SUM                (1ULL << 63)
 146 #define FPCR_INED               (1ULL << 62)
 147 #define FPCR_UNFD               (1ULL << 61)
 148 #define FPCR_UNDZ               (1ULL << 60)
 149 #define FPCR_DYN_SHIFT          58
 150 #define FPCR_DYN_CHOPPED        (0ULL << FPCR_DYN_SHIFT)
 151 #define FPCR_DYN_MINUS          (1ULL << FPCR_DYN_SHIFT)
 152 #define FPCR_DYN_NORMAL         (2ULL << FPCR_DYN_SHIFT)
 153 #define FPCR_DYN_PLUS           (3ULL << FPCR_DYN_SHIFT)
 154 #define FPCR_DYN_MASK           (3ULL << FPCR_DYN_SHIFT)
 155 #define FPCR_IOV                (1ULL << 57)
 156 #define FPCR_INE                (1ULL << 56)
 157 #define FPCR_UNF                (1ULL << 55)
 158 #define FPCR_OVF                (1ULL << 54)
 159 #define FPCR_DZE                (1ULL << 53)
 160 #define FPCR_INV                (1ULL << 52)
 161 #define FPCR_OVFD               (1ULL << 51)
 162 #define FPCR_DZED               (1ULL << 50)
 163 #define FPCR_INVD               (1ULL << 49)
 164 #define FPCR_DNZ                (1ULL << 48)
 165 #define FPCR_DNOD               (1ULL << 47)
 166 #define FPCR_STATUS_MASK        (FPCR_IOV | FPCR_INE | FPCR_UNF \
 167                                  | FPCR_OVF | FPCR_DZE | FPCR_INV)
 168
 169 /* The silly software trap enables implemented by the kernel emulation.
 170    These are more or less architecturally required, since the real hardware
 171    has read-as-zero bits in the FPCR when the features aren't implemented.
 172    For the purposes of QEMU, we pretend the FPCR can hold everything.  */
 173 #define SWCR_TRAP_ENABLE_INV    (1ULL << 1)
 174 #define SWCR_TRAP_ENABLE_DZE    (1ULL << 2)
 175 #define SWCR_TRAP_ENABLE_OVF    (1ULL << 3)
 176 #define SWCR_TRAP_ENABLE_UNF    (1ULL << 4)
 177 #define SWCR_TRAP_ENABLE_INE    (1ULL << 5)
 178 #define SWCR_TRAP_ENABLE_DNO    (1ULL << 6)
 179 #define SWCR_TRAP_ENABLE_MASK   ((1ULL << 7) - (1ULL << 1))
 180
 181 #define SWCR_MAP_DMZ            (1ULL << 12)
 182 #define SWCR_MAP_UMZ            (1ULL << 13)
 183 #define SWCR_MAP_MASK           (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
 184
 185 #define SWCR_STATUS_INV         (1ULL << 17)
 186 #define SWCR_STATUS_DZE         (1ULL << 18)
 187 #define SWCR_STATUS_OVF         (1ULL << 19)
 188 #define SWCR_STATUS_UNF         (1ULL << 20)
 189 #define SWCR_STATUS_INE         (1ULL << 21)
 190 #define SWCR_STATUS_DNO         (1ULL << 22)
 191 #define SWCR_STATUS_MASK        ((1ULL << 23) - (1ULL << 17))
 192
 193 #define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
 194
 195 /* MMU modes definitions */
 196
 197 /* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
 198    The Unix PALcode only exposes the kernel and user modes; presumably
 199    executive and supervisor are used by VMS.
 200
 201    PALcode itself uses physical mode for code and kernel mode for data;
 202    there are PALmode instructions that can access data via physical mode
 203    or via an os-installed "alternate mode", which is one of the 4 above.
 204
 205    QEMU does not currently properly distinguish between code/data when
 206    looking up addresses.  To avoid having to address this issue, our
 207    emulated PALcode will cheat and use the KSEG mapping for its code+data
 208    rather than physical addresses.
 209
 210    Moreover, we're only emulating Unix PALcode, and not attempting VMS.
 211
 212    All of which allows us to drop all but kernel and user modes.
 213    Elide the unused MMU modes to save space.  */
 214
 215 #define NB_MMU_MODES 2
 216
 217 #define MMU_MODE0_SUFFIX _kernel
 218 #define MMU_MODE1_SUFFIX _user
 219 #define MMU_KERNEL_IDX   0
 220 #define MMU_USER_IDX     1
 221
 222 typedef struct CPUAlphaState CPUAlphaState;
 223
 224 struct CPUAlphaState {
 225     uint64_t ir[31];
 226     float64 fir[31];
 227     uint64_t pc;
 228     uint64_t unique;
 229     uint64_t lock_addr;
 230     uint64_t lock_st_addr;
 231     uint64_t lock_value;
 232     float_status fp_status;
 233     /* The following fields make up the FPCR, but in FP_STATUS format.  */
 234     uint8_t fpcr_exc_status;
 235     uint8_t fpcr_exc_mask;
 236     uint8_t fpcr_dyn_round;
 237     uint8_t fpcr_flush_to_zero;
 238     uint8_t fpcr_dnz;
 239     uint8_t fpcr_dnod;
 240     uint8_t fpcr_undz;
 241
 242     /* The Internal Processor Registers.  Some of these we assume always
 243        exist for use in user-mode.  */
 244     uint8_t ps;
 245     uint8_t intr_flag;
 246     uint8_t pal_mode;
 247     uint8_t fen;
 248
 249     uint32_t pcc_ofs;
 250
 251     /* These pass data from the exception logic in the translator and
 252        helpers to the OS entry point.  This is used for both system
 253        emulation and user-mode.  */
 254     uint64_t trap_arg0;
 255     uint64_t trap_arg1;
 256     uint64_t trap_arg2;
 257
 258 #if !defined(CONFIG_USER_ONLY)
 259     /* The internal data required by our emulation of the Unix PALcode.  */
 260     uint64_t exc_addr;
 261     uint64_t palbr;
 262     uint64_t ptbr;
 263     uint64_t vptptr;
 264     uint64_t sysval;
 265     uint64_t usp;
 266     uint64_t shadow[8];
 267     uint64_t scratch[24];
 268 #endif
 269
 270 #if TARGET_LONG_BITS > HOST_LONG_BITS
 271     /* temporary fixed-point registers
 272      * used to emulate 64 bits target on 32 bits hosts
 273      */
 274     target_ulong t0, t1;
 275 #endif
 276
 277     /* Those resources are used only in Qemu core */
 278     CPU_COMMON
 279
 280     int error_code;
 281
 282     uint32_t features;
 283     uint32_t amask;
 284     int implver;
 285 };
 286
 287 #define cpu_init cpu_alpha_init
 288 #define cpu_exec cpu_alpha_exec
 289 #define cpu_gen_code cpu_alpha_gen_code
 290 #define cpu_signal_handler cpu_alpha_signal_handler
 291
 292 #include "cpu-all.h"
 293
 294 enum {
 295     FEATURE_ASN    = 0x00000001,
 296     FEATURE_SPS    = 0x00000002,
 297     FEATURE_VIRBND = 0x00000004,
 298     FEATURE_TBCHK  = 0x00000008,
 299 };
 300
 301 enum {
 302     EXCP_RESET,
 303     EXCP_MCHK,
 304     EXCP_SMP_INTERRUPT,
 305     EXCP_CLK_INTERRUPT,
 306     EXCP_DEV_INTERRUPT,
 307     EXCP_MMFAULT,
 308     EXCP_UNALIGN,
 309     EXCP_OPCDEC,
 310     EXCP_ARITH,
 311     EXCP_FEN,
 312     EXCP_CALL_PAL,
 313     /* For Usermode emulation.  */
 314     EXCP_STL_C,
 315     EXCP_STQ_C,
 316 };
 317
 318 /* Hardware interrupt (entInt) constants.  */
 319 enum {
 320     INT_K_IP,
 321     INT_K_CLK,
 322     INT_K_MCHK,
 323     INT_K_DEV,
 324     INT_K_PERF,
 325 };
 326
 327 /* Memory management (entMM) constants.  */
 328 enum {
 329     MM_K_TNV,
 330     MM_K_ACV,
 331     MM_K_FOR,
 332     MM_K_FOE,
 333     MM_K_FOW
 334 };
 335
 336 /* Arithmetic exception (entArith) constants.  */
 337 enum {
 338     EXC_M_SWC = 1,      /* Software completion */
 339     EXC_M_INV = 2,      /* Invalid operation */
 340     EXC_M_DZE = 4,      /* Division by zero */
 341     EXC_M_FOV = 8,      /* Overflow */
 342     EXC_M_UNF = 16,     /* Underflow */
 343     EXC_M_INE = 32,     /* Inexact result */
 344     EXC_M_IOV = 64      /* Integer Overflow */
 345 };
 346
 347 /* Processor status constants.  */
 348 enum {
 349     /* Low 3 bits are interrupt mask level.  */
 350     PS_INT_MASK = 7,
 351
 352     /* Bits 4 and 5 are the mmu mode.  The VMS PALcode uses all 4 modes;
 353        The Unix PALcode only uses bit 4.  */
 354     PS_USER_MODE = 8
 355 };
 356
 357 static inline int cpu_mmu_index(CPUState *env)
 358 {
 359     if (env->pal_mode) {
 360         return MMU_KERNEL_IDX;
 361     } else if (env->ps & PS_USER_MODE) {
 362         return MMU_USER_IDX;
 363     } else {
 364         return MMU_KERNEL_IDX;
 365     }
 366 }
 367
 368 enum {
 369     IR_V0   = 0,
 370     IR_T0   = 1,
 371     IR_T1   = 2,
 372     IR_T2   = 3,
 373     IR_T3   = 4,
 374     IR_T4   = 5,
 375     IR_T5   = 6,
 376     IR_T6   = 7,
 377     IR_T7   = 8,
 378     IR_S0   = 9,
 379     IR_S1   = 10,
 380     IR_S2   = 11,
 381     IR_S3   = 12,
 382     IR_S4   = 13,
 383     IR_S5   = 14,
 384     IR_S6   = 15,
 385     IR_FP   = IR_S6,
 386     IR_A0   = 16,
 387     IR_A1   = 17,
 388     IR_A2   = 18,
 389     IR_A3   = 19,
 390     IR_A4   = 20,
 391     IR_A5   = 21,
 392     IR_T8   = 22,
 393     IR_T9   = 23,
 394     IR_T10  = 24,
 395     IR_T11  = 25,
 396     IR_RA   = 26,
 397     IR_T12  = 27,
 398     IR_PV   = IR_T12,
 399     IR_AT   = 28,
 400     IR_GP   = 29,
 401     IR_SP   = 30,
 402     IR_ZERO = 31,
 403 };
 404
 405 CPUAlphaState * cpu_alpha_init (const char *cpu_model);
 406 int cpu_alpha_exec(CPUAlphaState *s);
 407 /* you can call this signal handler from your SIGBUS and SIGSEGV
 408    signal handlers to inform the virtual CPU of exceptions. non zero
 409    is returned if the signal was handled by the virtual CPU.  */
 410 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
 411                              void *puc);
 412 int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
 413                                 int mmu_idx, int is_softmmu);
 414 #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
 415 void do_interrupt (CPUState *env);
 416
 417 uint64_t cpu_alpha_load_fpcr (CPUState *env);
 418 void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
 419 extern void swap_shadow_regs(CPUState *env);
 420
 421 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 422                                         target_ulong *cs_base, int *flags)
 423 {
 424     *pc = env->pc;
 425     *cs_base = 0;
 426     *flags = env->ps;
 427 }
 428
 429 #if defined(CONFIG_USER_ONLY)
 430 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 431 {
 432     if (newsp) {
 433         env->ir[IR_SP] = newsp;
 434     }
 435     env->ir[IR_V0] = 0;
 436     env->ir[IR_A3] = 0;
 437 }
 438
 439 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 440 {
 441     env->unique = newtls;
 442 }
 443 #endif
 444
 445 #endif /* !defined (__CPU_ALPHA_H__) */