2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include "qemu-common.h"
32 #define DO_SINGLE_STEP
34 #define ALPHA_DEBUG_DISAS
37 typedef struct DisasContext DisasContext
;
41 #if !defined (CONFIG_USER_ONLY)
48 static TCGv cpu_ir
[31];
51 static char cpu_reg_names
[5*31];
53 #include "gen-icount.h"
55 static void alpha_translate_init(void)
59 static int done_init
= 0;
64 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
67 for (i
= 0; i
< 31; i
++) {
68 sprintf(p
, "ir%d", i
);
69 cpu_ir
[i
] = tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
70 offsetof(CPUState
, ir
[i
]), p
);
74 cpu_pc
= tcg_global_mem_new(TCG_TYPE_I64
, TCG_AREG0
,
75 offsetof(CPUState
, pc
), "pc");
77 /* register helpers */
79 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
85 static always_inline
void gen_op_nop (void)
87 #if defined(GENERATE_NOP)
92 #define GEN32(func, NAME) \
93 static GenOpFunc *NAME ## _table [32] = { \
94 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
95 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
96 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
97 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
98 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
99 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
100 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
101 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
103 static always_inline void func (int n) \
105 NAME ## _table[n](); \
109 /* Special hacks for ir31 */
110 #define gen_op_load_T0_ir31 gen_op_reset_T0
111 #define gen_op_load_T1_ir31 gen_op_reset_T1
112 #define gen_op_load_T2_ir31 gen_op_reset_T2
113 #define gen_op_store_T0_ir31 gen_op_nop
114 #define gen_op_store_T1_ir31 gen_op_nop
115 #define gen_op_store_T2_ir31 gen_op_nop
116 #define gen_op_cmov_ir31 gen_op_nop
117 GEN32(gen_op_load_T0_ir
, gen_op_load_T0_ir
);
118 GEN32(gen_op_load_T1_ir
, gen_op_load_T1_ir
);
119 GEN32(gen_op_load_T2_ir
, gen_op_load_T2_ir
);
120 GEN32(gen_op_store_T0_ir
, gen_op_store_T0_ir
);
121 GEN32(gen_op_store_T1_ir
, gen_op_store_T1_ir
);
122 GEN32(gen_op_store_T2_ir
, gen_op_store_T2_ir
);
123 GEN32(gen_op_cmov_ir
, gen_op_cmov_ir
);
125 static always_inline
void gen_load_ir (DisasContext
*ctx
, int irn
, int Tn
)
129 gen_op_load_T0_ir(irn
);
132 gen_op_load_T1_ir(irn
);
135 gen_op_load_T2_ir(irn
);
140 static always_inline
void gen_store_ir (DisasContext
*ctx
, int irn
, int Tn
)
144 gen_op_store_T0_ir(irn
);
147 gen_op_store_T1_ir(irn
);
150 gen_op_store_T2_ir(irn
);
155 static inline void get_ir (TCGv t
, int reg
)
158 tcg_gen_movi_i64(t
, 0);
160 tcg_gen_mov_i64(t
, cpu_ir
[reg
]);
163 static inline void set_ir (TCGv t
, int reg
)
166 tcg_gen_mov_i64(cpu_ir
[reg
], t
);
170 /* Special hacks for fir31 */
171 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
172 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
173 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
174 #define gen_op_store_FT0_fir31 gen_op_nop
175 #define gen_op_store_FT1_fir31 gen_op_nop
176 #define gen_op_store_FT2_fir31 gen_op_nop
177 #define gen_op_cmov_fir31 gen_op_nop
178 GEN32(gen_op_load_FT0_fir
, gen_op_load_FT0_fir
);
179 GEN32(gen_op_load_FT1_fir
, gen_op_load_FT1_fir
);
180 GEN32(gen_op_load_FT2_fir
, gen_op_load_FT2_fir
);
181 GEN32(gen_op_store_FT0_fir
, gen_op_store_FT0_fir
);
182 GEN32(gen_op_store_FT1_fir
, gen_op_store_FT1_fir
);
183 GEN32(gen_op_store_FT2_fir
, gen_op_store_FT2_fir
);
184 GEN32(gen_op_cmov_fir
, gen_op_cmov_fir
);
186 static always_inline
void gen_load_fir (DisasContext
*ctx
, int firn
, int Tn
)
190 gen_op_load_FT0_fir(firn
);
193 gen_op_load_FT1_fir(firn
);
196 gen_op_load_FT2_fir(firn
);
201 static always_inline
void gen_store_fir (DisasContext
*ctx
, int firn
, int Tn
)
205 gen_op_store_FT0_fir(firn
);
208 gen_op_store_FT1_fir(firn
);
211 gen_op_store_FT2_fir(firn
);
217 #if defined(CONFIG_USER_ONLY)
218 #define OP_LD_TABLE(width) \
219 static GenOpFunc *gen_op_ld##width[] = { \
220 &gen_op_ld##width##_raw, \
222 #define OP_ST_TABLE(width) \
223 static GenOpFunc *gen_op_st##width[] = { \
224 &gen_op_st##width##_raw, \
227 #define OP_LD_TABLE(width) \
228 static GenOpFunc *gen_op_ld##width[] = { \
229 &gen_op_ld##width##_kernel, \
230 &gen_op_ld##width##_executive, \
231 &gen_op_ld##width##_supervisor, \
232 &gen_op_ld##width##_user, \
234 #define OP_ST_TABLE(width) \
235 static GenOpFunc *gen_op_st##width[] = { \
236 &gen_op_st##width##_kernel, \
237 &gen_op_st##width##_executive, \
238 &gen_op_st##width##_supervisor, \
239 &gen_op_st##width##_user, \
243 #define GEN_LD(width) \
244 OP_LD_TABLE(width); \
245 static always_inline void gen_ld##width (DisasContext *ctx) \
247 (*gen_op_ld##width[ctx->mem_idx])(); \
250 #define GEN_ST(width) \
251 OP_ST_TABLE(width); \
252 static always_inline void gen_st##width (DisasContext *ctx) \
254 (*gen_op_st##width[ctx->mem_idx])(); \
272 #if 0 /* currently unused */
283 #if defined(__i386__) || defined(__x86_64__)
284 static always_inline
void gen_op_set_s16_T0 (int16_t imm
)
286 gen_op_set_s32_T0((int32_t)imm
);
289 static always_inline
void gen_op_set_s16_T1 (int16_t imm
)
291 gen_op_set_s32_T1((int32_t)imm
);
294 static always_inline
void gen_op_set_u16_T0 (uint16_t imm
)
296 gen_op_set_s32_T0((uint32_t)imm
);
299 static always_inline
void gen_op_set_u16_T1 (uint16_t imm
)
301 gen_op_set_s32_T1((uint32_t)imm
);
305 static always_inline
void gen_set_sT0 (DisasContext
*ctx
, int64_t imm
)
317 gen_op_set_s16_T0(imm16
);
320 gen_op_set_s32_T0(imm32
);
323 #if 0 // Qemu does not know how to do this...
324 gen_op_set_64_T0(imm
);
326 gen_op_set_64_T0(imm
>> 32, imm
);
331 static always_inline
void gen_set_sT1 (DisasContext
*ctx
, int64_t imm
)
343 gen_op_set_s16_T1(imm16
);
346 gen_op_set_s32_T1(imm32
);
349 #if 0 // Qemu does not know how to do this...
350 gen_op_set_64_T1(imm
);
352 gen_op_set_64_T1(imm
>> 32, imm
);
357 static always_inline
void gen_set_uT0 (DisasContext
*ctx
, uint64_t imm
)
364 gen_op_set_u16_T0(imm
);
366 gen_op_set_u32_T0(imm
);
369 #if 0 // Qemu does not know how to do this...
370 gen_op_set_64_T0(imm
);
372 gen_op_set_64_T0(imm
>> 32, imm
);
377 static always_inline
void gen_set_uT1 (DisasContext
*ctx
, uint64_t imm
)
384 gen_op_set_u16_T1(imm
);
386 gen_op_set_u32_T1(imm
);
389 #if 0 // Qemu does not know how to do this...
390 gen_op_set_64_T1(imm
);
392 gen_op_set_64_T1(imm
>> 32, imm
);
397 static always_inline
void _gen_op_bcond (DisasContext
*ctx
)
399 #if 0 // Qemu does not know how to do this...
400 gen_op_bcond(ctx
->pc
);
402 gen_op_bcond(ctx
->pc
>> 32, ctx
->pc
);
406 static always_inline
void gen_excp (DisasContext
*ctx
,
407 int exception
, int error_code
)
409 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
);
410 gen_op_excp(exception
, error_code
);
413 static always_inline
void gen_invalid (DisasContext
*ctx
)
415 gen_excp(ctx
, EXCP_OPCDEC
, 0);
418 static always_inline
void gen_load_mem (DisasContext
*ctx
,
419 void (*gen_load_op
)(DisasContext
*ctx
),
420 int ra
, int rb
, int32_t disp16
,
423 if (ra
== 31 && disp16
== 0) {
427 gen_load_ir(ctx
, rb
, 0);
429 gen_set_sT1(ctx
, disp16
);
435 gen_store_ir(ctx
, ra
, 1);
439 static always_inline
void gen_store_mem (DisasContext
*ctx
,
440 void (*gen_store_op
)(DisasContext
*ctx
),
441 int ra
, int rb
, int32_t disp16
,
444 gen_load_ir(ctx
, rb
, 0);
446 gen_set_sT1(ctx
, disp16
);
451 gen_load_ir(ctx
, ra
, 1);
452 (*gen_store_op
)(ctx
);
455 static always_inline
void gen_load_fmem (DisasContext
*ctx
,
456 void (*gen_load_fop
)(DisasContext
*ctx
),
457 int ra
, int rb
, int32_t disp16
)
459 gen_load_ir(ctx
, rb
, 0);
461 gen_set_sT1(ctx
, disp16
);
464 (*gen_load_fop
)(ctx
);
465 gen_store_fir(ctx
, ra
, 1);
468 static always_inline
void gen_store_fmem (DisasContext
*ctx
,
469 void (*gen_store_fop
)(DisasContext
*ctx
),
470 int ra
, int rb
, int32_t disp16
)
472 gen_load_ir(ctx
, rb
, 0);
474 gen_set_sT1(ctx
, disp16
);
477 gen_load_fir(ctx
, ra
, 1);
478 (*gen_store_fop
)(ctx
);
481 static always_inline
void gen_bcond (DisasContext
*ctx
,
482 void (*gen_test_op
)(void),
483 int ra
, int32_t disp16
)
486 gen_set_uT0(ctx
, ctx
->pc
);
487 gen_set_sT1(ctx
, disp16
<< 2);
490 gen_set_uT1(ctx
, ctx
->pc
);
492 gen_load_ir(ctx
, ra
, 0);
497 static always_inline
void gen_fbcond (DisasContext
*ctx
,
498 void (*gen_test_op
)(void),
499 int ra
, int32_t disp16
)
502 gen_set_uT0(ctx
, ctx
->pc
);
503 gen_set_sT1(ctx
, disp16
<< 2);
506 gen_set_uT1(ctx
, ctx
->pc
);
508 gen_load_fir(ctx
, ra
, 0);
513 static always_inline
void gen_arith2 (DisasContext
*ctx
,
514 void (*gen_arith_op
)(void),
515 int rb
, int rc
, int islit
, int8_t lit
)
518 gen_set_sT0(ctx
, lit
);
520 gen_load_ir(ctx
, rb
, 0);
522 gen_store_ir(ctx
, rc
, 0);
525 static always_inline
void gen_arith3 (DisasContext
*ctx
,
526 void (*gen_arith_op
)(void),
527 int ra
, int rb
, int rc
,
528 int islit
, int8_t lit
)
530 gen_load_ir(ctx
, ra
, 0);
532 gen_set_sT1(ctx
, lit
);
534 gen_load_ir(ctx
, rb
, 1);
536 gen_store_ir(ctx
, rc
, 0);
539 static always_inline
void gen_cmov (DisasContext
*ctx
,
540 void (*gen_test_op
)(void),
541 int ra
, int rb
, int rc
,
542 int islit
, int8_t lit
)
544 gen_load_ir(ctx
, ra
, 1);
546 gen_set_sT0(ctx
, lit
);
548 gen_load_ir(ctx
, rb
, 0);
553 static always_inline
void gen_farith2 (DisasContext
*ctx
,
554 void (*gen_arith_fop
)(void),
557 gen_load_fir(ctx
, rb
, 0);
559 gen_store_fir(ctx
, rc
, 0);
562 static always_inline
void gen_farith3 (DisasContext
*ctx
,
563 void (*gen_arith_fop
)(void),
564 int ra
, int rb
, int rc
)
566 gen_load_fir(ctx
, ra
, 0);
567 gen_load_fir(ctx
, rb
, 1);
569 gen_store_fir(ctx
, rc
, 0);
572 static always_inline
void gen_fcmov (DisasContext
*ctx
,
573 void (*gen_test_fop
)(void),
574 int ra
, int rb
, int rc
)
576 gen_load_fir(ctx
, ra
, 0);
577 gen_load_fir(ctx
, rb
, 1);
582 static always_inline
void gen_fti (DisasContext
*ctx
,
583 void (*gen_move_fop
)(void),
586 gen_load_fir(ctx
, rc
, 0);
588 gen_store_ir(ctx
, ra
, 0);
591 static always_inline
void gen_itf (DisasContext
*ctx
,
592 void (*gen_move_fop
)(void),
595 gen_load_ir(ctx
, ra
, 0);
597 gen_store_fir(ctx
, rc
, 0);
600 static always_inline
void gen_s4addl (void)
606 static always_inline
void gen_s4subl (void)
612 static always_inline
void gen_s8addl (void)
618 static always_inline
void gen_s8subl (void)
624 static always_inline
void gen_s4addq (void)
630 static always_inline
void gen_s4subq (void)
636 static always_inline
void gen_s8addq (void)
642 static always_inline
void gen_s8subq (void)
648 static always_inline
void gen_amask (void)
654 static always_inline
int translate_one (DisasContext
*ctx
, uint32_t insn
)
657 int32_t disp21
, disp16
, disp12
;
659 uint8_t opc
, ra
, rb
, rc
, sbz
, fpfn
, fn7
, fn2
, islit
;
663 /* Decode all instruction fields */
665 ra
= (insn
>> 21) & 0x1F;
666 rb
= (insn
>> 16) & 0x1F;
668 sbz
= (insn
>> 13) & 0x07;
669 islit
= (insn
>> 12) & 1;
670 lit
= (insn
>> 13) & 0xFF;
671 palcode
= insn
& 0x03FFFFFF;
672 disp21
= ((int32_t)((insn
& 0x001FFFFF) << 11)) >> 11;
673 disp16
= (int16_t)(insn
& 0x0000FFFF);
674 disp12
= (int32_t)((insn
& 0x00000FFF) << 20) >> 20;
675 fn16
= insn
& 0x0000FFFF;
676 fn11
= (insn
>> 5) & 0x000007FF;
678 fn7
= (insn
>> 5) & 0x0000007F;
679 fn2
= (insn
>> 5) & 0x00000003;
681 #if defined ALPHA_DEBUG_DISAS
682 if (logfile
!= NULL
) {
683 fprintf(logfile
, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
684 opc
, ra
, rb
, rc
, disp16
);
690 if (palcode
>= 0x80 && palcode
< 0xC0) {
691 /* Unprivileged PAL call */
692 gen_excp(ctx
, EXCP_CALL_PAL
+ ((palcode
& 0x1F) << 6), 0);
693 #if !defined (CONFIG_USER_ONLY)
694 } else if (palcode
< 0x40) {
695 /* Privileged PAL code */
696 if (ctx
->mem_idx
& 1)
699 gen_excp(ctx
, EXCP_CALL_PALP
+ ((palcode
& 0x1F) << 6), 0);
702 /* Invalid PAL call */
731 TCGv v
= tcg_const_i64(disp16
);
733 tcg_gen_add_i64(v
, cpu_ir
[rb
], v
);
741 TCGv v
= tcg_const_i64(disp16
<< 16);
743 tcg_gen_add_i64(v
, cpu_ir
[rb
], v
);
750 if (!(ctx
->amask
& AMASK_BWX
))
752 gen_load_mem(ctx
, &gen_ldbu
, ra
, rb
, disp16
, 0);
756 gen_load_mem(ctx
, &gen_ldq_u
, ra
, rb
, disp16
, 1);
760 if (!(ctx
->amask
& AMASK_BWX
))
762 gen_load_mem(ctx
, &gen_ldwu
, ra
, rb
, disp16
, 0);
766 if (!(ctx
->amask
& AMASK_BWX
))
768 gen_store_mem(ctx
, &gen_stw
, ra
, rb
, disp16
, 0);
772 if (!(ctx
->amask
& AMASK_BWX
))
774 gen_store_mem(ctx
, &gen_stb
, ra
, rb
, disp16
, 0);
778 gen_store_mem(ctx
, &gen_stq_u
, ra
, rb
, disp16
, 1);
784 gen_arith3(ctx
, &gen_op_addl
, ra
, rb
, rc
, islit
, lit
);
788 gen_arith3(ctx
, &gen_s4addl
, ra
, rb
, rc
, islit
, lit
);
792 gen_arith3(ctx
, &gen_op_subl
, ra
, rb
, rc
, islit
, lit
);
796 gen_arith3(ctx
, &gen_s4subl
, ra
, rb
, rc
, islit
, lit
);
800 gen_arith3(ctx
, &gen_op_cmpbge
, ra
, rb
, rc
, islit
, lit
);
804 gen_arith3(ctx
, &gen_s8addl
, ra
, rb
, rc
, islit
, lit
);
808 gen_arith3(ctx
, &gen_s8subl
, ra
, rb
, rc
, islit
, lit
);
812 gen_arith3(ctx
, &gen_op_cmpult
, ra
, rb
, rc
, islit
, lit
);
816 gen_arith3(ctx
, &gen_op_addq
, ra
, rb
, rc
, islit
, lit
);
820 gen_arith3(ctx
, &gen_s4addq
, ra
, rb
, rc
, islit
, lit
);
824 gen_arith3(ctx
, &gen_op_subq
, ra
, rb
, rc
, islit
, lit
);
828 gen_arith3(ctx
, &gen_s4subq
, ra
, rb
, rc
, islit
, lit
);
832 gen_arith3(ctx
, &gen_op_cmpeq
, ra
, rb
, rc
, islit
, lit
);
836 gen_arith3(ctx
, &gen_s8addq
, ra
, rb
, rc
, islit
, lit
);
840 gen_arith3(ctx
, &gen_s8subq
, ra
, rb
, rc
, islit
, lit
);
844 gen_arith3(ctx
, &gen_op_cmpule
, ra
, rb
, rc
, islit
, lit
);
848 gen_arith3(ctx
, &gen_op_addlv
, ra
, rb
, rc
, islit
, lit
);
852 gen_arith3(ctx
, &gen_op_sublv
, ra
, rb
, rc
, islit
, lit
);
856 gen_arith3(ctx
, &gen_op_cmplt
, ra
, rb
, rc
, islit
, lit
);
860 gen_arith3(ctx
, &gen_op_addqv
, ra
, rb
, rc
, islit
, lit
);
864 gen_arith3(ctx
, &gen_op_subqv
, ra
, rb
, rc
, islit
, lit
);
868 gen_arith3(ctx
, &gen_op_cmple
, ra
, rb
, rc
, islit
, lit
);
878 gen_arith3(ctx
, &gen_op_and
, ra
, rb
, rc
, islit
, lit
);
882 gen_arith3(ctx
, &gen_op_bic
, ra
, rb
, rc
, islit
, lit
);
886 gen_cmov(ctx
, &gen_op_cmplbs
, ra
, rb
, rc
, islit
, lit
);
890 gen_cmov(ctx
, &gen_op_cmplbc
, ra
, rb
, rc
, islit
, lit
);
894 if (ra
== rb
|| ra
== 31 || rb
== 31) {
895 if (ra
== 31 && rc
== 31) {
900 gen_load_ir(ctx
, rb
, 0);
901 gen_store_ir(ctx
, rc
, 0);
904 gen_arith3(ctx
, &gen_op_bis
, ra
, rb
, rc
, islit
, lit
);
909 gen_cmov(ctx
, &gen_op_cmpeqz
, ra
, rb
, rc
, islit
, lit
);
913 gen_cmov(ctx
, &gen_op_cmpnez
, ra
, rb
, rc
, islit
, lit
);
917 gen_arith3(ctx
, &gen_op_ornot
, ra
, rb
, rc
, islit
, lit
);
921 gen_arith3(ctx
, &gen_op_xor
, ra
, rb
, rc
, islit
, lit
);
925 gen_cmov(ctx
, &gen_op_cmpltz
, ra
, rb
, rc
, islit
, lit
);
929 gen_cmov(ctx
, &gen_op_cmpgez
, ra
, rb
, rc
, islit
, lit
);
933 gen_arith3(ctx
, &gen_op_eqv
, ra
, rb
, rc
, islit
, lit
);
937 gen_arith2(ctx
, &gen_amask
, rb
, rc
, islit
, lit
);
941 gen_cmov(ctx
, &gen_op_cmplez
, ra
, rb
, rc
, islit
, lit
);
945 gen_cmov(ctx
, &gen_op_cmpgtz
, ra
, rb
, rc
, islit
, lit
);
949 gen_op_load_implver();
950 gen_store_ir(ctx
, rc
, 0);
960 gen_arith3(ctx
, &gen_op_mskbl
, ra
, rb
, rc
, islit
, lit
);
964 gen_arith3(ctx
, &gen_op_extbl
, ra
, rb
, rc
, islit
, lit
);
968 gen_arith3(ctx
, &gen_op_insbl
, ra
, rb
, rc
, islit
, lit
);
972 gen_arith3(ctx
, &gen_op_mskwl
, ra
, rb
, rc
, islit
, lit
);
976 gen_arith3(ctx
, &gen_op_extwl
, ra
, rb
, rc
, islit
, lit
);
980 gen_arith3(ctx
, &gen_op_inswl
, ra
, rb
, rc
, islit
, lit
);
984 gen_arith3(ctx
, &gen_op_mskll
, ra
, rb
, rc
, islit
, lit
);
988 gen_arith3(ctx
, &gen_op_extll
, ra
, rb
, rc
, islit
, lit
);
992 gen_arith3(ctx
, &gen_op_insll
, ra
, rb
, rc
, islit
, lit
);
996 gen_arith3(ctx
, &gen_op_zap
, ra
, rb
, rc
, islit
, lit
);
1000 gen_arith3(ctx
, &gen_op_zapnot
, ra
, rb
, rc
, islit
, lit
);
1004 gen_arith3(ctx
, &gen_op_mskql
, ra
, rb
, rc
, islit
, lit
);
1008 gen_arith3(ctx
, &gen_op_srl
, ra
, rb
, rc
, islit
, lit
);
1012 gen_arith3(ctx
, &gen_op_extql
, ra
, rb
, rc
, islit
, lit
);
1016 gen_arith3(ctx
, &gen_op_sll
, ra
, rb
, rc
, islit
, lit
);
1020 gen_arith3(ctx
, &gen_op_insql
, ra
, rb
, rc
, islit
, lit
);
1024 gen_arith3(ctx
, &gen_op_sra
, ra
, rb
, rc
, islit
, lit
);
1028 gen_arith3(ctx
, &gen_op_mskwh
, ra
, rb
, rc
, islit
, lit
);
1032 gen_arith3(ctx
, &gen_op_inswh
, ra
, rb
, rc
, islit
, lit
);
1036 gen_arith3(ctx
, &gen_op_extwh
, ra
, rb
, rc
, islit
, lit
);
1040 gen_arith3(ctx
, &gen_op_msklh
, ra
, rb
, rc
, islit
, lit
);
1044 gen_arith3(ctx
, &gen_op_inslh
, ra
, rb
, rc
, islit
, lit
);
1048 gen_arith3(ctx
, &gen_op_extlh
, ra
, rb
, rc
, islit
, lit
);
1052 gen_arith3(ctx
, &gen_op_mskqh
, ra
, rb
, rc
, islit
, lit
);
1056 gen_arith3(ctx
, &gen_op_insqh
, ra
, rb
, rc
, islit
, lit
);
1060 gen_arith3(ctx
, &gen_op_extqh
, ra
, rb
, rc
, islit
, lit
);
1070 gen_arith3(ctx
, &gen_op_mull
, ra
, rb
, rc
, islit
, lit
);
1074 gen_arith3(ctx
, &gen_op_mulq
, ra
, rb
, rc
, islit
, lit
);
1078 gen_arith3(ctx
, &gen_op_umulh
, ra
, rb
, rc
, islit
, lit
);
1082 gen_arith3(ctx
, &gen_op_mullv
, ra
, rb
, rc
, islit
, lit
);
1086 gen_arith3(ctx
, &gen_op_mulqv
, ra
, rb
, rc
, islit
, lit
);
1093 switch (fpfn
) { /* f11 & 0x3F */
1096 if (!(ctx
->amask
& AMASK_FIX
))
1098 gen_itf(ctx
, &gen_op_itofs
, ra
, rc
);
1102 if (!(ctx
->amask
& AMASK_FIX
))
1104 gen_farith2(ctx
, &gen_op_sqrtf
, rb
, rc
);
1108 if (!(ctx
->amask
& AMASK_FIX
))
1110 gen_farith2(ctx
, &gen_op_sqrts
, rb
, rc
);
1114 if (!(ctx
->amask
& AMASK_FIX
))
1117 gen_itf(ctx
, &gen_op_itoff
, ra
, rc
);
1124 if (!(ctx
->amask
& AMASK_FIX
))
1126 gen_itf(ctx
, &gen_op_itoft
, ra
, rc
);
1130 if (!(ctx
->amask
& AMASK_FIX
))
1132 gen_farith2(ctx
, &gen_op_sqrtg
, rb
, rc
);
1136 if (!(ctx
->amask
& AMASK_FIX
))
1138 gen_farith2(ctx
, &gen_op_sqrtt
, rb
, rc
);
1145 /* VAX floating point */
1146 /* XXX: rounding mode and trap are ignored (!) */
1147 switch (fpfn
) { /* f11 & 0x3F */
1150 gen_farith3(ctx
, &gen_op_addf
, ra
, rb
, rc
);
1154 gen_farith3(ctx
, &gen_op_subf
, ra
, rb
, rc
);
1158 gen_farith3(ctx
, &gen_op_mulf
, ra
, rb
, rc
);
1162 gen_farith3(ctx
, &gen_op_divf
, ra
, rb
, rc
);
1167 gen_farith2(ctx
, &gen_op_cvtdg
, rb
, rc
);
1174 gen_farith3(ctx
, &gen_op_addg
, ra
, rb
, rc
);
1178 gen_farith3(ctx
, &gen_op_subg
, ra
, rb
, rc
);
1182 gen_farith3(ctx
, &gen_op_mulg
, ra
, rb
, rc
);
1186 gen_farith3(ctx
, &gen_op_divg
, ra
, rb
, rc
);
1190 gen_farith3(ctx
, &gen_op_cmpgeq
, ra
, rb
, rc
);
1194 gen_farith3(ctx
, &gen_op_cmpglt
, ra
, rb
, rc
);
1198 gen_farith3(ctx
, &gen_op_cmpgle
, ra
, rb
, rc
);
1202 gen_farith2(ctx
, &gen_op_cvtgf
, rb
, rc
);
1207 gen_farith2(ctx
, &gen_op_cvtgd
, rb
, rc
);
1214 gen_farith2(ctx
, &gen_op_cvtgq
, rb
, rc
);
1218 gen_farith2(ctx
, &gen_op_cvtqf
, rb
, rc
);
1222 gen_farith2(ctx
, &gen_op_cvtqg
, rb
, rc
);
1229 /* IEEE floating-point */
1230 /* XXX: rounding mode and traps are ignored (!) */
1231 switch (fpfn
) { /* f11 & 0x3F */
1234 gen_farith3(ctx
, &gen_op_adds
, ra
, rb
, rc
);
1238 gen_farith3(ctx
, &gen_op_subs
, ra
, rb
, rc
);
1242 gen_farith3(ctx
, &gen_op_muls
, ra
, rb
, rc
);
1246 gen_farith3(ctx
, &gen_op_divs
, ra
, rb
, rc
);
1250 gen_farith3(ctx
, &gen_op_addt
, ra
, rb
, rc
);
1254 gen_farith3(ctx
, &gen_op_subt
, ra
, rb
, rc
);
1258 gen_farith3(ctx
, &gen_op_mult
, ra
, rb
, rc
);
1262 gen_farith3(ctx
, &gen_op_divt
, ra
, rb
, rc
);
1266 gen_farith3(ctx
, &gen_op_cmptun
, ra
, rb
, rc
);
1270 gen_farith3(ctx
, &gen_op_cmpteq
, ra
, rb
, rc
);
1274 gen_farith3(ctx
, &gen_op_cmptlt
, ra
, rb
, rc
);
1278 gen_farith3(ctx
, &gen_op_cmptle
, ra
, rb
, rc
);
1281 /* XXX: incorrect */
1282 if (fn11
== 0x2AC) {
1284 gen_farith2(ctx
, &gen_op_cvtst
, rb
, rc
);
1287 gen_farith2(ctx
, &gen_op_cvtts
, rb
, rc
);
1292 gen_farith2(ctx
, &gen_op_cvttq
, rb
, rc
);
1296 gen_farith2(ctx
, &gen_op_cvtqs
, rb
, rc
);
1300 gen_farith2(ctx
, &gen_op_cvtqt
, rb
, rc
);
1310 gen_farith2(ctx
, &gen_op_cvtlq
, rb
, rc
);
1315 if (ra
== 31 && rc
== 31) {
1320 gen_load_fir(ctx
, rb
, 0);
1321 gen_store_fir(ctx
, rc
, 0);
1324 gen_farith3(ctx
, &gen_op_cpys
, ra
, rb
, rc
);
1329 gen_farith2(ctx
, &gen_op_cpysn
, rb
, rc
);
1333 gen_farith2(ctx
, &gen_op_cpyse
, rb
, rc
);
1337 gen_load_fir(ctx
, ra
, 0);
1338 gen_op_store_fpcr();
1343 gen_store_fir(ctx
, ra
, 0);
1347 gen_fcmov(ctx
, &gen_op_cmpfeq
, ra
, rb
, rc
);
1351 gen_fcmov(ctx
, &gen_op_cmpfne
, ra
, rb
, rc
);
1355 gen_fcmov(ctx
, &gen_op_cmpflt
, ra
, rb
, rc
);
1359 gen_fcmov(ctx
, &gen_op_cmpfge
, ra
, rb
, rc
);
1363 gen_fcmov(ctx
, &gen_op_cmpfle
, ra
, rb
, rc
);
1367 gen_fcmov(ctx
, &gen_op_cmpfgt
, ra
, rb
, rc
);
1371 gen_farith2(ctx
, &gen_op_cvtql
, rb
, rc
);
1375 gen_farith2(ctx
, &gen_op_cvtqlv
, rb
, rc
);
1379 gen_farith2(ctx
, &gen_op_cvtqlsv
, rb
, rc
);
1386 switch ((uint16_t)disp16
) {
1389 /* No-op. Just exit from the current tb */
1394 /* No-op. Just exit from the current tb */
1416 gen_store_ir(ctx
, ra
, 0);
1421 gen_store_ir(ctx
, ra
, 0);
1426 /* XXX: TODO: evict tb cache at address rb */
1436 gen_store_ir(ctx
, ra
, 0);
1448 /* HW_MFPR (PALcode) */
1449 #if defined (CONFIG_USER_ONLY)
1454 gen_op_mfpr(insn
& 0xFF);
1455 gen_store_ir(ctx
, ra
, 0);
1459 gen_load_ir(ctx
, rb
, 0);
1461 gen_set_uT1(ctx
, ctx
->pc
);
1462 gen_store_ir(ctx
, ra
, 1);
1465 /* Those four jumps only differ by the branch prediction hint */
1483 /* HW_LD (PALcode) */
1484 #if defined (CONFIG_USER_ONLY)
1489 gen_load_ir(ctx
, rb
, 0);
1490 gen_set_sT1(ctx
, disp12
);
1492 switch ((insn
>> 12) & 0xF) {
1494 /* Longword physical access */
1498 /* Quadword physical access */
1502 /* Longword physical access with lock */
1506 /* Quadword physical access with lock */
1510 /* Longword virtual PTE fetch */
1511 gen_op_ldl_kernel();
1514 /* Quadword virtual PTE fetch */
1515 gen_op_ldq_kernel();
1524 /* Longword virtual access */
1525 gen_op_ld_phys_to_virt();
1529 /* Quadword virtual access */
1530 gen_op_ld_phys_to_virt();
1534 /* Longword virtual access with protection check */
1538 /* Quadword virtual access with protection check */
1542 /* Longword virtual access with altenate access mode */
1543 gen_op_set_alt_mode();
1544 gen_op_ld_phys_to_virt();
1546 gen_op_restore_mode();
1549 /* Quadword virtual access with altenate access mode */
1550 gen_op_set_alt_mode();
1551 gen_op_ld_phys_to_virt();
1553 gen_op_restore_mode();
1556 /* Longword virtual access with alternate access mode and
1559 gen_op_set_alt_mode();
1561 gen_op_restore_mode();
1564 /* Quadword virtual access with alternate access mode and
1567 gen_op_set_alt_mode();
1569 gen_op_restore_mode();
1572 gen_store_ir(ctx
, ra
, 1);
1579 if (!(ctx
->amask
& AMASK_BWX
))
1581 gen_arith2(ctx
, &gen_op_sextb
, rb
, rc
, islit
, lit
);
1585 if (!(ctx
->amask
& AMASK_BWX
))
1587 gen_arith2(ctx
, &gen_op_sextw
, rb
, rc
, islit
, lit
);
1591 if (!(ctx
->amask
& AMASK_CIX
))
1593 gen_arith2(ctx
, &gen_op_ctpop
, rb
, rc
, 0, 0);
1597 if (!(ctx
->amask
& AMASK_MVI
))
1604 if (!(ctx
->amask
& AMASK_CIX
))
1606 gen_arith2(ctx
, &gen_op_ctlz
, rb
, rc
, 0, 0);
1610 if (!(ctx
->amask
& AMASK_CIX
))
1612 gen_arith2(ctx
, &gen_op_cttz
, rb
, rc
, 0, 0);
1616 if (!(ctx
->amask
& AMASK_MVI
))
1623 if (!(ctx
->amask
& AMASK_MVI
))
1630 if (!(ctx
->amask
& AMASK_MVI
))
1637 if (!(ctx
->amask
& AMASK_MVI
))
1644 if (!(ctx
->amask
& AMASK_MVI
))
1651 if (!(ctx
->amask
& AMASK_MVI
))
1658 if (!(ctx
->amask
& AMASK_MVI
))
1665 if (!(ctx
->amask
& AMASK_MVI
))
1672 if (!(ctx
->amask
& AMASK_MVI
))
1679 if (!(ctx
->amask
& AMASK_MVI
))
1686 if (!(ctx
->amask
& AMASK_MVI
))
1693 if (!(ctx
->amask
& AMASK_MVI
))
1700 if (!(ctx
->amask
& AMASK_FIX
))
1702 gen_fti(ctx
, &gen_op_ftoit
, ra
, rb
);
1706 if (!(ctx
->amask
& AMASK_FIX
))
1708 gen_fti(ctx
, &gen_op_ftois
, ra
, rb
);
1715 /* HW_MTPR (PALcode) */
1716 #if defined (CONFIG_USER_ONLY)
1721 gen_load_ir(ctx
, ra
, 0);
1722 gen_op_mtpr(insn
& 0xFF);
1727 /* HW_REI (PALcode) */
1728 #if defined (CONFIG_USER_ONLY)
1737 gen_load_ir(ctx
, rb
, 0);
1738 gen_set_uT1(ctx
, (((int64_t)insn
<< 51) >> 51));
1746 /* HW_ST (PALcode) */
1747 #if defined (CONFIG_USER_ONLY)
1752 gen_load_ir(ctx
, rb
, 0);
1753 gen_set_sT1(ctx
, disp12
);
1755 gen_load_ir(ctx
, ra
, 1);
1756 switch ((insn
>> 12) & 0xF) {
1758 /* Longword physical access */
1762 /* Quadword physical access */
1766 /* Longword physical access with lock */
1770 /* Quadword physical access with lock */
1774 /* Longword virtual access */
1775 gen_op_st_phys_to_virt();
1779 /* Quadword virtual access */
1780 gen_op_st_phys_to_virt();
1802 /* Longword virtual access with alternate access mode */
1803 gen_op_set_alt_mode();
1804 gen_op_st_phys_to_virt();
1806 gen_op_restore_mode();
1809 /* Quadword virtual access with alternate access mode */
1810 gen_op_set_alt_mode();
1811 gen_op_st_phys_to_virt();
1813 gen_op_restore_mode();
1828 gen_load_fmem(ctx
, &gen_ldf
, ra
, rb
, disp16
);
1836 gen_load_fmem(ctx
, &gen_ldg
, ra
, rb
, disp16
);
1843 gen_load_fmem(ctx
, &gen_lds
, ra
, rb
, disp16
);
1847 gen_load_fmem(ctx
, &gen_ldt
, ra
, rb
, disp16
);
1852 gen_store_fmem(ctx
, &gen_stf
, ra
, rb
, disp16
);
1860 gen_store_fmem(ctx
, &gen_stg
, ra
, rb
, disp16
);
1867 gen_store_fmem(ctx
, &gen_sts
, ra
, rb
, disp16
);
1871 gen_store_fmem(ctx
, &gen_stt
, ra
, rb
, disp16
);
1875 gen_load_mem(ctx
, &gen_ldl
, ra
, rb
, disp16
, 0);
1879 gen_load_mem(ctx
, &gen_ldq
, ra
, rb
, disp16
, 0);
1883 gen_load_mem(ctx
, &gen_ldl_l
, ra
, rb
, disp16
, 0);
1887 gen_load_mem(ctx
, &gen_ldq_l
, ra
, rb
, disp16
, 0);
1891 gen_store_mem(ctx
, &gen_stl
, ra
, rb
, disp16
, 0);
1895 gen_store_mem(ctx
, &gen_stq
, ra
, rb
, disp16
, 0);
1899 gen_store_mem(ctx
, &gen_stl_c
, ra
, rb
, disp16
, 0);
1903 gen_store_mem(ctx
, &gen_stq_c
, ra
, rb
, disp16
, 0);
1908 TCGv t
= tcg_const_i64(ctx
->pc
);
1912 tcg_gen_movi_i64(cpu_pc
, ctx
->pc
+ (disp21
<< 2));
1917 gen_fbcond(ctx
, &gen_op_cmpfeq
, ra
, disp16
);
1922 gen_fbcond(ctx
, &gen_op_cmpflt
, ra
, disp16
);
1927 gen_fbcond(ctx
, &gen_op_cmpfle
, ra
, disp16
);
1932 gen_set_uT0(ctx
, ctx
->pc
);
1933 gen_store_ir(ctx
, ra
, 0);
1935 gen_set_sT1(ctx
, disp21
<< 2);
1943 gen_fbcond(ctx
, &gen_op_cmpfne
, ra
, disp16
);
1948 gen_fbcond(ctx
, &gen_op_cmpfge
, ra
, disp16
);
1953 gen_fbcond(ctx
, &gen_op_cmpfgt
, ra
, disp16
);
1958 gen_bcond(ctx
, &gen_op_cmplbc
, ra
, disp16
);
1963 gen_bcond(ctx
, &gen_op_cmpeqz
, ra
, disp16
);
1968 gen_bcond(ctx
, &gen_op_cmpltz
, ra
, disp16
);
1973 gen_bcond(ctx
, &gen_op_cmplez
, ra
, disp16
);
1978 gen_bcond(ctx
, &gen_op_cmplbs
, ra
, disp16
);
1983 gen_bcond(ctx
, &gen_op_cmpnez
, ra
, disp16
);
1988 gen_bcond(ctx
, &gen_op_cmpgez
, ra
, disp16
);
1993 gen_bcond(ctx
, &gen_op_cmpgtz
, ra
, disp16
);
2005 static always_inline
void gen_intermediate_code_internal (CPUState
*env
,
2006 TranslationBlock
*tb
,
2009 #if defined ALPHA_DEBUG_DISAS
2010 static int insn_count
;
2012 DisasContext ctx
, *ctxp
= &ctx
;
2013 target_ulong pc_start
;
2015 uint16_t *gen_opc_end
;
2022 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
2024 ctx
.amask
= env
->amask
;
2025 #if defined (CONFIG_USER_ONLY)
2028 ctx
.mem_idx
= ((env
->ps
>> 3) & 3);
2029 ctx
.pal_mode
= env
->ipr
[IPR_EXC_ADDR
] & 1;
2032 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
2034 max_insns
= CF_COUNT_MASK
;
2037 for (ret
= 0; ret
== 0;) {
2038 if (env
->nb_breakpoints
> 0) {
2039 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
2040 if (env
->breakpoints
[j
] == ctx
.pc
) {
2041 gen_excp(&ctx
, EXCP_DEBUG
, 0);
2047 j
= gen_opc_ptr
- gen_opc_buf
;
2051 gen_opc_instr_start
[lj
++] = 0;
2052 gen_opc_pc
[lj
] = ctx
.pc
;
2053 gen_opc_instr_start
[lj
] = 1;
2054 gen_opc_icount
[lj
] = num_insns
;
2057 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
2059 #if defined ALPHA_DEBUG_DISAS
2061 if (logfile
!= NULL
) {
2062 fprintf(logfile
, "pc " TARGET_FMT_lx
" mem_idx %d\n",
2063 ctx
.pc
, ctx
.mem_idx
);
2066 insn
= ldl_code(ctx
.pc
);
2067 #if defined ALPHA_DEBUG_DISAS
2069 if (logfile
!= NULL
) {
2070 fprintf(logfile
, "opcode %08x %d\n", insn
, insn_count
);
2075 ret
= translate_one(ctxp
, insn
);
2078 /* if we reach a page boundary or are single stepping, stop
2081 if (((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0) ||
2082 (env
->singlestep_enabled
) ||
2083 num_insns
>= max_insns
) {
2086 #if defined (DO_SINGLE_STEP)
2090 if (ret
!= 1 && ret
!= 3) {
2091 tcg_gen_movi_i64(cpu_pc
, ctx
.pc
);
2093 #if defined (DO_TB_FLUSH)
2094 tcg_gen_helper_0_0(helper_tb_flush
);
2096 if (tb
->cflags
& CF_LAST_IO
)
2098 /* Generate the return instruction */
2100 gen_icount_end(tb
, num_insns
);
2101 *gen_opc_ptr
= INDEX_op_end
;
2103 j
= gen_opc_ptr
- gen_opc_buf
;
2106 gen_opc_instr_start
[lj
++] = 0;
2108 tb
->size
= ctx
.pc
- pc_start
;
2109 tb
->icount
= num_insns
;
2111 #if defined ALPHA_DEBUG_DISAS
2112 if (loglevel
& CPU_LOG_TB_CPU
) {
2113 cpu_dump_state(env
, logfile
, fprintf
, 0);
2115 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
2116 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
2117 target_disas(logfile
, pc_start
, ctx
.pc
- pc_start
, 1);
2118 fprintf(logfile
, "\n");
2123 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
2125 gen_intermediate_code_internal(env
, tb
, 0);
2128 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
2130 gen_intermediate_code_internal(env
, tb
, 1);
2133 CPUAlphaState
* cpu_alpha_init (const char *cpu_model
)
2138 env
= qemu_mallocz(sizeof(CPUAlphaState
));
2142 alpha_translate_init();
2144 /* XXX: should not be hardcoded */
2145 env
->implver
= IMPLVER_2106x
;
2147 #if defined (CONFIG_USER_ONLY)
2151 /* Initialize IPR */
2152 hwpcb
= env
->ipr
[IPR_PCBB
];
2153 env
->ipr
[IPR_ASN
] = 0;
2154 env
->ipr
[IPR_ASTEN
] = 0;
2155 env
->ipr
[IPR_ASTSR
] = 0;
2156 env
->ipr
[IPR_DATFX
] = 0;
2158 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2159 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2160 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2161 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2162 env
->ipr
[IPR_FEN
] = 0;
2163 env
->ipr
[IPR_IPL
] = 31;
2164 env
->ipr
[IPR_MCES
] = 0;
2165 env
->ipr
[IPR_PERFMON
] = 0; /* Implementation specific */
2166 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2167 env
->ipr
[IPR_SISR
] = 0;
2168 env
->ipr
[IPR_VIRBND
] = -1ULL;
2173 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
2174 unsigned long searched_pc
, int pc_pos
, void *puc
)
2176 env
->pc
= gen_opc_pc
[pc_pos
];