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target-alpha: Implement cvtql inline.
[qemu.git] / target-alpha / translate.c
1 /*
2 * Alpha emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <stdint.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23
24 #include "cpu.h"
25 #include "exec-all.h"
26 #include "disas.h"
27 #include "host-utils.h"
28 #include "tcg-op.h"
29 #include "qemu-common.h"
30
31 #include "helper.h"
32 #define GEN_HELPER 1
33 #include "helper.h"
34
35 #undef ALPHA_DEBUG_DISAS
36 #define CONFIG_SOFTFLOAT_INLINE
37
38 #ifdef ALPHA_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43
44 typedef struct DisasContext DisasContext;
45 struct DisasContext {
46 uint64_t pc;
47 int mem_idx;
48 #if !defined (CONFIG_USER_ONLY)
49 int pal_mode;
50 #endif
51 CPUAlphaState *env;
52 uint32_t amask;
53
54 /* Current rounding mode for this TB. */
55 int tb_rm;
56 /* Current flush-to-zero setting for this TB. */
57 int tb_ftz;
58 };
59
60 /* global register indexes */
61 static TCGv_ptr cpu_env;
62 static TCGv cpu_ir[31];
63 static TCGv cpu_fir[31];
64 static TCGv cpu_pc;
65 static TCGv cpu_lock;
66 #ifdef CONFIG_USER_ONLY
67 static TCGv cpu_uniq;
68 #endif
69
70 /* register names */
71 static char cpu_reg_names[10*4+21*5 + 10*5+21*6];
72
73 #include "gen-icount.h"
74
75 static void alpha_translate_init(void)
76 {
77 int i;
78 char *p;
79 static int done_init = 0;
80
81 if (done_init)
82 return;
83
84 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
85
86 p = cpu_reg_names;
87 for (i = 0; i < 31; i++) {
88 sprintf(p, "ir%d", i);
89 cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0,
90 offsetof(CPUState, ir[i]), p);
91 p += (i < 10) ? 4 : 5;
92
93 sprintf(p, "fir%d", i);
94 cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0,
95 offsetof(CPUState, fir[i]), p);
96 p += (i < 10) ? 5 : 6;
97 }
98
99 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,
100 offsetof(CPUState, pc), "pc");
101
102 cpu_lock = tcg_global_mem_new_i64(TCG_AREG0,
103 offsetof(CPUState, lock), "lock");
104
105 #ifdef CONFIG_USER_ONLY
106 cpu_uniq = tcg_global_mem_new_i64(TCG_AREG0,
107 offsetof(CPUState, unique), "uniq");
108 #endif
109
110 /* register helpers */
111 #define GEN_HELPER 2
112 #include "helper.h"
113
114 done_init = 1;
115 }
116
117 static inline void gen_excp(DisasContext *ctx, int exception, int error_code)
118 {
119 TCGv_i32 tmp1, tmp2;
120
121 tcg_gen_movi_i64(cpu_pc, ctx->pc);
122 tmp1 = tcg_const_i32(exception);
123 tmp2 = tcg_const_i32(error_code);
124 gen_helper_excp(tmp1, tmp2);
125 tcg_temp_free_i32(tmp2);
126 tcg_temp_free_i32(tmp1);
127 }
128
129 static inline void gen_invalid(DisasContext *ctx)
130 {
131 gen_excp(ctx, EXCP_OPCDEC, 0);
132 }
133
134 static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
135 {
136 TCGv tmp = tcg_temp_new();
137 TCGv_i32 tmp32 = tcg_temp_new_i32();
138 tcg_gen_qemu_ld32u(tmp, t1, flags);
139 tcg_gen_trunc_i64_i32(tmp32, tmp);
140 gen_helper_memory_to_f(t0, tmp32);
141 tcg_temp_free_i32(tmp32);
142 tcg_temp_free(tmp);
143 }
144
145 static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
146 {
147 TCGv tmp = tcg_temp_new();
148 tcg_gen_qemu_ld64(tmp, t1, flags);
149 gen_helper_memory_to_g(t0, tmp);
150 tcg_temp_free(tmp);
151 }
152
153 static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
154 {
155 TCGv tmp = tcg_temp_new();
156 TCGv_i32 tmp32 = tcg_temp_new_i32();
157 tcg_gen_qemu_ld32u(tmp, t1, flags);
158 tcg_gen_trunc_i64_i32(tmp32, tmp);
159 gen_helper_memory_to_s(t0, tmp32);
160 tcg_temp_free_i32(tmp32);
161 tcg_temp_free(tmp);
162 }
163
164 static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
165 {
166 tcg_gen_mov_i64(cpu_lock, t1);
167 tcg_gen_qemu_ld32s(t0, t1, flags);
168 }
169
170 static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
171 {
172 tcg_gen_mov_i64(cpu_lock, t1);
173 tcg_gen_qemu_ld64(t0, t1, flags);
174 }
175
176 static inline void gen_load_mem(DisasContext *ctx,
177 void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
178 int flags),
179 int ra, int rb, int32_t disp16, int fp,
180 int clear)
181 {
182 TCGv addr;
183
184 if (unlikely(ra == 31))
185 return;
186
187 addr = tcg_temp_new();
188 if (rb != 31) {
189 tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
190 if (clear)
191 tcg_gen_andi_i64(addr, addr, ~0x7);
192 } else {
193 if (clear)
194 disp16 &= ~0x7;
195 tcg_gen_movi_i64(addr, disp16);
196 }
197 if (fp)
198 tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx);
199 else
200 tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx);
201 tcg_temp_free(addr);
202 }
203
204 static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
205 {
206 TCGv_i32 tmp32 = tcg_temp_new_i32();
207 TCGv tmp = tcg_temp_new();
208 gen_helper_f_to_memory(tmp32, t0);
209 tcg_gen_extu_i32_i64(tmp, tmp32);
210 tcg_gen_qemu_st32(tmp, t1, flags);
211 tcg_temp_free(tmp);
212 tcg_temp_free_i32(tmp32);
213 }
214
215 static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
216 {
217 TCGv tmp = tcg_temp_new();
218 gen_helper_g_to_memory(tmp, t0);
219 tcg_gen_qemu_st64(tmp, t1, flags);
220 tcg_temp_free(tmp);
221 }
222
223 static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
224 {
225 TCGv_i32 tmp32 = tcg_temp_new_i32();
226 TCGv tmp = tcg_temp_new();
227 gen_helper_s_to_memory(tmp32, t0);
228 tcg_gen_extu_i32_i64(tmp, tmp32);
229 tcg_gen_qemu_st32(tmp, t1, flags);
230 tcg_temp_free(tmp);
231 tcg_temp_free_i32(tmp32);
232 }
233
234 static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags)
235 {
236 int l1, l2;
237
238 l1 = gen_new_label();
239 l2 = gen_new_label();
240 tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);
241 tcg_gen_qemu_st32(t0, t1, flags);
242 tcg_gen_movi_i64(t0, 1);
243 tcg_gen_br(l2);
244 gen_set_label(l1);
245 tcg_gen_movi_i64(t0, 0);
246 gen_set_label(l2);
247 tcg_gen_movi_i64(cpu_lock, -1);
248 }
249
250 static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags)
251 {
252 int l1, l2;
253
254 l1 = gen_new_label();
255 l2 = gen_new_label();
256 tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1);
257 tcg_gen_qemu_st64(t0, t1, flags);
258 tcg_gen_movi_i64(t0, 1);
259 tcg_gen_br(l2);
260 gen_set_label(l1);
261 tcg_gen_movi_i64(t0, 0);
262 gen_set_label(l2);
263 tcg_gen_movi_i64(cpu_lock, -1);
264 }
265
266 static inline void gen_store_mem(DisasContext *ctx,
267 void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
268 int flags),
269 int ra, int rb, int32_t disp16, int fp,
270 int clear, int local)
271 {
272 TCGv addr;
273 if (local)
274 addr = tcg_temp_local_new();
275 else
276 addr = tcg_temp_new();
277 if (rb != 31) {
278 tcg_gen_addi_i64(addr, cpu_ir[rb], disp16);
279 if (clear)
280 tcg_gen_andi_i64(addr, addr, ~0x7);
281 } else {
282 if (clear)
283 disp16 &= ~0x7;
284 tcg_gen_movi_i64(addr, disp16);
285 }
286 if (ra != 31) {
287 if (fp)
288 tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx);
289 else
290 tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx);
291 } else {
292 TCGv zero;
293 if (local)
294 zero = tcg_const_local_i64(0);
295 else
296 zero = tcg_const_i64(0);
297 tcg_gen_qemu_store(zero, addr, ctx->mem_idx);
298 tcg_temp_free(zero);
299 }
300 tcg_temp_free(addr);
301 }
302
303 static void gen_bcond_pcload(DisasContext *ctx, int32_t disp, int lab_true)
304 {
305 int lab_over = gen_new_label();
306
307 tcg_gen_movi_i64(cpu_pc, ctx->pc);
308 tcg_gen_br(lab_over);
309 gen_set_label(lab_true);
310 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
311 gen_set_label(lab_over);
312 }
313
314 static void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
315 int32_t disp, int mask)
316 {
317 int lab_true = gen_new_label();
318
319 if (likely(ra != 31)) {
320 if (mask) {
321 TCGv tmp = tcg_temp_new();
322 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
323 tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);
324 tcg_temp_free(tmp);
325 } else {
326 tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, lab_true);
327 }
328 } else {
329 /* Very uncommon case - Do not bother to optimize. */
330 TCGv tmp = tcg_const_i64(0);
331 tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);
332 tcg_temp_free(tmp);
333 }
334 gen_bcond_pcload(ctx, disp, lab_true);
335 }
336
337 /* Generate a forward TCG branch to LAB_TRUE if RA cmp 0.0.
338 This is complicated by the fact that -0.0 compares the same as +0.0. */
339
340 static void gen_fbcond_internal(TCGCond cond, TCGv src, int lab_true)
341 {
342 int lab_false = -1;
343 uint64_t mzero = 1ull << 63;
344 TCGv tmp;
345
346 switch (cond) {
347 case TCG_COND_LE:
348 case TCG_COND_GT:
349 /* For <= or >, the -0.0 value directly compares the way we want. */
350 tcg_gen_brcondi_i64(cond, src, 0, lab_true);
351 break;
352
353 case TCG_COND_EQ:
354 case TCG_COND_NE:
355 /* For == or !=, we can simply mask off the sign bit and compare. */
356 /* ??? Assume that the temporary is reclaimed at the branch. */
357 tmp = tcg_temp_new();
358 tcg_gen_andi_i64(tmp, src, mzero - 1);
359 tcg_gen_brcondi_i64(cond, tmp, 0, lab_true);
360 break;
361
362 case TCG_COND_GE:
363 /* For >=, emit two branches to the destination. */
364 tcg_gen_brcondi_i64(cond, src, 0, lab_true);
365 tcg_gen_brcondi_i64(TCG_COND_EQ, src, mzero, lab_true);
366 break;
367
368 case TCG_COND_LT:
369 /* For <, first filter out -0.0 to what will be the fallthru. */
370 lab_false = gen_new_label();
371 tcg_gen_brcondi_i64(TCG_COND_EQ, src, mzero, lab_false);
372 tcg_gen_brcondi_i64(cond, src, 0, lab_true);
373 gen_set_label(lab_false);
374 break;
375
376 default:
377 abort();
378 }
379 }
380
381 static void gen_fbcond(DisasContext *ctx, TCGCond cond, int ra, int32_t disp)
382 {
383 int lab_true;
384
385 if (unlikely(ra == 31)) {
386 /* Very uncommon case, but easier to optimize it to an integer
387 comparison than continuing with the floating point comparison. */
388 gen_bcond(ctx, cond, ra, disp, 0);
389 return;
390 }
391
392 lab_true = gen_new_label();
393 gen_fbcond_internal(cond, cpu_fir[ra], lab_true);
394 gen_bcond_pcload(ctx, disp, lab_true);
395 }
396
397 static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc,
398 int islit, uint8_t lit, int mask)
399 {
400 int l1;
401
402 if (unlikely(rc == 31))
403 return;
404
405 l1 = gen_new_label();
406
407 if (ra != 31) {
408 if (mask) {
409 TCGv tmp = tcg_temp_new();
410 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
411 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
412 tcg_temp_free(tmp);
413 } else
414 tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
415 } else {
416 /* Very uncommon case - Do not bother to optimize. */
417 TCGv tmp = tcg_const_i64(0);
418 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
419 tcg_temp_free(tmp);
420 }
421
422 if (islit)
423 tcg_gen_movi_i64(cpu_ir[rc], lit);
424 else
425 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
426 gen_set_label(l1);
427 }
428
429 static void gen_fcmov(TCGCond inv_cond, int ra, int rb, int rc)
430 {
431 TCGv va = cpu_fir[ra];
432 int l1;
433
434 if (unlikely(rc == 31))
435 return;
436 if (unlikely(ra == 31)) {
437 /* ??? Assume that the temporary is reclaimed at the branch. */
438 va = tcg_const_i64(0);
439 }
440
441 l1 = gen_new_label();
442 gen_fbcond_internal(inv_cond, va, l1);
443
444 if (rb != 31)
445 tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[rb]);
446 else
447 tcg_gen_movi_i64(cpu_fir[rc], 0);
448 gen_set_label(l1);
449 }
450
451 #define QUAL_RM_N 0x080 /* Round mode nearest even */
452 #define QUAL_RM_C 0x000 /* Round mode chopped */
453 #define QUAL_RM_M 0x040 /* Round mode minus infinity */
454 #define QUAL_RM_D 0x0c0 /* Round mode dynamic */
455 #define QUAL_RM_MASK 0x0c0
456
457 #define QUAL_U 0x100 /* Underflow enable (fp output) */
458 #define QUAL_V 0x100 /* Overflow enable (int output) */
459 #define QUAL_S 0x400 /* Software completion enable */
460 #define QUAL_I 0x200 /* Inexact detection enable */
461
462 static void gen_qual_roundmode(DisasContext *ctx, int fn11)
463 {
464 TCGv_i32 tmp;
465
466 fn11 &= QUAL_RM_MASK;
467 if (fn11 == ctx->tb_rm) {
468 return;
469 }
470 ctx->tb_rm = fn11;
471
472 tmp = tcg_temp_new_i32();
473 switch (fn11) {
474 case QUAL_RM_N:
475 tcg_gen_movi_i32(tmp, float_round_nearest_even);
476 break;
477 case QUAL_RM_C:
478 tcg_gen_movi_i32(tmp, float_round_to_zero);
479 break;
480 case QUAL_RM_M:
481 tcg_gen_movi_i32(tmp, float_round_down);
482 break;
483 case QUAL_RM_D:
484 tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_dyn_round));
485 break;
486 }
487
488 #if defined(CONFIG_SOFTFLOAT_INLINE)
489 /* ??? The "softfloat.h" interface is to call set_float_rounding_mode.
490 With CONFIG_SOFTFLOAT that expands to an out-of-line call that just
491 sets the one field. */
492 tcg_gen_st8_i32(tmp, cpu_env,
493 offsetof(CPUState, fp_status.float_rounding_mode));
494 #else
495 gen_helper_setroundmode(tmp);
496 #endif
497
498 tcg_temp_free_i32(tmp);
499 }
500
501 static void gen_qual_flushzero(DisasContext *ctx, int fn11)
502 {
503 TCGv_i32 tmp;
504
505 fn11 &= QUAL_U;
506 if (fn11 == ctx->tb_ftz) {
507 return;
508 }
509 ctx->tb_ftz = fn11;
510
511 tmp = tcg_temp_new_i32();
512 if (fn11) {
513 /* Underflow is enabled, use the FPCR setting. */
514 tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_flush_to_zero));
515 } else {
516 /* Underflow is disabled, force flush-to-zero. */
517 tcg_gen_movi_i32(tmp, 1);
518 }
519
520 #if defined(CONFIG_SOFTFLOAT_INLINE)
521 tcg_gen_st8_i32(tmp, cpu_env,
522 offsetof(CPUState, fp_status.flush_to_zero));
523 #else
524 gen_helper_setflushzero(tmp);
525 #endif
526
527 tcg_temp_free_i32(tmp);
528 }
529
530 static TCGv gen_ieee_input(int reg, int fn11, int is_cmp)
531 {
532 TCGv val = tcg_temp_new();
533 if (reg == 31) {
534 tcg_gen_movi_i64(val, 0);
535 } else if (fn11 & QUAL_S) {
536 gen_helper_ieee_input_s(val, cpu_fir[reg]);
537 } else if (is_cmp) {
538 gen_helper_ieee_input_cmp(val, cpu_fir[reg]);
539 } else {
540 gen_helper_ieee_input(val, cpu_fir[reg]);
541 }
542 return val;
543 }
544
545 static void gen_fp_exc_clear(void)
546 {
547 #if defined(CONFIG_SOFTFLOAT_INLINE)
548 TCGv_i32 zero = tcg_const_i32(0);
549 tcg_gen_st8_i32(zero, cpu_env,
550 offsetof(CPUState, fp_status.float_exception_flags));
551 tcg_temp_free_i32(zero);
552 #else
553 gen_helper_fp_exc_clear();
554 #endif
555 }
556
557 static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore)
558 {
559 /* ??? We ought to be able to do something with imprecise exceptions.
560 E.g. notice we're still in the trap shadow of something within the
561 TB and do not generate the code to signal the exception; end the TB
562 when an exception is forced to arrive, either by consumption of a
563 register value or TRAPB or EXCB. */
564 TCGv_i32 exc = tcg_temp_new_i32();
565 TCGv_i32 reg;
566
567 #if defined(CONFIG_SOFTFLOAT_INLINE)
568 tcg_gen_ld8u_i32(exc, cpu_env,
569 offsetof(CPUState, fp_status.float_exception_flags));
570 #else
571 gen_helper_fp_exc_get(exc);
572 #endif
573
574 if (ignore) {
575 tcg_gen_andi_i32(exc, exc, ~ignore);
576 }
577
578 /* ??? Pass in the regno of the destination so that the helper can
579 set EXC_MASK, which contains a bitmask of destination registers
580 that have caused arithmetic traps. A simple userspace emulation
581 does not require this. We do need it for a guest kernel's entArith,
582 or if we were to do something clever with imprecise exceptions. */
583 reg = tcg_const_i32(rc + 32);
584
585 if (fn11 & QUAL_S) {
586 gen_helper_fp_exc_raise_s(exc, reg);
587 } else {
588 gen_helper_fp_exc_raise(exc, reg);
589 }
590
591 tcg_temp_free_i32(reg);
592 tcg_temp_free_i32(exc);
593 }
594
595 static inline void gen_fp_exc_raise(int rc, int fn11)
596 {
597 gen_fp_exc_raise_ignore(rc, fn11, fn11 & QUAL_I ? 0 : float_flag_inexact);
598 }
599
600 static void gen_fcvtql(int rb, int rc)
601 {
602 if (unlikely(rc == 31)) {
603 return;
604 }
605 if (unlikely(rb == 31)) {
606 tcg_gen_movi_i64(cpu_fir[rc], 0);
607 } else {
608 TCGv tmp = tcg_temp_new();
609
610 tcg_gen_andi_i64(tmp, cpu_fir[rb], 0xC0000000);
611 tcg_gen_andi_i64(cpu_fir[rc], cpu_fir[rb], 0x3FFFFFFF);
612 tcg_gen_shli_i64(tmp, tmp, 32);
613 tcg_gen_shli_i64(cpu_fir[rc], cpu_fir[rc], 29);
614 tcg_gen_or_i64(cpu_fir[rc], cpu_fir[rc], tmp);
615
616 tcg_temp_free(tmp);
617 }
618 }
619
620 static void gen_fcvtql_v(DisasContext *ctx, int rb, int rc)
621 {
622 if (rb != 31) {
623 int lab = gen_new_label();
624 TCGv tmp = tcg_temp_new();
625
626 tcg_gen_ext32s_i64(tmp, cpu_fir[rb]);
627 tcg_gen_brcond_i64(TCG_COND_EQ, tmp, cpu_fir[rb], lab);
628 gen_excp(ctx, EXCP_ARITH, EXC_M_IOV);
629
630 gen_set_label(lab);
631 }
632 gen_fcvtql(rb, rc);
633 }
634
635 #define FARITH2(name) \
636 static inline void glue(gen_f, name)(int rb, int rc) \
637 { \
638 if (unlikely(rc == 31)) { \
639 return; \
640 } \
641 if (rb != 31) { \
642 gen_helper_ ## name (cpu_fir[rc], cpu_fir[rb]); \
643 } else { \
644 TCGv tmp = tcg_const_i64(0); \
645 gen_helper_ ## name (cpu_fir[rc], tmp); \
646 tcg_temp_free(tmp); \
647 } \
648 }
649 FARITH2(cvtlq)
650
651 /* ??? VAX instruction qualifiers ignored. */
652 FARITH2(sqrtf)
653 FARITH2(sqrtg)
654 FARITH2(cvtgf)
655 FARITH2(cvtgq)
656 FARITH2(cvtqf)
657 FARITH2(cvtqg)
658
659 static void gen_ieee_arith2(DisasContext *ctx, void (*helper)(TCGv, TCGv),
660 int rb, int rc, int fn11)
661 {
662 TCGv vb;
663
664 /* ??? This is wrong: the instruction is not a nop, it still may
665 raise exceptions. */
666 if (unlikely(rc == 31)) {
667 return;
668 }
669
670 gen_qual_roundmode(ctx, fn11);
671 gen_qual_flushzero(ctx, fn11);
672 gen_fp_exc_clear();
673
674 vb = gen_ieee_input(rb, fn11, 0);
675 helper(cpu_fir[rc], vb);
676 tcg_temp_free(vb);
677
678 gen_fp_exc_raise(rc, fn11);
679 }
680
681 #define IEEE_ARITH2(name) \
682 static inline void glue(gen_f, name)(DisasContext *ctx, \
683 int rb, int rc, int fn11) \
684 { \
685 gen_ieee_arith2(ctx, gen_helper_##name, rb, rc, fn11); \
686 }
687 IEEE_ARITH2(sqrts)
688 IEEE_ARITH2(sqrtt)
689 IEEE_ARITH2(cvtst)
690 IEEE_ARITH2(cvtts)
691
692 static void gen_fcvttq(DisasContext *ctx, int rb, int rc, int fn11)
693 {
694 TCGv vb;
695 int ignore = 0;
696
697 /* ??? This is wrong: the instruction is not a nop, it still may
698 raise exceptions. */
699 if (unlikely(rc == 31)) {
700 return;
701 }
702
703 /* No need to set flushzero, since we have an integer output. */
704 gen_fp_exc_clear();
705 vb = gen_ieee_input(rb, fn11, 0);
706
707 /* Almost all integer conversions use cropped rounding, and most
708 also do not have integer overflow enabled. Special case that. */
709 switch (fn11) {
710 case QUAL_RM_C:
711 gen_helper_cvttq_c(cpu_fir[rc], vb);
712 break;
713 case QUAL_V | QUAL_RM_C:
714 case QUAL_S | QUAL_V | QUAL_RM_C:
715 ignore = float_flag_inexact;
716 /* FALLTHRU */
717 case QUAL_S | QUAL_V | QUAL_I | QUAL_RM_C:
718 gen_helper_cvttq_svic(cpu_fir[rc], vb);
719 break;
720 default:
721 gen_qual_roundmode(ctx, fn11);
722 gen_helper_cvttq(cpu_fir[rc], vb);
723 ignore |= (fn11 & QUAL_V ? 0 : float_flag_overflow);
724 ignore |= (fn11 & QUAL_I ? 0 : float_flag_inexact);
725 break;
726 }
727 tcg_temp_free(vb);
728
729 gen_fp_exc_raise_ignore(rc, fn11, ignore);
730 }
731
732 static void gen_ieee_intcvt(DisasContext *ctx, void (*helper)(TCGv, TCGv),
733 int rb, int rc, int fn11)
734 {
735 TCGv vb;
736
737 /* ??? This is wrong: the instruction is not a nop, it still may
738 raise exceptions. */
739 if (unlikely(rc == 31)) {
740 return;
741 }
742
743 gen_qual_roundmode(ctx, fn11);
744
745 if (rb == 31) {
746 vb = tcg_const_i64(0);
747 } else {
748 vb = cpu_fir[rb];
749 }
750
751 /* The only exception that can be raised by integer conversion
752 is inexact. Thus we only need to worry about exceptions when
753 inexact handling is requested. */
754 if (fn11 & QUAL_I) {
755 gen_fp_exc_clear();
756 helper(cpu_fir[rc], vb);
757 gen_fp_exc_raise(rc, fn11);
758 } else {
759 helper(cpu_fir[rc], vb);
760 }
761
762 if (rb == 31) {
763 tcg_temp_free(vb);
764 }
765 }
766
767 #define IEEE_INTCVT(name) \
768 static inline void glue(gen_f, name)(DisasContext *ctx, \
769 int rb, int rc, int fn11) \
770 { \
771 gen_ieee_intcvt(ctx, gen_helper_##name, rb, rc, fn11); \
772 }
773 IEEE_INTCVT(cvtqs)
774 IEEE_INTCVT(cvtqt)
775
776 #define FARITH3(name) \
777 static inline void glue(gen_f, name)(int ra, int rb, int rc) \
778 { \
779 TCGv va, vb; \
780 \
781 if (unlikely(rc == 31)) { \
782 return; \
783 } \
784 if (ra == 31) { \
785 va = tcg_const_i64(0); \
786 } else { \
787 va = cpu_fir[ra]; \
788 } \
789 if (rb == 31) { \
790 vb = tcg_const_i64(0); \
791 } else { \
792 vb = cpu_fir[rb]; \
793 } \
794 \
795 gen_helper_ ## name (cpu_fir[rc], va, vb); \
796 \
797 if (ra == 31) { \
798 tcg_temp_free(va); \
799 } \
800 if (rb == 31) { \
801 tcg_temp_free(vb); \
802 } \
803 }
804 /* ??? Ought to expand these inline; simple masking operations. */
805 FARITH3(cpys)
806 FARITH3(cpysn)
807 FARITH3(cpyse)
808
809 /* ??? VAX instruction qualifiers ignored. */
810 FARITH3(addf)
811 FARITH3(subf)
812 FARITH3(mulf)
813 FARITH3(divf)
814 FARITH3(addg)
815 FARITH3(subg)
816 FARITH3(mulg)
817 FARITH3(divg)
818 FARITH3(cmpgeq)
819 FARITH3(cmpglt)
820 FARITH3(cmpgle)
821
822 static void gen_ieee_arith3(DisasContext *ctx,
823 void (*helper)(TCGv, TCGv, TCGv),
824 int ra, int rb, int rc, int fn11)
825 {
826 TCGv va, vb;
827
828 /* ??? This is wrong: the instruction is not a nop, it still may
829 raise exceptions. */
830 if (unlikely(rc == 31)) {
831 return;
832 }
833
834 gen_qual_roundmode(ctx, fn11);
835 gen_qual_flushzero(ctx, fn11);
836 gen_fp_exc_clear();
837
838 va = gen_ieee_input(ra, fn11, 0);
839 vb = gen_ieee_input(rb, fn11, 0);
840 helper(cpu_fir[rc], va, vb);
841 tcg_temp_free(va);
842 tcg_temp_free(vb);
843
844 gen_fp_exc_raise(rc, fn11);
845 }
846
847 #define IEEE_ARITH3(name) \
848 static inline void glue(gen_f, name)(DisasContext *ctx, \
849 int ra, int rb, int rc, int fn11) \
850 { \
851 gen_ieee_arith3(ctx, gen_helper_##name, ra, rb, rc, fn11); \
852 }
853 IEEE_ARITH3(adds)
854 IEEE_ARITH3(subs)
855 IEEE_ARITH3(muls)
856 IEEE_ARITH3(divs)
857 IEEE_ARITH3(addt)
858 IEEE_ARITH3(subt)
859 IEEE_ARITH3(mult)
860 IEEE_ARITH3(divt)
861
862 static void gen_ieee_compare(DisasContext *ctx,
863 void (*helper)(TCGv, TCGv, TCGv),
864 int ra, int rb, int rc, int fn11)
865 {
866 TCGv va, vb;
867
868 /* ??? This is wrong: the instruction is not a nop, it still may
869 raise exceptions. */
870 if (unlikely(rc == 31)) {
871 return;
872 }
873
874 gen_fp_exc_clear();
875
876 va = gen_ieee_input(ra, fn11, 1);
877 vb = gen_ieee_input(rb, fn11, 1);
878 helper(cpu_fir[rc], va, vb);
879 tcg_temp_free(va);
880 tcg_temp_free(vb);
881
882 gen_fp_exc_raise(rc, fn11);
883 }
884
885 #define IEEE_CMP3(name) \
886 static inline void glue(gen_f, name)(DisasContext *ctx, \
887 int ra, int rb, int rc, int fn11) \
888 { \
889 gen_ieee_compare(ctx, gen_helper_##name, ra, rb, rc, fn11); \
890 }
891 IEEE_CMP3(cmptun)
892 IEEE_CMP3(cmpteq)
893 IEEE_CMP3(cmptlt)
894 IEEE_CMP3(cmptle)
895
896 static inline uint64_t zapnot_mask(uint8_t lit)
897 {
898 uint64_t mask = 0;
899 int i;
900
901 for (i = 0; i < 8; ++i) {
902 if ((lit >> i) & 1)
903 mask |= 0xffull << (i * 8);
904 }
905 return mask;
906 }
907
908 /* Implement zapnot with an immediate operand, which expands to some
909 form of immediate AND. This is a basic building block in the
910 definition of many of the other byte manipulation instructions. */
911 static void gen_zapnoti(TCGv dest, TCGv src, uint8_t lit)
912 {
913 switch (lit) {
914 case 0x00:
915 tcg_gen_movi_i64(dest, 0);
916 break;
917 case 0x01:
918 tcg_gen_ext8u_i64(dest, src);
919 break;
920 case 0x03:
921 tcg_gen_ext16u_i64(dest, src);
922 break;
923 case 0x0f:
924 tcg_gen_ext32u_i64(dest, src);
925 break;
926 case 0xff:
927 tcg_gen_mov_i64(dest, src);
928 break;
929 default:
930 tcg_gen_andi_i64 (dest, src, zapnot_mask (lit));
931 break;
932 }
933 }
934
935 static inline void gen_zapnot(int ra, int rb, int rc, int islit, uint8_t lit)
936 {
937 if (unlikely(rc == 31))
938 return;
939 else if (unlikely(ra == 31))
940 tcg_gen_movi_i64(cpu_ir[rc], 0);
941 else if (islit)
942 gen_zapnoti(cpu_ir[rc], cpu_ir[ra], lit);
943 else
944 gen_helper_zapnot (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
945 }
946
947 static inline void gen_zap(int ra, int rb, int rc, int islit, uint8_t lit)
948 {
949 if (unlikely(rc == 31))
950 return;
951 else if (unlikely(ra == 31))
952 tcg_gen_movi_i64(cpu_ir[rc], 0);
953 else if (islit)
954 gen_zapnoti(cpu_ir[rc], cpu_ir[ra], ~lit);
955 else
956 gen_helper_zap (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
957 }
958
959
960 /* EXTWH, EXTLH, EXTQH */
961 static void gen_ext_h(int ra, int rb, int rc, int islit,
962 uint8_t lit, uint8_t byte_mask)
963 {
964 if (unlikely(rc == 31))
965 return;
966 else if (unlikely(ra == 31))
967 tcg_gen_movi_i64(cpu_ir[rc], 0);
968 else {
969 if (islit) {
970 lit = (64 - (lit & 7) * 8) & 0x3f;
971 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit);
972 } else {
973 TCGv tmp1 = tcg_temp_new();
974 tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
975 tcg_gen_shli_i64(tmp1, tmp1, 3);
976 tcg_gen_neg_i64(tmp1, tmp1);
977 tcg_gen_andi_i64(tmp1, tmp1, 0x3f);
978 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
979 tcg_temp_free(tmp1);
980 }
981 gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask);
982 }
983 }
984
985 /* EXTBL, EXTWL, EXTLL, EXTQL */
986 static void gen_ext_l(int ra, int rb, int rc, int islit,
987 uint8_t lit, uint8_t byte_mask)
988 {
989 if (unlikely(rc == 31))
990 return;
991 else if (unlikely(ra == 31))
992 tcg_gen_movi_i64(cpu_ir[rc], 0);
993 else {
994 if (islit) {
995 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);
996 } else {
997 TCGv tmp = tcg_temp_new();
998 tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
999 tcg_gen_shli_i64(tmp, tmp, 3);
1000 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1001 tcg_temp_free(tmp);
1002 }
1003 gen_zapnoti(cpu_ir[rc], cpu_ir[rc], byte_mask);
1004 }
1005 }
1006
1007 /* INSWH, INSLH, INSQH */
1008 static void gen_ins_h(int ra, int rb, int rc, int islit,
1009 uint8_t lit, uint8_t byte_mask)
1010 {
1011 if (unlikely(rc == 31))
1012 return;
1013 else if (unlikely(ra == 31) || (islit && (lit & 7) == 0))
1014 tcg_gen_movi_i64(cpu_ir[rc], 0);
1015 else {
1016 TCGv tmp = tcg_temp_new();
1017
1018 /* The instruction description has us left-shift the byte mask
1019 and extract bits <15:8> and apply that zap at the end. This
1020 is equivalent to simply performing the zap first and shifting
1021 afterward. */
1022 gen_zapnoti (tmp, cpu_ir[ra], byte_mask);
1023
1024 if (islit) {
1025 /* Note that we have handled the lit==0 case above. */
1026 tcg_gen_shri_i64 (cpu_ir[rc], tmp, 64 - (lit & 7) * 8);
1027 } else {
1028 TCGv shift = tcg_temp_new();
1029
1030 /* If (B & 7) == 0, we need to shift by 64 and leave a zero.
1031 Do this portably by splitting the shift into two parts:
1032 shift_count-1 and 1. Arrange for the -1 by using
1033 ones-complement instead of twos-complement in the negation:
1034 ~((B & 7) * 8) & 63. */
1035
1036 tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
1037 tcg_gen_shli_i64(shift, shift, 3);
1038 tcg_gen_not_i64(shift, shift);
1039 tcg_gen_andi_i64(shift, shift, 0x3f);
1040
1041 tcg_gen_shr_i64(cpu_ir[rc], tmp, shift);
1042 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[rc], 1);
1043 tcg_temp_free(shift);
1044 }
1045 tcg_temp_free(tmp);
1046 }
1047 }
1048
1049 /* INSBL, INSWL, INSLL, INSQL */
1050 static void gen_ins_l(int ra, int rb, int rc, int islit,
1051 uint8_t lit, uint8_t byte_mask)
1052 {
1053 if (unlikely(rc == 31))
1054 return;
1055 else if (unlikely(ra == 31))
1056 tcg_gen_movi_i64(cpu_ir[rc], 0);
1057 else {
1058 TCGv tmp = tcg_temp_new();
1059
1060 /* The instruction description has us left-shift the byte mask
1061 the same number of byte slots as the data and apply the zap
1062 at the end. This is equivalent to simply performing the zap
1063 first and shifting afterward. */
1064 gen_zapnoti (tmp, cpu_ir[ra], byte_mask);
1065
1066 if (islit) {
1067 tcg_gen_shli_i64(cpu_ir[rc], tmp, (lit & 7) * 8);
1068 } else {
1069 TCGv shift = tcg_temp_new();
1070 tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
1071 tcg_gen_shli_i64(shift, shift, 3);
1072 tcg_gen_shl_i64(cpu_ir[rc], tmp, shift);
1073 tcg_temp_free(shift);
1074 }
1075 tcg_temp_free(tmp);
1076 }
1077 }
1078
1079 /* MSKWH, MSKLH, MSKQH */
1080 static void gen_msk_h(int ra, int rb, int rc, int islit,
1081 uint8_t lit, uint8_t byte_mask)
1082 {
1083 if (unlikely(rc == 31))
1084 return;
1085 else if (unlikely(ra == 31))
1086 tcg_gen_movi_i64(cpu_ir[rc], 0);
1087 else if (islit) {
1088 gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~((byte_mask << (lit & 7)) >> 8));
1089 } else {
1090 TCGv shift = tcg_temp_new();
1091 TCGv mask = tcg_temp_new();
1092
1093 /* The instruction description is as above, where the byte_mask
1094 is shifted left, and then we extract bits <15:8>. This can be
1095 emulated with a right-shift on the expanded byte mask. This
1096 requires extra care because for an input <2:0> == 0 we need a
1097 shift of 64 bits in order to generate a zero. This is done by
1098 splitting the shift into two parts, the variable shift - 1
1099 followed by a constant 1 shift. The code we expand below is
1100 equivalent to ~((B & 7) * 8) & 63. */
1101
1102 tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
1103 tcg_gen_shli_i64(shift, shift, 3);
1104 tcg_gen_not_i64(shift, shift);
1105 tcg_gen_andi_i64(shift, shift, 0x3f);
1106 tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));
1107 tcg_gen_shr_i64(mask, mask, shift);
1108 tcg_gen_shri_i64(mask, mask, 1);
1109
1110 tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);
1111
1112 tcg_temp_free(mask);
1113 tcg_temp_free(shift);
1114 }
1115 }
1116
1117 /* MSKBL, MSKWL, MSKLL, MSKQL */
1118 static void gen_msk_l(int ra, int rb, int rc, int islit,
1119 uint8_t lit, uint8_t byte_mask)
1120 {
1121 if (unlikely(rc == 31))
1122 return;
1123 else if (unlikely(ra == 31))
1124 tcg_gen_movi_i64(cpu_ir[rc], 0);
1125 else if (islit) {
1126 gen_zapnoti (cpu_ir[rc], cpu_ir[ra], ~(byte_mask << (lit & 7)));
1127 } else {
1128 TCGv shift = tcg_temp_new();
1129 TCGv mask = tcg_temp_new();
1130
1131 tcg_gen_andi_i64(shift, cpu_ir[rb], 7);
1132 tcg_gen_shli_i64(shift, shift, 3);
1133 tcg_gen_movi_i64(mask, zapnot_mask (byte_mask));
1134 tcg_gen_shl_i64(mask, mask, shift);
1135
1136 tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], mask);
1137
1138 tcg_temp_free(mask);
1139 tcg_temp_free(shift);
1140 }
1141 }
1142
1143 /* Code to call arith3 helpers */
1144 #define ARITH3(name) \
1145 static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
1146 uint8_t lit) \
1147 { \
1148 if (unlikely(rc == 31)) \
1149 return; \
1150 \
1151 if (ra != 31) { \
1152 if (islit) { \
1153 TCGv tmp = tcg_const_i64(lit); \
1154 gen_helper_ ## name(cpu_ir[rc], cpu_ir[ra], tmp); \
1155 tcg_temp_free(tmp); \
1156 } else \
1157 gen_helper_ ## name (cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); \
1158 } else { \
1159 TCGv tmp1 = tcg_const_i64(0); \
1160 if (islit) { \
1161 TCGv tmp2 = tcg_const_i64(lit); \
1162 gen_helper_ ## name (cpu_ir[rc], tmp1, tmp2); \
1163 tcg_temp_free(tmp2); \
1164 } else \
1165 gen_helper_ ## name (cpu_ir[rc], tmp1, cpu_ir[rb]); \
1166 tcg_temp_free(tmp1); \
1167 } \
1168 }
1169 ARITH3(cmpbge)
1170 ARITH3(addlv)
1171 ARITH3(sublv)
1172 ARITH3(addqv)
1173 ARITH3(subqv)
1174 ARITH3(umulh)
1175 ARITH3(mullv)
1176 ARITH3(mulqv)
1177 ARITH3(minub8)
1178 ARITH3(minsb8)
1179 ARITH3(minuw4)
1180 ARITH3(minsw4)
1181 ARITH3(maxub8)
1182 ARITH3(maxsb8)
1183 ARITH3(maxuw4)
1184 ARITH3(maxsw4)
1185 ARITH3(perr)
1186
1187 #define MVIOP2(name) \
1188 static inline void glue(gen_, name)(int rb, int rc) \
1189 { \
1190 if (unlikely(rc == 31)) \
1191 return; \
1192 if (unlikely(rb == 31)) \
1193 tcg_gen_movi_i64(cpu_ir[rc], 0); \
1194 else \
1195 gen_helper_ ## name (cpu_ir[rc], cpu_ir[rb]); \
1196 }
1197 MVIOP2(pklb)
1198 MVIOP2(pkwb)
1199 MVIOP2(unpkbl)
1200 MVIOP2(unpkbw)
1201
1202 static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit,
1203 uint8_t lit)
1204 {
1205 int l1, l2;
1206 TCGv tmp;
1207
1208 if (unlikely(rc == 31))
1209 return;
1210
1211 l1 = gen_new_label();
1212 l2 = gen_new_label();
1213
1214 if (ra != 31) {
1215 tmp = tcg_temp_new();
1216 tcg_gen_mov_i64(tmp, cpu_ir[ra]);
1217 } else
1218 tmp = tcg_const_i64(0);
1219 if (islit)
1220 tcg_gen_brcondi_i64(cond, tmp, lit, l1);
1221 else
1222 tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);
1223
1224 tcg_gen_movi_i64(cpu_ir[rc], 0);
1225 tcg_gen_br(l2);
1226 gen_set_label(l1);
1227 tcg_gen_movi_i64(cpu_ir[rc], 1);
1228 gen_set_label(l2);
1229 }
1230
1231 static inline int translate_one(DisasContext *ctx, uint32_t insn)
1232 {
1233 uint32_t palcode;
1234 int32_t disp21, disp16, disp12;
1235 uint16_t fn11, fn16;
1236 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit, real_islit;
1237 uint8_t lit;
1238 int ret;
1239
1240 /* Decode all instruction fields */
1241 opc = insn >> 26;
1242 ra = (insn >> 21) & 0x1F;
1243 rb = (insn >> 16) & 0x1F;
1244 rc = insn & 0x1F;
1245 sbz = (insn >> 13) & 0x07;
1246 real_islit = islit = (insn >> 12) & 1;
1247 if (rb == 31 && !islit) {
1248 islit = 1;
1249 lit = 0;
1250 } else
1251 lit = (insn >> 13) & 0xFF;
1252 palcode = insn & 0x03FFFFFF;
1253 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
1254 disp16 = (int16_t)(insn & 0x0000FFFF);
1255 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
1256 fn16 = insn & 0x0000FFFF;
1257 fn11 = (insn >> 5) & 0x000007FF;
1258 fpfn = fn11 & 0x3F;
1259 fn7 = (insn >> 5) & 0x0000007F;
1260 fn2 = (insn >> 5) & 0x00000003;
1261 ret = 0;
1262 LOG_DISAS("opc %02x ra %2d rb %2d rc %2d disp16 %6d\n",
1263 opc, ra, rb, rc, disp16);
1264
1265 switch (opc) {
1266 case 0x00:
1267 /* CALL_PAL */
1268 #ifdef CONFIG_USER_ONLY
1269 if (palcode == 0x9E) {
1270 /* RDUNIQUE */
1271 tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_uniq);
1272 break;
1273 } else if (palcode == 0x9F) {
1274 /* WRUNIQUE */
1275 tcg_gen_mov_i64(cpu_uniq, cpu_ir[IR_A0]);
1276 break;
1277 }
1278 #endif
1279 if (palcode >= 0x80 && palcode < 0xC0) {
1280 /* Unprivileged PAL call */
1281 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x3F) << 6), 0);
1282 ret = 3;
1283 break;
1284 }
1285 #ifndef CONFIG_USER_ONLY
1286 if (palcode < 0x40) {
1287 /* Privileged PAL code */
1288 if (ctx->mem_idx & 1)
1289 goto invalid_opc;
1290 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0);
1291 ret = 3;
1292 }
1293 #endif
1294 /* Invalid PAL call */
1295 goto invalid_opc;
1296 case 0x01:
1297 /* OPC01 */
1298 goto invalid_opc;
1299 case 0x02:
1300 /* OPC02 */
1301 goto invalid_opc;
1302 case 0x03:
1303 /* OPC03 */
1304 goto invalid_opc;
1305 case 0x04:
1306 /* OPC04 */
1307 goto invalid_opc;
1308 case 0x05:
1309 /* OPC05 */
1310 goto invalid_opc;
1311 case 0x06:
1312 /* OPC06 */
1313 goto invalid_opc;
1314 case 0x07:
1315 /* OPC07 */
1316 goto invalid_opc;
1317 case 0x08:
1318 /* LDA */
1319 if (likely(ra != 31)) {
1320 if (rb != 31)
1321 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
1322 else
1323 tcg_gen_movi_i64(cpu_ir[ra], disp16);
1324 }
1325 break;
1326 case 0x09:
1327 /* LDAH */
1328 if (likely(ra != 31)) {
1329 if (rb != 31)
1330 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
1331 else
1332 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
1333 }
1334 break;
1335 case 0x0A:
1336 /* LDBU */
1337 if (!(ctx->amask & AMASK_BWX))
1338 goto invalid_opc;
1339 gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0);
1340 break;
1341 case 0x0B:
1342 /* LDQ_U */
1343 gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1);
1344 break;
1345 case 0x0C:
1346 /* LDWU */
1347 if (!(ctx->amask & AMASK_BWX))
1348 goto invalid_opc;
1349 gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 0);
1350 break;
1351 case 0x0D:
1352 /* STW */
1353 gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0, 0);
1354 break;
1355 case 0x0E:
1356 /* STB */
1357 gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0, 0);
1358 break;
1359 case 0x0F:
1360 /* STQ_U */
1361 gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1, 0);
1362 break;
1363 case 0x10:
1364 switch (fn7) {
1365 case 0x00:
1366 /* ADDL */
1367 if (likely(rc != 31)) {
1368 if (ra != 31) {
1369 if (islit) {
1370 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1371 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1372 } else {
1373 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1374 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1375 }
1376 } else {
1377 if (islit)
1378 tcg_gen_movi_i64(cpu_ir[rc], lit);
1379 else
1380 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
1381 }
1382 }
1383 break;
1384 case 0x02:
1385 /* S4ADDL */
1386 if (likely(rc != 31)) {
1387 if (ra != 31) {
1388 TCGv tmp = tcg_temp_new();
1389 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
1390 if (islit)
1391 tcg_gen_addi_i64(tmp, tmp, lit);
1392 else
1393 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
1394 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
1395 tcg_temp_free(tmp);
1396 } else {
1397 if (islit)
1398 tcg_gen_movi_i64(cpu_ir[rc], lit);
1399 else
1400 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
1401 }
1402 }
1403 break;
1404 case 0x09:
1405 /* SUBL */
1406 if (likely(rc != 31)) {
1407 if (ra != 31) {
1408 if (islit)
1409 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1410 else
1411 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1412 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1413 } else {
1414 if (islit)
1415 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1416 else {
1417 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1418 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1419 }
1420 }
1421 break;
1422 case 0x0B:
1423 /* S4SUBL */
1424 if (likely(rc != 31)) {
1425 if (ra != 31) {
1426 TCGv tmp = tcg_temp_new();
1427 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
1428 if (islit)
1429 tcg_gen_subi_i64(tmp, tmp, lit);
1430 else
1431 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
1432 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
1433 tcg_temp_free(tmp);
1434 } else {
1435 if (islit)
1436 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1437 else {
1438 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1439 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1440 }
1441 }
1442 }
1443 break;
1444 case 0x0F:
1445 /* CMPBGE */
1446 gen_cmpbge(ra, rb, rc, islit, lit);
1447 break;
1448 case 0x12:
1449 /* S8ADDL */
1450 if (likely(rc != 31)) {
1451 if (ra != 31) {
1452 TCGv tmp = tcg_temp_new();
1453 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
1454 if (islit)
1455 tcg_gen_addi_i64(tmp, tmp, lit);
1456 else
1457 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
1458 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
1459 tcg_temp_free(tmp);
1460 } else {
1461 if (islit)
1462 tcg_gen_movi_i64(cpu_ir[rc], lit);
1463 else
1464 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
1465 }
1466 }
1467 break;
1468 case 0x1B:
1469 /* S8SUBL */
1470 if (likely(rc != 31)) {
1471 if (ra != 31) {
1472 TCGv tmp = tcg_temp_new();
1473 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
1474 if (islit)
1475 tcg_gen_subi_i64(tmp, tmp, lit);
1476 else
1477 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
1478 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
1479 tcg_temp_free(tmp);
1480 } else {
1481 if (islit)
1482 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1483 else
1484 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1485 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1486 }
1487 }
1488 }
1489 break;
1490 case 0x1D:
1491 /* CMPULT */
1492 gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
1493 break;
1494 case 0x20:
1495 /* ADDQ */
1496 if (likely(rc != 31)) {
1497 if (ra != 31) {
1498 if (islit)
1499 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1500 else
1501 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1502 } else {
1503 if (islit)
1504 tcg_gen_movi_i64(cpu_ir[rc], lit);
1505 else
1506 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1507 }
1508 }
1509 break;
1510 case 0x22:
1511 /* S4ADDQ */
1512 if (likely(rc != 31)) {
1513 if (ra != 31) {
1514 TCGv tmp = tcg_temp_new();
1515 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
1516 if (islit)
1517 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
1518 else
1519 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
1520 tcg_temp_free(tmp);
1521 } else {
1522 if (islit)
1523 tcg_gen_movi_i64(cpu_ir[rc], lit);
1524 else
1525 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1526 }
1527 }
1528 break;
1529 case 0x29:
1530 /* SUBQ */
1531 if (likely(rc != 31)) {
1532 if (ra != 31) {
1533 if (islit)
1534 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1535 else
1536 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1537 } else {
1538 if (islit)
1539 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1540 else
1541 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1542 }
1543 }
1544 break;
1545 case 0x2B:
1546 /* S4SUBQ */
1547 if (likely(rc != 31)) {
1548 if (ra != 31) {
1549 TCGv tmp = tcg_temp_new();
1550 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
1551 if (islit)
1552 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
1553 else
1554 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
1555 tcg_temp_free(tmp);
1556 } else {
1557 if (islit)
1558 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1559 else
1560 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1561 }
1562 }
1563 break;
1564 case 0x2D:
1565 /* CMPEQ */
1566 gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
1567 break;
1568 case 0x32:
1569 /* S8ADDQ */
1570 if (likely(rc != 31)) {
1571 if (ra != 31) {
1572 TCGv tmp = tcg_temp_new();
1573 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
1574 if (islit)
1575 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
1576 else
1577 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
1578 tcg_temp_free(tmp);
1579 } else {
1580 if (islit)
1581 tcg_gen_movi_i64(cpu_ir[rc], lit);
1582 else
1583 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1584 }
1585 }
1586 break;
1587 case 0x3B:
1588 /* S8SUBQ */
1589 if (likely(rc != 31)) {
1590 if (ra != 31) {
1591 TCGv tmp = tcg_temp_new();
1592 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
1593 if (islit)
1594 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
1595 else
1596 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
1597 tcg_temp_free(tmp);
1598 } else {
1599 if (islit)
1600 tcg_gen_movi_i64(cpu_ir[rc], -lit);
1601 else
1602 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
1603 }
1604 }
1605 break;
1606 case 0x3D:
1607 /* CMPULE */
1608 gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
1609 break;
1610 case 0x40:
1611 /* ADDL/V */
1612 gen_addlv(ra, rb, rc, islit, lit);
1613 break;
1614 case 0x49:
1615 /* SUBL/V */
1616 gen_sublv(ra, rb, rc, islit, lit);
1617 break;
1618 case 0x4D:
1619 /* CMPLT */
1620 gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
1621 break;
1622 case 0x60:
1623 /* ADDQ/V */
1624 gen_addqv(ra, rb, rc, islit, lit);
1625 break;
1626 case 0x69:
1627 /* SUBQ/V */
1628 gen_subqv(ra, rb, rc, islit, lit);
1629 break;
1630 case 0x6D:
1631 /* CMPLE */
1632 gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
1633 break;
1634 default:
1635 goto invalid_opc;
1636 }
1637 break;
1638 case 0x11:
1639 switch (fn7) {
1640 case 0x00:
1641 /* AND */
1642 if (likely(rc != 31)) {
1643 if (ra == 31)
1644 tcg_gen_movi_i64(cpu_ir[rc], 0);
1645 else if (islit)
1646 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1647 else
1648 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1649 }
1650 break;
1651 case 0x08:
1652 /* BIC */
1653 if (likely(rc != 31)) {
1654 if (ra != 31) {
1655 if (islit)
1656 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1657 else
1658 tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1659 } else
1660 tcg_gen_movi_i64(cpu_ir[rc], 0);
1661 }
1662 break;
1663 case 0x14:
1664 /* CMOVLBS */
1665 gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
1666 break;
1667 case 0x16:
1668 /* CMOVLBC */
1669 gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1);
1670 break;
1671 case 0x20:
1672 /* BIS */
1673 if (likely(rc != 31)) {
1674 if (ra != 31) {
1675 if (islit)
1676 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1677 else
1678 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1679 } else {
1680 if (islit)
1681 tcg_gen_movi_i64(cpu_ir[rc], lit);
1682 else
1683 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1684 }
1685 }
1686 break;
1687 case 0x24:
1688 /* CMOVEQ */
1689 gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0);
1690 break;
1691 case 0x26:
1692 /* CMOVNE */
1693 gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
1694 break;
1695 case 0x28:
1696 /* ORNOT */
1697 if (likely(rc != 31)) {
1698 if (ra != 31) {
1699 if (islit)
1700 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1701 else
1702 tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1703 } else {
1704 if (islit)
1705 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1706 else
1707 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1708 }
1709 }
1710 break;
1711 case 0x40:
1712 /* XOR */
1713 if (likely(rc != 31)) {
1714 if (ra != 31) {
1715 if (islit)
1716 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1717 else
1718 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1719 } else {
1720 if (islit)
1721 tcg_gen_movi_i64(cpu_ir[rc], lit);
1722 else
1723 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1724 }
1725 }
1726 break;
1727 case 0x44:
1728 /* CMOVLT */
1729 gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0);
1730 break;
1731 case 0x46:
1732 /* CMOVGE */
1733 gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0);
1734 break;
1735 case 0x48:
1736 /* EQV */
1737 if (likely(rc != 31)) {
1738 if (ra != 31) {
1739 if (islit)
1740 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1741 else
1742 tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1743 } else {
1744 if (islit)
1745 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1746 else
1747 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1748 }
1749 }
1750 break;
1751 case 0x61:
1752 /* AMASK */
1753 if (likely(rc != 31)) {
1754 if (islit)
1755 tcg_gen_movi_i64(cpu_ir[rc], lit);
1756 else
1757 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1758 switch (ctx->env->implver) {
1759 case IMPLVER_2106x:
1760 /* EV4, EV45, LCA, LCA45 & EV5 */
1761 break;
1762 case IMPLVER_21164:
1763 case IMPLVER_21264:
1764 case IMPLVER_21364:
1765 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rc],
1766 ~(uint64_t)ctx->amask);
1767 break;
1768 }
1769 }
1770 break;
1771 case 0x64:
1772 /* CMOVLE */
1773 gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0);
1774 break;
1775 case 0x66:
1776 /* CMOVGT */
1777 gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0);
1778 break;
1779 case 0x6C:
1780 /* IMPLVER */
1781 if (rc != 31)
1782 tcg_gen_movi_i64(cpu_ir[rc], ctx->env->implver);
1783 break;
1784 default:
1785 goto invalid_opc;
1786 }
1787 break;
1788 case 0x12:
1789 switch (fn7) {
1790 case 0x02:
1791 /* MSKBL */
1792 gen_msk_l(ra, rb, rc, islit, lit, 0x01);
1793 break;
1794 case 0x06:
1795 /* EXTBL */
1796 gen_ext_l(ra, rb, rc, islit, lit, 0x01);
1797 break;
1798 case 0x0B:
1799 /* INSBL */
1800 gen_ins_l(ra, rb, rc, islit, lit, 0x01);
1801 break;
1802 case 0x12:
1803 /* MSKWL */
1804 gen_msk_l(ra, rb, rc, islit, lit, 0x03);
1805 break;
1806 case 0x16:
1807 /* EXTWL */
1808 gen_ext_l(ra, rb, rc, islit, lit, 0x03);
1809 break;
1810 case 0x1B:
1811 /* INSWL */
1812 gen_ins_l(ra, rb, rc, islit, lit, 0x03);
1813 break;
1814 case 0x22:
1815 /* MSKLL */
1816 gen_msk_l(ra, rb, rc, islit, lit, 0x0f);
1817 break;
1818 case 0x26:
1819 /* EXTLL */
1820 gen_ext_l(ra, rb, rc, islit, lit, 0x0f);
1821 break;
1822 case 0x2B:
1823 /* INSLL */
1824 gen_ins_l(ra, rb, rc, islit, lit, 0x0f);
1825 break;
1826 case 0x30:
1827 /* ZAP */
1828 gen_zap(ra, rb, rc, islit, lit);
1829 break;
1830 case 0x31:
1831 /* ZAPNOT */
1832 gen_zapnot(ra, rb, rc, islit, lit);
1833 break;
1834 case 0x32:
1835 /* MSKQL */
1836 gen_msk_l(ra, rb, rc, islit, lit, 0xff);
1837 break;
1838 case 0x34:
1839 /* SRL */
1840 if (likely(rc != 31)) {
1841 if (ra != 31) {
1842 if (islit)
1843 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1844 else {
1845 TCGv shift = tcg_temp_new();
1846 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1847 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift);
1848 tcg_temp_free(shift);
1849 }
1850 } else
1851 tcg_gen_movi_i64(cpu_ir[rc], 0);
1852 }
1853 break;
1854 case 0x36:
1855 /* EXTQL */
1856 gen_ext_l(ra, rb, rc, islit, lit, 0xff);
1857 break;
1858 case 0x39:
1859 /* SLL */
1860 if (likely(rc != 31)) {
1861 if (ra != 31) {
1862 if (islit)
1863 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1864 else {
1865 TCGv shift = tcg_temp_new();
1866 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1867 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift);
1868 tcg_temp_free(shift);
1869 }
1870 } else
1871 tcg_gen_movi_i64(cpu_ir[rc], 0);
1872 }
1873 break;
1874 case 0x3B:
1875 /* INSQL */
1876 gen_ins_l(ra, rb, rc, islit, lit, 0xff);
1877 break;
1878 case 0x3C:
1879 /* SRA */
1880 if (likely(rc != 31)) {
1881 if (ra != 31) {
1882 if (islit)
1883 tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1884 else {
1885 TCGv shift = tcg_temp_new();
1886 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1887 tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift);
1888 tcg_temp_free(shift);
1889 }
1890 } else
1891 tcg_gen_movi_i64(cpu_ir[rc], 0);
1892 }
1893 break;
1894 case 0x52:
1895 /* MSKWH */
1896 gen_msk_h(ra, rb, rc, islit, lit, 0x03);
1897 break;
1898 case 0x57:
1899 /* INSWH */
1900 gen_ins_h(ra, rb, rc, islit, lit, 0x03);
1901 break;
1902 case 0x5A:
1903 /* EXTWH */
1904 gen_ext_h(ra, rb, rc, islit, lit, 0x03);
1905 break;
1906 case 0x62:
1907 /* MSKLH */
1908 gen_msk_h(ra, rb, rc, islit, lit, 0x0f);
1909 break;
1910 case 0x67:
1911 /* INSLH */
1912 gen_ins_h(ra, rb, rc, islit, lit, 0x0f);
1913 break;
1914 case 0x6A:
1915 /* EXTLH */
1916 gen_ext_h(ra, rb, rc, islit, lit, 0x0f);
1917 break;
1918 case 0x72:
1919 /* MSKQH */
1920 gen_msk_h(ra, rb, rc, islit, lit, 0xff);
1921 break;
1922 case 0x77:
1923 /* INSQH */
1924 gen_ins_h(ra, rb, rc, islit, lit, 0xff);
1925 break;
1926 case 0x7A:
1927 /* EXTQH */
1928 gen_ext_h(ra, rb, rc, islit, lit, 0xff);
1929 break;
1930 default:
1931 goto invalid_opc;
1932 }
1933 break;
1934 case 0x13:
1935 switch (fn7) {
1936 case 0x00:
1937 /* MULL */
1938 if (likely(rc != 31)) {
1939 if (ra == 31)
1940 tcg_gen_movi_i64(cpu_ir[rc], 0);
1941 else {
1942 if (islit)
1943 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1944 else
1945 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1946 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1947 }
1948 }
1949 break;
1950 case 0x20:
1951 /* MULQ */
1952 if (likely(rc != 31)) {
1953 if (ra == 31)
1954 tcg_gen_movi_i64(cpu_ir[rc], 0);
1955 else if (islit)
1956 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1957 else
1958 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1959 }
1960 break;
1961 case 0x30:
1962 /* UMULH */
1963 gen_umulh(ra, rb, rc, islit, lit);
1964 break;
1965 case 0x40:
1966 /* MULL/V */
1967 gen_mullv(ra, rb, rc, islit, lit);
1968 break;
1969 case 0x60:
1970 /* MULQ/V */
1971 gen_mulqv(ra, rb, rc, islit, lit);
1972 break;
1973 default:
1974 goto invalid_opc;
1975 }
1976 break;
1977 case 0x14:
1978 switch (fpfn) { /* fn11 & 0x3F */
1979 case 0x04:
1980 /* ITOFS */
1981 if (!(ctx->amask & AMASK_FIX))
1982 goto invalid_opc;
1983 if (likely(rc != 31)) {
1984 if (ra != 31) {
1985 TCGv_i32 tmp = tcg_temp_new_i32();
1986 tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
1987 gen_helper_memory_to_s(cpu_fir[rc], tmp);
1988 tcg_temp_free_i32(tmp);
1989 } else
1990 tcg_gen_movi_i64(cpu_fir[rc], 0);
1991 }
1992 break;
1993 case 0x0A:
1994 /* SQRTF */
1995 if (!(ctx->amask & AMASK_FIX))
1996 goto invalid_opc;
1997 gen_fsqrtf(rb, rc);
1998 break;
1999 case 0x0B:
2000 /* SQRTS */
2001 if (!(ctx->amask & AMASK_FIX))
2002 goto invalid_opc;
2003 gen_fsqrts(ctx, rb, rc, fn11);
2004 break;
2005 case 0x14:
2006 /* ITOFF */
2007 if (!(ctx->amask & AMASK_FIX))
2008 goto invalid_opc;
2009 if (likely(rc != 31)) {
2010 if (ra != 31) {
2011 TCGv_i32 tmp = tcg_temp_new_i32();
2012 tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]);
2013 gen_helper_memory_to_f(cpu_fir[rc], tmp);
2014 tcg_temp_free_i32(tmp);
2015 } else
2016 tcg_gen_movi_i64(cpu_fir[rc], 0);
2017 }
2018 break;
2019 case 0x24:
2020 /* ITOFT */
2021 if (!(ctx->amask & AMASK_FIX))
2022 goto invalid_opc;
2023 if (likely(rc != 31)) {
2024 if (ra != 31)
2025 tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]);
2026 else
2027 tcg_gen_movi_i64(cpu_fir[rc], 0);
2028 }
2029 break;
2030 case 0x2A:
2031 /* SQRTG */
2032 if (!(ctx->amask & AMASK_FIX))
2033 goto invalid_opc;
2034 gen_fsqrtg(rb, rc);
2035 break;
2036 case 0x02B:
2037 /* SQRTT */
2038 if (!(ctx->amask & AMASK_FIX))
2039 goto invalid_opc;
2040 gen_fsqrtt(ctx, rb, rc, fn11);
2041 break;
2042 default:
2043 goto invalid_opc;
2044 }
2045 break;
2046 case 0x15:
2047 /* VAX floating point */
2048 /* XXX: rounding mode and trap are ignored (!) */
2049 switch (fpfn) { /* fn11 & 0x3F */
2050 case 0x00:
2051 /* ADDF */
2052 gen_faddf(ra, rb, rc);
2053 break;
2054 case 0x01:
2055 /* SUBF */
2056 gen_fsubf(ra, rb, rc);
2057 break;
2058 case 0x02:
2059 /* MULF */
2060 gen_fmulf(ra, rb, rc);
2061 break;
2062 case 0x03:
2063 /* DIVF */
2064 gen_fdivf(ra, rb, rc);
2065 break;
2066 case 0x1E:
2067 /* CVTDG */
2068 #if 0 // TODO
2069 gen_fcvtdg(rb, rc);
2070 #else
2071 goto invalid_opc;
2072 #endif
2073 break;
2074 case 0x20:
2075 /* ADDG */
2076 gen_faddg(ra, rb, rc);
2077 break;
2078 case 0x21:
2079 /* SUBG */
2080 gen_fsubg(ra, rb, rc);
2081 break;
2082 case 0x22:
2083 /* MULG */
2084 gen_fmulg(ra, rb, rc);
2085 break;
2086 case 0x23:
2087 /* DIVG */
2088 gen_fdivg(ra, rb, rc);
2089 break;
2090 case 0x25:
2091 /* CMPGEQ */
2092 gen_fcmpgeq(ra, rb, rc);
2093 break;
2094 case 0x26:
2095 /* CMPGLT */
2096 gen_fcmpglt(ra, rb, rc);
2097 break;
2098 case 0x27:
2099 /* CMPGLE */
2100 gen_fcmpgle(ra, rb, rc);
2101 break;
2102 case 0x2C:
2103 /* CVTGF */
2104 gen_fcvtgf(rb, rc);
2105 break;
2106 case 0x2D:
2107 /* CVTGD */
2108 #if 0 // TODO
2109 gen_fcvtgd(rb, rc);
2110 #else
2111 goto invalid_opc;
2112 #endif
2113 break;
2114 case 0x2F:
2115 /* CVTGQ */
2116 gen_fcvtgq(rb, rc);
2117 break;
2118 case 0x3C:
2119 /* CVTQF */
2120 gen_fcvtqf(rb, rc);
2121 break;
2122 case 0x3E:
2123 /* CVTQG */
2124 gen_fcvtqg(rb, rc);
2125 break;
2126 default:
2127 goto invalid_opc;
2128 }
2129 break;
2130 case 0x16:
2131 /* IEEE floating-point */
2132 switch (fpfn) { /* fn11 & 0x3F */
2133 case 0x00:
2134 /* ADDS */
2135 gen_fadds(ctx, ra, rb, rc, fn11);
2136 break;
2137 case 0x01:
2138 /* SUBS */
2139 gen_fsubs(ctx, ra, rb, rc, fn11);
2140 break;
2141 case 0x02:
2142 /* MULS */
2143 gen_fmuls(ctx, ra, rb, rc, fn11);
2144 break;
2145 case 0x03:
2146 /* DIVS */
2147 gen_fdivs(ctx, ra, rb, rc, fn11);
2148 break;
2149 case 0x20:
2150 /* ADDT */
2151 gen_faddt(ctx, ra, rb, rc, fn11);
2152 break;
2153 case 0x21:
2154 /* SUBT */
2155 gen_fsubt(ctx, ra, rb, rc, fn11);
2156 break;
2157 case 0x22:
2158 /* MULT */
2159 gen_fmult(ctx, ra, rb, rc, fn11);
2160 break;
2161 case 0x23:
2162 /* DIVT */
2163 gen_fdivt(ctx, ra, rb, rc, fn11);
2164 break;
2165 case 0x24:
2166 /* CMPTUN */
2167 gen_fcmptun(ctx, ra, rb, rc, fn11);
2168 break;
2169 case 0x25:
2170 /* CMPTEQ */
2171 gen_fcmpteq(ctx, ra, rb, rc, fn11);
2172 break;
2173 case 0x26:
2174 /* CMPTLT */
2175 gen_fcmptlt(ctx, ra, rb, rc, fn11);
2176 break;
2177 case 0x27:
2178 /* CMPTLE */
2179 gen_fcmptle(ctx, ra, rb, rc, fn11);
2180 break;
2181 case 0x2C:
2182 if (fn11 == 0x2AC || fn11 == 0x6AC) {
2183 /* CVTST */
2184 gen_fcvtst(ctx, rb, rc, fn11);
2185 } else {
2186 /* CVTTS */
2187 gen_fcvtts(ctx, rb, rc, fn11);
2188 }
2189 break;
2190 case 0x2F:
2191 /* CVTTQ */
2192 gen_fcvttq(ctx, rb, rc, fn11);
2193 break;
2194 case 0x3C:
2195 /* CVTQS */
2196 gen_fcvtqs(ctx, rb, rc, fn11);
2197 break;
2198 case 0x3E:
2199 /* CVTQT */
2200 gen_fcvtqt(ctx, rb, rc, fn11);
2201 break;
2202 default:
2203 goto invalid_opc;
2204 }
2205 break;
2206 case 0x17:
2207 switch (fn11) {
2208 case 0x010:
2209 /* CVTLQ */
2210 gen_fcvtlq(rb, rc);
2211 break;
2212 case 0x020:
2213 if (likely(rc != 31)) {
2214 if (ra == rb) {
2215 /* FMOV */
2216 if (ra == 31)
2217 tcg_gen_movi_i64(cpu_fir[rc], 0);
2218 else
2219 tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);
2220 } else {
2221 /* CPYS */
2222 gen_fcpys(ra, rb, rc);
2223 }
2224 }
2225 break;
2226 case 0x021:
2227 /* CPYSN */
2228 gen_fcpysn(ra, rb, rc);
2229 break;
2230 case 0x022:
2231 /* CPYSE */
2232 gen_fcpyse(ra, rb, rc);
2233 break;
2234 case 0x024:
2235 /* MT_FPCR */
2236 if (likely(ra != 31))
2237 gen_helper_store_fpcr(cpu_fir[ra]);
2238 else {
2239 TCGv tmp = tcg_const_i64(0);
2240 gen_helper_store_fpcr(tmp);
2241 tcg_temp_free(tmp);
2242 }
2243 break;
2244 case 0x025:
2245 /* MF_FPCR */
2246 if (likely(ra != 31))
2247 gen_helper_load_fpcr(cpu_fir[ra]);
2248 break;
2249 case 0x02A:
2250 /* FCMOVEQ */
2251 gen_fcmov(TCG_COND_NE, ra, rb, rc);
2252 break;
2253 case 0x02B:
2254 /* FCMOVNE */
2255 gen_fcmov(TCG_COND_EQ, ra, rb, rc);
2256 break;
2257 case 0x02C:
2258 /* FCMOVLT */
2259 gen_fcmov(TCG_COND_GE, ra, rb, rc);
2260 break;
2261 case 0x02D:
2262 /* FCMOVGE */
2263 gen_fcmov(TCG_COND_LT, ra, rb, rc);
2264 break;
2265 case 0x02E:
2266 /* FCMOVLE */
2267 gen_fcmov(TCG_COND_GT, ra, rb, rc);
2268 break;
2269 case 0x02F:
2270 /* FCMOVGT */
2271 gen_fcmov(TCG_COND_LE, ra, rb, rc);
2272 break;
2273 case 0x030:
2274 /* CVTQL */
2275 gen_fcvtql(rb, rc);
2276 break;
2277 case 0x130:
2278 /* CVTQL/V */
2279 case 0x530:
2280 /* CVTQL/SV */
2281 /* ??? I'm pretty sure there's nothing that /sv needs to do that
2282 /v doesn't do. The only thing I can think is that /sv is a
2283 valid instruction merely for completeness in the ISA. */
2284 gen_fcvtql_v(ctx, rb, rc);
2285 break;
2286 default:
2287 goto invalid_opc;
2288 }
2289 break;
2290 case 0x18:
2291 switch ((uint16_t)disp16) {
2292 case 0x0000:
2293 /* TRAPB */
2294 /* No-op. Just exit from the current tb */
2295 ret = 2;
2296 break;
2297 case 0x0400:
2298 /* EXCB */
2299 /* No-op. Just exit from the current tb */
2300 ret = 2;
2301 break;
2302 case 0x4000:
2303 /* MB */
2304 /* No-op */
2305 break;
2306 case 0x4400:
2307 /* WMB */
2308 /* No-op */
2309 break;
2310 case 0x8000:
2311 /* FETCH */
2312 /* No-op */
2313 break;
2314 case 0xA000:
2315 /* FETCH_M */
2316 /* No-op */
2317 break;
2318 case 0xC000:
2319 /* RPCC */
2320 if (ra != 31)
2321 gen_helper_load_pcc(cpu_ir[ra]);
2322 break;
2323 case 0xE000:
2324 /* RC */
2325 if (ra != 31)
2326 gen_helper_rc(cpu_ir[ra]);
2327 break;
2328 case 0xE800:
2329 /* ECB */
2330 break;
2331 case 0xF000:
2332 /* RS */
2333 if (ra != 31)
2334 gen_helper_rs(cpu_ir[ra]);
2335 break;
2336 case 0xF800:
2337 /* WH64 */
2338 /* No-op */
2339 break;
2340 default:
2341 goto invalid_opc;
2342 }
2343 break;
2344 case 0x19:
2345 /* HW_MFPR (PALcode) */
2346 #if defined (CONFIG_USER_ONLY)
2347 goto invalid_opc;
2348 #else
2349 if (!ctx->pal_mode)
2350 goto invalid_opc;
2351 if (ra != 31) {
2352 TCGv tmp = tcg_const_i32(insn & 0xFF);
2353 gen_helper_mfpr(cpu_ir[ra], tmp, cpu_ir[ra]);
2354 tcg_temp_free(tmp);
2355 }
2356 break;
2357 #endif
2358 case 0x1A:
2359 if (rb != 31)
2360 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
2361 else
2362 tcg_gen_movi_i64(cpu_pc, 0);
2363 if (ra != 31)
2364 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2365 /* Those four jumps only differ by the branch prediction hint */
2366 switch (fn2) {
2367 case 0x0:
2368 /* JMP */
2369 break;
2370 case 0x1:
2371 /* JSR */
2372 break;
2373 case 0x2:
2374 /* RET */
2375 break;
2376 case 0x3:
2377 /* JSR_COROUTINE */
2378 break;
2379 }
2380 ret = 1;
2381 break;
2382 case 0x1B:
2383 /* HW_LD (PALcode) */
2384 #if defined (CONFIG_USER_ONLY)
2385 goto invalid_opc;
2386 #else
2387 if (!ctx->pal_mode)
2388 goto invalid_opc;
2389 if (ra != 31) {
2390 TCGv addr = tcg_temp_new();
2391 if (rb != 31)
2392 tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
2393 else
2394 tcg_gen_movi_i64(addr, disp12);
2395 switch ((insn >> 12) & 0xF) {
2396 case 0x0:
2397 /* Longword physical access (hw_ldl/p) */
2398 gen_helper_ldl_raw(cpu_ir[ra], addr);
2399 break;
2400 case 0x1:
2401 /* Quadword physical access (hw_ldq/p) */
2402 gen_helper_ldq_raw(cpu_ir[ra], addr);
2403 break;
2404 case 0x2:
2405 /* Longword physical access with lock (hw_ldl_l/p) */
2406 gen_helper_ldl_l_raw(cpu_ir[ra], addr);
2407 break;
2408 case 0x3:
2409 /* Quadword physical access with lock (hw_ldq_l/p) */
2410 gen_helper_ldq_l_raw(cpu_ir[ra], addr);
2411 break;
2412 case 0x4:
2413 /* Longword virtual PTE fetch (hw_ldl/v) */
2414 tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
2415 break;
2416 case 0x5:
2417 /* Quadword virtual PTE fetch (hw_ldq/v) */
2418 tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
2419 break;
2420 case 0x6:
2421 /* Incpu_ir[ra]id */
2422 goto invalid_opc;
2423 case 0x7:
2424 /* Incpu_ir[ra]id */
2425 goto invalid_opc;
2426 case 0x8:
2427 /* Longword virtual access (hw_ldl) */
2428 gen_helper_st_virt_to_phys(addr, addr);
2429 gen_helper_ldl_raw(cpu_ir[ra], addr);
2430 break;
2431 case 0x9:
2432 /* Quadword virtual access (hw_ldq) */
2433 gen_helper_st_virt_to_phys(addr, addr);
2434 gen_helper_ldq_raw(cpu_ir[ra], addr);
2435 break;
2436 case 0xA:
2437 /* Longword virtual access with protection check (hw_ldl/w) */
2438 tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0);
2439 break;
2440 case 0xB:
2441 /* Quadword virtual access with protection check (hw_ldq/w) */
2442 tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0);
2443 break;
2444 case 0xC:
2445 /* Longword virtual access with alt access mode (hw_ldl/a)*/
2446 gen_helper_set_alt_mode();
2447 gen_helper_st_virt_to_phys(addr, addr);
2448 gen_helper_ldl_raw(cpu_ir[ra], addr);
2449 gen_helper_restore_mode();
2450 break;
2451 case 0xD:
2452 /* Quadword virtual access with alt access mode (hw_ldq/a) */
2453 gen_helper_set_alt_mode();
2454 gen_helper_st_virt_to_phys(addr, addr);
2455 gen_helper_ldq_raw(cpu_ir[ra], addr);
2456 gen_helper_restore_mode();
2457 break;
2458 case 0xE:
2459 /* Longword virtual access with alternate access mode and
2460 * protection checks (hw_ldl/wa)
2461 */
2462 gen_helper_set_alt_mode();
2463 gen_helper_ldl_data(cpu_ir[ra], addr);
2464 gen_helper_restore_mode();
2465 break;
2466 case 0xF:
2467 /* Quadword virtual access with alternate access mode and
2468 * protection checks (hw_ldq/wa)
2469 */
2470 gen_helper_set_alt_mode();
2471 gen_helper_ldq_data(cpu_ir[ra], addr);
2472 gen_helper_restore_mode();
2473 break;
2474 }
2475 tcg_temp_free(addr);
2476 }
2477 break;
2478 #endif
2479 case 0x1C:
2480 switch (fn7) {
2481 case 0x00:
2482 /* SEXTB */
2483 if (!(ctx->amask & AMASK_BWX))
2484 goto invalid_opc;
2485 if (likely(rc != 31)) {
2486 if (islit)
2487 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
2488 else
2489 tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
2490 }
2491 break;
2492 case 0x01:
2493 /* SEXTW */
2494 if (!(ctx->amask & AMASK_BWX))
2495 goto invalid_opc;
2496 if (likely(rc != 31)) {
2497 if (islit)
2498 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
2499 else
2500 tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
2501 }
2502 break;
2503 case 0x30:
2504 /* CTPOP */
2505 if (!(ctx->amask & AMASK_CIX))
2506 goto invalid_opc;
2507 if (likely(rc != 31)) {
2508 if (islit)
2509 tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
2510 else
2511 gen_helper_ctpop(cpu_ir[rc], cpu_ir[rb]);
2512 }
2513 break;
2514 case 0x31:
2515 /* PERR */
2516 if (!(ctx->amask & AMASK_MVI))
2517 goto invalid_opc;
2518 gen_perr(ra, rb, rc, islit, lit);
2519 break;
2520 case 0x32:
2521 /* CTLZ */
2522 if (!(ctx->amask & AMASK_CIX))
2523 goto invalid_opc;
2524 if (likely(rc != 31)) {
2525 if (islit)
2526 tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
2527 else
2528 gen_helper_ctlz(cpu_ir[rc], cpu_ir[rb]);
2529 }
2530 break;
2531 case 0x33:
2532 /* CTTZ */
2533 if (!(ctx->amask & AMASK_CIX))
2534 goto invalid_opc;
2535 if (likely(rc != 31)) {
2536 if (islit)
2537 tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
2538 else
2539 gen_helper_cttz(cpu_ir[rc], cpu_ir[rb]);
2540 }
2541 break;
2542 case 0x34:
2543 /* UNPKBW */
2544 if (!(ctx->amask & AMASK_MVI))
2545 goto invalid_opc;
2546 if (real_islit || ra != 31)
2547 goto invalid_opc;
2548 gen_unpkbw (rb, rc);
2549 break;
2550 case 0x35:
2551 /* UNPKBL */
2552 if (!(ctx->amask & AMASK_MVI))
2553 goto invalid_opc;
2554 if (real_islit || ra != 31)
2555 goto invalid_opc;
2556 gen_unpkbl (rb, rc);
2557 break;
2558 case 0x36:
2559 /* PKWB */
2560 if (!(ctx->amask & AMASK_MVI))
2561 goto invalid_opc;
2562 if (real_islit || ra != 31)
2563 goto invalid_opc;
2564 gen_pkwb (rb, rc);
2565 break;
2566 case 0x37:
2567 /* PKLB */
2568 if (!(ctx->amask & AMASK_MVI))
2569 goto invalid_opc;
2570 if (real_islit || ra != 31)
2571 goto invalid_opc;
2572 gen_pklb (rb, rc);
2573 break;
2574 case 0x38:
2575 /* MINSB8 */
2576 if (!(ctx->amask & AMASK_MVI))
2577 goto invalid_opc;
2578 gen_minsb8 (ra, rb, rc, islit, lit);
2579 break;
2580 case 0x39:
2581 /* MINSW4 */
2582 if (!(ctx->amask & AMASK_MVI))
2583 goto invalid_opc;
2584 gen_minsw4 (ra, rb, rc, islit, lit);
2585 break;
2586 case 0x3A:
2587 /* MINUB8 */
2588 if (!(ctx->amask & AMASK_MVI))
2589 goto invalid_opc;
2590 gen_minub8 (ra, rb, rc, islit, lit);
2591 break;
2592 case 0x3B:
2593 /* MINUW4 */
2594 if (!(ctx->amask & AMASK_MVI))
2595 goto invalid_opc;
2596 gen_minuw4 (ra, rb, rc, islit, lit);
2597 break;
2598 case 0x3C:
2599 /* MAXUB8 */
2600 if (!(ctx->amask & AMASK_MVI))
2601 goto invalid_opc;
2602 gen_maxub8 (ra, rb, rc, islit, lit);
2603 break;
2604 case 0x3D:
2605 /* MAXUW4 */
2606 if (!(ctx->amask & AMASK_MVI))
2607 goto invalid_opc;
2608 gen_maxuw4 (ra, rb, rc, islit, lit);
2609 break;
2610 case 0x3E:
2611 /* MAXSB8 */
2612 if (!(ctx->amask & AMASK_MVI))
2613 goto invalid_opc;
2614 gen_maxsb8 (ra, rb, rc, islit, lit);
2615 break;
2616 case 0x3F:
2617 /* MAXSW4 */
2618 if (!(ctx->amask & AMASK_MVI))
2619 goto invalid_opc;
2620 gen_maxsw4 (ra, rb, rc, islit, lit);
2621 break;
2622 case 0x70:
2623 /* FTOIT */
2624 if (!(ctx->amask & AMASK_FIX))
2625 goto invalid_opc;
2626 if (likely(rc != 31)) {
2627 if (ra != 31)
2628 tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]);
2629 else
2630 tcg_gen_movi_i64(cpu_ir[rc], 0);
2631 }
2632 break;
2633 case 0x78:
2634 /* FTOIS */
2635 if (!(ctx->amask & AMASK_FIX))
2636 goto invalid_opc;
2637 if (rc != 31) {
2638 TCGv_i32 tmp1 = tcg_temp_new_i32();
2639 if (ra != 31)
2640 gen_helper_s_to_memory(tmp1, cpu_fir[ra]);
2641 else {
2642 TCGv tmp2 = tcg_const_i64(0);
2643 gen_helper_s_to_memory(tmp1, tmp2);
2644 tcg_temp_free(tmp2);
2645 }
2646 tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1);
2647 tcg_temp_free_i32(tmp1);
2648 }
2649 break;
2650 default:
2651 goto invalid_opc;
2652 }
2653 break;
2654 case 0x1D:
2655 /* HW_MTPR (PALcode) */
2656 #if defined (CONFIG_USER_ONLY)
2657 goto invalid_opc;
2658 #else
2659 if (!ctx->pal_mode)
2660 goto invalid_opc;
2661 else {
2662 TCGv tmp1 = tcg_const_i32(insn & 0xFF);
2663 if (ra != 31)
2664 gen_helper_mtpr(tmp1, cpu_ir[ra]);
2665 else {
2666 TCGv tmp2 = tcg_const_i64(0);
2667 gen_helper_mtpr(tmp1, tmp2);
2668 tcg_temp_free(tmp2);
2669 }
2670 tcg_temp_free(tmp1);
2671 ret = 2;
2672 }
2673 break;
2674 #endif
2675 case 0x1E:
2676 /* HW_REI (PALcode) */
2677 #if defined (CONFIG_USER_ONLY)
2678 goto invalid_opc;
2679 #else
2680 if (!ctx->pal_mode)
2681 goto invalid_opc;
2682 if (rb == 31) {
2683 /* "Old" alpha */
2684 gen_helper_hw_rei();
2685 } else {
2686 TCGv tmp;
2687
2688 if (ra != 31) {
2689 tmp = tcg_temp_new();
2690 tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51));
2691 } else
2692 tmp = tcg_const_i64(((int64_t)insn << 51) >> 51);
2693 gen_helper_hw_ret(tmp);
2694 tcg_temp_free(tmp);
2695 }
2696 ret = 2;
2697 break;
2698 #endif
2699 case 0x1F:
2700 /* HW_ST (PALcode) */
2701 #if defined (CONFIG_USER_ONLY)
2702 goto invalid_opc;
2703 #else
2704 if (!ctx->pal_mode)
2705 goto invalid_opc;
2706 else {
2707 TCGv addr, val;
2708 addr = tcg_temp_new();
2709 if (rb != 31)
2710 tcg_gen_addi_i64(addr, cpu_ir[rb], disp12);
2711 else
2712 tcg_gen_movi_i64(addr, disp12);
2713 if (ra != 31)
2714 val = cpu_ir[ra];
2715 else {
2716 val = tcg_temp_new();
2717 tcg_gen_movi_i64(val, 0);
2718 }
2719 switch ((insn >> 12) & 0xF) {
2720 case 0x0:
2721 /* Longword physical access */
2722 gen_helper_stl_raw(val, addr);
2723 break;
2724 case 0x1:
2725 /* Quadword physical access */
2726 gen_helper_stq_raw(val, addr);
2727 break;
2728 case 0x2:
2729 /* Longword physical access with lock */
2730 gen_helper_stl_c_raw(val, val, addr);
2731 break;
2732 case 0x3:
2733 /* Quadword physical access with lock */
2734 gen_helper_stq_c_raw(val, val, addr);
2735 break;
2736 case 0x4:
2737 /* Longword virtual access */
2738 gen_helper_st_virt_to_phys(addr, addr);
2739 gen_helper_stl_raw(val, addr);
2740 break;
2741 case 0x5:
2742 /* Quadword virtual access */
2743 gen_helper_st_virt_to_phys(addr, addr);
2744 gen_helper_stq_raw(val, addr);
2745 break;
2746 case 0x6:
2747 /* Invalid */
2748 goto invalid_opc;
2749 case 0x7:
2750 /* Invalid */
2751 goto invalid_opc;
2752 case 0x8:
2753 /* Invalid */
2754 goto invalid_opc;
2755 case 0x9:
2756 /* Invalid */
2757 goto invalid_opc;
2758 case 0xA:
2759 /* Invalid */
2760 goto invalid_opc;
2761 case 0xB:
2762 /* Invalid */
2763 goto invalid_opc;
2764 case 0xC:
2765 /* Longword virtual access with alternate access mode */
2766 gen_helper_set_alt_mode();
2767 gen_helper_st_virt_to_phys(addr, addr);
2768 gen_helper_stl_raw(val, addr);
2769 gen_helper_restore_mode();
2770 break;
2771 case 0xD:
2772 /* Quadword virtual access with alternate access mode */
2773 gen_helper_set_alt_mode();
2774 gen_helper_st_virt_to_phys(addr, addr);
2775 gen_helper_stl_raw(val, addr);
2776 gen_helper_restore_mode();
2777 break;
2778 case 0xE:
2779 /* Invalid */
2780 goto invalid_opc;
2781 case 0xF:
2782 /* Invalid */
2783 goto invalid_opc;
2784 }
2785 if (ra == 31)
2786 tcg_temp_free(val);
2787 tcg_temp_free(addr);
2788 }
2789 break;
2790 #endif
2791 case 0x20:
2792 /* LDF */
2793 gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0);
2794 break;
2795 case 0x21:
2796 /* LDG */
2797 gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0);
2798 break;
2799 case 0x22:
2800 /* LDS */
2801 gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0);
2802 break;
2803 case 0x23:
2804 /* LDT */
2805 gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0);
2806 break;
2807 case 0x24:
2808 /* STF */
2809 gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0, 0);
2810 break;
2811 case 0x25:
2812 /* STG */
2813 gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0, 0);
2814 break;
2815 case 0x26:
2816 /* STS */
2817 gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0, 0);
2818 break;
2819 case 0x27:
2820 /* STT */
2821 gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0, 0);
2822 break;
2823 case 0x28:
2824 /* LDL */
2825 gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0);
2826 break;
2827 case 0x29:
2828 /* LDQ */
2829 gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0);
2830 break;
2831 case 0x2A:
2832 /* LDL_L */
2833 gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0);
2834 break;
2835 case 0x2B:
2836 /* LDQ_L */
2837 gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0);
2838 break;
2839 case 0x2C:
2840 /* STL */
2841 gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0, 0);
2842 break;
2843 case 0x2D:
2844 /* STQ */
2845 gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0, 0);
2846 break;
2847 case 0x2E:
2848 /* STL_C */
2849 gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0, 1);
2850 break;
2851 case 0x2F:
2852 /* STQ_C */
2853 gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0, 1);
2854 break;
2855 case 0x30:
2856 /* BR */
2857 if (ra != 31)
2858 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2859 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2860 ret = 1;
2861 break;
2862 case 0x31: /* FBEQ */
2863 gen_fbcond(ctx, TCG_COND_EQ, ra, disp21);
2864 ret = 1;
2865 break;
2866 case 0x32: /* FBLT */
2867 gen_fbcond(ctx, TCG_COND_LT, ra, disp21);
2868 ret = 1;
2869 break;
2870 case 0x33: /* FBLE */
2871 gen_fbcond(ctx, TCG_COND_LE, ra, disp21);
2872 ret = 1;
2873 break;
2874 case 0x34:
2875 /* BSR */
2876 if (ra != 31)
2877 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2878 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2879 ret = 1;
2880 break;
2881 case 0x35: /* FBNE */
2882 gen_fbcond(ctx, TCG_COND_NE, ra, disp21);
2883 ret = 1;
2884 break;
2885 case 0x36: /* FBGE */
2886 gen_fbcond(ctx, TCG_COND_GE, ra, disp21);
2887 ret = 1;
2888 break;
2889 case 0x37: /* FBGT */
2890 gen_fbcond(ctx, TCG_COND_GT, ra, disp21);
2891 ret = 1;
2892 break;
2893 case 0x38:
2894 /* BLBC */
2895 gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 1);
2896 ret = 1;
2897 break;
2898 case 0x39:
2899 /* BEQ */
2900 gen_bcond(ctx, TCG_COND_EQ, ra, disp21, 0);
2901 ret = 1;
2902 break;
2903 case 0x3A:
2904 /* BLT */
2905 gen_bcond(ctx, TCG_COND_LT, ra, disp21, 0);
2906 ret = 1;
2907 break;
2908 case 0x3B:
2909 /* BLE */
2910 gen_bcond(ctx, TCG_COND_LE, ra, disp21, 0);
2911 ret = 1;
2912 break;
2913 case 0x3C:
2914 /* BLBS */
2915 gen_bcond(ctx, TCG_COND_NE, ra, disp21, 1);
2916 ret = 1;
2917 break;
2918 case 0x3D:
2919 /* BNE */
2920 gen_bcond(ctx, TCG_COND_NE, ra, disp21, 0);
2921 ret = 1;
2922 break;
2923 case 0x3E:
2924 /* BGE */
2925 gen_bcond(ctx, TCG_COND_GE, ra, disp21, 0);
2926 ret = 1;
2927 break;
2928 case 0x3F:
2929 /* BGT */
2930 gen_bcond(ctx, TCG_COND_GT, ra, disp21, 0);
2931 ret = 1;
2932 break;
2933 invalid_opc:
2934 gen_invalid(ctx);
2935 ret = 3;
2936 break;
2937 }
2938
2939 return ret;
2940 }
2941
2942 static inline void gen_intermediate_code_internal(CPUState *env,
2943 TranslationBlock *tb,
2944 int search_pc)
2945 {
2946 DisasContext ctx, *ctxp = &ctx;
2947 target_ulong pc_start;
2948 uint32_t insn;
2949 uint16_t *gen_opc_end;
2950 CPUBreakpoint *bp;
2951 int j, lj = -1;
2952 int ret;
2953 int num_insns;
2954 int max_insns;
2955
2956 pc_start = tb->pc;
2957 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2958 ctx.pc = pc_start;
2959 ctx.amask = env->amask;
2960 ctx.env = env;
2961 #if defined (CONFIG_USER_ONLY)
2962 ctx.mem_idx = 0;
2963 #else
2964 ctx.mem_idx = ((env->ps >> 3) & 3);
2965 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
2966 #endif
2967
2968 /* ??? Every TB begins with unset rounding mode, to be initialized on
2969 the first fp insn of the TB. Alternately we could define a proper
2970 default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure
2971 to reset the FP_STATUS to that default at the end of any TB that
2972 changes the default. We could even (gasp) dynamiclly figure out
2973 what default would be most efficient given the running program. */
2974 ctx.tb_rm = -1;
2975 /* Similarly for flush-to-zero. */
2976 ctx.tb_ftz = -1;
2977
2978 num_insns = 0;
2979 max_insns = tb->cflags & CF_COUNT_MASK;
2980 if (max_insns == 0)
2981 max_insns = CF_COUNT_MASK;
2982
2983 gen_icount_start();
2984 for (ret = 0; ret == 0;) {
2985 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
2986 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
2987 if (bp->pc == ctx.pc) {
2988 gen_excp(&ctx, EXCP_DEBUG, 0);
2989 break;
2990 }
2991 }
2992 }
2993 if (search_pc) {
2994 j = gen_opc_ptr - gen_opc_buf;
2995 if (lj < j) {
2996 lj++;
2997 while (lj < j)
2998 gen_opc_instr_start[lj++] = 0;
2999 }
3000 gen_opc_pc[lj] = ctx.pc;
3001 gen_opc_instr_start[lj] = 1;
3002 gen_opc_icount[lj] = num_insns;
3003 }
3004 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3005 gen_io_start();
3006 insn = ldl_code(ctx.pc);
3007 num_insns++;
3008
3009 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
3010 tcg_gen_debug_insn_start(ctx.pc);
3011 }
3012
3013 ctx.pc += 4;
3014 ret = translate_one(ctxp, insn);
3015 if (ret != 0)
3016 break;
3017 /* if we reach a page boundary or are single stepping, stop
3018 * generation
3019 */
3020 if (env->singlestep_enabled) {
3021 gen_excp(&ctx, EXCP_DEBUG, 0);
3022 break;
3023 }
3024
3025 if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
3026 break;
3027
3028 if (gen_opc_ptr >= gen_opc_end)
3029 break;
3030
3031 if (num_insns >= max_insns)
3032 break;
3033
3034 if (singlestep) {
3035 break;
3036 }
3037 }
3038 if (ret != 1 && ret != 3) {
3039 tcg_gen_movi_i64(cpu_pc, ctx.pc);
3040 }
3041 if (tb->cflags & CF_LAST_IO)
3042 gen_io_end();
3043 /* Generate the return instruction */
3044 tcg_gen_exit_tb(0);
3045 gen_icount_end(tb, num_insns);
3046 *gen_opc_ptr = INDEX_op_end;
3047 if (search_pc) {
3048 j = gen_opc_ptr - gen_opc_buf;
3049 lj++;
3050 while (lj <= j)
3051 gen_opc_instr_start[lj++] = 0;
3052 } else {
3053 tb->size = ctx.pc - pc_start;
3054 tb->icount = num_insns;
3055 }
3056 #ifdef DEBUG_DISAS
3057 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3058 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3059 log_target_disas(pc_start, ctx.pc - pc_start, 1);
3060 qemu_log("\n");
3061 }
3062 #endif
3063 }
3064
3065 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3066 {
3067 gen_intermediate_code_internal(env, tb, 0);
3068 }
3069
3070 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3071 {
3072 gen_intermediate_code_internal(env, tb, 1);
3073 }
3074
3075 struct cpu_def_t {
3076 const char *name;
3077 int implver, amask;
3078 };
3079
3080 static const struct cpu_def_t cpu_defs[] = {
3081 { "ev4", IMPLVER_2106x, 0 },
3082 { "ev5", IMPLVER_21164, 0 },
3083 { "ev56", IMPLVER_21164, AMASK_BWX },
3084 { "pca56", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
3085 { "ev6", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
3086 { "ev67", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
3087 | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
3088 { "ev68", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
3089 | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), },
3090 { "21064", IMPLVER_2106x, 0 },
3091 { "21164", IMPLVER_21164, 0 },
3092 { "21164a", IMPLVER_21164, AMASK_BWX },
3093 { "21164pc", IMPLVER_21164, AMASK_BWX | AMASK_MVI },
3094 { "21264", IMPLVER_21264, AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP },
3095 { "21264a", IMPLVER_21264, (AMASK_BWX | AMASK_FIX | AMASK_CIX
3096 | AMASK_MVI | AMASK_TRAP | AMASK_PREFETCH), }
3097 };
3098
3099 CPUAlphaState * cpu_alpha_init (const char *cpu_model)
3100 {
3101 CPUAlphaState *env;
3102 int implver, amask, i, max;
3103
3104 env = qemu_mallocz(sizeof(CPUAlphaState));
3105 cpu_exec_init(env);
3106 alpha_translate_init();
3107 tlb_flush(env, 1);
3108
3109 /* Default to ev67; no reason not to emulate insns by default. */
3110 implver = IMPLVER_21264;
3111 amask = (AMASK_BWX | AMASK_FIX | AMASK_CIX | AMASK_MVI
3112 | AMASK_TRAP | AMASK_PREFETCH);
3113
3114 max = ARRAY_SIZE(cpu_defs);
3115 for (i = 0; i < max; i++) {
3116 if (strcmp (cpu_model, cpu_defs[i].name) == 0) {
3117 implver = cpu_defs[i].implver;
3118 amask = cpu_defs[i].amask;
3119 break;
3120 }
3121 }
3122 env->implver = implver;
3123 env->amask = amask;
3124
3125 env->ps = 0x1F00;
3126 #if defined (CONFIG_USER_ONLY)
3127 env->ps |= 1 << 3;
3128 cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD
3129 | FPCR_UNFD | FPCR_INED | FPCR_DNOD));
3130 #else
3131 pal_init(env);
3132 #endif
3133
3134 /* Initialize IPR */
3135 #if defined (CONFIG_USER_ONLY)
3136 env->ipr[IPR_EXC_ADDR] = 0;
3137 env->ipr[IPR_EXC_SUM] = 0;
3138 env->ipr[IPR_EXC_MASK] = 0;
3139 #else
3140 {
3141 uint64_t hwpcb;
3142 hwpcb = env->ipr[IPR_PCBB];
3143 env->ipr[IPR_ASN] = 0;
3144 env->ipr[IPR_ASTEN] = 0;
3145 env->ipr[IPR_ASTSR] = 0;
3146 env->ipr[IPR_DATFX] = 0;
3147 /* XXX: fix this */
3148 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
3149 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
3150 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
3151 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
3152 env->ipr[IPR_FEN] = 0;
3153 env->ipr[IPR_IPL] = 31;
3154 env->ipr[IPR_MCES] = 0;
3155 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
3156 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
3157 env->ipr[IPR_SISR] = 0;
3158 env->ipr[IPR_VIRBND] = -1ULL;
3159 }
3160 #endif
3161
3162 qemu_init_vcpu(env);
3163 return env;
3164 }
3165
3166 void gen_pc_load(CPUState *env, TranslationBlock *tb,
3167 unsigned long searched_pc, int pc_pos, void *puc)
3168 {
3169 env->pc = gen_opc_pc[pc_pos];
3170 }
Qemu copy for testing