]> git.proxmox.com Git - qemu.git/blob - target-alpha/translate.c
projects / qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
alpha: fix lit sign
[qemu.git] / target-alpha / translate.c
1 /*
2 * Alpha emulation cpu translation for qemu.
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #include <stdint.h>
22 #include <stdlib.h>
23 #include <stdio.h>
24
25 #include "cpu.h"
26 #include "exec-all.h"
27 #include "disas.h"
28 #include "helper.h"
29 #include "tcg-op.h"
30 #include "qemu-common.h"
31
32 #define DO_SINGLE_STEP
33 #define GENERATE_NOP
34 #define ALPHA_DEBUG_DISAS
35 #define DO_TB_FLUSH
36
37 typedef struct DisasContext DisasContext;
38 struct DisasContext {
39 uint64_t pc;
40 int mem_idx;
41 #if !defined (CONFIG_USER_ONLY)
42 int pal_mode;
43 #endif
44 uint32_t amask;
45 };
46
47 /* global register indexes */
48 static TCGv cpu_env;
49 static TCGv cpu_ir[31];
50 static TCGv cpu_pc;
51
52 /* dyngen register indexes */
53 static TCGv cpu_T[3];
54
55 /* register names */
56 static char cpu_reg_names[5*31];
57
58 #include "gen-icount.h"
59
60 static void alpha_translate_init(void)
61 {
62 int i;
63 char *p;
64 static int done_init = 0;
65
66 if (done_init)
67 return;
68
69 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
70
71 #if TARGET_LONG_BITS > HOST_LONG_BITS
72 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
73 offsetof(CPUState, t0), "T0");
74 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
75 offsetof(CPUState, t1), "T1");
76 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
77 offsetof(CPUState, t2), "T2");
78 #else
79 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");
80 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");
81 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2");
82 #endif
83
84 p = cpu_reg_names;
85 for (i = 0; i < 31; i++) {
86 sprintf(p, "ir%d", i);
87 cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
88 offsetof(CPUState, ir[i]), p);
89 p += 4;
90 }
91
92 cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
93 offsetof(CPUState, pc), "pc");
94
95 /* register helpers */
96 #undef DEF_HELPER
97 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
98 #include "helper.h"
99
100 done_init = 1;
101 }
102
103 static always_inline void gen_op_nop (void)
104 {
105 #if defined(GENERATE_NOP)
106 gen_op_no_op();
107 #endif
108 }
109
110 #define GEN32(func, NAME) \
111 static GenOpFunc *NAME ## _table [32] = { \
112 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
113 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
114 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
115 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
116 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
117 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
118 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
119 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
120 }; \
121 static always_inline void func (int n) \
122 { \
123 NAME ## _table[n](); \
124 }
125
126 /* IR moves */
127 /* Special hacks for ir31 */
128 #define gen_op_cmov_ir31 gen_op_nop
129 GEN32(gen_op_cmov_ir, gen_op_cmov_ir);
130
131 /* FIR moves */
132 /* Special hacks for fir31 */
133 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
134 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
135 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
136 #define gen_op_store_FT0_fir31 gen_op_nop
137 #define gen_op_store_FT1_fir31 gen_op_nop
138 #define gen_op_store_FT2_fir31 gen_op_nop
139 #define gen_op_cmov_fir31 gen_op_nop
140 GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
141 GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
142 GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
143 GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
144 GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
145 GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
146 GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
147
148 static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
149 {
150 switch (Tn) {
151 case 0:
152 gen_op_load_FT0_fir(firn);
153 break;
154 case 1:
155 gen_op_load_FT1_fir(firn);
156 break;
157 case 2:
158 gen_op_load_FT2_fir(firn);
159 break;
160 }
161 }
162
163 static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
164 {
165 switch (Tn) {
166 case 0:
167 gen_op_store_FT0_fir(firn);
168 break;
169 case 1:
170 gen_op_store_FT1_fir(firn);
171 break;
172 case 2:
173 gen_op_store_FT2_fir(firn);
174 break;
175 }
176 }
177
178 /* Memory moves */
179 #if defined(CONFIG_USER_ONLY)
180 #define OP_LD_TABLE(width) \
181 static GenOpFunc *gen_op_ld##width[] = { \
182 &gen_op_ld##width##_raw, \
183 }
184 #define OP_ST_TABLE(width) \
185 static GenOpFunc *gen_op_st##width[] = { \
186 &gen_op_st##width##_raw, \
187 }
188 #else
189 #define OP_LD_TABLE(width) \
190 static GenOpFunc *gen_op_ld##width[] = { \
191 &gen_op_ld##width##_kernel, \
192 &gen_op_ld##width##_executive, \
193 &gen_op_ld##width##_supervisor, \
194 &gen_op_ld##width##_user, \
195 }
196 #define OP_ST_TABLE(width) \
197 static GenOpFunc *gen_op_st##width[] = { \
198 &gen_op_st##width##_kernel, \
199 &gen_op_st##width##_executive, \
200 &gen_op_st##width##_supervisor, \
201 &gen_op_st##width##_user, \
202 }
203 #endif
204
205 #define GEN_LD(width) \
206 OP_LD_TABLE(width); \
207 static always_inline void gen_ld##width (DisasContext *ctx) \
208 { \
209 (*gen_op_ld##width[ctx->mem_idx])(); \
210 }
211
212 #define GEN_ST(width) \
213 OP_ST_TABLE(width); \
214 static always_inline void gen_st##width (DisasContext *ctx) \
215 { \
216 (*gen_op_st##width[ctx->mem_idx])(); \
217 }
218
219 GEN_LD(bu);
220 GEN_ST(b);
221 GEN_LD(wu);
222 GEN_ST(w);
223 GEN_LD(l);
224 GEN_ST(l);
225 GEN_LD(q);
226 GEN_ST(q);
227 GEN_LD(q_u);
228 GEN_ST(q_u);
229 GEN_LD(l_l);
230 GEN_ST(l_c);
231 GEN_LD(q_l);
232 GEN_ST(q_c);
233
234 #if 0 /* currently unused */
235 GEN_LD(f);
236 GEN_ST(f);
237 GEN_LD(g);
238 GEN_ST(g);
239 #endif /* 0 */
240 GEN_LD(s);
241 GEN_ST(s);
242 GEN_LD(t);
243 GEN_ST(t);
244
245 static always_inline void _gen_op_bcond (DisasContext *ctx)
246 {
247 #if 0 // Qemu does not know how to do this...
248 gen_op_bcond(ctx->pc);
249 #else
250 gen_op_bcond(ctx->pc >> 32, ctx->pc);
251 #endif
252 }
253
254 static always_inline void gen_excp (DisasContext *ctx,
255 int exception, int error_code)
256 {
257 tcg_gen_movi_i64(cpu_pc, ctx->pc);
258 gen_op_excp(exception, error_code);
259 }
260
261 static always_inline void gen_invalid (DisasContext *ctx)
262 {
263 gen_excp(ctx, EXCP_OPCDEC, 0);
264 }
265
266 static always_inline void gen_load_mem (DisasContext *ctx,
267 void (*gen_load_op)(DisasContext *ctx),
268 int ra, int rb, int32_t disp16,
269 int clear)
270 {
271 if (ra == 31 && disp16 == 0) {
272 /* UNOP */
273 gen_op_nop();
274 } else {
275 if (rb != 31)
276 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
277 else
278 tcg_gen_movi_i64(cpu_T[0], disp16);
279 if (clear)
280 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
281 (*gen_load_op)(ctx);
282 if (ra != 31)
283 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
284 }
285 }
286
287 static always_inline void gen_store_mem (DisasContext *ctx,
288 void (*gen_store_op)(DisasContext *ctx),
289 int ra, int rb, int32_t disp16,
290 int clear)
291 {
292 if (rb != 31)
293 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
294 else
295 tcg_gen_movi_i64(cpu_T[0], disp16);
296 if (clear)
297 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
298 if (ra != 31)
299 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
300 else
301 tcg_gen_movi_i64(cpu_T[1], 0);
302 (*gen_store_op)(ctx);
303 }
304
305 static always_inline void gen_load_fmem (DisasContext *ctx,
306 void (*gen_load_fop)(DisasContext *ctx),
307 int ra, int rb, int32_t disp16)
308 {
309 if (rb != 31)
310 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
311 else
312 tcg_gen_movi_i64(cpu_T[0], disp16);
313 (*gen_load_fop)(ctx);
314 gen_store_fir(ctx, ra, 1);
315 }
316
317 static always_inline void gen_store_fmem (DisasContext *ctx,
318 void (*gen_store_fop)(DisasContext *ctx),
319 int ra, int rb, int32_t disp16)
320 {
321 if (rb != 31)
322 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
323 else
324 tcg_gen_movi_i64(cpu_T[0], disp16);
325 gen_load_fir(ctx, ra, 1);
326 (*gen_store_fop)(ctx);
327 }
328
329 static always_inline void gen_bcond (DisasContext *ctx,
330 void (*gen_test_op)(void),
331 int ra, int32_t disp16)
332 {
333 tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));
334 if (ra != 31)
335 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
336 else
337 tcg_gen_movi_i64(cpu_T[0], 0);
338 (*gen_test_op)();
339 _gen_op_bcond(ctx);
340 }
341
342 static always_inline void gen_fbcond (DisasContext *ctx,
343 void (*gen_test_op)(void),
344 int ra, int32_t disp16)
345 {
346 tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));
347 gen_load_fir(ctx, ra, 0);
348 (*gen_test_op)();
349 _gen_op_bcond(ctx);
350 }
351
352 static always_inline void gen_arith2 (DisasContext *ctx,
353 void (*gen_arith_op)(void),
354 int rb, int rc, int islit, uint8_t lit)
355 {
356 if (islit)
357 tcg_gen_movi_i64(cpu_T[0], lit);
358 else if (rb != 31)
359 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
360 else
361 tcg_gen_movi_i64(cpu_T[0], 0);
362 (*gen_arith_op)();
363 if (rc != 31)
364 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
365 }
366
367 static always_inline void gen_arith3 (DisasContext *ctx,
368 void (*gen_arith_op)(void),
369 int ra, int rb, int rc,
370 int islit, uint8_t lit)
371 {
372 if (ra != 31)
373 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
374 else
375 tcg_gen_movi_i64(cpu_T[0], 0);
376 if (islit)
377 tcg_gen_movi_i64(cpu_T[1], lit);
378 else if (rb != 31)
379 tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
380 else
381 tcg_gen_movi_i64(cpu_T[1], 0);
382 (*gen_arith_op)();
383 if (rc != 31)
384 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
385 }
386
387 static always_inline void gen_cmov (DisasContext *ctx,
388 void (*gen_test_op)(void),
389 int ra, int rb, int rc,
390 int islit, uint8_t lit)
391 {
392 if (ra != 31)
393 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
394 else
395 tcg_gen_movi_i64(cpu_T[0], 0);
396 if (islit)
397 tcg_gen_movi_i64(cpu_T[1], lit);
398 else if (rb != 31)
399 tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
400 else
401 tcg_gen_movi_i64(cpu_T[1], 0);
402 (*gen_test_op)();
403 gen_op_cmov_ir(rc);
404 }
405
406 static always_inline void gen_farith2 (DisasContext *ctx,
407 void (*gen_arith_fop)(void),
408 int rb, int rc)
409 {
410 gen_load_fir(ctx, rb, 0);
411 (*gen_arith_fop)();
412 gen_store_fir(ctx, rc, 0);
413 }
414
415 static always_inline void gen_farith3 (DisasContext *ctx,
416 void (*gen_arith_fop)(void),
417 int ra, int rb, int rc)
418 {
419 gen_load_fir(ctx, ra, 0);
420 gen_load_fir(ctx, rb, 1);
421 (*gen_arith_fop)();
422 gen_store_fir(ctx, rc, 0);
423 }
424
425 static always_inline void gen_fcmov (DisasContext *ctx,
426 void (*gen_test_fop)(void),
427 int ra, int rb, int rc)
428 {
429 gen_load_fir(ctx, ra, 0);
430 gen_load_fir(ctx, rb, 1);
431 (*gen_test_fop)();
432 gen_op_cmov_fir(rc);
433 }
434
435 static always_inline void gen_fti (DisasContext *ctx,
436 void (*gen_move_fop)(void),
437 int ra, int rc)
438 {
439 gen_load_fir(ctx, rc, 0);
440 (*gen_move_fop)();
441 if (ra != 31)
442 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
443 }
444
445 static always_inline void gen_itf (DisasContext *ctx,
446 void (*gen_move_fop)(void),
447 int ra, int rc)
448 {
449 if (ra != 31)
450 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
451 else
452 tcg_gen_movi_i64(cpu_T[0], 0);
453 (*gen_move_fop)();
454 gen_store_fir(ctx, rc, 0);
455 }
456
457 static always_inline void gen_s4addl (void)
458 {
459 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
460 gen_op_addl();
461 }
462
463 static always_inline void gen_s4subl (void)
464 {
465 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
466 gen_op_subl();
467 }
468
469 static always_inline void gen_s8addl (void)
470 {
471 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3);
472 gen_op_addl();
473 }
474
475 static always_inline void gen_s8subl (void)
476 {
477 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3);
478 gen_op_subl();
479 }
480
481 static always_inline void gen_s4addq (void)
482 {
483 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
484 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
485 }
486
487 static always_inline void gen_s4subq (void)
488 {
489 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 2);
490 tcg_gen_sub_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
491 }
492
493 static always_inline void gen_s8addq (void)
494 {
495 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3);
496 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
497 }
498
499 static always_inline void gen_s8subq (void)
500 {
501 tcg_gen_shli_i64(cpu_T[0], cpu_T[0], 3);
502 tcg_gen_sub_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
503 }
504
505 static always_inline void gen_amask (void)
506 {
507 gen_op_load_amask();
508 gen_op_bic();
509 }
510
511 static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
512 {
513 uint32_t palcode;
514 int32_t disp21, disp16, disp12;
515 uint16_t fn11, fn16;
516 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
517 int8_t lit;
518 int ret;
519
520 /* Decode all instruction fields */
521 opc = insn >> 26;
522 ra = (insn >> 21) & 0x1F;
523 rb = (insn >> 16) & 0x1F;
524 rc = insn & 0x1F;
525 sbz = (insn >> 13) & 0x07;
526 islit = (insn >> 12) & 1;
527 lit = (insn >> 13) & 0xFF;
528 palcode = insn & 0x03FFFFFF;
529 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
530 disp16 = (int16_t)(insn & 0x0000FFFF);
531 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
532 fn16 = insn & 0x0000FFFF;
533 fn11 = (insn >> 5) & 0x000007FF;
534 fpfn = fn11 & 0x3F;
535 fn7 = (insn >> 5) & 0x0000007F;
536 fn2 = (insn >> 5) & 0x00000003;
537 ret = 0;
538 #if defined ALPHA_DEBUG_DISAS
539 if (logfile != NULL) {
540 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
541 opc, ra, rb, rc, disp16);
542 }
543 #endif
544 switch (opc) {
545 case 0x00:
546 /* CALL_PAL */
547 if (palcode >= 0x80 && palcode < 0xC0) {
548 /* Unprivileged PAL call */
549 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
550 #if !defined (CONFIG_USER_ONLY)
551 } else if (palcode < 0x40) {
552 /* Privileged PAL code */
553 if (ctx->mem_idx & 1)
554 goto invalid_opc;
555 else
556 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
557 #endif
558 } else {
559 /* Invalid PAL call */
560 goto invalid_opc;
561 }
562 ret = 3;
563 break;
564 case 0x01:
565 /* OPC01 */
566 goto invalid_opc;
567 case 0x02:
568 /* OPC02 */
569 goto invalid_opc;
570 case 0x03:
571 /* OPC03 */
572 goto invalid_opc;
573 case 0x04:
574 /* OPC04 */
575 goto invalid_opc;
576 case 0x05:
577 /* OPC05 */
578 goto invalid_opc;
579 case 0x06:
580 /* OPC06 */
581 goto invalid_opc;
582 case 0x07:
583 /* OPC07 */
584 goto invalid_opc;
585 case 0x08:
586 /* LDA */
587 if (ra != 31) {
588 if (rb != 31)
589 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
590 else
591 tcg_gen_movi_i64(cpu_ir[ra], disp16);
592 }
593 break;
594 case 0x09:
595 /* LDAH */
596 if (ra != 31) {
597 if (rb != 31)
598 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
599 else
600 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
601 }
602 break;
603 case 0x0A:
604 /* LDBU */
605 if (!(ctx->amask & AMASK_BWX))
606 goto invalid_opc;
607 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
608 break;
609 case 0x0B:
610 /* LDQ_U */
611 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
612 break;
613 case 0x0C:
614 /* LDWU */
615 if (!(ctx->amask & AMASK_BWX))
616 goto invalid_opc;
617 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
618 break;
619 case 0x0D:
620 /* STW */
621 if (!(ctx->amask & AMASK_BWX))
622 goto invalid_opc;
623 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
624 break;
625 case 0x0E:
626 /* STB */
627 if (!(ctx->amask & AMASK_BWX))
628 goto invalid_opc;
629 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
630 break;
631 case 0x0F:
632 /* STQ_U */
633 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
634 break;
635 case 0x10:
636 switch (fn7) {
637 case 0x00:
638 /* ADDL */
639 gen_arith3(ctx, &gen_op_addl, ra, rb, rc, islit, lit);
640 break;
641 case 0x02:
642 /* S4ADDL */
643 gen_arith3(ctx, &gen_s4addl, ra, rb, rc, islit, lit);
644 break;
645 case 0x09:
646 /* SUBL */
647 gen_arith3(ctx, &gen_op_subl, ra, rb, rc, islit, lit);
648 break;
649 case 0x0B:
650 /* S4SUBL */
651 gen_arith3(ctx, &gen_s4subl, ra, rb, rc, islit, lit);
652 break;
653 case 0x0F:
654 /* CMPBGE */
655 gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
656 break;
657 case 0x12:
658 /* S8ADDL */
659 gen_arith3(ctx, &gen_s8addl, ra, rb, rc, islit, lit);
660 break;
661 case 0x1B:
662 /* S8SUBL */
663 gen_arith3(ctx, &gen_s8subl, ra, rb, rc, islit, lit);
664 break;
665 case 0x1D:
666 /* CMPULT */
667 gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit);
668 break;
669 case 0x20:
670 /* ADDQ */
671 gen_arith3(ctx, &gen_op_addq, ra, rb, rc, islit, lit);
672 break;
673 case 0x22:
674 /* S4ADDQ */
675 gen_arith3(ctx, &gen_s4addq, ra, rb, rc, islit, lit);
676 break;
677 case 0x29:
678 /* SUBQ */
679 gen_arith3(ctx, &gen_op_subq, ra, rb, rc, islit, lit);
680 break;
681 case 0x2B:
682 /* S4SUBQ */
683 gen_arith3(ctx, &gen_s4subq, ra, rb, rc, islit, lit);
684 break;
685 case 0x2D:
686 /* CMPEQ */
687 gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit);
688 break;
689 case 0x32:
690 /* S8ADDQ */
691 gen_arith3(ctx, &gen_s8addq, ra, rb, rc, islit, lit);
692 break;
693 case 0x3B:
694 /* S8SUBQ */
695 gen_arith3(ctx, &gen_s8subq, ra, rb, rc, islit, lit);
696 break;
697 case 0x3D:
698 /* CMPULE */
699 gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit);
700 break;
701 case 0x40:
702 /* ADDL/V */
703 gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
704 break;
705 case 0x49:
706 /* SUBL/V */
707 gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
708 break;
709 case 0x4D:
710 /* CMPLT */
711 gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit);
712 break;
713 case 0x60:
714 /* ADDQ/V */
715 gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
716 break;
717 case 0x69:
718 /* SUBQ/V */
719 gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
720 break;
721 case 0x6D:
722 /* CMPLE */
723 gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit);
724 break;
725 default:
726 goto invalid_opc;
727 }
728 break;
729 case 0x11:
730 switch (fn7) {
731 case 0x00:
732 /* AND */
733 gen_arith3(ctx, &gen_op_and, ra, rb, rc, islit, lit);
734 break;
735 case 0x08:
736 /* BIC */
737 gen_arith3(ctx, &gen_op_bic, ra, rb, rc, islit, lit);
738 break;
739 case 0x14:
740 /* CMOVLBS */
741 gen_cmov(ctx, &gen_op_cmplbs, ra, rb, rc, islit, lit);
742 break;
743 case 0x16:
744 /* CMOVLBC */
745 gen_cmov(ctx, &gen_op_cmplbc, ra, rb, rc, islit, lit);
746 break;
747 case 0x20:
748 /* BIS */
749 if (ra == rb || ra == 31 || rb == 31) {
750 if (ra == 31 && rc == 31) {
751 /* NOP */
752 gen_op_nop();
753 } else {
754 /* MOV */
755 if (rc != 31) {
756 if (rb != 31)
757 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
758 else
759 tcg_gen_movi_i64(cpu_ir[rc], 0);
760 }
761 }
762 } else {
763 gen_arith3(ctx, &gen_op_bis, ra, rb, rc, islit, lit);
764 }
765 break;
766 case 0x24:
767 /* CMOVEQ */
768 gen_cmov(ctx, &gen_op_cmpeqz, ra, rb, rc, islit, lit);
769 break;
770 case 0x26:
771 /* CMOVNE */
772 gen_cmov(ctx, &gen_op_cmpnez, ra, rb, rc, islit, lit);
773 break;
774 case 0x28:
775 /* ORNOT */
776 gen_arith3(ctx, &gen_op_ornot, ra, rb, rc, islit, lit);
777 break;
778 case 0x40:
779 /* XOR */
780 gen_arith3(ctx, &gen_op_xor, ra, rb, rc, islit, lit);
781 break;
782 case 0x44:
783 /* CMOVLT */
784 gen_cmov(ctx, &gen_op_cmpltz, ra, rb, rc, islit, lit);
785 break;
786 case 0x46:
787 /* CMOVGE */
788 gen_cmov(ctx, &gen_op_cmpgez, ra, rb, rc, islit, lit);
789 break;
790 case 0x48:
791 /* EQV */
792 gen_arith3(ctx, &gen_op_eqv, ra, rb, rc, islit, lit);
793 break;
794 case 0x61:
795 /* AMASK */
796 gen_arith2(ctx, &gen_amask, rb, rc, islit, lit);
797 break;
798 case 0x64:
799 /* CMOVLE */
800 gen_cmov(ctx, &gen_op_cmplez, ra, rb, rc, islit, lit);
801 break;
802 case 0x66:
803 /* CMOVGT */
804 gen_cmov(ctx, &gen_op_cmpgtz, ra, rb, rc, islit, lit);
805 break;
806 case 0x6C:
807 /* IMPLVER */
808 gen_op_load_implver();
809 if (rc != 31)
810 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
811 break;
812 default:
813 goto invalid_opc;
814 }
815 break;
816 case 0x12:
817 switch (fn7) {
818 case 0x02:
819 /* MSKBL */
820 gen_arith3(ctx, &gen_op_mskbl, ra, rb, rc, islit, lit);
821 break;
822 case 0x06:
823 /* EXTBL */
824 gen_arith3(ctx, &gen_op_extbl, ra, rb, rc, islit, lit);
825 break;
826 case 0x0B:
827 /* INSBL */
828 gen_arith3(ctx, &gen_op_insbl, ra, rb, rc, islit, lit);
829 break;
830 case 0x12:
831 /* MSKWL */
832 gen_arith3(ctx, &gen_op_mskwl, ra, rb, rc, islit, lit);
833 break;
834 case 0x16:
835 /* EXTWL */
836 gen_arith3(ctx, &gen_op_extwl, ra, rb, rc, islit, lit);
837 break;
838 case 0x1B:
839 /* INSWL */
840 gen_arith3(ctx, &gen_op_inswl, ra, rb, rc, islit, lit);
841 break;
842 case 0x22:
843 /* MSKLL */
844 gen_arith3(ctx, &gen_op_mskll, ra, rb, rc, islit, lit);
845 break;
846 case 0x26:
847 /* EXTLL */
848 gen_arith3(ctx, &gen_op_extll, ra, rb, rc, islit, lit);
849 break;
850 case 0x2B:
851 /* INSLL */
852 gen_arith3(ctx, &gen_op_insll, ra, rb, rc, islit, lit);
853 break;
854 case 0x30:
855 /* ZAP */
856 gen_arith3(ctx, &gen_op_zap, ra, rb, rc, islit, lit);
857 break;
858 case 0x31:
859 /* ZAPNOT */
860 gen_arith3(ctx, &gen_op_zapnot, ra, rb, rc, islit, lit);
861 break;
862 case 0x32:
863 /* MSKQL */
864 gen_arith3(ctx, &gen_op_mskql, ra, rb, rc, islit, lit);
865 break;
866 case 0x34:
867 /* SRL */
868 gen_arith3(ctx, &gen_op_srl, ra, rb, rc, islit, lit);
869 break;
870 case 0x36:
871 /* EXTQL */
872 gen_arith3(ctx, &gen_op_extql, ra, rb, rc, islit, lit);
873 break;
874 case 0x39:
875 /* SLL */
876 gen_arith3(ctx, &gen_op_sll, ra, rb, rc, islit, lit);
877 break;
878 case 0x3B:
879 /* INSQL */
880 gen_arith3(ctx, &gen_op_insql, ra, rb, rc, islit, lit);
881 break;
882 case 0x3C:
883 /* SRA */
884 gen_arith3(ctx, &gen_op_sra, ra, rb, rc, islit, lit);
885 break;
886 case 0x52:
887 /* MSKWH */
888 gen_arith3(ctx, &gen_op_mskwh, ra, rb, rc, islit, lit);
889 break;
890 case 0x57:
891 /* INSWH */
892 gen_arith3(ctx, &gen_op_inswh, ra, rb, rc, islit, lit);
893 break;
894 case 0x5A:
895 /* EXTWH */
896 gen_arith3(ctx, &gen_op_extwh, ra, rb, rc, islit, lit);
897 break;
898 case 0x62:
899 /* MSKLH */
900 gen_arith3(ctx, &gen_op_msklh, ra, rb, rc, islit, lit);
901 break;
902 case 0x67:
903 /* INSLH */
904 gen_arith3(ctx, &gen_op_inslh, ra, rb, rc, islit, lit);
905 break;
906 case 0x6A:
907 /* EXTLH */
908 gen_arith3(ctx, &gen_op_extlh, ra, rb, rc, islit, lit);
909 break;
910 case 0x72:
911 /* MSKQH */
912 gen_arith3(ctx, &gen_op_mskqh, ra, rb, rc, islit, lit);
913 break;
914 case 0x77:
915 /* INSQH */
916 gen_arith3(ctx, &gen_op_insqh, ra, rb, rc, islit, lit);
917 break;
918 case 0x7A:
919 /* EXTQH */
920 gen_arith3(ctx, &gen_op_extqh, ra, rb, rc, islit, lit);
921 break;
922 default:
923 goto invalid_opc;
924 }
925 break;
926 case 0x13:
927 switch (fn7) {
928 case 0x00:
929 /* MULL */
930 gen_arith3(ctx, &gen_op_mull, ra, rb, rc, islit, lit);
931 break;
932 case 0x20:
933 /* MULQ */
934 gen_arith3(ctx, &gen_op_mulq, ra, rb, rc, islit, lit);
935 break;
936 case 0x30:
937 /* UMULH */
938 gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
939 break;
940 case 0x40:
941 /* MULL/V */
942 gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
943 break;
944 case 0x60:
945 /* MULQ/V */
946 gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
947 break;
948 default:
949 goto invalid_opc;
950 }
951 break;
952 case 0x14:
953 switch (fpfn) { /* f11 & 0x3F */
954 case 0x04:
955 /* ITOFS */
956 if (!(ctx->amask & AMASK_FIX))
957 goto invalid_opc;
958 gen_itf(ctx, &gen_op_itofs, ra, rc);
959 break;
960 case 0x0A:
961 /* SQRTF */
962 if (!(ctx->amask & AMASK_FIX))
963 goto invalid_opc;
964 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
965 break;
966 case 0x0B:
967 /* SQRTS */
968 if (!(ctx->amask & AMASK_FIX))
969 goto invalid_opc;
970 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
971 break;
972 case 0x14:
973 /* ITOFF */
974 if (!(ctx->amask & AMASK_FIX))
975 goto invalid_opc;
976 #if 0 // TODO
977 gen_itf(ctx, &gen_op_itoff, ra, rc);
978 #else
979 goto invalid_opc;
980 #endif
981 break;
982 case 0x24:
983 /* ITOFT */
984 if (!(ctx->amask & AMASK_FIX))
985 goto invalid_opc;
986 gen_itf(ctx, &gen_op_itoft, ra, rc);
987 break;
988 case 0x2A:
989 /* SQRTG */
990 if (!(ctx->amask & AMASK_FIX))
991 goto invalid_opc;
992 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
993 break;
994 case 0x02B:
995 /* SQRTT */
996 if (!(ctx->amask & AMASK_FIX))
997 goto invalid_opc;
998 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
999 break;
1000 default:
1001 goto invalid_opc;
1002 }
1003 break;
1004 case 0x15:
1005 /* VAX floating point */
1006 /* XXX: rounding mode and trap are ignored (!) */
1007 switch (fpfn) { /* f11 & 0x3F */
1008 case 0x00:
1009 /* ADDF */
1010 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1011 break;
1012 case 0x01:
1013 /* SUBF */
1014 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1015 break;
1016 case 0x02:
1017 /* MULF */
1018 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1019 break;
1020 case 0x03:
1021 /* DIVF */
1022 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1023 break;
1024 case 0x1E:
1025 /* CVTDG */
1026 #if 0 // TODO
1027 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1028 #else
1029 goto invalid_opc;
1030 #endif
1031 break;
1032 case 0x20:
1033 /* ADDG */
1034 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1035 break;
1036 case 0x21:
1037 /* SUBG */
1038 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1039 break;
1040 case 0x22:
1041 /* MULG */
1042 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1043 break;
1044 case 0x23:
1045 /* DIVG */
1046 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1047 break;
1048 case 0x25:
1049 /* CMPGEQ */
1050 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1051 break;
1052 case 0x26:
1053 /* CMPGLT */
1054 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1055 break;
1056 case 0x27:
1057 /* CMPGLE */
1058 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1059 break;
1060 case 0x2C:
1061 /* CVTGF */
1062 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1063 break;
1064 case 0x2D:
1065 /* CVTGD */
1066 #if 0 // TODO
1067 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1068 #else
1069 goto invalid_opc;
1070 #endif
1071 break;
1072 case 0x2F:
1073 /* CVTGQ */
1074 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1075 break;
1076 case 0x3C:
1077 /* CVTQF */
1078 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1079 break;
1080 case 0x3E:
1081 /* CVTQG */
1082 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1083 break;
1084 default:
1085 goto invalid_opc;
1086 }
1087 break;
1088 case 0x16:
1089 /* IEEE floating-point */
1090 /* XXX: rounding mode and traps are ignored (!) */
1091 switch (fpfn) { /* f11 & 0x3F */
1092 case 0x00:
1093 /* ADDS */
1094 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1095 break;
1096 case 0x01:
1097 /* SUBS */
1098 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1099 break;
1100 case 0x02:
1101 /* MULS */
1102 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1103 break;
1104 case 0x03:
1105 /* DIVS */
1106 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1107 break;
1108 case 0x20:
1109 /* ADDT */
1110 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1111 break;
1112 case 0x21:
1113 /* SUBT */
1114 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1115 break;
1116 case 0x22:
1117 /* MULT */
1118 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1119 break;
1120 case 0x23:
1121 /* DIVT */
1122 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1123 break;
1124 case 0x24:
1125 /* CMPTUN */
1126 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1127 break;
1128 case 0x25:
1129 /* CMPTEQ */
1130 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1131 break;
1132 case 0x26:
1133 /* CMPTLT */
1134 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1135 break;
1136 case 0x27:
1137 /* CMPTLE */
1138 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1139 break;
1140 case 0x2C:
1141 /* XXX: incorrect */
1142 if (fn11 == 0x2AC) {
1143 /* CVTST */
1144 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1145 } else {
1146 /* CVTTS */
1147 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1148 }
1149 break;
1150 case 0x2F:
1151 /* CVTTQ */
1152 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1153 break;
1154 case 0x3C:
1155 /* CVTQS */
1156 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1157 break;
1158 case 0x3E:
1159 /* CVTQT */
1160 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1161 break;
1162 default:
1163 goto invalid_opc;
1164 }
1165 break;
1166 case 0x17:
1167 switch (fn11) {
1168 case 0x010:
1169 /* CVTLQ */
1170 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1171 break;
1172 case 0x020:
1173 /* CPYS */
1174 if (ra == rb) {
1175 if (ra == 31 && rc == 31) {
1176 /* FNOP */
1177 gen_op_nop();
1178 } else {
1179 /* FMOV */
1180 gen_load_fir(ctx, rb, 0);
1181 gen_store_fir(ctx, rc, 0);
1182 }
1183 } else {
1184 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1185 }
1186 break;
1187 case 0x021:
1188 /* CPYSN */
1189 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1190 break;
1191 case 0x022:
1192 /* CPYSE */
1193 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1194 break;
1195 case 0x024:
1196 /* MT_FPCR */
1197 gen_load_fir(ctx, ra, 0);
1198 gen_op_store_fpcr();
1199 break;
1200 case 0x025:
1201 /* MF_FPCR */
1202 gen_op_load_fpcr();
1203 gen_store_fir(ctx, ra, 0);
1204 break;
1205 case 0x02A:
1206 /* FCMOVEQ */
1207 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1208 break;
1209 case 0x02B:
1210 /* FCMOVNE */
1211 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1212 break;
1213 case 0x02C:
1214 /* FCMOVLT */
1215 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1216 break;
1217 case 0x02D:
1218 /* FCMOVGE */
1219 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1220 break;
1221 case 0x02E:
1222 /* FCMOVLE */
1223 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1224 break;
1225 case 0x02F:
1226 /* FCMOVGT */
1227 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1228 break;
1229 case 0x030:
1230 /* CVTQL */
1231 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1232 break;
1233 case 0x130:
1234 /* CVTQL/V */
1235 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1236 break;
1237 case 0x530:
1238 /* CVTQL/SV */
1239 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1240 break;
1241 default:
1242 goto invalid_opc;
1243 }
1244 break;
1245 case 0x18:
1246 switch ((uint16_t)disp16) {
1247 case 0x0000:
1248 /* TRAPB */
1249 /* No-op. Just exit from the current tb */
1250 ret = 2;
1251 break;
1252 case 0x0400:
1253 /* EXCB */
1254 /* No-op. Just exit from the current tb */
1255 ret = 2;
1256 break;
1257 case 0x4000:
1258 /* MB */
1259 /* No-op */
1260 break;
1261 case 0x4400:
1262 /* WMB */
1263 /* No-op */
1264 break;
1265 case 0x8000:
1266 /* FETCH */
1267 /* No-op */
1268 break;
1269 case 0xA000:
1270 /* FETCH_M */
1271 /* No-op */
1272 break;
1273 case 0xC000:
1274 /* RPCC */
1275 gen_op_load_pcc();
1276 if (ra != 31)
1277 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
1278 break;
1279 case 0xE000:
1280 /* RC */
1281 gen_op_load_irf();
1282 if (ra != 31)
1283 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
1284 gen_op_clear_irf();
1285 break;
1286 case 0xE800:
1287 /* ECB */
1288 /* XXX: TODO: evict tb cache at address rb */
1289 #if 0
1290 ret = 2;
1291 #else
1292 goto invalid_opc;
1293 #endif
1294 break;
1295 case 0xF000:
1296 /* RS */
1297 gen_op_load_irf();
1298 if (ra != 31)
1299 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
1300 gen_op_set_irf();
1301 break;
1302 case 0xF800:
1303 /* WH64 */
1304 /* No-op */
1305 break;
1306 default:
1307 goto invalid_opc;
1308 }
1309 break;
1310 case 0x19:
1311 /* HW_MFPR (PALcode) */
1312 #if defined (CONFIG_USER_ONLY)
1313 goto invalid_opc;
1314 #else
1315 if (!ctx->pal_mode)
1316 goto invalid_opc;
1317 gen_op_mfpr(insn & 0xFF);
1318 if (ra != 31)
1319 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
1320 break;
1321 #endif
1322 case 0x1A:
1323 if (ra != 31)
1324 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1325 if (rb != 31)
1326 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
1327 else
1328 tcg_gen_movi_i64(cpu_pc, 0);
1329 /* Those four jumps only differ by the branch prediction hint */
1330 switch (fn2) {
1331 case 0x0:
1332 /* JMP */
1333 break;
1334 case 0x1:
1335 /* JSR */
1336 break;
1337 case 0x2:
1338 /* RET */
1339 break;
1340 case 0x3:
1341 /* JSR_COROUTINE */
1342 break;
1343 }
1344 ret = 1;
1345 break;
1346 case 0x1B:
1347 /* HW_LD (PALcode) */
1348 #if defined (CONFIG_USER_ONLY)
1349 goto invalid_opc;
1350 #else
1351 if (!ctx->pal_mode)
1352 goto invalid_opc;
1353 if (rb != 31)
1354 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1355 else
1356 tcg_gen_movi_i64(cpu_T[0], 0);
1357 tcg_gen_movi_i64(cpu_T[1], disp12);
1358 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
1359 switch ((insn >> 12) & 0xF) {
1360 case 0x0:
1361 /* Longword physical access */
1362 gen_op_ldl_raw();
1363 break;
1364 case 0x1:
1365 /* Quadword physical access */
1366 gen_op_ldq_raw();
1367 break;
1368 case 0x2:
1369 /* Longword physical access with lock */
1370 gen_op_ldl_l_raw();
1371 break;
1372 case 0x3:
1373 /* Quadword physical access with lock */
1374 gen_op_ldq_l_raw();
1375 break;
1376 case 0x4:
1377 /* Longword virtual PTE fetch */
1378 gen_op_ldl_kernel();
1379 break;
1380 case 0x5:
1381 /* Quadword virtual PTE fetch */
1382 gen_op_ldq_kernel();
1383 break;
1384 case 0x6:
1385 /* Invalid */
1386 goto invalid_opc;
1387 case 0x7:
1388 /* Invalid */
1389 goto invalid_opc;
1390 case 0x8:
1391 /* Longword virtual access */
1392 gen_op_ld_phys_to_virt();
1393 gen_op_ldl_raw();
1394 break;
1395 case 0x9:
1396 /* Quadword virtual access */
1397 gen_op_ld_phys_to_virt();
1398 gen_op_ldq_raw();
1399 break;
1400 case 0xA:
1401 /* Longword virtual access with protection check */
1402 gen_ldl(ctx);
1403 break;
1404 case 0xB:
1405 /* Quadword virtual access with protection check */
1406 gen_ldq(ctx);
1407 break;
1408 case 0xC:
1409 /* Longword virtual access with altenate access mode */
1410 gen_op_set_alt_mode();
1411 gen_op_ld_phys_to_virt();
1412 gen_op_ldl_raw();
1413 gen_op_restore_mode();
1414 break;
1415 case 0xD:
1416 /* Quadword virtual access with altenate access mode */
1417 gen_op_set_alt_mode();
1418 gen_op_ld_phys_to_virt();
1419 gen_op_ldq_raw();
1420 gen_op_restore_mode();
1421 break;
1422 case 0xE:
1423 /* Longword virtual access with alternate access mode and
1424 * protection checks
1425 */
1426 gen_op_set_alt_mode();
1427 gen_op_ldl_data();
1428 gen_op_restore_mode();
1429 break;
1430 case 0xF:
1431 /* Quadword virtual access with alternate access mode and
1432 * protection checks
1433 */
1434 gen_op_set_alt_mode();
1435 gen_op_ldq_data();
1436 gen_op_restore_mode();
1437 break;
1438 }
1439 if (ra != 31)
1440 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
1441 break;
1442 #endif
1443 case 0x1C:
1444 switch (fn7) {
1445 case 0x00:
1446 /* SEXTB */
1447 if (!(ctx->amask & AMASK_BWX))
1448 goto invalid_opc;
1449 gen_arith2(ctx, &gen_op_sextb, rb, rc, islit, lit);
1450 break;
1451 case 0x01:
1452 /* SEXTW */
1453 if (!(ctx->amask & AMASK_BWX))
1454 goto invalid_opc;
1455 gen_arith2(ctx, &gen_op_sextw, rb, rc, islit, lit);
1456 break;
1457 case 0x30:
1458 /* CTPOP */
1459 if (!(ctx->amask & AMASK_CIX))
1460 goto invalid_opc;
1461 gen_arith2(ctx, &gen_op_ctpop, rb, rc, 0, 0);
1462 break;
1463 case 0x31:
1464 /* PERR */
1465 if (!(ctx->amask & AMASK_MVI))
1466 goto invalid_opc;
1467 /* XXX: TODO */
1468 goto invalid_opc;
1469 break;
1470 case 0x32:
1471 /* CTLZ */
1472 if (!(ctx->amask & AMASK_CIX))
1473 goto invalid_opc;
1474 gen_arith2(ctx, &gen_op_ctlz, rb, rc, 0, 0);
1475 break;
1476 case 0x33:
1477 /* CTTZ */
1478 if (!(ctx->amask & AMASK_CIX))
1479 goto invalid_opc;
1480 gen_arith2(ctx, &gen_op_cttz, rb, rc, 0, 0);
1481 break;
1482 case 0x34:
1483 /* UNPKBW */
1484 if (!(ctx->amask & AMASK_MVI))
1485 goto invalid_opc;
1486 /* XXX: TODO */
1487 goto invalid_opc;
1488 break;
1489 case 0x35:
1490 /* UNPKWL */
1491 if (!(ctx->amask & AMASK_MVI))
1492 goto invalid_opc;
1493 /* XXX: TODO */
1494 goto invalid_opc;
1495 break;
1496 case 0x36:
1497 /* PKWB */
1498 if (!(ctx->amask & AMASK_MVI))
1499 goto invalid_opc;
1500 /* XXX: TODO */
1501 goto invalid_opc;
1502 break;
1503 case 0x37:
1504 /* PKLB */
1505 if (!(ctx->amask & AMASK_MVI))
1506 goto invalid_opc;
1507 /* XXX: TODO */
1508 goto invalid_opc;
1509 break;
1510 case 0x38:
1511 /* MINSB8 */
1512 if (!(ctx->amask & AMASK_MVI))
1513 goto invalid_opc;
1514 /* XXX: TODO */
1515 goto invalid_opc;
1516 break;
1517 case 0x39:
1518 /* MINSW4 */
1519 if (!(ctx->amask & AMASK_MVI))
1520 goto invalid_opc;
1521 /* XXX: TODO */
1522 goto invalid_opc;
1523 break;
1524 case 0x3A:
1525 /* MINUB8 */
1526 if (!(ctx->amask & AMASK_MVI))
1527 goto invalid_opc;
1528 /* XXX: TODO */
1529 goto invalid_opc;
1530 break;
1531 case 0x3B:
1532 /* MINUW4 */
1533 if (!(ctx->amask & AMASK_MVI))
1534 goto invalid_opc;
1535 /* XXX: TODO */
1536 goto invalid_opc;
1537 break;
1538 case 0x3C:
1539 /* MAXUB8 */
1540 if (!(ctx->amask & AMASK_MVI))
1541 goto invalid_opc;
1542 /* XXX: TODO */
1543 goto invalid_opc;
1544 break;
1545 case 0x3D:
1546 /* MAXUW4 */
1547 if (!(ctx->amask & AMASK_MVI))
1548 goto invalid_opc;
1549 /* XXX: TODO */
1550 goto invalid_opc;
1551 break;
1552 case 0x3E:
1553 /* MAXSB8 */
1554 if (!(ctx->amask & AMASK_MVI))
1555 goto invalid_opc;
1556 /* XXX: TODO */
1557 goto invalid_opc;
1558 break;
1559 case 0x3F:
1560 /* MAXSW4 */
1561 if (!(ctx->amask & AMASK_MVI))
1562 goto invalid_opc;
1563 /* XXX: TODO */
1564 goto invalid_opc;
1565 break;
1566 case 0x70:
1567 /* FTOIT */
1568 if (!(ctx->amask & AMASK_FIX))
1569 goto invalid_opc;
1570 gen_fti(ctx, &gen_op_ftoit, ra, rb);
1571 break;
1572 case 0x78:
1573 /* FTOIS */
1574 if (!(ctx->amask & AMASK_FIX))
1575 goto invalid_opc;
1576 gen_fti(ctx, &gen_op_ftois, ra, rb);
1577 break;
1578 default:
1579 goto invalid_opc;
1580 }
1581 break;
1582 case 0x1D:
1583 /* HW_MTPR (PALcode) */
1584 #if defined (CONFIG_USER_ONLY)
1585 goto invalid_opc;
1586 #else
1587 if (!ctx->pal_mode)
1588 goto invalid_opc;
1589 if (ra != 31)
1590 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
1591 else
1592 tcg_gen_movi_i64(cpu_T[0], 0);
1593 gen_op_mtpr(insn & 0xFF);
1594 ret = 2;
1595 break;
1596 #endif
1597 case 0x1E:
1598 /* HW_REI (PALcode) */
1599 #if defined (CONFIG_USER_ONLY)
1600 goto invalid_opc;
1601 #else
1602 if (!ctx->pal_mode)
1603 goto invalid_opc;
1604 if (rb == 31) {
1605 /* "Old" alpha */
1606 gen_op_hw_rei();
1607 } else {
1608 if (ra != 31)
1609 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1610 else
1611 tcg_gen_movi_i64(cpu_T[0], 0);
1612 tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51));
1613 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
1614 gen_op_hw_ret();
1615 }
1616 ret = 2;
1617 break;
1618 #endif
1619 case 0x1F:
1620 /* HW_ST (PALcode) */
1621 #if defined (CONFIG_USER_ONLY)
1622 goto invalid_opc;
1623 #else
1624 if (!ctx->pal_mode)
1625 goto invalid_opc;
1626 if (ra != 31)
1627 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
1628 else
1629 tcg_gen_movi_i64(cpu_T[0], disp12);
1630 if (ra != 31)
1631 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
1632 else
1633 tcg_gen_movi_i64(cpu_T[1], 0);
1634 switch ((insn >> 12) & 0xF) {
1635 case 0x0:
1636 /* Longword physical access */
1637 gen_op_stl_raw();
1638 break;
1639 case 0x1:
1640 /* Quadword physical access */
1641 gen_op_stq_raw();
1642 break;
1643 case 0x2:
1644 /* Longword physical access with lock */
1645 gen_op_stl_c_raw();
1646 break;
1647 case 0x3:
1648 /* Quadword physical access with lock */
1649 gen_op_stq_c_raw();
1650 break;
1651 case 0x4:
1652 /* Longword virtual access */
1653 gen_op_st_phys_to_virt();
1654 gen_op_stl_raw();
1655 break;
1656 case 0x5:
1657 /* Quadword virtual access */
1658 gen_op_st_phys_to_virt();
1659 gen_op_stq_raw();
1660 break;
1661 case 0x6:
1662 /* Invalid */
1663 goto invalid_opc;
1664 case 0x7:
1665 /* Invalid */
1666 goto invalid_opc;
1667 case 0x8:
1668 /* Invalid */
1669 goto invalid_opc;
1670 case 0x9:
1671 /* Invalid */
1672 goto invalid_opc;
1673 case 0xA:
1674 /* Invalid */
1675 goto invalid_opc;
1676 case 0xB:
1677 /* Invalid */
1678 goto invalid_opc;
1679 case 0xC:
1680 /* Longword virtual access with alternate access mode */
1681 gen_op_set_alt_mode();
1682 gen_op_st_phys_to_virt();
1683 gen_op_ldl_raw();
1684 gen_op_restore_mode();
1685 break;
1686 case 0xD:
1687 /* Quadword virtual access with alternate access mode */
1688 gen_op_set_alt_mode();
1689 gen_op_st_phys_to_virt();
1690 gen_op_ldq_raw();
1691 gen_op_restore_mode();
1692 break;
1693 case 0xE:
1694 /* Invalid */
1695 goto invalid_opc;
1696 case 0xF:
1697 /* Invalid */
1698 goto invalid_opc;
1699 }
1700 ret = 2;
1701 break;
1702 #endif
1703 case 0x20:
1704 /* LDF */
1705 #if 0 // TODO
1706 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
1707 #else
1708 goto invalid_opc;
1709 #endif
1710 break;
1711 case 0x21:
1712 /* LDG */
1713 #if 0 // TODO
1714 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
1715 #else
1716 goto invalid_opc;
1717 #endif
1718 break;
1719 case 0x22:
1720 /* LDS */
1721 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
1722 break;
1723 case 0x23:
1724 /* LDT */
1725 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
1726 break;
1727 case 0x24:
1728 /* STF */
1729 #if 0 // TODO
1730 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
1731 #else
1732 goto invalid_opc;
1733 #endif
1734 break;
1735 case 0x25:
1736 /* STG */
1737 #if 0 // TODO
1738 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
1739 #else
1740 goto invalid_opc;
1741 #endif
1742 break;
1743 case 0x26:
1744 /* STS */
1745 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
1746 break;
1747 case 0x27:
1748 /* STT */
1749 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
1750 break;
1751 case 0x28:
1752 /* LDL */
1753 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
1754 break;
1755 case 0x29:
1756 /* LDQ */
1757 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
1758 break;
1759 case 0x2A:
1760 /* LDL_L */
1761 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
1762 break;
1763 case 0x2B:
1764 /* LDQ_L */
1765 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
1766 break;
1767 case 0x2C:
1768 /* STL */
1769 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
1770 break;
1771 case 0x2D:
1772 /* STQ */
1773 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
1774 break;
1775 case 0x2E:
1776 /* STL_C */
1777 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
1778 break;
1779 case 0x2F:
1780 /* STQ_C */
1781 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
1782 break;
1783 case 0x30:
1784 /* BR */
1785 if (ra != 31)
1786 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1787 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
1788 ret = 1;
1789 break;
1790 case 0x31:
1791 /* FBEQ */
1792 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
1793 ret = 1;
1794 break;
1795 case 0x32:
1796 /* FBLT */
1797 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
1798 ret = 1;
1799 break;
1800 case 0x33:
1801 /* FBLE */
1802 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
1803 ret = 1;
1804 break;
1805 case 0x34:
1806 /* BSR */
1807 if (ra != 31)
1808 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1809 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
1810 ret = 1;
1811 break;
1812 case 0x35:
1813 /* FBNE */
1814 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
1815 ret = 1;
1816 break;
1817 case 0x36:
1818 /* FBGE */
1819 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
1820 ret = 1;
1821 break;
1822 case 0x37:
1823 /* FBGT */
1824 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
1825 ret = 1;
1826 break;
1827 case 0x38:
1828 /* BLBC */
1829 gen_bcond(ctx, &gen_op_cmplbc, ra, disp16);
1830 ret = 1;
1831 break;
1832 case 0x39:
1833 /* BEQ */
1834 gen_bcond(ctx, &gen_op_cmpeqz, ra, disp16);
1835 ret = 1;
1836 break;
1837 case 0x3A:
1838 /* BLT */
1839 gen_bcond(ctx, &gen_op_cmpltz, ra, disp16);
1840 ret = 1;
1841 break;
1842 case 0x3B:
1843 /* BLE */
1844 gen_bcond(ctx, &gen_op_cmplez, ra, disp16);
1845 ret = 1;
1846 break;
1847 case 0x3C:
1848 /* BLBS */
1849 gen_bcond(ctx, &gen_op_cmplbs, ra, disp16);
1850 ret = 1;
1851 break;
1852 case 0x3D:
1853 /* BNE */
1854 gen_bcond(ctx, &gen_op_cmpnez, ra, disp16);
1855 ret = 1;
1856 break;
1857 case 0x3E:
1858 /* BGE */
1859 gen_bcond(ctx, &gen_op_cmpgez, ra, disp16);
1860 ret = 1;
1861 break;
1862 case 0x3F:
1863 /* BGT */
1864 gen_bcond(ctx, &gen_op_cmpgtz, ra, disp16);
1865 ret = 1;
1866 break;
1867 invalid_opc:
1868 gen_invalid(ctx);
1869 ret = 3;
1870 break;
1871 }
1872
1873 return ret;
1874 }
1875
1876 static always_inline void gen_intermediate_code_internal (CPUState *env,
1877 TranslationBlock *tb,
1878 int search_pc)
1879 {
1880 #if defined ALPHA_DEBUG_DISAS
1881 static int insn_count;
1882 #endif
1883 DisasContext ctx, *ctxp = &ctx;
1884 target_ulong pc_start;
1885 uint32_t insn;
1886 uint16_t *gen_opc_end;
1887 int j, lj = -1;
1888 int ret;
1889 int num_insns;
1890 int max_insns;
1891
1892 pc_start = tb->pc;
1893 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1894 ctx.pc = pc_start;
1895 ctx.amask = env->amask;
1896 #if defined (CONFIG_USER_ONLY)
1897 ctx.mem_idx = 0;
1898 #else
1899 ctx.mem_idx = ((env->ps >> 3) & 3);
1900 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
1901 #endif
1902 num_insns = 0;
1903 max_insns = tb->cflags & CF_COUNT_MASK;
1904 if (max_insns == 0)
1905 max_insns = CF_COUNT_MASK;
1906
1907 gen_icount_start();
1908 for (ret = 0; ret == 0;) {
1909 if (env->nb_breakpoints > 0) {
1910 for(j = 0; j < env->nb_breakpoints; j++) {
1911 if (env->breakpoints[j] == ctx.pc) {
1912 gen_excp(&ctx, EXCP_DEBUG, 0);
1913 break;
1914 }
1915 }
1916 }
1917 if (search_pc) {
1918 j = gen_opc_ptr - gen_opc_buf;
1919 if (lj < j) {
1920 lj++;
1921 while (lj < j)
1922 gen_opc_instr_start[lj++] = 0;
1923 gen_opc_pc[lj] = ctx.pc;
1924 gen_opc_instr_start[lj] = 1;
1925 gen_opc_icount[lj] = num_insns;
1926 }
1927 }
1928 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1929 gen_io_start();
1930 #if defined ALPHA_DEBUG_DISAS
1931 insn_count++;
1932 if (logfile != NULL) {
1933 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
1934 ctx.pc, ctx.mem_idx);
1935 }
1936 #endif
1937 insn = ldl_code(ctx.pc);
1938 #if defined ALPHA_DEBUG_DISAS
1939 insn_count++;
1940 if (logfile != NULL) {
1941 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
1942 }
1943 #endif
1944 num_insns++;
1945 ctx.pc += 4;
1946 ret = translate_one(ctxp, insn);
1947 if (ret != 0)
1948 break;
1949 /* if we reach a page boundary or are single stepping, stop
1950 * generation
1951 */
1952 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
1953 (env->singlestep_enabled) ||
1954 num_insns >= max_insns) {
1955 break;
1956 }
1957 #if defined (DO_SINGLE_STEP)
1958 break;
1959 #endif
1960 }
1961 if (ret != 1 && ret != 3) {
1962 tcg_gen_movi_i64(cpu_pc, ctx.pc);
1963 }
1964 #if defined (DO_TB_FLUSH)
1965 tcg_gen_helper_0_0(helper_tb_flush);
1966 #endif
1967 if (tb->cflags & CF_LAST_IO)
1968 gen_io_end();
1969 /* Generate the return instruction */
1970 tcg_gen_exit_tb(0);
1971 gen_icount_end(tb, num_insns);
1972 *gen_opc_ptr = INDEX_op_end;
1973 if (search_pc) {
1974 j = gen_opc_ptr - gen_opc_buf;
1975 lj++;
1976 while (lj <= j)
1977 gen_opc_instr_start[lj++] = 0;
1978 } else {
1979 tb->size = ctx.pc - pc_start;
1980 tb->icount = num_insns;
1981 }
1982 #if defined ALPHA_DEBUG_DISAS
1983 if (loglevel & CPU_LOG_TB_CPU) {
1984 cpu_dump_state(env, logfile, fprintf, 0);
1985 }
1986 if (loglevel & CPU_LOG_TB_IN_ASM) {
1987 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
1988 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
1989 fprintf(logfile, "\n");
1990 }
1991 #endif
1992 }
1993
1994 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1995 {
1996 gen_intermediate_code_internal(env, tb, 0);
1997 }
1998
1999 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2000 {
2001 gen_intermediate_code_internal(env, tb, 1);
2002 }
2003
2004 CPUAlphaState * cpu_alpha_init (const char *cpu_model)
2005 {
2006 CPUAlphaState *env;
2007 uint64_t hwpcb;
2008
2009 env = qemu_mallocz(sizeof(CPUAlphaState));
2010 if (!env)
2011 return NULL;
2012 cpu_exec_init(env);
2013 alpha_translate_init();
2014 tlb_flush(env, 1);
2015 /* XXX: should not be hardcoded */
2016 env->implver = IMPLVER_2106x;
2017 env->ps = 0x1F00;
2018 #if defined (CONFIG_USER_ONLY)
2019 env->ps |= 1 << 3;
2020 #endif
2021 pal_init(env);
2022 /* Initialize IPR */
2023 hwpcb = env->ipr[IPR_PCBB];
2024 env->ipr[IPR_ASN] = 0;
2025 env->ipr[IPR_ASTEN] = 0;
2026 env->ipr[IPR_ASTSR] = 0;
2027 env->ipr[IPR_DATFX] = 0;
2028 /* XXX: fix this */
2029 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2030 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2031 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2032 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2033 env->ipr[IPR_FEN] = 0;
2034 env->ipr[IPR_IPL] = 31;
2035 env->ipr[IPR_MCES] = 0;
2036 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2037 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2038 env->ipr[IPR_SISR] = 0;
2039 env->ipr[IPR_VIRBND] = -1ULL;
2040
2041 return env;
2042 }
2043
2044 void gen_pc_load(CPUState *env, TranslationBlock *tb,
2045 unsigned long searched_pc, int pc_pos, void *puc)
2046 {
2047 env->pc = gen_opc_pc[pc_pos];
2048 }
Qemu copy for testing