target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26 #include "sysemu/sysemu.h"
  27
  28 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  29 {
  30     /* Reset a single ARMCPRegInfo register */
  31     ARMCPRegInfo *ri = value;
  32     ARMCPU *cpu = opaque;
  33
  34     if (ri->type & ARM_CP_SPECIAL) {
  35         return;
  36     }
  37
  38     if (ri->resetfn) {
  39         ri->resetfn(&cpu->env, ri);
  40         return;
  41     }
  42
  43     /* A zero offset is never possible as it would be regs[0]
  44      * so we use it to indicate that reset is being handled elsewhere.
  45      * This is basically only used for fields in non-core coprocessors
  46      * (like the pxa2xx ones).
  47      */
  48     if (!ri->fieldoffset) {
  49         return;
  50     }
  51
  52     if (ri->type & ARM_CP_64BIT) {
  53         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  54     } else {
  55         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  56     }
  57 }
  58
  59 /* CPUClass::reset() */
  60 static void arm_cpu_reset(CPUState *s)
  61 {
  62     ARMCPU *cpu = ARM_CPU(s);
  63     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  64     CPUARMState *env = &cpu->env;
  65
  66     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  67         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
  68         log_cpu_state(env, 0);
  69     }
  70
  71     acc->parent_reset(s);
  72
  73     memset(env, 0, offsetof(CPUARMState, breakpoints));
  74     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  75     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  76     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  77     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  78
  79     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  80         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  81     }
  82
  83 #if defined(CONFIG_USER_ONLY)
  84     env->uncached_cpsr = ARM_CPU_MODE_USR;
  85     /* For user mode we must enable access to coprocessors */
  86     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  87     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  88         env->cp15.c15_cpar = 3;
  89     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
  90         env->cp15.c15_cpar = 1;
  91     }
  92 #else
  93     /* SVC mode with interrupts disabled.  */
  94     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
  95     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
  96        clear at reset.  Initial SP and PC are loaded from ROM.  */
  97     if (IS_M(env)) {
  98         uint32_t pc;
  99         uint8_t *rom;
 100         env->uncached_cpsr &= ~CPSR_I;
 101         rom = rom_ptr(0);
 102         if (rom) {
 103             /* We should really use ldl_phys here, in case the guest
 104                modified flash and reset itself.  However images
 105                loaded via -kernel have not been copied yet, so load the
 106                values directly from there.  */
 107             env->regs[13] = ldl_p(rom);
 108             pc = ldl_p(rom + 4);
 109             env->thumb = pc & 1;
 110             env->regs[15] = pc & ~1;
 111         }
 112     }
 113     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 114 #endif
 115     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 116     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 117     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 118     set_float_detect_tininess(float_tininess_before_rounding,
 119                               &env->vfp.fp_status);
 120     set_float_detect_tininess(float_tininess_before_rounding,
 121                               &env->vfp.standard_fp_status);
 122     tlb_flush(env, 1);
 123     /* Reset is a state change for some CPUARMState fields which we
 124      * bake assumptions about into translated code, so we need to
 125      * tb_flush().
 126      */
 127     tb_flush(env);
 128 }
 129
 130 static inline void set_feature(CPUARMState *env, int feature)
 131 {
 132     env->features |= 1ULL << feature;
 133 }
 134
 135 static void arm_cpu_initfn(Object *obj)
 136 {
 137     ARMCPU *cpu = ARM_CPU(obj);
 138
 139     cpu_exec_init(&cpu->env);
 140     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 141                                          g_free, g_free);
 142 }
 143
 144 static void arm_cpu_finalizefn(Object *obj)
 145 {
 146     ARMCPU *cpu = ARM_CPU(obj);
 147     g_hash_table_destroy(cpu->cp_regs);
 148 }
 149
 150 void arm_cpu_realize(ARMCPU *cpu)
 151 {
 152     /* This function is called by cpu_arm_init() because it
 153      * needs to do common actions based on feature bits, etc
 154      * that have been set by the subclass init functions.
 155      * When we have QOM realize support it should become
 156      * a true realize function instead.
 157      */
 158     CPUARMState *env = &cpu->env;
 159     /* Some features automatically imply others: */
 160     if (arm_feature(env, ARM_FEATURE_V7)) {
 161         set_feature(env, ARM_FEATURE_VAPA);
 162         set_feature(env, ARM_FEATURE_THUMB2);
 163         set_feature(env, ARM_FEATURE_MPIDR);
 164         if (!arm_feature(env, ARM_FEATURE_M)) {
 165             set_feature(env, ARM_FEATURE_V6K);
 166         } else {
 167             set_feature(env, ARM_FEATURE_V6);
 168         }
 169     }
 170     if (arm_feature(env, ARM_FEATURE_V6K)) {
 171         set_feature(env, ARM_FEATURE_V6);
 172         set_feature(env, ARM_FEATURE_MVFR);
 173     }
 174     if (arm_feature(env, ARM_FEATURE_V6)) {
 175         set_feature(env, ARM_FEATURE_V5);
 176         if (!arm_feature(env, ARM_FEATURE_M)) {
 177             set_feature(env, ARM_FEATURE_AUXCR);
 178         }
 179     }
 180     if (arm_feature(env, ARM_FEATURE_V5)) {
 181         set_feature(env, ARM_FEATURE_V4T);
 182     }
 183     if (arm_feature(env, ARM_FEATURE_M)) {
 184         set_feature(env, ARM_FEATURE_THUMB_DIV);
 185     }
 186     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 187         set_feature(env, ARM_FEATURE_THUMB_DIV);
 188     }
 189     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 190         set_feature(env, ARM_FEATURE_VFP3);
 191     }
 192     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 193         set_feature(env, ARM_FEATURE_VFP);
 194     }
 195     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 196         set_feature(env, ARM_FEATURE_PXN);
 197     }
 198
 199     register_cp_regs_for_features(cpu);
 200 }
 201
 202 /* CPU models */
 203
 204 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 205 {
 206     ObjectClass *oc;
 207
 208     if (!cpu_model) {
 209         return NULL;
 210     }
 211
 212     oc = object_class_by_name(cpu_model);
 213     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU)) {
 214         return NULL;
 215     }
 216     return oc;
 217 }
 218
 219 static void arm926_initfn(Object *obj)
 220 {
 221     ARMCPU *cpu = ARM_CPU(obj);
 222     set_feature(&cpu->env, ARM_FEATURE_V5);
 223     set_feature(&cpu->env, ARM_FEATURE_VFP);
 224     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 225     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 226     cpu->midr = 0x41069265;
 227     cpu->reset_fpsid = 0x41011090;
 228     cpu->ctr = 0x1dd20d2;
 229     cpu->reset_sctlr = 0x00090078;
 230 }
 231
 232 static void arm946_initfn(Object *obj)
 233 {
 234     ARMCPU *cpu = ARM_CPU(obj);
 235     set_feature(&cpu->env, ARM_FEATURE_V5);
 236     set_feature(&cpu->env, ARM_FEATURE_MPU);
 237     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 238     cpu->midr = 0x41059461;
 239     cpu->ctr = 0x0f004006;
 240     cpu->reset_sctlr = 0x00000078;
 241 }
 242
 243 static void arm1026_initfn(Object *obj)
 244 {
 245     ARMCPU *cpu = ARM_CPU(obj);
 246     set_feature(&cpu->env, ARM_FEATURE_V5);
 247     set_feature(&cpu->env, ARM_FEATURE_VFP);
 248     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 249     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 250     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 251     cpu->midr = 0x4106a262;
 252     cpu->reset_fpsid = 0x410110a0;
 253     cpu->ctr = 0x1dd20d2;
 254     cpu->reset_sctlr = 0x00090078;
 255     cpu->reset_auxcr = 1;
 256     {
 257         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 258         ARMCPRegInfo ifar = {
 259             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 260             .access = PL1_RW,
 261             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 262             .resetvalue = 0
 263         };
 264         define_one_arm_cp_reg(cpu, &ifar);
 265     }
 266 }
 267
 268 static void arm1136_r2_initfn(Object *obj)
 269 {
 270     ARMCPU *cpu = ARM_CPU(obj);
 271     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 272      * older core than plain "arm1136". In particular this does not
 273      * have the v6K features.
 274      * These ID register values are correct for 1136 but may be wrong
 275      * for 1136_r2 (in particular r0p2 does not actually implement most
 276      * of the ID registers).
 277      */
 278     set_feature(&cpu->env, ARM_FEATURE_V6);
 279     set_feature(&cpu->env, ARM_FEATURE_VFP);
 280     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 281     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 282     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 283     cpu->midr = 0x4107b362;
 284     cpu->reset_fpsid = 0x410120b4;
 285     cpu->mvfr0 = 0x11111111;
 286     cpu->mvfr1 = 0x00000000;
 287     cpu->ctr = 0x1dd20d2;
 288     cpu->reset_sctlr = 0x00050078;
 289     cpu->id_pfr0 = 0x111;
 290     cpu->id_pfr1 = 0x1;
 291     cpu->id_dfr0 = 0x2;
 292     cpu->id_afr0 = 0x3;
 293     cpu->id_mmfr0 = 0x01130003;
 294     cpu->id_mmfr1 = 0x10030302;
 295     cpu->id_mmfr2 = 0x01222110;
 296     cpu->id_isar0 = 0x00140011;
 297     cpu->id_isar1 = 0x12002111;
 298     cpu->id_isar2 = 0x11231111;
 299     cpu->id_isar3 = 0x01102131;
 300     cpu->id_isar4 = 0x141;
 301     cpu->reset_auxcr = 7;
 302 }
 303
 304 static void arm1136_initfn(Object *obj)
 305 {
 306     ARMCPU *cpu = ARM_CPU(obj);
 307     set_feature(&cpu->env, ARM_FEATURE_V6K);
 308     set_feature(&cpu->env, ARM_FEATURE_V6);
 309     set_feature(&cpu->env, ARM_FEATURE_VFP);
 310     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 311     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 312     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 313     cpu->midr = 0x4117b363;
 314     cpu->reset_fpsid = 0x410120b4;
 315     cpu->mvfr0 = 0x11111111;
 316     cpu->mvfr1 = 0x00000000;
 317     cpu->ctr = 0x1dd20d2;
 318     cpu->reset_sctlr = 0x00050078;
 319     cpu->id_pfr0 = 0x111;
 320     cpu->id_pfr1 = 0x1;
 321     cpu->id_dfr0 = 0x2;
 322     cpu->id_afr0 = 0x3;
 323     cpu->id_mmfr0 = 0x01130003;
 324     cpu->id_mmfr1 = 0x10030302;
 325     cpu->id_mmfr2 = 0x01222110;
 326     cpu->id_isar0 = 0x00140011;
 327     cpu->id_isar1 = 0x12002111;
 328     cpu->id_isar2 = 0x11231111;
 329     cpu->id_isar3 = 0x01102131;
 330     cpu->id_isar4 = 0x141;
 331     cpu->reset_auxcr = 7;
 332 }
 333
 334 static void arm1176_initfn(Object *obj)
 335 {
 336     ARMCPU *cpu = ARM_CPU(obj);
 337     set_feature(&cpu->env, ARM_FEATURE_V6K);
 338     set_feature(&cpu->env, ARM_FEATURE_VFP);
 339     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 340     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 341     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 342     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 343     cpu->midr = 0x410fb767;
 344     cpu->reset_fpsid = 0x410120b5;
 345     cpu->mvfr0 = 0x11111111;
 346     cpu->mvfr1 = 0x00000000;
 347     cpu->ctr = 0x1dd20d2;
 348     cpu->reset_sctlr = 0x00050078;
 349     cpu->id_pfr0 = 0x111;
 350     cpu->id_pfr1 = 0x11;
 351     cpu->id_dfr0 = 0x33;
 352     cpu->id_afr0 = 0;
 353     cpu->id_mmfr0 = 0x01130003;
 354     cpu->id_mmfr1 = 0x10030302;
 355     cpu->id_mmfr2 = 0x01222100;
 356     cpu->id_isar0 = 0x0140011;
 357     cpu->id_isar1 = 0x12002111;
 358     cpu->id_isar2 = 0x11231121;
 359     cpu->id_isar3 = 0x01102131;
 360     cpu->id_isar4 = 0x01141;
 361     cpu->reset_auxcr = 7;
 362 }
 363
 364 static void arm11mpcore_initfn(Object *obj)
 365 {
 366     ARMCPU *cpu = ARM_CPU(obj);
 367     set_feature(&cpu->env, ARM_FEATURE_V6K);
 368     set_feature(&cpu->env, ARM_FEATURE_VFP);
 369     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 370     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 371     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 372     cpu->midr = 0x410fb022;
 373     cpu->reset_fpsid = 0x410120b4;
 374     cpu->mvfr0 = 0x11111111;
 375     cpu->mvfr1 = 0x00000000;
 376     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 377     cpu->id_pfr0 = 0x111;
 378     cpu->id_pfr1 = 0x1;
 379     cpu->id_dfr0 = 0;
 380     cpu->id_afr0 = 0x2;
 381     cpu->id_mmfr0 = 0x01100103;
 382     cpu->id_mmfr1 = 0x10020302;
 383     cpu->id_mmfr2 = 0x01222000;
 384     cpu->id_isar0 = 0x00100011;
 385     cpu->id_isar1 = 0x12002111;
 386     cpu->id_isar2 = 0x11221011;
 387     cpu->id_isar3 = 0x01102131;
 388     cpu->id_isar4 = 0x141;
 389     cpu->reset_auxcr = 1;
 390 }
 391
 392 static void cortex_m3_initfn(Object *obj)
 393 {
 394     ARMCPU *cpu = ARM_CPU(obj);
 395     set_feature(&cpu->env, ARM_FEATURE_V7);
 396     set_feature(&cpu->env, ARM_FEATURE_M);
 397     cpu->midr = 0x410fc231;
 398 }
 399
 400 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 401     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 402       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 403     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 404       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 405     REGINFO_SENTINEL
 406 };
 407
 408 static void cortex_a8_initfn(Object *obj)
 409 {
 410     ARMCPU *cpu = ARM_CPU(obj);
 411     set_feature(&cpu->env, ARM_FEATURE_V7);
 412     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 413     set_feature(&cpu->env, ARM_FEATURE_NEON);
 414     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 415     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 416     cpu->midr = 0x410fc080;
 417     cpu->reset_fpsid = 0x410330c0;
 418     cpu->mvfr0 = 0x11110222;
 419     cpu->mvfr1 = 0x00011100;
 420     cpu->ctr = 0x82048004;
 421     cpu->reset_sctlr = 0x00c50078;
 422     cpu->id_pfr0 = 0x1031;
 423     cpu->id_pfr1 = 0x11;
 424     cpu->id_dfr0 = 0x400;
 425     cpu->id_afr0 = 0;
 426     cpu->id_mmfr0 = 0x31100003;
 427     cpu->id_mmfr1 = 0x20000000;
 428     cpu->id_mmfr2 = 0x01202000;
 429     cpu->id_mmfr3 = 0x11;
 430     cpu->id_isar0 = 0x00101111;
 431     cpu->id_isar1 = 0x12112111;
 432     cpu->id_isar2 = 0x21232031;
 433     cpu->id_isar3 = 0x11112131;
 434     cpu->id_isar4 = 0x00111142;
 435     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 436     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 437     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 438     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 439     cpu->reset_auxcr = 2;
 440     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 441 }
 442
 443 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 444     /* power_control should be set to maximum latency. Again,
 445      * default to 0 and set by private hook
 446      */
 447     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 448       .access = PL1_RW, .resetvalue = 0,
 449       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 450     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 451       .access = PL1_RW, .resetvalue = 0,
 452       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 453     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 454       .access = PL1_RW, .resetvalue = 0,
 455       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 456     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 457       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 458     /* TLB lockdown control */
 459     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 460       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 461     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 462       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 463     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 464       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 465     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 466       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 467     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 468       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 469     REGINFO_SENTINEL
 470 };
 471
 472 static void cortex_a9_initfn(Object *obj)
 473 {
 474     ARMCPU *cpu = ARM_CPU(obj);
 475     set_feature(&cpu->env, ARM_FEATURE_V7);
 476     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 477     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 478     set_feature(&cpu->env, ARM_FEATURE_NEON);
 479     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 480     /* Note that A9 supports the MP extensions even for
 481      * A9UP and single-core A9MP (which are both different
 482      * and valid configurations; we don't model A9UP).
 483      */
 484     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 485     cpu->midr = 0x410fc090;
 486     cpu->reset_fpsid = 0x41033090;
 487     cpu->mvfr0 = 0x11110222;
 488     cpu->mvfr1 = 0x01111111;
 489     cpu->ctr = 0x80038003;
 490     cpu->reset_sctlr = 0x00c50078;
 491     cpu->id_pfr0 = 0x1031;
 492     cpu->id_pfr1 = 0x11;
 493     cpu->id_dfr0 = 0x000;
 494     cpu->id_afr0 = 0;
 495     cpu->id_mmfr0 = 0x00100103;
 496     cpu->id_mmfr1 = 0x20000000;
 497     cpu->id_mmfr2 = 0x01230000;
 498     cpu->id_mmfr3 = 0x00002111;
 499     cpu->id_isar0 = 0x00101111;
 500     cpu->id_isar1 = 0x13112111;
 501     cpu->id_isar2 = 0x21232041;
 502     cpu->id_isar3 = 0x11112131;
 503     cpu->id_isar4 = 0x00111142;
 504     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 505     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 506     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 507     {
 508         ARMCPRegInfo cbar = {
 509             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 510             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 511             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 512         };
 513         define_one_arm_cp_reg(cpu, &cbar);
 514         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 515     }
 516 }
 517
 518 #ifndef CONFIG_USER_ONLY
 519 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 520                            uint64_t *value)
 521 {
 522     /* Linux wants the number of processors from here.
 523      * Might as well set the interrupt-controller bit too.
 524      */
 525     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 526     return 0;
 527 }
 528 #endif
 529
 530 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 531 #ifndef CONFIG_USER_ONLY
 532     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 533       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 534       .writefn = arm_cp_write_ignore, },
 535 #endif
 536     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 537       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 538     REGINFO_SENTINEL
 539 };
 540
 541 static void cortex_a15_initfn(Object *obj)
 542 {
 543     ARMCPU *cpu = ARM_CPU(obj);
 544     set_feature(&cpu->env, ARM_FEATURE_V7);
 545     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 546     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 547     set_feature(&cpu->env, ARM_FEATURE_NEON);
 548     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 549     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 550     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 551     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 552     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 553     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 554     cpu->midr = 0x412fc0f1;
 555     cpu->reset_fpsid = 0x410430f0;
 556     cpu->mvfr0 = 0x10110222;
 557     cpu->mvfr1 = 0x11111111;
 558     cpu->ctr = 0x8444c004;
 559     cpu->reset_sctlr = 0x00c50078;
 560     cpu->id_pfr0 = 0x00001131;
 561     cpu->id_pfr1 = 0x00011011;
 562     cpu->id_dfr0 = 0x02010555;
 563     cpu->id_afr0 = 0x00000000;
 564     cpu->id_mmfr0 = 0x10201105;
 565     cpu->id_mmfr1 = 0x20000000;
 566     cpu->id_mmfr2 = 0x01240000;
 567     cpu->id_mmfr3 = 0x02102211;
 568     cpu->id_isar0 = 0x02101110;
 569     cpu->id_isar1 = 0x13112111;
 570     cpu->id_isar2 = 0x21232041;
 571     cpu->id_isar3 = 0x11112131;
 572     cpu->id_isar4 = 0x10011142;
 573     cpu->clidr = 0x0a200023;
 574     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 575     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 576     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 577     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 578 }
 579
 580 static void ti925t_initfn(Object *obj)
 581 {
 582     ARMCPU *cpu = ARM_CPU(obj);
 583     set_feature(&cpu->env, ARM_FEATURE_V4T);
 584     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 585     cpu->midr = ARM_CPUID_TI925T;
 586     cpu->ctr = 0x5109149;
 587     cpu->reset_sctlr = 0x00000070;
 588 }
 589
 590 static void sa1100_initfn(Object *obj)
 591 {
 592     ARMCPU *cpu = ARM_CPU(obj);
 593     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 594     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 595     cpu->midr = 0x4401A11B;
 596     cpu->reset_sctlr = 0x00000070;
 597 }
 598
 599 static void sa1110_initfn(Object *obj)
 600 {
 601     ARMCPU *cpu = ARM_CPU(obj);
 602     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 603     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 604     cpu->midr = 0x6901B119;
 605     cpu->reset_sctlr = 0x00000070;
 606 }
 607
 608 static void pxa250_initfn(Object *obj)
 609 {
 610     ARMCPU *cpu = ARM_CPU(obj);
 611     set_feature(&cpu->env, ARM_FEATURE_V5);
 612     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 613     cpu->midr = 0x69052100;
 614     cpu->ctr = 0xd172172;
 615     cpu->reset_sctlr = 0x00000078;
 616 }
 617
 618 static void pxa255_initfn(Object *obj)
 619 {
 620     ARMCPU *cpu = ARM_CPU(obj);
 621     set_feature(&cpu->env, ARM_FEATURE_V5);
 622     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 623     cpu->midr = 0x69052d00;
 624     cpu->ctr = 0xd172172;
 625     cpu->reset_sctlr = 0x00000078;
 626 }
 627
 628 static void pxa260_initfn(Object *obj)
 629 {
 630     ARMCPU *cpu = ARM_CPU(obj);
 631     set_feature(&cpu->env, ARM_FEATURE_V5);
 632     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 633     cpu->midr = 0x69052903;
 634     cpu->ctr = 0xd172172;
 635     cpu->reset_sctlr = 0x00000078;
 636 }
 637
 638 static void pxa261_initfn(Object *obj)
 639 {
 640     ARMCPU *cpu = ARM_CPU(obj);
 641     set_feature(&cpu->env, ARM_FEATURE_V5);
 642     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 643     cpu->midr = 0x69052d05;
 644     cpu->ctr = 0xd172172;
 645     cpu->reset_sctlr = 0x00000078;
 646 }
 647
 648 static void pxa262_initfn(Object *obj)
 649 {
 650     ARMCPU *cpu = ARM_CPU(obj);
 651     set_feature(&cpu->env, ARM_FEATURE_V5);
 652     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 653     cpu->midr = 0x69052d06;
 654     cpu->ctr = 0xd172172;
 655     cpu->reset_sctlr = 0x00000078;
 656 }
 657
 658 static void pxa270a0_initfn(Object *obj)
 659 {
 660     ARMCPU *cpu = ARM_CPU(obj);
 661     set_feature(&cpu->env, ARM_FEATURE_V5);
 662     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 663     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 664     cpu->midr = 0x69054110;
 665     cpu->ctr = 0xd172172;
 666     cpu->reset_sctlr = 0x00000078;
 667 }
 668
 669 static void pxa270a1_initfn(Object *obj)
 670 {
 671     ARMCPU *cpu = ARM_CPU(obj);
 672     set_feature(&cpu->env, ARM_FEATURE_V5);
 673     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 674     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 675     cpu->midr = 0x69054111;
 676     cpu->ctr = 0xd172172;
 677     cpu->reset_sctlr = 0x00000078;
 678 }
 679
 680 static void pxa270b0_initfn(Object *obj)
 681 {
 682     ARMCPU *cpu = ARM_CPU(obj);
 683     set_feature(&cpu->env, ARM_FEATURE_V5);
 684     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 685     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 686     cpu->midr = 0x69054112;
 687     cpu->ctr = 0xd172172;
 688     cpu->reset_sctlr = 0x00000078;
 689 }
 690
 691 static void pxa270b1_initfn(Object *obj)
 692 {
 693     ARMCPU *cpu = ARM_CPU(obj);
 694     set_feature(&cpu->env, ARM_FEATURE_V5);
 695     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 696     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 697     cpu->midr = 0x69054113;
 698     cpu->ctr = 0xd172172;
 699     cpu->reset_sctlr = 0x00000078;
 700 }
 701
 702 static void pxa270c0_initfn(Object *obj)
 703 {
 704     ARMCPU *cpu = ARM_CPU(obj);
 705     set_feature(&cpu->env, ARM_FEATURE_V5);
 706     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 707     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 708     cpu->midr = 0x69054114;
 709     cpu->ctr = 0xd172172;
 710     cpu->reset_sctlr = 0x00000078;
 711 }
 712
 713 static void pxa270c5_initfn(Object *obj)
 714 {
 715     ARMCPU *cpu = ARM_CPU(obj);
 716     set_feature(&cpu->env, ARM_FEATURE_V5);
 717     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 718     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 719     cpu->midr = 0x69054117;
 720     cpu->ctr = 0xd172172;
 721     cpu->reset_sctlr = 0x00000078;
 722 }
 723
 724 static void arm_any_initfn(Object *obj)
 725 {
 726     ARMCPU *cpu = ARM_CPU(obj);
 727     set_feature(&cpu->env, ARM_FEATURE_V7);
 728     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 729     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 730     set_feature(&cpu->env, ARM_FEATURE_NEON);
 731     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 732     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 733     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 734     cpu->midr = 0xffffffff;
 735 }
 736
 737 typedef struct ARMCPUInfo {
 738     const char *name;
 739     void (*initfn)(Object *obj);
 740 } ARMCPUInfo;
 741
 742 static const ARMCPUInfo arm_cpus[] = {
 743     { .name = "arm926",      .initfn = arm926_initfn },
 744     { .name = "arm946",      .initfn = arm946_initfn },
 745     { .name = "arm1026",     .initfn = arm1026_initfn },
 746     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 747      * older core than plain "arm1136". In particular this does not
 748      * have the v6K features.
 749      */
 750     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 751     { .name = "arm1136",     .initfn = arm1136_initfn },
 752     { .name = "arm1176",     .initfn = arm1176_initfn },
 753     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 754     { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
 755     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 756     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 757     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 758     { .name = "ti925t",      .initfn = ti925t_initfn },
 759     { .name = "sa1100",      .initfn = sa1100_initfn },
 760     { .name = "sa1110",      .initfn = sa1110_initfn },
 761     { .name = "pxa250",      .initfn = pxa250_initfn },
 762     { .name = "pxa255",      .initfn = pxa255_initfn },
 763     { .name = "pxa260",      .initfn = pxa260_initfn },
 764     { .name = "pxa261",      .initfn = pxa261_initfn },
 765     { .name = "pxa262",      .initfn = pxa262_initfn },
 766     /* "pxa270" is an alias for "pxa270-a0" */
 767     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 768     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 769     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 770     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 771     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 772     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 773     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 774     { .name = "any",         .initfn = arm_any_initfn },
 775 };
 776
 777 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 778 {
 779     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 780     CPUClass *cc = CPU_CLASS(acc);
 781
 782     acc->parent_reset = cc->reset;
 783     cc->reset = arm_cpu_reset;
 784
 785     cc->class_by_name = arm_cpu_class_by_name;
 786 }
 787
 788 static void cpu_register(const ARMCPUInfo *info)
 789 {
 790     TypeInfo type_info = {
 791         .name = info->name,
 792         .parent = TYPE_ARM_CPU,
 793         .instance_size = sizeof(ARMCPU),
 794         .instance_init = info->initfn,
 795         .class_size = sizeof(ARMCPUClass),
 796     };
 797
 798     type_register(&type_info);
 799 }
 800
 801 static const TypeInfo arm_cpu_type_info = {
 802     .name = TYPE_ARM_CPU,
 803     .parent = TYPE_CPU,
 804     .instance_size = sizeof(ARMCPU),
 805     .instance_init = arm_cpu_initfn,
 806     .instance_finalize = arm_cpu_finalizefn,
 807     .abstract = true,
 808     .class_size = sizeof(ARMCPUClass),
 809     .class_init = arm_cpu_class_init,
 810 };
 811
 812 static void arm_cpu_register_types(void)
 813 {
 814     int i;
 815
 816     type_register_static(&arm_cpu_type_info);
 817     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 818         cpu_register(&arm_cpus[i]);
 819     }
 820 }
 821
 822 type_init(arm_cpu_register_types)