4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
22 #include "qemu-common.h"
23 #if !defined(CONFIG_USER_ONLY)
24 #include "hw/loader.h"
26 #include "sysemu/sysemu.h"
28 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
30 /* Reset a single ARMCPRegInfo register */
31 ARMCPRegInfo
*ri
= value
;
34 if (ri
->type
& ARM_CP_SPECIAL
) {
39 ri
->resetfn(&cpu
->env
, ri
);
43 /* A zero offset is never possible as it would be regs[0]
44 * so we use it to indicate that reset is being handled elsewhere.
45 * This is basically only used for fields in non-core coprocessors
46 * (like the pxa2xx ones).
48 if (!ri
->fieldoffset
) {
52 if (ri
->type
& ARM_CP_64BIT
) {
53 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
55 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
59 /* CPUClass::reset() */
60 static void arm_cpu_reset(CPUState
*s
)
62 ARMCPU
*cpu
= ARM_CPU(s
);
63 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
64 CPUARMState
*env
= &cpu
->env
;
66 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
67 qemu_log("CPU Reset (CPU %d)\n", s
->cpu_index
);
68 log_cpu_state(env
, 0);
73 memset(env
, 0, offsetof(CPUARMState
, breakpoints
));
74 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
75 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
76 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
77 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
79 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
80 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
83 #if defined(CONFIG_USER_ONLY)
84 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
85 /* For user mode we must enable access to coprocessors */
86 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
87 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
88 env
->cp15
.c15_cpar
= 3;
89 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
90 env
->cp15
.c15_cpar
= 1;
93 /* SVC mode with interrupts disabled. */
94 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
| CPSR_A
| CPSR_F
| CPSR_I
;
95 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
96 clear at reset. Initial SP and PC are loaded from ROM. */
100 env
->uncached_cpsr
&= ~CPSR_I
;
103 /* We should really use ldl_phys here, in case the guest
104 modified flash and reset itself. However images
105 loaded via -kernel have not been copied yet, so load the
106 values directly from there. */
107 env
->regs
[13] = ldl_p(rom
);
110 env
->regs
[15] = pc
& ~1;
113 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
115 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
116 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
117 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
118 set_float_detect_tininess(float_tininess_before_rounding
,
119 &env
->vfp
.fp_status
);
120 set_float_detect_tininess(float_tininess_before_rounding
,
121 &env
->vfp
.standard_fp_status
);
123 /* Reset is a state change for some CPUARMState fields which we
124 * bake assumptions about into translated code, so we need to
130 static inline void set_feature(CPUARMState
*env
, int feature
)
132 env
->features
|= 1ULL << feature
;
135 static void arm_cpu_initfn(Object
*obj
)
137 CPUState
*cs
= CPU(obj
);
138 ARMCPU
*cpu
= ARM_CPU(obj
);
141 cs
->env_ptr
= &cpu
->env
;
142 cpu_exec_init(&cpu
->env
);
143 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
146 if (tcg_enabled() && !inited
) {
148 arm_translate_init();
152 static void arm_cpu_finalizefn(Object
*obj
)
154 ARMCPU
*cpu
= ARM_CPU(obj
);
155 g_hash_table_destroy(cpu
->cp_regs
);
158 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
160 ARMCPU
*cpu
= ARM_CPU(dev
);
161 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
162 CPUARMState
*env
= &cpu
->env
;
164 /* Some features automatically imply others: */
165 if (arm_feature(env
, ARM_FEATURE_V7
)) {
166 set_feature(env
, ARM_FEATURE_VAPA
);
167 set_feature(env
, ARM_FEATURE_THUMB2
);
168 set_feature(env
, ARM_FEATURE_MPIDR
);
169 if (!arm_feature(env
, ARM_FEATURE_M
)) {
170 set_feature(env
, ARM_FEATURE_V6K
);
172 set_feature(env
, ARM_FEATURE_V6
);
175 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
176 set_feature(env
, ARM_FEATURE_V6
);
177 set_feature(env
, ARM_FEATURE_MVFR
);
179 if (arm_feature(env
, ARM_FEATURE_V6
)) {
180 set_feature(env
, ARM_FEATURE_V5
);
181 if (!arm_feature(env
, ARM_FEATURE_M
)) {
182 set_feature(env
, ARM_FEATURE_AUXCR
);
185 if (arm_feature(env
, ARM_FEATURE_V5
)) {
186 set_feature(env
, ARM_FEATURE_V4T
);
188 if (arm_feature(env
, ARM_FEATURE_M
)) {
189 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
191 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
192 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
194 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
195 set_feature(env
, ARM_FEATURE_VFP3
);
197 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
198 set_feature(env
, ARM_FEATURE_VFP
);
200 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
201 set_feature(env
, ARM_FEATURE_V7MP
);
202 set_feature(env
, ARM_FEATURE_PXN
);
205 register_cp_regs_for_features(cpu
);
206 arm_cpu_register_gdb_regs_for_features(cpu
);
208 init_cpreg_list(cpu
);
213 acc
->parent_realize(dev
, errp
);
218 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
227 typename
= g_strdup_printf("%s-" TYPE_ARM_CPU
, cpu_model
);
228 oc
= object_class_by_name(typename
);
230 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
231 object_class_is_abstract(oc
)) {
237 static void arm926_initfn(Object
*obj
)
239 ARMCPU
*cpu
= ARM_CPU(obj
);
240 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
241 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
242 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
243 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
244 cpu
->midr
= 0x41069265;
245 cpu
->reset_fpsid
= 0x41011090;
246 cpu
->ctr
= 0x1dd20d2;
247 cpu
->reset_sctlr
= 0x00090078;
250 static void arm946_initfn(Object
*obj
)
252 ARMCPU
*cpu
= ARM_CPU(obj
);
253 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
254 set_feature(&cpu
->env
, ARM_FEATURE_MPU
);
255 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
256 cpu
->midr
= 0x41059461;
257 cpu
->ctr
= 0x0f004006;
258 cpu
->reset_sctlr
= 0x00000078;
261 static void arm1026_initfn(Object
*obj
)
263 ARMCPU
*cpu
= ARM_CPU(obj
);
264 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
265 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
266 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
267 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
268 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
269 cpu
->midr
= 0x4106a262;
270 cpu
->reset_fpsid
= 0x410110a0;
271 cpu
->ctr
= 0x1dd20d2;
272 cpu
->reset_sctlr
= 0x00090078;
273 cpu
->reset_auxcr
= 1;
275 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
276 ARMCPRegInfo ifar
= {
277 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
279 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
282 define_one_arm_cp_reg(cpu
, &ifar
);
286 static void arm1136_r2_initfn(Object
*obj
)
288 ARMCPU
*cpu
= ARM_CPU(obj
);
289 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
290 * older core than plain "arm1136". In particular this does not
291 * have the v6K features.
292 * These ID register values are correct for 1136 but may be wrong
293 * for 1136_r2 (in particular r0p2 does not actually implement most
294 * of the ID registers).
296 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
297 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
298 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
299 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
300 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
301 cpu
->midr
= 0x4107b362;
302 cpu
->reset_fpsid
= 0x410120b4;
303 cpu
->mvfr0
= 0x11111111;
304 cpu
->mvfr1
= 0x00000000;
305 cpu
->ctr
= 0x1dd20d2;
306 cpu
->reset_sctlr
= 0x00050078;
307 cpu
->id_pfr0
= 0x111;
311 cpu
->id_mmfr0
= 0x01130003;
312 cpu
->id_mmfr1
= 0x10030302;
313 cpu
->id_mmfr2
= 0x01222110;
314 cpu
->id_isar0
= 0x00140011;
315 cpu
->id_isar1
= 0x12002111;
316 cpu
->id_isar2
= 0x11231111;
317 cpu
->id_isar3
= 0x01102131;
318 cpu
->id_isar4
= 0x141;
319 cpu
->reset_auxcr
= 7;
322 static void arm1136_initfn(Object
*obj
)
324 ARMCPU
*cpu
= ARM_CPU(obj
);
325 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
326 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
327 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
328 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
329 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
330 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
331 cpu
->midr
= 0x4117b363;
332 cpu
->reset_fpsid
= 0x410120b4;
333 cpu
->mvfr0
= 0x11111111;
334 cpu
->mvfr1
= 0x00000000;
335 cpu
->ctr
= 0x1dd20d2;
336 cpu
->reset_sctlr
= 0x00050078;
337 cpu
->id_pfr0
= 0x111;
341 cpu
->id_mmfr0
= 0x01130003;
342 cpu
->id_mmfr1
= 0x10030302;
343 cpu
->id_mmfr2
= 0x01222110;
344 cpu
->id_isar0
= 0x00140011;
345 cpu
->id_isar1
= 0x12002111;
346 cpu
->id_isar2
= 0x11231111;
347 cpu
->id_isar3
= 0x01102131;
348 cpu
->id_isar4
= 0x141;
349 cpu
->reset_auxcr
= 7;
352 static void arm1176_initfn(Object
*obj
)
354 ARMCPU
*cpu
= ARM_CPU(obj
);
355 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
356 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
357 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
358 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
359 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
360 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
361 cpu
->midr
= 0x410fb767;
362 cpu
->reset_fpsid
= 0x410120b5;
363 cpu
->mvfr0
= 0x11111111;
364 cpu
->mvfr1
= 0x00000000;
365 cpu
->ctr
= 0x1dd20d2;
366 cpu
->reset_sctlr
= 0x00050078;
367 cpu
->id_pfr0
= 0x111;
371 cpu
->id_mmfr0
= 0x01130003;
372 cpu
->id_mmfr1
= 0x10030302;
373 cpu
->id_mmfr2
= 0x01222100;
374 cpu
->id_isar0
= 0x0140011;
375 cpu
->id_isar1
= 0x12002111;
376 cpu
->id_isar2
= 0x11231121;
377 cpu
->id_isar3
= 0x01102131;
378 cpu
->id_isar4
= 0x01141;
379 cpu
->reset_auxcr
= 7;
382 static void arm11mpcore_initfn(Object
*obj
)
384 ARMCPU
*cpu
= ARM_CPU(obj
);
385 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
386 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
387 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
388 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
389 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
390 cpu
->midr
= 0x410fb022;
391 cpu
->reset_fpsid
= 0x410120b4;
392 cpu
->mvfr0
= 0x11111111;
393 cpu
->mvfr1
= 0x00000000;
394 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
395 cpu
->id_pfr0
= 0x111;
399 cpu
->id_mmfr0
= 0x01100103;
400 cpu
->id_mmfr1
= 0x10020302;
401 cpu
->id_mmfr2
= 0x01222000;
402 cpu
->id_isar0
= 0x00100011;
403 cpu
->id_isar1
= 0x12002111;
404 cpu
->id_isar2
= 0x11221011;
405 cpu
->id_isar3
= 0x01102131;
406 cpu
->id_isar4
= 0x141;
407 cpu
->reset_auxcr
= 1;
410 static void cortex_m3_initfn(Object
*obj
)
412 ARMCPU
*cpu
= ARM_CPU(obj
);
413 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
414 set_feature(&cpu
->env
, ARM_FEATURE_M
);
415 cpu
->midr
= 0x410fc231;
418 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
420 #ifndef CONFIG_USER_ONLY
421 CPUClass
*cc
= CPU_CLASS(oc
);
423 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
427 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
428 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
429 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
430 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
431 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
435 static void cortex_a8_initfn(Object
*obj
)
437 ARMCPU
*cpu
= ARM_CPU(obj
);
438 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
439 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
440 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
441 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
442 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
443 cpu
->midr
= 0x410fc080;
444 cpu
->reset_fpsid
= 0x410330c0;
445 cpu
->mvfr0
= 0x11110222;
446 cpu
->mvfr1
= 0x00011100;
447 cpu
->ctr
= 0x82048004;
448 cpu
->reset_sctlr
= 0x00c50078;
449 cpu
->id_pfr0
= 0x1031;
451 cpu
->id_dfr0
= 0x400;
453 cpu
->id_mmfr0
= 0x31100003;
454 cpu
->id_mmfr1
= 0x20000000;
455 cpu
->id_mmfr2
= 0x01202000;
456 cpu
->id_mmfr3
= 0x11;
457 cpu
->id_isar0
= 0x00101111;
458 cpu
->id_isar1
= 0x12112111;
459 cpu
->id_isar2
= 0x21232031;
460 cpu
->id_isar3
= 0x11112131;
461 cpu
->id_isar4
= 0x00111142;
462 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
463 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
464 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
465 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
466 cpu
->reset_auxcr
= 2;
467 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
470 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
471 /* power_control should be set to maximum latency. Again,
472 * default to 0 and set by private hook
474 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
475 .access
= PL1_RW
, .resetvalue
= 0,
476 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
477 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
478 .access
= PL1_RW
, .resetvalue
= 0,
479 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
480 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
481 .access
= PL1_RW
, .resetvalue
= 0,
482 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
483 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
484 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
485 /* TLB lockdown control */
486 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
487 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
488 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
489 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
490 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
491 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
492 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
493 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
494 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
495 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
499 static void cortex_a9_initfn(Object
*obj
)
501 ARMCPU
*cpu
= ARM_CPU(obj
);
502 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
503 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
504 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
505 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
506 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
507 /* Note that A9 supports the MP extensions even for
508 * A9UP and single-core A9MP (which are both different
509 * and valid configurations; we don't model A9UP).
511 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
512 cpu
->midr
= 0x410fc090;
513 cpu
->reset_fpsid
= 0x41033090;
514 cpu
->mvfr0
= 0x11110222;
515 cpu
->mvfr1
= 0x01111111;
516 cpu
->ctr
= 0x80038003;
517 cpu
->reset_sctlr
= 0x00c50078;
518 cpu
->id_pfr0
= 0x1031;
520 cpu
->id_dfr0
= 0x000;
522 cpu
->id_mmfr0
= 0x00100103;
523 cpu
->id_mmfr1
= 0x20000000;
524 cpu
->id_mmfr2
= 0x01230000;
525 cpu
->id_mmfr3
= 0x00002111;
526 cpu
->id_isar0
= 0x00101111;
527 cpu
->id_isar1
= 0x13112111;
528 cpu
->id_isar2
= 0x21232041;
529 cpu
->id_isar3
= 0x11112131;
530 cpu
->id_isar4
= 0x00111142;
531 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
532 cpu
->ccsidr
[0] = 0xe00fe015; /* 16k L1 dcache. */
533 cpu
->ccsidr
[1] = 0x200fe015; /* 16k L1 icache. */
535 ARMCPRegInfo cbar
= {
536 .name
= "CBAR", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4,
537 .opc2
= 0, .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
538 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_config_base_address
)
540 define_one_arm_cp_reg(cpu
, &cbar
);
541 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
545 #ifndef CONFIG_USER_ONLY
546 static int a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
549 /* Linux wants the number of processors from here.
550 * Might as well set the interrupt-controller bit too.
552 *value
= ((smp_cpus
- 1) << 24) | (1 << 23);
557 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
558 #ifndef CONFIG_USER_ONLY
559 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
560 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
561 .writefn
= arm_cp_write_ignore
, },
563 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
564 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
568 static void cortex_a15_initfn(Object
*obj
)
570 ARMCPU
*cpu
= ARM_CPU(obj
);
571 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
572 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
573 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
574 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
575 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
576 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
577 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
578 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
579 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
580 cpu
->midr
= 0x412fc0f1;
581 cpu
->reset_fpsid
= 0x410430f0;
582 cpu
->mvfr0
= 0x10110222;
583 cpu
->mvfr1
= 0x11111111;
584 cpu
->ctr
= 0x8444c004;
585 cpu
->reset_sctlr
= 0x00c50078;
586 cpu
->id_pfr0
= 0x00001131;
587 cpu
->id_pfr1
= 0x00011011;
588 cpu
->id_dfr0
= 0x02010555;
589 cpu
->id_afr0
= 0x00000000;
590 cpu
->id_mmfr0
= 0x10201105;
591 cpu
->id_mmfr1
= 0x20000000;
592 cpu
->id_mmfr2
= 0x01240000;
593 cpu
->id_mmfr3
= 0x02102211;
594 cpu
->id_isar0
= 0x02101110;
595 cpu
->id_isar1
= 0x13112111;
596 cpu
->id_isar2
= 0x21232041;
597 cpu
->id_isar3
= 0x11112131;
598 cpu
->id_isar4
= 0x10011142;
599 cpu
->clidr
= 0x0a200023;
600 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
601 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
602 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
603 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
606 static void ti925t_initfn(Object
*obj
)
608 ARMCPU
*cpu
= ARM_CPU(obj
);
609 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
610 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
611 cpu
->midr
= ARM_CPUID_TI925T
;
612 cpu
->ctr
= 0x5109149;
613 cpu
->reset_sctlr
= 0x00000070;
616 static void sa1100_initfn(Object
*obj
)
618 ARMCPU
*cpu
= ARM_CPU(obj
);
619 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
620 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
621 cpu
->midr
= 0x4401A11B;
622 cpu
->reset_sctlr
= 0x00000070;
625 static void sa1110_initfn(Object
*obj
)
627 ARMCPU
*cpu
= ARM_CPU(obj
);
628 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
629 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
630 cpu
->midr
= 0x6901B119;
631 cpu
->reset_sctlr
= 0x00000070;
634 static void pxa250_initfn(Object
*obj
)
636 ARMCPU
*cpu
= ARM_CPU(obj
);
637 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
638 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
639 cpu
->midr
= 0x69052100;
640 cpu
->ctr
= 0xd172172;
641 cpu
->reset_sctlr
= 0x00000078;
644 static void pxa255_initfn(Object
*obj
)
646 ARMCPU
*cpu
= ARM_CPU(obj
);
647 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
648 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
649 cpu
->midr
= 0x69052d00;
650 cpu
->ctr
= 0xd172172;
651 cpu
->reset_sctlr
= 0x00000078;
654 static void pxa260_initfn(Object
*obj
)
656 ARMCPU
*cpu
= ARM_CPU(obj
);
657 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
658 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
659 cpu
->midr
= 0x69052903;
660 cpu
->ctr
= 0xd172172;
661 cpu
->reset_sctlr
= 0x00000078;
664 static void pxa261_initfn(Object
*obj
)
666 ARMCPU
*cpu
= ARM_CPU(obj
);
667 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
668 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
669 cpu
->midr
= 0x69052d05;
670 cpu
->ctr
= 0xd172172;
671 cpu
->reset_sctlr
= 0x00000078;
674 static void pxa262_initfn(Object
*obj
)
676 ARMCPU
*cpu
= ARM_CPU(obj
);
677 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
678 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
679 cpu
->midr
= 0x69052d06;
680 cpu
->ctr
= 0xd172172;
681 cpu
->reset_sctlr
= 0x00000078;
684 static void pxa270a0_initfn(Object
*obj
)
686 ARMCPU
*cpu
= ARM_CPU(obj
);
687 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
688 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
689 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
690 cpu
->midr
= 0x69054110;
691 cpu
->ctr
= 0xd172172;
692 cpu
->reset_sctlr
= 0x00000078;
695 static void pxa270a1_initfn(Object
*obj
)
697 ARMCPU
*cpu
= ARM_CPU(obj
);
698 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
699 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
700 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
701 cpu
->midr
= 0x69054111;
702 cpu
->ctr
= 0xd172172;
703 cpu
->reset_sctlr
= 0x00000078;
706 static void pxa270b0_initfn(Object
*obj
)
708 ARMCPU
*cpu
= ARM_CPU(obj
);
709 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
710 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
711 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
712 cpu
->midr
= 0x69054112;
713 cpu
->ctr
= 0xd172172;
714 cpu
->reset_sctlr
= 0x00000078;
717 static void pxa270b1_initfn(Object
*obj
)
719 ARMCPU
*cpu
= ARM_CPU(obj
);
720 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
721 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
722 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
723 cpu
->midr
= 0x69054113;
724 cpu
->ctr
= 0xd172172;
725 cpu
->reset_sctlr
= 0x00000078;
728 static void pxa270c0_initfn(Object
*obj
)
730 ARMCPU
*cpu
= ARM_CPU(obj
);
731 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
732 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
733 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
734 cpu
->midr
= 0x69054114;
735 cpu
->ctr
= 0xd172172;
736 cpu
->reset_sctlr
= 0x00000078;
739 static void pxa270c5_initfn(Object
*obj
)
741 ARMCPU
*cpu
= ARM_CPU(obj
);
742 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
743 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
744 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
745 cpu
->midr
= 0x69054117;
746 cpu
->ctr
= 0xd172172;
747 cpu
->reset_sctlr
= 0x00000078;
750 static void arm_any_initfn(Object
*obj
)
752 ARMCPU
*cpu
= ARM_CPU(obj
);
753 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
754 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
755 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
756 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
757 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
758 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
759 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
760 cpu
->midr
= 0xffffffff;
763 typedef struct ARMCPUInfo
{
765 void (*initfn
)(Object
*obj
);
766 void (*class_init
)(ObjectClass
*oc
, void *data
);
769 static const ARMCPUInfo arm_cpus
[] = {
770 { .name
= "arm926", .initfn
= arm926_initfn
},
771 { .name
= "arm946", .initfn
= arm946_initfn
},
772 { .name
= "arm1026", .initfn
= arm1026_initfn
},
773 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
774 * older core than plain "arm1136". In particular this does not
775 * have the v6K features.
777 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
778 { .name
= "arm1136", .initfn
= arm1136_initfn
},
779 { .name
= "arm1176", .initfn
= arm1176_initfn
},
780 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
781 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
782 .class_init
= arm_v7m_class_init
},
783 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
784 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
785 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
786 { .name
= "ti925t", .initfn
= ti925t_initfn
},
787 { .name
= "sa1100", .initfn
= sa1100_initfn
},
788 { .name
= "sa1110", .initfn
= sa1110_initfn
},
789 { .name
= "pxa250", .initfn
= pxa250_initfn
},
790 { .name
= "pxa255", .initfn
= pxa255_initfn
},
791 { .name
= "pxa260", .initfn
= pxa260_initfn
},
792 { .name
= "pxa261", .initfn
= pxa261_initfn
},
793 { .name
= "pxa262", .initfn
= pxa262_initfn
},
794 /* "pxa270" is an alias for "pxa270-a0" */
795 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
796 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
797 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
798 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
799 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
800 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
801 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
802 { .name
= "any", .initfn
= arm_any_initfn
},
805 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
807 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
808 CPUClass
*cc
= CPU_CLASS(acc
);
809 DeviceClass
*dc
= DEVICE_CLASS(oc
);
811 acc
->parent_realize
= dc
->realize
;
812 dc
->realize
= arm_cpu_realizefn
;
814 acc
->parent_reset
= cc
->reset
;
815 cc
->reset
= arm_cpu_reset
;
817 cc
->class_by_name
= arm_cpu_class_by_name
;
818 cc
->do_interrupt
= arm_cpu_do_interrupt
;
819 cc
->dump_state
= arm_cpu_dump_state
;
820 cpu_class_set_vmsd(cc
, &vmstate_arm_cpu
);
823 static void cpu_register(const ARMCPUInfo
*info
)
825 TypeInfo type_info
= {
826 .parent
= TYPE_ARM_CPU
,
827 .instance_size
= sizeof(ARMCPU
),
828 .instance_init
= info
->initfn
,
829 .class_size
= sizeof(ARMCPUClass
),
830 .class_init
= info
->class_init
,
833 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
834 type_register(&type_info
);
835 g_free((void *)type_info
.name
);
838 static const TypeInfo arm_cpu_type_info
= {
839 .name
= TYPE_ARM_CPU
,
841 .instance_size
= sizeof(ARMCPU
),
842 .instance_init
= arm_cpu_initfn
,
843 .instance_finalize
= arm_cpu_finalizefn
,
845 .class_size
= sizeof(ARMCPUClass
),
846 .class_init
= arm_cpu_class_init
,
849 static void arm_cpu_register_types(void)
853 type_register_static(&arm_cpu_type_info
);
854 for (i
= 0; i
< ARRAY_SIZE(arm_cpus
); i
++) {
855 cpu_register(&arm_cpus
[i
]);
859 type_init(arm_cpu_register_types
)