target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26
  27 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  28 {
  29     /* Reset a single ARMCPRegInfo register */
  30     ARMCPRegInfo *ri = value;
  31     ARMCPU *cpu = opaque;
  32
  33     if (ri->type & ARM_CP_SPECIAL) {
  34         return;
  35     }
  36
  37     if (ri->resetfn) {
  38         ri->resetfn(&cpu->env, ri);
  39         return;
  40     }
  41
  42     /* A zero offset is never possible as it would be regs[0]
  43      * so we use it to indicate that reset is being handled elsewhere.
  44      * This is basically only used for fields in non-core coprocessors
  45      * (like the pxa2xx ones).
  46      */
  47     if (!ri->fieldoffset) {
  48         return;
  49     }
  50
  51     if (ri->type & ARM_CP_64BIT) {
  52         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  53     } else {
  54         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  55     }
  56 }
  57
  58 /* CPUClass::reset() */
  59 static void arm_cpu_reset(CPUState *s)
  60 {
  61     ARMCPU *cpu = ARM_CPU(s);
  62     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  63     CPUARMState *env = &cpu->env;
  64
  65     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  66         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
  67         log_cpu_state(env, 0);
  68     }
  69
  70     acc->parent_reset(s);
  71
  72     memset(env, 0, offsetof(CPUARMState, breakpoints));
  73     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  74     env->cp15.c0_cpuid = cpu->midr;
  75     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  76     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  77     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  78     env->cp15.c0_cachetype = cpu->ctr;
  79     env->cp15.c1_sys = cpu->reset_sctlr;
  80     env->cp15.c0_c1[0] = cpu->id_pfr0;
  81     env->cp15.c0_c1[1] = cpu->id_pfr1;
  82     env->cp15.c0_c1[2] = cpu->id_dfr0;
  83     env->cp15.c0_c1[3] = cpu->id_afr0;
  84     env->cp15.c0_c1[4] = cpu->id_mmfr0;
  85     env->cp15.c0_c1[5] = cpu->id_mmfr1;
  86     env->cp15.c0_c1[6] = cpu->id_mmfr2;
  87     env->cp15.c0_c1[7] = cpu->id_mmfr3;
  88     env->cp15.c0_c2[0] = cpu->id_isar0;
  89     env->cp15.c0_c2[1] = cpu->id_isar1;
  90     env->cp15.c0_c2[2] = cpu->id_isar2;
  91     env->cp15.c0_c2[3] = cpu->id_isar3;
  92     env->cp15.c0_c2[4] = cpu->id_isar4;
  93     env->cp15.c0_c2[5] = cpu->id_isar5;
  94     env->cp15.c0_clid = cpu->clidr;
  95     memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
  96
  97     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  98         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  99     }
 100
 101 #if defined(CONFIG_USER_ONLY)
 102     env->uncached_cpsr = ARM_CPU_MODE_USR;
 103     /* For user mode we must enable access to coprocessors */
 104     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 105     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 106         env->cp15.c15_cpar = 3;
 107     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 108         env->cp15.c15_cpar = 1;
 109     }
 110 #else
 111     /* SVC mode with interrupts disabled.  */
 112     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 113     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 114        clear at reset.  Initial SP and PC are loaded from ROM.  */
 115     if (IS_M(env)) {
 116         uint32_t pc;
 117         uint8_t *rom;
 118         env->uncached_cpsr &= ~CPSR_I;
 119         rom = rom_ptr(0);
 120         if (rom) {
 121             /* We should really use ldl_phys here, in case the guest
 122                modified flash and reset itself.  However images
 123                loaded via -kernel have not been copied yet, so load the
 124                values directly from there.  */
 125             env->regs[13] = ldl_p(rom);
 126             pc = ldl_p(rom + 4);
 127             env->thumb = pc & 1;
 128             env->regs[15] = pc & ~1;
 129         }
 130     }
 131     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 132 #endif
 133     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 134     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 135     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 136     set_float_detect_tininess(float_tininess_before_rounding,
 137                               &env->vfp.fp_status);
 138     set_float_detect_tininess(float_tininess_before_rounding,
 139                               &env->vfp.standard_fp_status);
 140     tlb_flush(env, 1);
 141     /* Reset is a state change for some CPUARMState fields which we
 142      * bake assumptions about into translated code, so we need to
 143      * tb_flush().
 144      */
 145     tb_flush(env);
 146 }
 147
 148 static inline void set_feature(CPUARMState *env, int feature)
 149 {
 150     env->features |= 1u << feature;
 151 }
 152
 153 static void arm_cpu_initfn(Object *obj)
 154 {
 155     ARMCPU *cpu = ARM_CPU(obj);
 156
 157     cpu_exec_init(&cpu->env);
 158     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 159                                          g_free, g_free);
 160 }
 161
 162 static void arm_cpu_finalizefn(Object *obj)
 163 {
 164     ARMCPU *cpu = ARM_CPU(obj);
 165     g_hash_table_destroy(cpu->cp_regs);
 166 }
 167
 168 void arm_cpu_realize(ARMCPU *cpu)
 169 {
 170     /* This function is called by cpu_arm_init() because it
 171      * needs to do common actions based on feature bits, etc
 172      * that have been set by the subclass init functions.
 173      * When we have QOM realize support it should become
 174      * a true realize function instead.
 175      */
 176     CPUARMState *env = &cpu->env;
 177     /* Some features automatically imply others: */
 178     if (arm_feature(env, ARM_FEATURE_V7)) {
 179         set_feature(env, ARM_FEATURE_VAPA);
 180         set_feature(env, ARM_FEATURE_THUMB2);
 181         if (!arm_feature(env, ARM_FEATURE_M)) {
 182             set_feature(env, ARM_FEATURE_V6K);
 183         } else {
 184             set_feature(env, ARM_FEATURE_V6);
 185         }
 186     }
 187     if (arm_feature(env, ARM_FEATURE_V6K)) {
 188         set_feature(env, ARM_FEATURE_V6);
 189         set_feature(env, ARM_FEATURE_MVFR);
 190     }
 191     if (arm_feature(env, ARM_FEATURE_V6)) {
 192         set_feature(env, ARM_FEATURE_V5);
 193         if (!arm_feature(env, ARM_FEATURE_M)) {
 194             set_feature(env, ARM_FEATURE_AUXCR);
 195         }
 196     }
 197     if (arm_feature(env, ARM_FEATURE_V5)) {
 198         set_feature(env, ARM_FEATURE_V4T);
 199     }
 200     if (arm_feature(env, ARM_FEATURE_M)) {
 201         set_feature(env, ARM_FEATURE_THUMB_DIV);
 202     }
 203     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 204         set_feature(env, ARM_FEATURE_THUMB_DIV);
 205     }
 206     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 207         set_feature(env, ARM_FEATURE_VFP3);
 208     }
 209     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 210         set_feature(env, ARM_FEATURE_VFP);
 211     }
 212
 213     register_cp_regs_for_features(cpu);
 214 }
 215
 216 /* CPU models */
 217
 218 static void arm926_initfn(Object *obj)
 219 {
 220     ARMCPU *cpu = ARM_CPU(obj);
 221     set_feature(&cpu->env, ARM_FEATURE_V5);
 222     set_feature(&cpu->env, ARM_FEATURE_VFP);
 223     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 224     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 225     cpu->midr = ARM_CPUID_ARM926;
 226     cpu->reset_fpsid = 0x41011090;
 227     cpu->ctr = 0x1dd20d2;
 228     cpu->reset_sctlr = 0x00090078;
 229 }
 230
 231 static void arm946_initfn(Object *obj)
 232 {
 233     ARMCPU *cpu = ARM_CPU(obj);
 234     set_feature(&cpu->env, ARM_FEATURE_V5);
 235     set_feature(&cpu->env, ARM_FEATURE_MPU);
 236     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 237     cpu->midr = ARM_CPUID_ARM946;
 238     cpu->ctr = 0x0f004006;
 239     cpu->reset_sctlr = 0x00000078;
 240 }
 241
 242 static void arm1026_initfn(Object *obj)
 243 {
 244     ARMCPU *cpu = ARM_CPU(obj);
 245     set_feature(&cpu->env, ARM_FEATURE_V5);
 246     set_feature(&cpu->env, ARM_FEATURE_VFP);
 247     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 248     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 249     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 250     cpu->midr = ARM_CPUID_ARM1026;
 251     cpu->reset_fpsid = 0x410110a0;
 252     cpu->ctr = 0x1dd20d2;
 253     cpu->reset_sctlr = 0x00090078;
 254     {
 255         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 256         ARMCPRegInfo ifar = {
 257             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 258             .access = PL1_RW,
 259             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 260             .resetvalue = 0
 261         };
 262         define_one_arm_cp_reg(cpu, &ifar);
 263     }
 264 }
 265
 266 static void arm1136_r2_initfn(Object *obj)
 267 {
 268     ARMCPU *cpu = ARM_CPU(obj);
 269     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 270      * older core than plain "arm1136". In particular this does not
 271      * have the v6K features.
 272      * These ID register values are correct for 1136 but may be wrong
 273      * for 1136_r2 (in particular r0p2 does not actually implement most
 274      * of the ID registers).
 275      */
 276     set_feature(&cpu->env, ARM_FEATURE_V6);
 277     set_feature(&cpu->env, ARM_FEATURE_VFP);
 278     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 279     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 280     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 281     cpu->midr = ARM_CPUID_ARM1136_R2;
 282     cpu->reset_fpsid = 0x410120b4;
 283     cpu->mvfr0 = 0x11111111;
 284     cpu->mvfr1 = 0x00000000;
 285     cpu->ctr = 0x1dd20d2;
 286     cpu->reset_sctlr = 0x00050078;
 287     cpu->id_pfr0 = 0x111;
 288     cpu->id_pfr1 = 0x1;
 289     cpu->id_dfr0 = 0x2;
 290     cpu->id_afr0 = 0x3;
 291     cpu->id_mmfr0 = 0x01130003;
 292     cpu->id_mmfr1 = 0x10030302;
 293     cpu->id_mmfr2 = 0x01222110;
 294     cpu->id_isar0 = 0x00140011;
 295     cpu->id_isar1 = 0x12002111;
 296     cpu->id_isar2 = 0x11231111;
 297     cpu->id_isar3 = 0x01102131;
 298     cpu->id_isar4 = 0x141;
 299 }
 300
 301 static void arm1136_initfn(Object *obj)
 302 {
 303     ARMCPU *cpu = ARM_CPU(obj);
 304     set_feature(&cpu->env, ARM_FEATURE_V6K);
 305     set_feature(&cpu->env, ARM_FEATURE_V6);
 306     set_feature(&cpu->env, ARM_FEATURE_VFP);
 307     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 308     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 309     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 310     cpu->midr = ARM_CPUID_ARM1136;
 311     cpu->reset_fpsid = 0x410120b4;
 312     cpu->mvfr0 = 0x11111111;
 313     cpu->mvfr1 = 0x00000000;
 314     cpu->ctr = 0x1dd20d2;
 315     cpu->reset_sctlr = 0x00050078;
 316     cpu->id_pfr0 = 0x111;
 317     cpu->id_pfr1 = 0x1;
 318     cpu->id_dfr0 = 0x2;
 319     cpu->id_afr0 = 0x3;
 320     cpu->id_mmfr0 = 0x01130003;
 321     cpu->id_mmfr1 = 0x10030302;
 322     cpu->id_mmfr2 = 0x01222110;
 323     cpu->id_isar0 = 0x00140011;
 324     cpu->id_isar1 = 0x12002111;
 325     cpu->id_isar2 = 0x11231111;
 326     cpu->id_isar3 = 0x01102131;
 327     cpu->id_isar4 = 0x141;
 328 }
 329
 330 static void arm1176_initfn(Object *obj)
 331 {
 332     ARMCPU *cpu = ARM_CPU(obj);
 333     set_feature(&cpu->env, ARM_FEATURE_V6K);
 334     set_feature(&cpu->env, ARM_FEATURE_VFP);
 335     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 336     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 337     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 338     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 339     cpu->midr = ARM_CPUID_ARM1176;
 340     cpu->reset_fpsid = 0x410120b5;
 341     cpu->mvfr0 = 0x11111111;
 342     cpu->mvfr1 = 0x00000000;
 343     cpu->ctr = 0x1dd20d2;
 344     cpu->reset_sctlr = 0x00050078;
 345     cpu->id_pfr0 = 0x111;
 346     cpu->id_pfr1 = 0x11;
 347     cpu->id_dfr0 = 0x33;
 348     cpu->id_afr0 = 0;
 349     cpu->id_mmfr0 = 0x01130003;
 350     cpu->id_mmfr1 = 0x10030302;
 351     cpu->id_mmfr2 = 0x01222100;
 352     cpu->id_isar0 = 0x0140011;
 353     cpu->id_isar1 = 0x12002111;
 354     cpu->id_isar2 = 0x11231121;
 355     cpu->id_isar3 = 0x01102131;
 356     cpu->id_isar4 = 0x01141;
 357 }
 358
 359 static void arm11mpcore_initfn(Object *obj)
 360 {
 361     ARMCPU *cpu = ARM_CPU(obj);
 362     set_feature(&cpu->env, ARM_FEATURE_V6K);
 363     set_feature(&cpu->env, ARM_FEATURE_VFP);
 364     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 365     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 366     cpu->midr = ARM_CPUID_ARM11MPCORE;
 367     cpu->reset_fpsid = 0x410120b4;
 368     cpu->mvfr0 = 0x11111111;
 369     cpu->mvfr1 = 0x00000000;
 370     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 371     cpu->id_pfr0 = 0x111;
 372     cpu->id_pfr1 = 0x1;
 373     cpu->id_dfr0 = 0;
 374     cpu->id_afr0 = 0x2;
 375     cpu->id_mmfr0 = 0x01100103;
 376     cpu->id_mmfr1 = 0x10020302;
 377     cpu->id_mmfr2 = 0x01222000;
 378     cpu->id_isar0 = 0x00100011;
 379     cpu->id_isar1 = 0x12002111;
 380     cpu->id_isar2 = 0x11221011;
 381     cpu->id_isar3 = 0x01102131;
 382     cpu->id_isar4 = 0x141;
 383 }
 384
 385 static void cortex_m3_initfn(Object *obj)
 386 {
 387     ARMCPU *cpu = ARM_CPU(obj);
 388     set_feature(&cpu->env, ARM_FEATURE_V7);
 389     set_feature(&cpu->env, ARM_FEATURE_M);
 390     cpu->midr = ARM_CPUID_CORTEXM3;
 391 }
 392
 393 static void cortex_a8_initfn(Object *obj)
 394 {
 395     ARMCPU *cpu = ARM_CPU(obj);
 396     set_feature(&cpu->env, ARM_FEATURE_V7);
 397     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 398     set_feature(&cpu->env, ARM_FEATURE_NEON);
 399     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 400     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 401     cpu->midr = ARM_CPUID_CORTEXA8;
 402     cpu->reset_fpsid = 0x410330c0;
 403     cpu->mvfr0 = 0x11110222;
 404     cpu->mvfr1 = 0x00011100;
 405     cpu->ctr = 0x82048004;
 406     cpu->reset_sctlr = 0x00c50078;
 407     cpu->id_pfr0 = 0x1031;
 408     cpu->id_pfr1 = 0x11;
 409     cpu->id_dfr0 = 0x400;
 410     cpu->id_afr0 = 0;
 411     cpu->id_mmfr0 = 0x31100003;
 412     cpu->id_mmfr1 = 0x20000000;
 413     cpu->id_mmfr2 = 0x01202000;
 414     cpu->id_mmfr3 = 0x11;
 415     cpu->id_isar0 = 0x00101111;
 416     cpu->id_isar1 = 0x12112111;
 417     cpu->id_isar2 = 0x21232031;
 418     cpu->id_isar3 = 0x11112131;
 419     cpu->id_isar4 = 0x00111142;
 420     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 421     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 422     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 423     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 424 }
 425
 426 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 427     /* power_control should be set to maximum latency. Again,
 428      * default to 0 and set by private hook
 429      */
 430     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 431       .access = PL1_RW, .resetvalue = 0,
 432       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 433     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 434       .access = PL1_RW, .resetvalue = 0,
 435       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 436     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 437       .access = PL1_RW, .resetvalue = 0,
 438       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 439     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 440       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 441     /* TLB lockdown control */
 442     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 443       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 444     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 445       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 446     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 447       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 448     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 449       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 450     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 451       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 452     REGINFO_SENTINEL
 453 };
 454
 455 static void cortex_a9_initfn(Object *obj)
 456 {
 457     ARMCPU *cpu = ARM_CPU(obj);
 458     set_feature(&cpu->env, ARM_FEATURE_V7);
 459     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 460     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 461     set_feature(&cpu->env, ARM_FEATURE_NEON);
 462     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 463     /* Note that A9 supports the MP extensions even for
 464      * A9UP and single-core A9MP (which are both different
 465      * and valid configurations; we don't model A9UP).
 466      */
 467     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 468     cpu->midr = ARM_CPUID_CORTEXA9;
 469     cpu->reset_fpsid = 0x41033090;
 470     cpu->mvfr0 = 0x11110222;
 471     cpu->mvfr1 = 0x01111111;
 472     cpu->ctr = 0x80038003;
 473     cpu->reset_sctlr = 0x00c50078;
 474     cpu->id_pfr0 = 0x1031;
 475     cpu->id_pfr1 = 0x11;
 476     cpu->id_dfr0 = 0x000;
 477     cpu->id_afr0 = 0;
 478     cpu->id_mmfr0 = 0x00100103;
 479     cpu->id_mmfr1 = 0x20000000;
 480     cpu->id_mmfr2 = 0x01230000;
 481     cpu->id_mmfr3 = 0x00002111;
 482     cpu->id_isar0 = 0x00101111;
 483     cpu->id_isar1 = 0x13112111;
 484     cpu->id_isar2 = 0x21232041;
 485     cpu->id_isar3 = 0x11112131;
 486     cpu->id_isar4 = 0x00111142;
 487     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 488     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 489     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 490     {
 491         ARMCPRegInfo cbar = {
 492             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 493             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 494             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 495         };
 496         define_one_arm_cp_reg(cpu, &cbar);
 497         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 498     }
 499 }
 500
 501 static void cortex_a15_initfn(Object *obj)
 502 {
 503     ARMCPU *cpu = ARM_CPU(obj);
 504     set_feature(&cpu->env, ARM_FEATURE_V7);
 505     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 506     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 507     set_feature(&cpu->env, ARM_FEATURE_NEON);
 508     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 509     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 510     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 511     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 512     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 513     cpu->midr = ARM_CPUID_CORTEXA15;
 514     cpu->reset_fpsid = 0x410430f0;
 515     cpu->mvfr0 = 0x10110222;
 516     cpu->mvfr1 = 0x11111111;
 517     cpu->ctr = 0x8444c004;
 518     cpu->reset_sctlr = 0x00c50078;
 519     cpu->id_pfr0 = 0x00001131;
 520     cpu->id_pfr1 = 0x00011011;
 521     cpu->id_dfr0 = 0x02010555;
 522     cpu->id_afr0 = 0x00000000;
 523     cpu->id_mmfr0 = 0x10201105;
 524     cpu->id_mmfr1 = 0x20000000;
 525     cpu->id_mmfr2 = 0x01240000;
 526     cpu->id_mmfr3 = 0x02102211;
 527     cpu->id_isar0 = 0x02101110;
 528     cpu->id_isar1 = 0x13112111;
 529     cpu->id_isar2 = 0x21232041;
 530     cpu->id_isar3 = 0x11112131;
 531     cpu->id_isar4 = 0x10011142;
 532     cpu->clidr = 0x0a200023;
 533     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 534     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 535     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 536 }
 537
 538 static void ti925t_initfn(Object *obj)
 539 {
 540     ARMCPU *cpu = ARM_CPU(obj);
 541     set_feature(&cpu->env, ARM_FEATURE_V4T);
 542     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 543     cpu->midr = ARM_CPUID_TI925T;
 544     cpu->ctr = 0x5109149;
 545     cpu->reset_sctlr = 0x00000070;
 546 }
 547
 548 static void sa1100_initfn(Object *obj)
 549 {
 550     ARMCPU *cpu = ARM_CPU(obj);
 551     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 552     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 553     cpu->midr = ARM_CPUID_SA1100;
 554     cpu->reset_sctlr = 0x00000070;
 555 }
 556
 557 static void sa1110_initfn(Object *obj)
 558 {
 559     ARMCPU *cpu = ARM_CPU(obj);
 560     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 561     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 562     cpu->midr = ARM_CPUID_SA1110;
 563     cpu->reset_sctlr = 0x00000070;
 564 }
 565
 566 static void pxa250_initfn(Object *obj)
 567 {
 568     ARMCPU *cpu = ARM_CPU(obj);
 569     set_feature(&cpu->env, ARM_FEATURE_V5);
 570     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 571     cpu->midr = ARM_CPUID_PXA250;
 572     cpu->ctr = 0xd172172;
 573     cpu->reset_sctlr = 0x00000078;
 574 }
 575
 576 static void pxa255_initfn(Object *obj)
 577 {
 578     ARMCPU *cpu = ARM_CPU(obj);
 579     set_feature(&cpu->env, ARM_FEATURE_V5);
 580     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 581     cpu->midr = ARM_CPUID_PXA255;
 582     cpu->ctr = 0xd172172;
 583     cpu->reset_sctlr = 0x00000078;
 584 }
 585
 586 static void pxa260_initfn(Object *obj)
 587 {
 588     ARMCPU *cpu = ARM_CPU(obj);
 589     set_feature(&cpu->env, ARM_FEATURE_V5);
 590     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 591     cpu->midr = ARM_CPUID_PXA260;
 592     cpu->ctr = 0xd172172;
 593     cpu->reset_sctlr = 0x00000078;
 594 }
 595
 596 static void pxa261_initfn(Object *obj)
 597 {
 598     ARMCPU *cpu = ARM_CPU(obj);
 599     set_feature(&cpu->env, ARM_FEATURE_V5);
 600     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 601     cpu->midr = ARM_CPUID_PXA261;
 602     cpu->ctr = 0xd172172;
 603     cpu->reset_sctlr = 0x00000078;
 604 }
 605
 606 static void pxa262_initfn(Object *obj)
 607 {
 608     ARMCPU *cpu = ARM_CPU(obj);
 609     set_feature(&cpu->env, ARM_FEATURE_V5);
 610     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 611     cpu->midr = ARM_CPUID_PXA262;
 612     cpu->ctr = 0xd172172;
 613     cpu->reset_sctlr = 0x00000078;
 614 }
 615
 616 static void pxa270a0_initfn(Object *obj)
 617 {
 618     ARMCPU *cpu = ARM_CPU(obj);
 619     set_feature(&cpu->env, ARM_FEATURE_V5);
 620     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 621     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 622     cpu->midr = ARM_CPUID_PXA270_A0;
 623     cpu->ctr = 0xd172172;
 624     cpu->reset_sctlr = 0x00000078;
 625 }
 626
 627 static void pxa270a1_initfn(Object *obj)
 628 {
 629     ARMCPU *cpu = ARM_CPU(obj);
 630     set_feature(&cpu->env, ARM_FEATURE_V5);
 631     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 632     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 633     cpu->midr = ARM_CPUID_PXA270_A1;
 634     cpu->ctr = 0xd172172;
 635     cpu->reset_sctlr = 0x00000078;
 636 }
 637
 638 static void pxa270b0_initfn(Object *obj)
 639 {
 640     ARMCPU *cpu = ARM_CPU(obj);
 641     set_feature(&cpu->env, ARM_FEATURE_V5);
 642     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 643     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 644     cpu->midr = ARM_CPUID_PXA270_B0;
 645     cpu->ctr = 0xd172172;
 646     cpu->reset_sctlr = 0x00000078;
 647 }
 648
 649 static void pxa270b1_initfn(Object *obj)
 650 {
 651     ARMCPU *cpu = ARM_CPU(obj);
 652     set_feature(&cpu->env, ARM_FEATURE_V5);
 653     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 654     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 655     cpu->midr = ARM_CPUID_PXA270_B1;
 656     cpu->ctr = 0xd172172;
 657     cpu->reset_sctlr = 0x00000078;
 658 }
 659
 660 static void pxa270c0_initfn(Object *obj)
 661 {
 662     ARMCPU *cpu = ARM_CPU(obj);
 663     set_feature(&cpu->env, ARM_FEATURE_V5);
 664     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 665     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 666     cpu->midr = ARM_CPUID_PXA270_C0;
 667     cpu->ctr = 0xd172172;
 668     cpu->reset_sctlr = 0x00000078;
 669 }
 670
 671 static void pxa270c5_initfn(Object *obj)
 672 {
 673     ARMCPU *cpu = ARM_CPU(obj);
 674     set_feature(&cpu->env, ARM_FEATURE_V5);
 675     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 676     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 677     cpu->midr = ARM_CPUID_PXA270_C5;
 678     cpu->ctr = 0xd172172;
 679     cpu->reset_sctlr = 0x00000078;
 680 }
 681
 682 static void arm_any_initfn(Object *obj)
 683 {
 684     ARMCPU *cpu = ARM_CPU(obj);
 685     set_feature(&cpu->env, ARM_FEATURE_V7);
 686     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 687     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 688     set_feature(&cpu->env, ARM_FEATURE_NEON);
 689     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 690     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 691     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 692     cpu->midr = ARM_CPUID_ANY;
 693 }
 694
 695 typedef struct ARMCPUInfo {
 696     const char *name;
 697     void (*initfn)(Object *obj);
 698 } ARMCPUInfo;
 699
 700 static const ARMCPUInfo arm_cpus[] = {
 701     { .name = "arm926",      .initfn = arm926_initfn },
 702     { .name = "arm946",      .initfn = arm946_initfn },
 703     { .name = "arm1026",     .initfn = arm1026_initfn },
 704     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 705      * older core than plain "arm1136". In particular this does not
 706      * have the v6K features.
 707      */
 708     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 709     { .name = "arm1136",     .initfn = arm1136_initfn },
 710     { .name = "arm1176",     .initfn = arm1176_initfn },
 711     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 712     { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
 713     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 714     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 715     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 716     { .name = "ti925t",      .initfn = ti925t_initfn },
 717     { .name = "sa1100",      .initfn = sa1100_initfn },
 718     { .name = "sa1110",      .initfn = sa1110_initfn },
 719     { .name = "pxa250",      .initfn = pxa250_initfn },
 720     { .name = "pxa255",      .initfn = pxa255_initfn },
 721     { .name = "pxa260",      .initfn = pxa260_initfn },
 722     { .name = "pxa261",      .initfn = pxa261_initfn },
 723     { .name = "pxa262",      .initfn = pxa262_initfn },
 724     /* "pxa270" is an alias for "pxa270-a0" */
 725     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 726     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 727     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 728     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 729     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 730     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 731     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 732     { .name = "any",         .initfn = arm_any_initfn },
 733 };
 734
 735 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 736 {
 737     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 738     CPUClass *cc = CPU_CLASS(acc);
 739
 740     acc->parent_reset = cc->reset;
 741     cc->reset = arm_cpu_reset;
 742 }
 743
 744 static void cpu_register(const ARMCPUInfo *info)
 745 {
 746     TypeInfo type_info = {
 747         .name = info->name,
 748         .parent = TYPE_ARM_CPU,
 749         .instance_size = sizeof(ARMCPU),
 750         .instance_init = info->initfn,
 751         .class_size = sizeof(ARMCPUClass),
 752     };
 753
 754     type_register_static(&type_info);
 755 }
 756
 757 static const TypeInfo arm_cpu_type_info = {
 758     .name = TYPE_ARM_CPU,
 759     .parent = TYPE_CPU,
 760     .instance_size = sizeof(ARMCPU),
 761     .instance_init = arm_cpu_initfn,
 762     .instance_finalize = arm_cpu_finalizefn,
 763     .abstract = true,
 764     .class_size = sizeof(ARMCPUClass),
 765     .class_init = arm_cpu_class_init,
 766 };
 767
 768 static void arm_cpu_register_types(void)
 769 {
 770     int i;
 771
 772     type_register_static(&arm_cpu_type_info);
 773     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 774         cpu_register(&arm_cpus[i]);
 775     }
 776 }
 777
 778 type_init(arm_cpu_register_types)