target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26
  27 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  28 {
  29     /* Reset a single ARMCPRegInfo register */
  30     ARMCPRegInfo *ri = value;
  31     ARMCPU *cpu = opaque;
  32
  33     if (ri->type & ARM_CP_SPECIAL) {
  34         return;
  35     }
  36
  37     if (ri->resetfn) {
  38         ri->resetfn(&cpu->env, ri);
  39         return;
  40     }
  41
  42     /* A zero offset is never possible as it would be regs[0]
  43      * so we use it to indicate that reset is being handled elsewhere.
  44      * This is basically only used for fields in non-core coprocessors
  45      * (like the pxa2xx ones).
  46      */
  47     if (!ri->fieldoffset) {
  48         return;
  49     }
  50
  51     if (ri->type & ARM_CP_64BIT) {
  52         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  53     } else {
  54         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  55     }
  56 }
  57
  58 /* CPUClass::reset() */
  59 static void arm_cpu_reset(CPUState *s)
  60 {
  61     ARMCPU *cpu = ARM_CPU(s);
  62     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  63     CPUARMState *env = &cpu->env;
  64
  65     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  66         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
  67         log_cpu_state(env, 0);
  68     }
  69
  70     acc->parent_reset(s);
  71
  72     memset(env, 0, offsetof(CPUARMState, breakpoints));
  73     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  74     env->cp15.c0_cpuid = cpu->midr;
  75     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  76     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  77     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  78     env->cp15.c0_cachetype = cpu->ctr;
  79     env->cp15.c1_sys = cpu->reset_sctlr;
  80     env->cp15.c0_c1[0] = cpu->id_pfr0;
  81     env->cp15.c0_c1[1] = cpu->id_pfr1;
  82     env->cp15.c0_c1[2] = cpu->id_dfr0;
  83     env->cp15.c0_c1[3] = cpu->id_afr0;
  84     env->cp15.c0_c1[4] = cpu->id_mmfr0;
  85     env->cp15.c0_c1[5] = cpu->id_mmfr1;
  86     env->cp15.c0_c1[6] = cpu->id_mmfr2;
  87     env->cp15.c0_c1[7] = cpu->id_mmfr3;
  88     env->cp15.c0_c2[0] = cpu->id_isar0;
  89     env->cp15.c0_c2[1] = cpu->id_isar1;
  90     env->cp15.c0_c2[2] = cpu->id_isar2;
  91     env->cp15.c0_c2[3] = cpu->id_isar3;
  92     env->cp15.c0_c2[4] = cpu->id_isar4;
  93     env->cp15.c0_c2[5] = cpu->id_isar5;
  94     env->cp15.c0_clid = cpu->clidr;
  95     memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
  96
  97     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  98         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  99     }
 100
 101 #if defined(CONFIG_USER_ONLY)
 102     env->uncached_cpsr = ARM_CPU_MODE_USR;
 103     /* For user mode we must enable access to coprocessors */
 104     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 105     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 106         env->cp15.c15_cpar = 3;
 107     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 108         env->cp15.c15_cpar = 1;
 109     }
 110 #else
 111     /* SVC mode with interrupts disabled.  */
 112     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 113     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 114        clear at reset.  Initial SP and PC are loaded from ROM.  */
 115     if (IS_M(env)) {
 116         uint32_t pc;
 117         uint8_t *rom;
 118         env->uncached_cpsr &= ~CPSR_I;
 119         rom = rom_ptr(0);
 120         if (rom) {
 121             /* We should really use ldl_phys here, in case the guest
 122                modified flash and reset itself.  However images
 123                loaded via -kernel have not been copied yet, so load the
 124                values directly from there.  */
 125             env->regs[13] = ldl_p(rom);
 126             pc = ldl_p(rom + 4);
 127             env->thumb = pc & 1;
 128             env->regs[15] = pc & ~1;
 129         }
 130     }
 131     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 132 #endif
 133     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 134     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 135     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 136     set_float_detect_tininess(float_tininess_before_rounding,
 137                               &env->vfp.fp_status);
 138     set_float_detect_tininess(float_tininess_before_rounding,
 139                               &env->vfp.standard_fp_status);
 140     tlb_flush(env, 1);
 141     /* Reset is a state change for some CPUARMState fields which we
 142      * bake assumptions about into translated code, so we need to
 143      * tb_flush().
 144      */
 145     tb_flush(env);
 146 }
 147
 148 static inline void set_feature(CPUARMState *env, int feature)
 149 {
 150     env->features |= 1u << feature;
 151 }
 152
 153 static void arm_cpu_initfn(Object *obj)
 154 {
 155     ARMCPU *cpu = ARM_CPU(obj);
 156
 157     cpu_exec_init(&cpu->env);
 158     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 159                                          g_free, g_free);
 160 }
 161
 162 static void arm_cpu_finalizefn(Object *obj)
 163 {
 164     ARMCPU *cpu = ARM_CPU(obj);
 165     g_hash_table_destroy(cpu->cp_regs);
 166 }
 167
 168 void arm_cpu_realize(ARMCPU *cpu)
 169 {
 170     /* This function is called by cpu_arm_init() because it
 171      * needs to do common actions based on feature bits, etc
 172      * that have been set by the subclass init functions.
 173      * When we have QOM realize support it should become
 174      * a true realize function instead.
 175      */
 176     CPUARMState *env = &cpu->env;
 177     /* Some features automatically imply others: */
 178     if (arm_feature(env, ARM_FEATURE_V7)) {
 179         set_feature(env, ARM_FEATURE_VAPA);
 180         set_feature(env, ARM_FEATURE_THUMB2);
 181         if (!arm_feature(env, ARM_FEATURE_M)) {
 182             set_feature(env, ARM_FEATURE_V6K);
 183         } else {
 184             set_feature(env, ARM_FEATURE_V6);
 185         }
 186     }
 187     if (arm_feature(env, ARM_FEATURE_V6K)) {
 188         set_feature(env, ARM_FEATURE_V6);
 189         set_feature(env, ARM_FEATURE_MVFR);
 190     }
 191     if (arm_feature(env, ARM_FEATURE_V6)) {
 192         set_feature(env, ARM_FEATURE_V5);
 193         if (!arm_feature(env, ARM_FEATURE_M)) {
 194             set_feature(env, ARM_FEATURE_AUXCR);
 195         }
 196     }
 197     if (arm_feature(env, ARM_FEATURE_V5)) {
 198         set_feature(env, ARM_FEATURE_V4T);
 199     }
 200     if (arm_feature(env, ARM_FEATURE_M)) {
 201         set_feature(env, ARM_FEATURE_THUMB_DIV);
 202     }
 203     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 204         set_feature(env, ARM_FEATURE_THUMB_DIV);
 205     }
 206     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 207         set_feature(env, ARM_FEATURE_VFP3);
 208     }
 209     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 210         set_feature(env, ARM_FEATURE_VFP);
 211     }
 212
 213     register_cp_regs_for_features(cpu);
 214 }
 215
 216 /* CPU models */
 217
 218 static void arm926_initfn(Object *obj)
 219 {
 220     ARMCPU *cpu = ARM_CPU(obj);
 221     set_feature(&cpu->env, ARM_FEATURE_V5);
 222     set_feature(&cpu->env, ARM_FEATURE_VFP);
 223     cpu->midr = ARM_CPUID_ARM926;
 224     cpu->reset_fpsid = 0x41011090;
 225     cpu->ctr = 0x1dd20d2;
 226     cpu->reset_sctlr = 0x00090078;
 227 }
 228
 229 static void arm946_initfn(Object *obj)
 230 {
 231     ARMCPU *cpu = ARM_CPU(obj);
 232     set_feature(&cpu->env, ARM_FEATURE_V5);
 233     set_feature(&cpu->env, ARM_FEATURE_MPU);
 234     cpu->midr = ARM_CPUID_ARM946;
 235     cpu->ctr = 0x0f004006;
 236     cpu->reset_sctlr = 0x00000078;
 237 }
 238
 239 static void arm1026_initfn(Object *obj)
 240 {
 241     ARMCPU *cpu = ARM_CPU(obj);
 242     set_feature(&cpu->env, ARM_FEATURE_V5);
 243     set_feature(&cpu->env, ARM_FEATURE_VFP);
 244     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 245     cpu->midr = ARM_CPUID_ARM1026;
 246     cpu->reset_fpsid = 0x410110a0;
 247     cpu->ctr = 0x1dd20d2;
 248     cpu->reset_sctlr = 0x00090078;
 249 }
 250
 251 static void arm1136_r2_initfn(Object *obj)
 252 {
 253     ARMCPU *cpu = ARM_CPU(obj);
 254     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 255      * older core than plain "arm1136". In particular this does not
 256      * have the v6K features.
 257      * These ID register values are correct for 1136 but may be wrong
 258      * for 1136_r2 (in particular r0p2 does not actually implement most
 259      * of the ID registers).
 260      */
 261     set_feature(&cpu->env, ARM_FEATURE_V6);
 262     set_feature(&cpu->env, ARM_FEATURE_VFP);
 263     cpu->midr = ARM_CPUID_ARM1136_R2;
 264     cpu->reset_fpsid = 0x410120b4;
 265     cpu->mvfr0 = 0x11111111;
 266     cpu->mvfr1 = 0x00000000;
 267     cpu->ctr = 0x1dd20d2;
 268     cpu->reset_sctlr = 0x00050078;
 269     cpu->id_pfr0 = 0x111;
 270     cpu->id_pfr1 = 0x1;
 271     cpu->id_dfr0 = 0x2;
 272     cpu->id_afr0 = 0x3;
 273     cpu->id_mmfr0 = 0x01130003;
 274     cpu->id_mmfr1 = 0x10030302;
 275     cpu->id_mmfr2 = 0x01222110;
 276     cpu->id_isar0 = 0x00140011;
 277     cpu->id_isar1 = 0x12002111;
 278     cpu->id_isar2 = 0x11231111;
 279     cpu->id_isar3 = 0x01102131;
 280     cpu->id_isar4 = 0x141;
 281 }
 282
 283 static void arm1136_initfn(Object *obj)
 284 {
 285     ARMCPU *cpu = ARM_CPU(obj);
 286     set_feature(&cpu->env, ARM_FEATURE_V6K);
 287     set_feature(&cpu->env, ARM_FEATURE_V6);
 288     set_feature(&cpu->env, ARM_FEATURE_VFP);
 289     cpu->midr = ARM_CPUID_ARM1136;
 290     cpu->reset_fpsid = 0x410120b4;
 291     cpu->mvfr0 = 0x11111111;
 292     cpu->mvfr1 = 0x00000000;
 293     cpu->ctr = 0x1dd20d2;
 294     cpu->reset_sctlr = 0x00050078;
 295     cpu->id_pfr0 = 0x111;
 296     cpu->id_pfr1 = 0x1;
 297     cpu->id_dfr0 = 0x2;
 298     cpu->id_afr0 = 0x3;
 299     cpu->id_mmfr0 = 0x01130003;
 300     cpu->id_mmfr1 = 0x10030302;
 301     cpu->id_mmfr2 = 0x01222110;
 302     cpu->id_isar0 = 0x00140011;
 303     cpu->id_isar1 = 0x12002111;
 304     cpu->id_isar2 = 0x11231111;
 305     cpu->id_isar3 = 0x01102131;
 306     cpu->id_isar4 = 0x141;
 307 }
 308
 309 static void arm1176_initfn(Object *obj)
 310 {
 311     ARMCPU *cpu = ARM_CPU(obj);
 312     set_feature(&cpu->env, ARM_FEATURE_V6K);
 313     set_feature(&cpu->env, ARM_FEATURE_VFP);
 314     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 315     cpu->midr = ARM_CPUID_ARM1176;
 316     cpu->reset_fpsid = 0x410120b5;
 317     cpu->mvfr0 = 0x11111111;
 318     cpu->mvfr1 = 0x00000000;
 319     cpu->ctr = 0x1dd20d2;
 320     cpu->reset_sctlr = 0x00050078;
 321     cpu->id_pfr0 = 0x111;
 322     cpu->id_pfr1 = 0x11;
 323     cpu->id_dfr0 = 0x33;
 324     cpu->id_afr0 = 0;
 325     cpu->id_mmfr0 = 0x01130003;
 326     cpu->id_mmfr1 = 0x10030302;
 327     cpu->id_mmfr2 = 0x01222100;
 328     cpu->id_isar0 = 0x0140011;
 329     cpu->id_isar1 = 0x12002111;
 330     cpu->id_isar2 = 0x11231121;
 331     cpu->id_isar3 = 0x01102131;
 332     cpu->id_isar4 = 0x01141;
 333 }
 334
 335 static void arm11mpcore_initfn(Object *obj)
 336 {
 337     ARMCPU *cpu = ARM_CPU(obj);
 338     set_feature(&cpu->env, ARM_FEATURE_V6K);
 339     set_feature(&cpu->env, ARM_FEATURE_VFP);
 340     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 341     cpu->midr = ARM_CPUID_ARM11MPCORE;
 342     cpu->reset_fpsid = 0x410120b4;
 343     cpu->mvfr0 = 0x11111111;
 344     cpu->mvfr1 = 0x00000000;
 345     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 346     cpu->id_pfr0 = 0x111;
 347     cpu->id_pfr1 = 0x1;
 348     cpu->id_dfr0 = 0;
 349     cpu->id_afr0 = 0x2;
 350     cpu->id_mmfr0 = 0x01100103;
 351     cpu->id_mmfr1 = 0x10020302;
 352     cpu->id_mmfr2 = 0x01222000;
 353     cpu->id_isar0 = 0x00100011;
 354     cpu->id_isar1 = 0x12002111;
 355     cpu->id_isar2 = 0x11221011;
 356     cpu->id_isar3 = 0x01102131;
 357     cpu->id_isar4 = 0x141;
 358 }
 359
 360 static void cortex_m3_initfn(Object *obj)
 361 {
 362     ARMCPU *cpu = ARM_CPU(obj);
 363     set_feature(&cpu->env, ARM_FEATURE_V7);
 364     set_feature(&cpu->env, ARM_FEATURE_M);
 365     cpu->midr = ARM_CPUID_CORTEXM3;
 366 }
 367
 368 static void cortex_a8_initfn(Object *obj)
 369 {
 370     ARMCPU *cpu = ARM_CPU(obj);
 371     set_feature(&cpu->env, ARM_FEATURE_V7);
 372     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 373     set_feature(&cpu->env, ARM_FEATURE_NEON);
 374     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 375     cpu->midr = ARM_CPUID_CORTEXA8;
 376     cpu->reset_fpsid = 0x410330c0;
 377     cpu->mvfr0 = 0x11110222;
 378     cpu->mvfr1 = 0x00011100;
 379     cpu->ctr = 0x82048004;
 380     cpu->reset_sctlr = 0x00c50078;
 381     cpu->id_pfr0 = 0x1031;
 382     cpu->id_pfr1 = 0x11;
 383     cpu->id_dfr0 = 0x400;
 384     cpu->id_afr0 = 0;
 385     cpu->id_mmfr0 = 0x31100003;
 386     cpu->id_mmfr1 = 0x20000000;
 387     cpu->id_mmfr2 = 0x01202000;
 388     cpu->id_mmfr3 = 0x11;
 389     cpu->id_isar0 = 0x00101111;
 390     cpu->id_isar1 = 0x12112111;
 391     cpu->id_isar2 = 0x21232031;
 392     cpu->id_isar3 = 0x11112131;
 393     cpu->id_isar4 = 0x00111142;
 394     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 395     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 396     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 397     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 398 }
 399
 400 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 401     /* power_control should be set to maximum latency. Again,
 402      * default to 0 and set by private hook
 403      */
 404     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 405       .access = PL1_RW, .resetvalue = 0,
 406       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 407     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 408       .access = PL1_RW, .resetvalue = 0,
 409       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 410     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 411       .access = PL1_RW, .resetvalue = 0,
 412       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 413     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 414       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 415     /* TLB lockdown control */
 416     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 417       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 418     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 419       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 420     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 421       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 422     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 423       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 424     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 425       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 426     REGINFO_SENTINEL
 427 };
 428
 429 static void cortex_a9_initfn(Object *obj)
 430 {
 431     ARMCPU *cpu = ARM_CPU(obj);
 432     set_feature(&cpu->env, ARM_FEATURE_V7);
 433     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 434     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 435     set_feature(&cpu->env, ARM_FEATURE_NEON);
 436     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 437     /* Note that A9 supports the MP extensions even for
 438      * A9UP and single-core A9MP (which are both different
 439      * and valid configurations; we don't model A9UP).
 440      */
 441     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 442     cpu->midr = ARM_CPUID_CORTEXA9;
 443     cpu->reset_fpsid = 0x41033090;
 444     cpu->mvfr0 = 0x11110222;
 445     cpu->mvfr1 = 0x01111111;
 446     cpu->ctr = 0x80038003;
 447     cpu->reset_sctlr = 0x00c50078;
 448     cpu->id_pfr0 = 0x1031;
 449     cpu->id_pfr1 = 0x11;
 450     cpu->id_dfr0 = 0x000;
 451     cpu->id_afr0 = 0;
 452     cpu->id_mmfr0 = 0x00100103;
 453     cpu->id_mmfr1 = 0x20000000;
 454     cpu->id_mmfr2 = 0x01230000;
 455     cpu->id_mmfr3 = 0x00002111;
 456     cpu->id_isar0 = 0x00101111;
 457     cpu->id_isar1 = 0x13112111;
 458     cpu->id_isar2 = 0x21232041;
 459     cpu->id_isar3 = 0x11112131;
 460     cpu->id_isar4 = 0x00111142;
 461     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 462     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 463     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 464     {
 465         ARMCPRegInfo cbar = {
 466             .name = "CBAR", .cp = 15, .crn = 15,  .crm = 0, .opc1 = 4,
 467             .opc2 = 0, .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
 468             .fieldoffset = offsetof(CPUARMState, cp15.c15_config_base_address)
 469         };
 470         define_one_arm_cp_reg(cpu, &cbar);
 471         define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 472     }
 473 }
 474
 475 static void cortex_a15_initfn(Object *obj)
 476 {
 477     ARMCPU *cpu = ARM_CPU(obj);
 478     set_feature(&cpu->env, ARM_FEATURE_V7);
 479     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 480     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 481     set_feature(&cpu->env, ARM_FEATURE_NEON);
 482     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 483     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 484     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 485     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 486     cpu->midr = ARM_CPUID_CORTEXA15;
 487     cpu->reset_fpsid = 0x410430f0;
 488     cpu->mvfr0 = 0x10110222;
 489     cpu->mvfr1 = 0x11111111;
 490     cpu->ctr = 0x8444c004;
 491     cpu->reset_sctlr = 0x00c50078;
 492     cpu->id_pfr0 = 0x00001131;
 493     cpu->id_pfr1 = 0x00011011;
 494     cpu->id_dfr0 = 0x02010555;
 495     cpu->id_afr0 = 0x00000000;
 496     cpu->id_mmfr0 = 0x10201105;
 497     cpu->id_mmfr1 = 0x20000000;
 498     cpu->id_mmfr2 = 0x01240000;
 499     cpu->id_mmfr3 = 0x02102211;
 500     cpu->id_isar0 = 0x02101110;
 501     cpu->id_isar1 = 0x13112111;
 502     cpu->id_isar2 = 0x21232041;
 503     cpu->id_isar3 = 0x11112131;
 504     cpu->id_isar4 = 0x10011142;
 505     cpu->clidr = 0x0a200023;
 506     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 507     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 508     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 509 }
 510
 511 static void ti925t_initfn(Object *obj)
 512 {
 513     ARMCPU *cpu = ARM_CPU(obj);
 514     set_feature(&cpu->env, ARM_FEATURE_V4T);
 515     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 516     cpu->midr = ARM_CPUID_TI925T;
 517     cpu->ctr = 0x5109149;
 518     cpu->reset_sctlr = 0x00000070;
 519 }
 520
 521 static void sa1100_initfn(Object *obj)
 522 {
 523     ARMCPU *cpu = ARM_CPU(obj);
 524     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 525     cpu->midr = ARM_CPUID_SA1100;
 526     cpu->reset_sctlr = 0x00000070;
 527 }
 528
 529 static void sa1110_initfn(Object *obj)
 530 {
 531     ARMCPU *cpu = ARM_CPU(obj);
 532     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 533     cpu->midr = ARM_CPUID_SA1110;
 534     cpu->reset_sctlr = 0x00000070;
 535 }
 536
 537 static void pxa250_initfn(Object *obj)
 538 {
 539     ARMCPU *cpu = ARM_CPU(obj);
 540     set_feature(&cpu->env, ARM_FEATURE_V5);
 541     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 542     cpu->midr = ARM_CPUID_PXA250;
 543     cpu->ctr = 0xd172172;
 544     cpu->reset_sctlr = 0x00000078;
 545 }
 546
 547 static void pxa255_initfn(Object *obj)
 548 {
 549     ARMCPU *cpu = ARM_CPU(obj);
 550     set_feature(&cpu->env, ARM_FEATURE_V5);
 551     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 552     cpu->midr = ARM_CPUID_PXA255;
 553     cpu->ctr = 0xd172172;
 554     cpu->reset_sctlr = 0x00000078;
 555 }
 556
 557 static void pxa260_initfn(Object *obj)
 558 {
 559     ARMCPU *cpu = ARM_CPU(obj);
 560     set_feature(&cpu->env, ARM_FEATURE_V5);
 561     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 562     cpu->midr = ARM_CPUID_PXA260;
 563     cpu->ctr = 0xd172172;
 564     cpu->reset_sctlr = 0x00000078;
 565 }
 566
 567 static void pxa261_initfn(Object *obj)
 568 {
 569     ARMCPU *cpu = ARM_CPU(obj);
 570     set_feature(&cpu->env, ARM_FEATURE_V5);
 571     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 572     cpu->midr = ARM_CPUID_PXA261;
 573     cpu->ctr = 0xd172172;
 574     cpu->reset_sctlr = 0x00000078;
 575 }
 576
 577 static void pxa262_initfn(Object *obj)
 578 {
 579     ARMCPU *cpu = ARM_CPU(obj);
 580     set_feature(&cpu->env, ARM_FEATURE_V5);
 581     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 582     cpu->midr = ARM_CPUID_PXA262;
 583     cpu->ctr = 0xd172172;
 584     cpu->reset_sctlr = 0x00000078;
 585 }
 586
 587 static void pxa270a0_initfn(Object *obj)
 588 {
 589     ARMCPU *cpu = ARM_CPU(obj);
 590     set_feature(&cpu->env, ARM_FEATURE_V5);
 591     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 592     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 593     cpu->midr = ARM_CPUID_PXA270_A0;
 594     cpu->ctr = 0xd172172;
 595     cpu->reset_sctlr = 0x00000078;
 596 }
 597
 598 static void pxa270a1_initfn(Object *obj)
 599 {
 600     ARMCPU *cpu = ARM_CPU(obj);
 601     set_feature(&cpu->env, ARM_FEATURE_V5);
 602     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 603     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 604     cpu->midr = ARM_CPUID_PXA270_A1;
 605     cpu->ctr = 0xd172172;
 606     cpu->reset_sctlr = 0x00000078;
 607 }
 608
 609 static void pxa270b0_initfn(Object *obj)
 610 {
 611     ARMCPU *cpu = ARM_CPU(obj);
 612     set_feature(&cpu->env, ARM_FEATURE_V5);
 613     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 614     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 615     cpu->midr = ARM_CPUID_PXA270_B0;
 616     cpu->ctr = 0xd172172;
 617     cpu->reset_sctlr = 0x00000078;
 618 }
 619
 620 static void pxa270b1_initfn(Object *obj)
 621 {
 622     ARMCPU *cpu = ARM_CPU(obj);
 623     set_feature(&cpu->env, ARM_FEATURE_V5);
 624     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 625     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 626     cpu->midr = ARM_CPUID_PXA270_B1;
 627     cpu->ctr = 0xd172172;
 628     cpu->reset_sctlr = 0x00000078;
 629 }
 630
 631 static void pxa270c0_initfn(Object *obj)
 632 {
 633     ARMCPU *cpu = ARM_CPU(obj);
 634     set_feature(&cpu->env, ARM_FEATURE_V5);
 635     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 636     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 637     cpu->midr = ARM_CPUID_PXA270_C0;
 638     cpu->ctr = 0xd172172;
 639     cpu->reset_sctlr = 0x00000078;
 640 }
 641
 642 static void pxa270c5_initfn(Object *obj)
 643 {
 644     ARMCPU *cpu = ARM_CPU(obj);
 645     set_feature(&cpu->env, ARM_FEATURE_V5);
 646     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 647     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 648     cpu->midr = ARM_CPUID_PXA270_C5;
 649     cpu->ctr = 0xd172172;
 650     cpu->reset_sctlr = 0x00000078;
 651 }
 652
 653 static void arm_any_initfn(Object *obj)
 654 {
 655     ARMCPU *cpu = ARM_CPU(obj);
 656     set_feature(&cpu->env, ARM_FEATURE_V7);
 657     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 658     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 659     set_feature(&cpu->env, ARM_FEATURE_NEON);
 660     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 661     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 662     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 663     cpu->midr = ARM_CPUID_ANY;
 664 }
 665
 666 typedef struct ARMCPUInfo {
 667     const char *name;
 668     void (*initfn)(Object *obj);
 669 } ARMCPUInfo;
 670
 671 static const ARMCPUInfo arm_cpus[] = {
 672     { .name = "arm926",      .initfn = arm926_initfn },
 673     { .name = "arm946",      .initfn = arm946_initfn },
 674     { .name = "arm1026",     .initfn = arm1026_initfn },
 675     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 676      * older core than plain "arm1136". In particular this does not
 677      * have the v6K features.
 678      */
 679     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 680     { .name = "arm1136",     .initfn = arm1136_initfn },
 681     { .name = "arm1176",     .initfn = arm1176_initfn },
 682     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 683     { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
 684     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 685     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 686     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 687     { .name = "ti925t",      .initfn = ti925t_initfn },
 688     { .name = "sa1100",      .initfn = sa1100_initfn },
 689     { .name = "sa1110",      .initfn = sa1110_initfn },
 690     { .name = "pxa250",      .initfn = pxa250_initfn },
 691     { .name = "pxa255",      .initfn = pxa255_initfn },
 692     { .name = "pxa260",      .initfn = pxa260_initfn },
 693     { .name = "pxa261",      .initfn = pxa261_initfn },
 694     { .name = "pxa262",      .initfn = pxa262_initfn },
 695     /* "pxa270" is an alias for "pxa270-a0" */
 696     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 697     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 698     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 699     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 700     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 701     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 702     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 703     { .name = "any",         .initfn = arm_any_initfn },
 704 };
 705
 706 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 707 {
 708     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 709     CPUClass *cc = CPU_CLASS(acc);
 710
 711     acc->parent_reset = cc->reset;
 712     cc->reset = arm_cpu_reset;
 713 }
 714
 715 static void cpu_register(const ARMCPUInfo *info)
 716 {
 717     TypeInfo type_info = {
 718         .name = info->name,
 719         .parent = TYPE_ARM_CPU,
 720         .instance_size = sizeof(ARMCPU),
 721         .instance_init = info->initfn,
 722         .class_size = sizeof(ARMCPUClass),
 723     };
 724
 725     type_register_static(&type_info);
 726 }
 727
 728 static const TypeInfo arm_cpu_type_info = {
 729     .name = TYPE_ARM_CPU,
 730     .parent = TYPE_CPU,
 731     .instance_size = sizeof(ARMCPU),
 732     .instance_init = arm_cpu_initfn,
 733     .instance_finalize = arm_cpu_finalizefn,
 734     .abstract = true,
 735     .class_size = sizeof(ARMCPUClass),
 736     .class_init = arm_cpu_class_init,
 737 };
 738
 739 static void arm_cpu_register_types(void)
 740 {
 741     int i;
 742
 743     type_register_static(&arm_cpu_type_info);
 744     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 745         cpu_register(&arm_cpus[i]);
 746     }
 747 }
 748
 749 type_init(arm_cpu_register_types)