target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_ARM_H
  21 #define CPU_ARM_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define ELF_MACHINE     EM_ARM
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #define EXCP_UDEF            1   /* undefined instruction */
  34 #define EXCP_SWI             2   /* software interrupt */
  35 #define EXCP_PREFETCH_ABORT  3
  36 #define EXCP_DATA_ABORT      4
  37 #define EXCP_IRQ             5
  38 #define EXCP_FIQ             6
  39 #define EXCP_BKPT            7
  40 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  41
  42 #define ARMV7M_EXCP_RESET   1
  43 #define ARMV7M_EXCP_NMI     2
  44 #define ARMV7M_EXCP_HARD    3
  45 #define ARMV7M_EXCP_MEM     4
  46 #define ARMV7M_EXCP_BUS     5
  47 #define ARMV7M_EXCP_USAGE   6
  48 #define ARMV7M_EXCP_SVC     11
  49 #define ARMV7M_EXCP_DEBUG   12
  50 #define ARMV7M_EXCP_PENDSV  14
  51 #define ARMV7M_EXCP_SYSTICK 15
  52
  53 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  54                             int srcreg, int operand, uint32_t value);
  55 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  56                                int dstreg, int operand);
  57
  58 #define NB_MMU_MODES 2
  59
  60 /* We currently assume float and double are IEEE single and double
  61    precision respectively.
  62    Doing runtime conversions is tricky because VFP registers may contain
  63    integer values (eg. as the result of a FTOSI instruction).
  64    s<2n> maps to the least significant half of d<n>
  65    s<2n+1> maps to the most significant half of d<n>
  66  */
  67
  68 typedef struct CPUARMState {
  69     /* Regs for current mode.  */
  70     uint32_t regs[16];
  71     /* Frequently accessed CPSR bits are stored separately for efficiently.
  72        This contains all the other bits.  Use cpsr_{read,write} to access
  73        the whole CPSR.  */
  74     uint32_t uncached_cpsr;
  75     uint32_t spsr;
  76
  77     /* Banked registers.  */
  78     uint32_t banked_spsr[6];
  79     uint32_t banked_r13[6];
  80     uint32_t banked_r14[6];
  81
  82     /* These hold r8-r12.  */
  83     uint32_t usr_regs[5];
  84     uint32_t fiq_regs[5];
  85
  86     /* cpsr flag cache for faster execution */
  87     uint32_t CF; /* 0 or 1 */
  88     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  89     uint32_t NZF; /* N is bit 31. Z is computed from NZF */
  90     uint32_t QF; /* 0 or 1 */
  91     uint32_t GE; /* cpsr[19:16] */
  92     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
  93     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
  94
  95     /* System control coprocessor (cp15) */
  96     struct {
  97         uint32_t c0_cpuid;
  98         uint32_t c0_cachetype;
  99         uint32_t c0_c1[8]; /* Feature registers.  */
 100         uint32_t c0_c2[8]; /* Instruction set registers.  */
 101         uint32_t c1_sys; /* System control register.  */
 102         uint32_t c1_coproc; /* Coprocessor access register.  */
 103         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 104         uint32_t c2_base0; /* MMU translation table base 0.  */
 105         uint32_t c2_base1; /* MMU translation table base 1.  */
 106         uint32_t c2_mask; /* MMU translation table base mask.  */
 107         uint32_t c2_data; /* MPU data cachable bits.  */
 108         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 109         uint32_t c3; /* MMU domain access control register
 110                         MPU write buffer control.  */
 111         uint32_t c5_insn; /* Fault status registers.  */
 112         uint32_t c5_data;
 113         uint32_t c6_region[8]; /* MPU base/size registers.  */
 114         uint32_t c6_insn; /* Fault address registers.  */
 115         uint32_t c6_data;
 116         uint32_t c9_insn; /* Cache lockdown registers.  */
 117         uint32_t c9_data;
 118         uint32_t c13_fcse; /* FCSE PID.  */
 119         uint32_t c13_context; /* Context ID.  */
 120         uint32_t c13_tls1; /* User RW Thread register.  */
 121         uint32_t c13_tls2; /* User RO Thread register.  */
 122         uint32_t c13_tls3; /* Privileged Thread register.  */
 123         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 124         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 125         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 126         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 127         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 128     } cp15;
 129
 130     struct {
 131         uint32_t other_sp;
 132         uint32_t vecbase;
 133         uint32_t basepri;
 134         uint32_t control;
 135         int current_sp;
 136         int exception;
 137         int pending_exception;
 138         void *nvic;
 139     } v7m;
 140
 141     /* Coprocessor IO used by peripherals */
 142     struct {
 143         ARMReadCPFunc *cp_read;
 144         ARMWriteCPFunc *cp_write;
 145         void *opaque;
 146     } cp[15];
 147
 148     /* Internal CPU feature flags.  */
 149     uint32_t features;
 150
 151     /* Callback for vectored interrupt controller.  */
 152     int (*get_irq_vector)(struct CPUARMState *);
 153     void *irq_opaque;
 154
 155     /* exception/interrupt handling */
 156     jmp_buf jmp_env;
 157     int exception_index;
 158     int interrupt_request;
 159     int user_mode_only;
 160     int halted;
 161
 162     /* VFP coprocessor state.  */
 163     struct {
 164         float64 regs[32];
 165
 166         uint32_t xregs[16];
 167         /* We store these fpcsr fields separately for convenience.  */
 168         int vec_len;
 169         int vec_stride;
 170
 171         /* Temporary variables if we don't have spare fp regs.  */
 172         float32 tmp0s, tmp1s;
 173         float64 tmp0d, tmp1d;
 174         /* scratch space when Tn are not sufficient.  */
 175         uint32_t scratch[8];
 176
 177         float_status fp_status;
 178     } vfp;
 179 #if defined(CONFIG_USER_ONLY)
 180     struct mmon_state *mmon_entry;
 181 #else
 182     uint32_t mmon_addr;
 183 #endif
 184
 185     /* iwMMXt coprocessor state.  */
 186     struct {
 187         uint64_t regs[16];
 188         uint64_t val;
 189
 190         uint32_t cregs[16];
 191     } iwmmxt;
 192
 193 #if defined(CONFIG_USER_ONLY)
 194     /* For usermode syscall translation.  */
 195     int eabi;
 196 #endif
 197
 198     CPU_COMMON
 199
 200     /* These fields after the common ones so they are preserved on reset.  */
 201     int ram_size;
 202     const char *kernel_filename;
 203     const char *kernel_cmdline;
 204     const char *initrd_filename;
 205     int board_id;
 206     target_phys_addr_t loader_start;
 207 } CPUARMState;
 208
 209 CPUARMState *cpu_arm_init(const char *cpu_model);
 210 void arm_translate_init(void);
 211 int cpu_arm_exec(CPUARMState *s);
 212 void cpu_arm_close(CPUARMState *s);
 213 void do_interrupt(CPUARMState *);
 214 void switch_mode(CPUARMState *, int);
 215 uint32_t do_arm_semihosting(CPUARMState *env);
 216
 217 /* you can call this signal handler from your SIGBUS and SIGSEGV
 218    signal handlers to inform the virtual CPU of exceptions. non zero
 219    is returned if the signal was handled by the virtual CPU.  */
 220 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 221                            void *puc);
 222
 223 void cpu_lock(void);
 224 void cpu_unlock(void);
 225
 226 #define CPSR_M (0x1f)
 227 #define CPSR_T (1 << 5)
 228 #define CPSR_F (1 << 6)
 229 #define CPSR_I (1 << 7)
 230 #define CPSR_A (1 << 8)
 231 #define CPSR_E (1 << 9)
 232 #define CPSR_IT_2_7 (0xfc00)
 233 #define CPSR_GE (0xf << 16)
 234 #define CPSR_RESERVED (0xf << 20)
 235 #define CPSR_J (1 << 24)
 236 #define CPSR_IT_0_1 (3 << 25)
 237 #define CPSR_Q (1 << 27)
 238 #define CPSR_V (1 << 28)
 239 #define CPSR_C (1 << 29)
 240 #define CPSR_Z (1 << 30)
 241 #define CPSR_N (1 << 31)
 242 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 243
 244 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 245 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 246 /* Bits writable in user mode.  */
 247 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 248 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 249 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 250
 251 /* Return the current CPSR value.  */
 252 uint32_t cpsr_read(CPUARMState *env);
 253 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 254 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 255
 256 /* Return the current xPSR value.  */
 257 static inline uint32_t xpsr_read(CPUARMState *env)
 258 {
 259     int ZF;
 260     ZF = (env->NZF == 0);
 261     return (env->NZF & 0x80000000) | (ZF << 30)
 262         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 263         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 264         | ((env->condexec_bits & 0xfc) << 8)
 265         | env->v7m.exception;
 266 }
 267
 268 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 269 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 270 {
 271     /* NOTE: N = 1 and Z = 1 cannot be stored currently */
 272     if (mask & CPSR_NZCV) {
 273         env->NZF = (val & 0xc0000000) ^ 0x40000000;
 274         env->CF = (val >> 29) & 1;
 275         env->VF = (val << 3) & 0x80000000;
 276     }
 277     if (mask & CPSR_Q)
 278         env->QF = ((val & CPSR_Q) != 0);
 279     if (mask & (1 << 24))
 280         env->thumb = ((val & (1 << 24)) != 0);
 281     if (mask & CPSR_IT_0_1) {
 282         env->condexec_bits &= ~3;
 283         env->condexec_bits |= (val >> 25) & 3;
 284     }
 285     if (mask & CPSR_IT_2_7) {
 286         env->condexec_bits &= 3;
 287         env->condexec_bits |= (val >> 8) & 0xfc;
 288     }
 289     if (mask & 0x1ff) {
 290         env->v7m.exception = val & 0x1ff;
 291     }
 292 }
 293
 294 enum arm_cpu_mode {
 295   ARM_CPU_MODE_USR = 0x10,
 296   ARM_CPU_MODE_FIQ = 0x11,
 297   ARM_CPU_MODE_IRQ = 0x12,
 298   ARM_CPU_MODE_SVC = 0x13,
 299   ARM_CPU_MODE_ABT = 0x17,
 300   ARM_CPU_MODE_UND = 0x1b,
 301   ARM_CPU_MODE_SYS = 0x1f
 302 };
 303
 304 /* VFP system registers.  */
 305 #define ARM_VFP_FPSID   0
 306 #define ARM_VFP_FPSCR   1
 307 #define ARM_VFP_MVFR1   6
 308 #define ARM_VFP_MVFR0   7
 309 #define ARM_VFP_FPEXC   8
 310 #define ARM_VFP_FPINST  9
 311 #define ARM_VFP_FPINST2 10
 312
 313 /* iwMMXt coprocessor control registers.  */
 314 #define ARM_IWMMXT_wCID         0
 315 #define ARM_IWMMXT_wCon         1
 316 #define ARM_IWMMXT_wCSSF        2
 317 #define ARM_IWMMXT_wCASF        3
 318 #define ARM_IWMMXT_wCGR0        8
 319 #define ARM_IWMMXT_wCGR1        9
 320 #define ARM_IWMMXT_wCGR2        10
 321 #define ARM_IWMMXT_wCGR3        11
 322
 323 enum arm_features {
 324     ARM_FEATURE_VFP,
 325     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 326     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 327     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 328     ARM_FEATURE_V6,
 329     ARM_FEATURE_V6K,
 330     ARM_FEATURE_V7,
 331     ARM_FEATURE_THUMB2,
 332     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 333     ARM_FEATURE_VFP3,
 334     ARM_FEATURE_NEON,
 335     ARM_FEATURE_DIV,
 336     ARM_FEATURE_M, /* Microcontroller profile.  */
 337     ARM_FEATURE_OMAPCP  /* OMAP specific CP15 ops handling.  */
 338 };
 339
 340 static inline int arm_feature(CPUARMState *env, int feature)
 341 {
 342     return (env->features & (1u << feature)) != 0;
 343 }
 344
 345 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 346
 347 /* Interface between CPU and Interrupt controller.  */
 348 void armv7m_nvic_set_pending(void *opaque, int irq);
 349 int armv7m_nvic_acknowledge_irq(void *opaque);
 350 void armv7m_nvic_complete_irq(void *opaque, int irq);
 351
 352 void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
 353                        ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
 354                        void *opaque);
 355
 356 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 357    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 358    conventional cores (ie. Application or Realtime profile).  */
 359
 360 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 361 #define ARM_CPUID(env) (env->cp15.c0_cpuid)
 362
 363 #define ARM_CPUID_ARM1026     0x4106a262
 364 #define ARM_CPUID_ARM926      0x41069265
 365 #define ARM_CPUID_ARM946      0x41059461
 366 #define ARM_CPUID_TI915T      0x54029152
 367 #define ARM_CPUID_TI925T      0x54029252
 368 #define ARM_CPUID_PXA250      0x69052100
 369 #define ARM_CPUID_PXA255      0x69052d00
 370 #define ARM_CPUID_PXA260      0x69052903
 371 #define ARM_CPUID_PXA261      0x69052d05
 372 #define ARM_CPUID_PXA262      0x69052d06
 373 #define ARM_CPUID_PXA270      0x69054110
 374 #define ARM_CPUID_PXA270_A0   0x69054110
 375 #define ARM_CPUID_PXA270_A1   0x69054111
 376 #define ARM_CPUID_PXA270_B0   0x69054112
 377 #define ARM_CPUID_PXA270_B1   0x69054113
 378 #define ARM_CPUID_PXA270_C0   0x69054114
 379 #define ARM_CPUID_PXA270_C5   0x69054117
 380 #define ARM_CPUID_ARM1136     0x4117b363
 381 #define ARM_CPUID_ARM11MPCORE 0x410fb022
 382 #define ARM_CPUID_CORTEXA8    0x410fc080
 383 #define ARM_CPUID_CORTEXM3    0x410fc231
 384 #define ARM_CPUID_ANY         0xffffffff
 385
 386 #if defined(CONFIG_USER_ONLY)
 387 #define TARGET_PAGE_BITS 12
 388 #else
 389 /* The ARM MMU allows 1k pages.  */
 390 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 391    architecture revisions.  Maybe a configure option to disable them.  */
 392 #define TARGET_PAGE_BITS 10
 393 #endif
 394
 395 #define CPUState CPUARMState
 396 #define cpu_init cpu_arm_init
 397 #define cpu_exec cpu_arm_exec
 398 #define cpu_gen_code cpu_arm_gen_code
 399 #define cpu_signal_handler cpu_arm_signal_handler
 400 #define cpu_list arm_cpu_list
 401
 402 #define ARM_CPU_SAVE_VERSION 1
 403
 404 /* MMU modes definitions */
 405 #define MMU_MODE0_SUFFIX _kernel
 406 #define MMU_MODE1_SUFFIX _user
 407 #define MMU_USER_IDX 1
 408 static inline int cpu_mmu_index (CPUState *env)
 409 {
 410     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 411 }
 412
 413 #include "cpu-all.h"
 414
 415 #endif